Commit | Line | Data |
---|---|---|
7c2f891c | 1 | /* |
7c2f891c SH |
2 | * Freescale i.MX Frame Buffer device driver |
3 | * | |
4 | * Copyright (C) 2004 Sascha Hauer, Pengutronix | |
5 | * Based on acornfb.c Copyright (C) Russell King. | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file COPYING in the main directory of this archive for | |
9 | * more details. | |
10 | * | |
11 | * Please direct your questions and comments on this driver to the following | |
12 | * email address: | |
13 | * | |
14 | * linux-arm-kernel@lists.arm.linux.org.uk | |
15 | */ | |
16 | ||
7c2f891c SH |
17 | #include <linux/module.h> |
18 | #include <linux/kernel.h> | |
7c2f891c SH |
19 | #include <linux/errno.h> |
20 | #include <linux/string.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/slab.h> | |
27ac792c | 23 | #include <linux/mm.h> |
7c2f891c SH |
24 | #include <linux/fb.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/init.h> | |
27 | #include <linux/ioport.h> | |
28 | #include <linux/cpufreq.h> | |
f909ef64 | 29 | #include <linux/clk.h> |
d052d1be | 30 | #include <linux/platform_device.h> |
7c2f891c | 31 | #include <linux/dma-mapping.h> |
72330b0e | 32 | #include <linux/io.h> |
f909ef64 | 33 | #include <linux/math64.h> |
1b6c7936 MP |
34 | #include <linux/of.h> |
35 | #include <linux/of_device.h> | |
36 | ||
37 | #include <video/of_display_timing.h> | |
38 | #include <video/of_videomode.h> | |
39 | #include <video/videomode.h> | |
7c2f891c | 40 | |
82906b13 | 41 | #include <linux/platform_data/video-imxfb.h> |
7c2f891c SH |
42 | |
43 | /* | |
44 | * Complain if VAR is out of range. | |
45 | */ | |
46 | #define DEBUG_VAR 1 | |
47 | ||
81ef8061 EB |
48 | #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ |
49 | (defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) && \ | |
50 | defined(CONFIG_FB_IMX_MODULE)) | |
51 | #define PWMR_BACKLIGHT_AVAILABLE | |
52 | #endif | |
53 | ||
72330b0e JB |
54 | #define DRIVER_NAME "imx-fb" |
55 | ||
56 | #define LCDC_SSA 0x00 | |
57 | ||
58 | #define LCDC_SIZE 0x04 | |
59 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) | |
1d0f9870 | 60 | |
e69dc9a9 SG |
61 | #define YMAX_MASK_IMX1 0x1ff |
62 | #define YMAX_MASK_IMX21 0x3ff | |
72330b0e JB |
63 | |
64 | #define LCDC_VPW 0x08 | |
65 | #define VPW_VPW(x) ((x) & 0x3ff) | |
66 | ||
67 | #define LCDC_CPOS 0x0C | |
68 | #define CPOS_CC1 (1<<31) | |
69 | #define CPOS_CC0 (1<<30) | |
70 | #define CPOS_OP (1<<28) | |
71 | #define CPOS_CXP(x) (((x) & 3ff) << 16) | |
1d0f9870 | 72 | |
72330b0e JB |
73 | #define LCDC_LCWHB 0x10 |
74 | #define LCWHB_BK_EN (1<<31) | |
75 | #define LCWHB_CW(w) (((w) & 0x1f) << 24) | |
76 | #define LCWHB_CH(h) (((h) & 0x1f) << 16) | |
77 | #define LCWHB_BD(x) ((x) & 0xff) | |
78 | ||
79 | #define LCDC_LCHCC 0x14 | |
1d0f9870 | 80 | |
72330b0e JB |
81 | #define LCDC_PCR 0x18 |
82 | ||
83 | #define LCDC_HCR 0x1C | |
84 | #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) | |
85 | #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) | |
86 | #define HCR_H_WAIT_2(x) ((x) & 0xff) | |
87 | ||
88 | #define LCDC_VCR 0x20 | |
89 | #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) | |
90 | #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) | |
91 | #define VCR_V_WAIT_2(x) ((x) & 0xff) | |
92 | ||
93 | #define LCDC_POS 0x24 | |
94 | #define POS_POS(x) ((x) & 1f) | |
95 | ||
96 | #define LCDC_LSCR1 0x28 | |
97 | /* bit fields in imxfb.h */ | |
98 | ||
99 | #define LCDC_PWMR 0x2C | |
100 | /* bit fields in imxfb.h */ | |
101 | ||
102 | #define LCDC_DMACR 0x30 | |
103 | /* bit fields in imxfb.h */ | |
104 | ||
105 | #define LCDC_RMCR 0x34 | |
1d0f9870 | 106 | |
f142b619 | 107 | #define RMCR_LCDC_EN_MX1 (1<<1) |
1d0f9870 | 108 | |
72330b0e JB |
109 | #define RMCR_SELF_REF (1<<0) |
110 | ||
111 | #define LCDC_LCDICR 0x38 | |
112 | #define LCDICR_INT_SYN (1<<2) | |
113 | #define LCDICR_INT_CON (1) | |
114 | ||
115 | #define LCDC_LCDISR 0x40 | |
116 | #define LCDISR_UDR_ERR (1<<3) | |
117 | #define LCDISR_ERR_RES (1<<2) | |
118 | #define LCDISR_EOF (1<<1) | |
119 | #define LCDISR_BOF (1<<0) | |
120 | ||
1b6c7936 MP |
121 | #define IMXFB_LSCR1_DEFAULT 0x00120300 |
122 | ||
343684ff SH |
123 | /* Used fb-mode. Can be set on kernel command line, therefore file-static. */ |
124 | static const char *fb_mode; | |
125 | ||
24b9baf7 SH |
126 | /* |
127 | * These are the bitfields for each | |
128 | * display depth that we support. | |
129 | */ | |
130 | struct imxfb_rgb { | |
131 | struct fb_bitfield red; | |
132 | struct fb_bitfield green; | |
133 | struct fb_bitfield blue; | |
134 | struct fb_bitfield transp; | |
135 | }; | |
136 | ||
e69dc9a9 SG |
137 | enum imxfb_type { |
138 | IMX1_FB, | |
139 | IMX21_FB, | |
140 | }; | |
141 | ||
24b9baf7 SH |
142 | struct imxfb_info { |
143 | struct platform_device *pdev; | |
144 | void __iomem *regs; | |
13aaea03 SH |
145 | struct clk *clk_ipg; |
146 | struct clk *clk_ahb; | |
147 | struct clk *clk_per; | |
e69dc9a9 | 148 | enum imxfb_type devtype; |
e6b267ce | 149 | bool enabled; |
24b9baf7 | 150 | |
24b9baf7 SH |
151 | /* |
152 | * These are the addresses we mapped | |
153 | * the framebuffer memory region to. | |
154 | */ | |
155 | dma_addr_t map_dma; | |
156 | u_char *map_cpu; | |
157 | u_int map_size; | |
158 | ||
159 | u_char *screen_cpu; | |
160 | dma_addr_t screen_dma; | |
161 | u_int palette_size; | |
162 | ||
163 | dma_addr_t dbar1; | |
164 | dma_addr_t dbar2; | |
165 | ||
166 | u_int pcr; | |
167 | u_int pwmr; | |
168 | u_int lscr1; | |
169 | u_int dmacr; | |
170 | u_int cmap_inverse:1, | |
171 | cmap_static:1, | |
172 | unused:30; | |
173 | ||
343684ff SH |
174 | struct imx_fb_videomode *mode; |
175 | int num_modes; | |
81ef8061 | 176 | #ifdef PWMR_BACKLIGHT_AVAILABLE |
7a2bb23c | 177 | struct backlight_device *bl; |
81ef8061 | 178 | #endif |
343684ff | 179 | |
24b9baf7 SH |
180 | void (*lcd_power)(int); |
181 | void (*backlight_power)(int); | |
182 | }; | |
183 | ||
e69dc9a9 SG |
184 | static struct platform_device_id imxfb_devtype[] = { |
185 | { | |
186 | .name = "imx1-fb", | |
187 | .driver_data = IMX1_FB, | |
188 | }, { | |
189 | .name = "imx21-fb", | |
190 | .driver_data = IMX21_FB, | |
191 | }, { | |
192 | /* sentinel */ | |
193 | } | |
194 | }; | |
195 | MODULE_DEVICE_TABLE(platform, imxfb_devtype); | |
196 | ||
1b6c7936 MP |
197 | static struct of_device_id imxfb_of_dev_id[] = { |
198 | { | |
199 | .compatible = "fsl,imx1-fb", | |
200 | .data = &imxfb_devtype[IMX1_FB], | |
201 | }, { | |
202 | .compatible = "fsl,imx21-fb", | |
203 | .data = &imxfb_devtype[IMX21_FB], | |
204 | }, { | |
205 | /* sentinel */ | |
206 | } | |
207 | }; | |
208 | MODULE_DEVICE_TABLE(of, imxfb_of_dev_id); | |
209 | ||
e69dc9a9 SG |
210 | static inline int is_imx1_fb(struct imxfb_info *fbi) |
211 | { | |
212 | return fbi->devtype == IMX1_FB; | |
213 | } | |
214 | ||
24b9baf7 SH |
215 | #define IMX_NAME "IMX" |
216 | ||
217 | /* | |
218 | * Minimum X and Y resolutions | |
219 | */ | |
220 | #define MIN_XRES 64 | |
221 | #define MIN_YRES 64 | |
222 | ||
1512222b SH |
223 | /* Actually this really is 18bit support, the lowest 2 bits of each colour |
224 | * are unused in hardware. We claim to have 24bit support to make software | |
225 | * like X work, which does not support 18bit. | |
226 | */ | |
227 | static struct imxfb_rgb def_rgb_18 = { | |
228 | .red = {.offset = 16, .length = 8,}, | |
229 | .green = {.offset = 8, .length = 8,}, | |
230 | .blue = {.offset = 0, .length = 8,}, | |
231 | .transp = {.offset = 0, .length = 0,}, | |
232 | }; | |
233 | ||
80eee6bc SH |
234 | static struct imxfb_rgb def_rgb_16_tft = { |
235 | .red = {.offset = 11, .length = 5,}, | |
236 | .green = {.offset = 5, .length = 6,}, | |
237 | .blue = {.offset = 0, .length = 5,}, | |
238 | .transp = {.offset = 0, .length = 0,}, | |
239 | }; | |
240 | ||
241 | static struct imxfb_rgb def_rgb_16_stn = { | |
66c8719b SH |
242 | .red = {.offset = 8, .length = 4,}, |
243 | .green = {.offset = 4, .length = 4,}, | |
244 | .blue = {.offset = 0, .length = 4,}, | |
245 | .transp = {.offset = 0, .length = 0,}, | |
7c2f891c SH |
246 | }; |
247 | ||
248 | static struct imxfb_rgb def_rgb_8 = { | |
66c8719b SH |
249 | .red = {.offset = 0, .length = 8,}, |
250 | .green = {.offset = 0, .length = 8,}, | |
251 | .blue = {.offset = 0, .length = 8,}, | |
252 | .transp = {.offset = 0, .length = 0,}, | |
7c2f891c SH |
253 | }; |
254 | ||
66c8719b SH |
255 | static int imxfb_activate_var(struct fb_var_screeninfo *var, |
256 | struct fb_info *info); | |
7c2f891c SH |
257 | |
258 | static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) | |
259 | { | |
260 | chan &= 0xffff; | |
261 | chan >>= 16 - bf->length; | |
262 | return chan << bf->offset; | |
263 | } | |
264 | ||
66c8719b SH |
265 | static int imxfb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, |
266 | u_int trans, struct fb_info *info) | |
7c2f891c SH |
267 | { |
268 | struct imxfb_info *fbi = info->par; | |
269 | u_int val, ret = 1; | |
270 | ||
271 | #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) | |
272 | if (regno < fbi->palette_size) { | |
273 | val = (CNVT_TOHW(red, 4) << 8) | | |
274 | (CNVT_TOHW(green,4) << 4) | | |
275 | CNVT_TOHW(blue, 4); | |
276 | ||
72330b0e | 277 | writel(val, fbi->regs + 0x800 + (regno << 2)); |
7c2f891c SH |
278 | ret = 0; |
279 | } | |
280 | return ret; | |
281 | } | |
282 | ||
66c8719b | 283 | static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, |
7c2f891c SH |
284 | u_int trans, struct fb_info *info) |
285 | { | |
286 | struct imxfb_info *fbi = info->par; | |
287 | unsigned int val; | |
288 | int ret = 1; | |
289 | ||
290 | /* | |
291 | * If inverse mode was selected, invert all the colours | |
292 | * rather than the register number. The register number | |
293 | * is what you poke into the framebuffer to produce the | |
294 | * colour you requested. | |
295 | */ | |
296 | if (fbi->cmap_inverse) { | |
297 | red = 0xffff - red; | |
298 | green = 0xffff - green; | |
299 | blue = 0xffff - blue; | |
300 | } | |
301 | ||
302 | /* | |
303 | * If greyscale is true, then we convert the RGB value | |
304 | * to greyscale no mater what visual we are using. | |
305 | */ | |
306 | if (info->var.grayscale) | |
307 | red = green = blue = (19595 * red + 38470 * green + | |
308 | 7471 * blue) >> 16; | |
309 | ||
310 | switch (info->fix.visual) { | |
311 | case FB_VISUAL_TRUECOLOR: | |
312 | /* | |
313 | * 12 or 16-bit True Colour. We encode the RGB value | |
314 | * according to the RGB bitfield information. | |
315 | */ | |
316 | if (regno < 16) { | |
317 | u32 *pal = info->pseudo_palette; | |
318 | ||
319 | val = chan_to_field(red, &info->var.red); | |
320 | val |= chan_to_field(green, &info->var.green); | |
321 | val |= chan_to_field(blue, &info->var.blue); | |
322 | ||
323 | pal[regno] = val; | |
324 | ret = 0; | |
325 | } | |
326 | break; | |
327 | ||
328 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | |
329 | case FB_VISUAL_PSEUDOCOLOR: | |
330 | ret = imxfb_setpalettereg(regno, red, green, blue, trans, info); | |
331 | break; | |
332 | } | |
333 | ||
334 | return ret; | |
335 | } | |
336 | ||
343684ff SH |
337 | static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi) |
338 | { | |
339 | struct imx_fb_videomode *m; | |
340 | int i; | |
341 | ||
1b6c7936 MP |
342 | if (!fb_mode) |
343 | return &fbi->mode[0]; | |
344 | ||
343684ff SH |
345 | for (i = 0, m = &fbi->mode[0]; i < fbi->num_modes; i++, m++) { |
346 | if (!strcmp(m->mode.name, fb_mode)) | |
347 | return m; | |
348 | } | |
349 | return NULL; | |
350 | } | |
351 | ||
7c2f891c SH |
352 | /* |
353 | * imxfb_check_var(): | |
354 | * Round up in the following order: bits_per_pixel, xres, | |
355 | * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, | |
356 | * bitfields, horizontal timing, vertical timing. | |
357 | */ | |
66c8719b | 358 | static int imxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) |
7c2f891c SH |
359 | { |
360 | struct imxfb_info *fbi = info->par; | |
80eee6bc | 361 | struct imxfb_rgb *rgb; |
343684ff SH |
362 | const struct imx_fb_videomode *imxfb_mode; |
363 | unsigned long lcd_clk; | |
364 | unsigned long long tmp; | |
365 | u32 pcr = 0; | |
7c2f891c SH |
366 | |
367 | if (var->xres < MIN_XRES) | |
368 | var->xres = MIN_XRES; | |
369 | if (var->yres < MIN_YRES) | |
370 | var->yres = MIN_YRES; | |
343684ff SH |
371 | |
372 | imxfb_mode = imxfb_find_mode(fbi); | |
373 | if (!imxfb_mode) | |
374 | return -EINVAL; | |
375 | ||
376 | var->xres = imxfb_mode->mode.xres; | |
377 | var->yres = imxfb_mode->mode.yres; | |
378 | var->bits_per_pixel = imxfb_mode->bpp; | |
379 | var->pixclock = imxfb_mode->mode.pixclock; | |
380 | var->hsync_len = imxfb_mode->mode.hsync_len; | |
381 | var->left_margin = imxfb_mode->mode.left_margin; | |
382 | var->right_margin = imxfb_mode->mode.right_margin; | |
383 | var->vsync_len = imxfb_mode->mode.vsync_len; | |
384 | var->upper_margin = imxfb_mode->mode.upper_margin; | |
385 | var->lower_margin = imxfb_mode->mode.lower_margin; | |
386 | var->sync = imxfb_mode->mode.sync; | |
387 | var->xres_virtual = max(var->xres_virtual, var->xres); | |
388 | var->yres_virtual = max(var->yres_virtual, var->yres); | |
7c2f891c SH |
389 | |
390 | pr_debug("var->bits_per_pixel=%d\n", var->bits_per_pixel); | |
343684ff | 391 | |
13aaea03 | 392 | lcd_clk = clk_get_rate(fbi->clk_per); |
343684ff SH |
393 | |
394 | tmp = var->pixclock * (unsigned long long)lcd_clk; | |
395 | ||
396 | do_div(tmp, 1000000); | |
397 | ||
398 | if (do_div(tmp, 1000000) > 500000) | |
399 | tmp++; | |
400 | ||
401 | pcr = (unsigned int)tmp; | |
402 | ||
403 | if (--pcr > 0x3F) { | |
404 | pcr = 0x3F; | |
405 | printk(KERN_WARNING "Must limit pixel clock to %luHz\n", | |
406 | lcd_clk / pcr); | |
407 | } | |
408 | ||
7c2f891c | 409 | switch (var->bits_per_pixel) { |
1512222b | 410 | case 32: |
343684ff | 411 | pcr |= PCR_BPIX_18; |
1512222b SH |
412 | rgb = &def_rgb_18; |
413 | break; | |
7c2f891c | 414 | case 16: |
80eee6bc | 415 | default: |
e69dc9a9 | 416 | if (is_imx1_fb(fbi)) |
343684ff SH |
417 | pcr |= PCR_BPIX_12; |
418 | else | |
419 | pcr |= PCR_BPIX_16; | |
420 | ||
421 | if (imxfb_mode->pcr & PCR_TFT) | |
80eee6bc SH |
422 | rgb = &def_rgb_16_tft; |
423 | else | |
424 | rgb = &def_rgb_16_stn; | |
7c2f891c SH |
425 | break; |
426 | case 8: | |
343684ff | 427 | pcr |= PCR_BPIX_8; |
80eee6bc | 428 | rgb = &def_rgb_8; |
7c2f891c | 429 | break; |
7c2f891c SH |
430 | } |
431 | ||
343684ff SH |
432 | /* add sync polarities */ |
433 | pcr |= imxfb_mode->pcr & ~(0x3f | (7 << 25)); | |
434 | ||
435 | fbi->pcr = pcr; | |
436 | ||
7c2f891c SH |
437 | /* |
438 | * Copy the RGB parameters for this display | |
439 | * from the machine specific parameters. | |
440 | */ | |
80eee6bc SH |
441 | var->red = rgb->red; |
442 | var->green = rgb->green; | |
443 | var->blue = rgb->blue; | |
444 | var->transp = rgb->transp; | |
7c2f891c SH |
445 | |
446 | pr_debug("RGBT length = %d:%d:%d:%d\n", | |
447 | var->red.length, var->green.length, var->blue.length, | |
448 | var->transp.length); | |
449 | ||
450 | pr_debug("RGBT offset = %d:%d:%d:%d\n", | |
451 | var->red.offset, var->green.offset, var->blue.offset, | |
452 | var->transp.offset); | |
453 | ||
454 | return 0; | |
455 | } | |
456 | ||
457 | /* | |
458 | * imxfb_set_par(): | |
459 | * Set the user defined part of the display for the specified console | |
460 | */ | |
461 | static int imxfb_set_par(struct fb_info *info) | |
462 | { | |
463 | struct imxfb_info *fbi = info->par; | |
464 | struct fb_var_screeninfo *var = &info->var; | |
465 | ||
1512222b | 466 | if (var->bits_per_pixel == 16 || var->bits_per_pixel == 32) |
7c2f891c SH |
467 | info->fix.visual = FB_VISUAL_TRUECOLOR; |
468 | else if (!fbi->cmap_static) | |
469 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
470 | else { | |
471 | /* | |
472 | * Some people have weird ideas about wanting static | |
473 | * pseudocolor maps. I suspect their user space | |
474 | * applications are broken. | |
475 | */ | |
476 | info->fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; | |
477 | } | |
478 | ||
66c8719b | 479 | info->fix.line_length = var->xres_virtual * var->bits_per_pixel / 8; |
7c2f891c SH |
480 | fbi->palette_size = var->bits_per_pixel == 8 ? 256 : 16; |
481 | ||
482 | imxfb_activate_var(var, info); | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
81ef8061 | 487 | #ifdef PWMR_BACKLIGHT_AVAILABLE |
7a2bb23c EB |
488 | static int imxfb_bl_get_brightness(struct backlight_device *bl) |
489 | { | |
490 | struct imxfb_info *fbi = bl_get_data(bl); | |
491 | ||
492 | return readl(fbi->regs + LCDC_PWMR) & 0xFF; | |
493 | } | |
494 | ||
495 | static int imxfb_bl_update_status(struct backlight_device *bl) | |
496 | { | |
497 | struct imxfb_info *fbi = bl_get_data(bl); | |
498 | int brightness = bl->props.brightness; | |
499 | ||
1b6c7936 MP |
500 | if (!fbi->pwmr) |
501 | return 0; | |
502 | ||
7a2bb23c EB |
503 | if (bl->props.power != FB_BLANK_UNBLANK) |
504 | brightness = 0; | |
505 | if (bl->props.fb_blank != FB_BLANK_UNBLANK) | |
506 | brightness = 0; | |
507 | ||
508 | fbi->pwmr = (fbi->pwmr & ~0xFF) | brightness; | |
509 | ||
13aaea03 SH |
510 | if (bl->props.fb_blank != FB_BLANK_UNBLANK) { |
511 | clk_prepare_enable(fbi->clk_ipg); | |
512 | clk_prepare_enable(fbi->clk_ahb); | |
513 | clk_prepare_enable(fbi->clk_per); | |
514 | } | |
7a2bb23c | 515 | writel(fbi->pwmr, fbi->regs + LCDC_PWMR); |
13aaea03 SH |
516 | if (bl->props.fb_blank != FB_BLANK_UNBLANK) { |
517 | clk_disable_unprepare(fbi->clk_per); | |
518 | clk_disable_unprepare(fbi->clk_ahb); | |
519 | clk_disable_unprepare(fbi->clk_ipg); | |
520 | } | |
7a2bb23c EB |
521 | |
522 | return 0; | |
523 | } | |
524 | ||
525 | static const struct backlight_ops imxfb_lcdc_bl_ops = { | |
526 | .update_status = imxfb_bl_update_status, | |
527 | .get_brightness = imxfb_bl_get_brightness, | |
528 | }; | |
529 | ||
530 | static void imxfb_init_backlight(struct imxfb_info *fbi) | |
531 | { | |
532 | struct backlight_properties props; | |
533 | struct backlight_device *bl; | |
534 | ||
535 | if (fbi->bl) | |
536 | return; | |
537 | ||
538 | memset(&props, 0, sizeof(struct backlight_properties)); | |
539 | props.max_brightness = 0xff; | |
bb7ca747 | 540 | props.type = BACKLIGHT_RAW; |
7a2bb23c EB |
541 | writel(fbi->pwmr, fbi->regs + LCDC_PWMR); |
542 | ||
543 | bl = backlight_device_register("imxfb-bl", &fbi->pdev->dev, fbi, | |
544 | &imxfb_lcdc_bl_ops, &props); | |
545 | if (IS_ERR(bl)) { | |
546 | dev_err(&fbi->pdev->dev, "error %ld on backlight register\n", | |
547 | PTR_ERR(bl)); | |
548 | return; | |
549 | } | |
550 | ||
551 | fbi->bl = bl; | |
552 | bl->props.power = FB_BLANK_UNBLANK; | |
553 | bl->props.fb_blank = FB_BLANK_UNBLANK; | |
554 | bl->props.brightness = imxfb_bl_get_brightness(bl); | |
555 | } | |
556 | ||
557 | static void imxfb_exit_backlight(struct imxfb_info *fbi) | |
558 | { | |
559 | if (fbi->bl) | |
560 | backlight_device_unregister(fbi->bl); | |
561 | } | |
81ef8061 | 562 | #endif |
7a2bb23c | 563 | |
7c2f891c SH |
564 | static void imxfb_enable_controller(struct imxfb_info *fbi) |
565 | { | |
e6b267ce FE |
566 | |
567 | if (fbi->enabled) | |
568 | return; | |
569 | ||
7c2f891c SH |
570 | pr_debug("Enabling LCD controller\n"); |
571 | ||
72330b0e | 572 | writel(fbi->screen_dma, fbi->regs + LCDC_SSA); |
7c2f891c | 573 | |
72330b0e JB |
574 | /* panning offset 0 (0 pixel offset) */ |
575 | writel(0x00000000, fbi->regs + LCDC_POS); | |
7c2f891c SH |
576 | |
577 | /* disable hardware cursor */ | |
72330b0e JB |
578 | writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1), |
579 | fbi->regs + LCDC_CPOS); | |
7c2f891c | 580 | |
f142b619 SH |
581 | /* |
582 | * RMCR_LCDC_EN_MX1 is present on i.MX1 only, but doesn't hurt | |
583 | * on other SoCs | |
584 | */ | |
585 | writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR); | |
7c2f891c | 586 | |
13aaea03 SH |
587 | clk_prepare_enable(fbi->clk_ipg); |
588 | clk_prepare_enable(fbi->clk_ahb); | |
589 | clk_prepare_enable(fbi->clk_per); | |
e6b267ce | 590 | fbi->enabled = true; |
f909ef64 | 591 | |
66c8719b | 592 | if (fbi->backlight_power) |
7c2f891c | 593 | fbi->backlight_power(1); |
66c8719b | 594 | if (fbi->lcd_power) |
7c2f891c SH |
595 | fbi->lcd_power(1); |
596 | } | |
597 | ||
598 | static void imxfb_disable_controller(struct imxfb_info *fbi) | |
599 | { | |
e6b267ce FE |
600 | if (!fbi->enabled) |
601 | return; | |
602 | ||
7c2f891c SH |
603 | pr_debug("Disabling LCD controller\n"); |
604 | ||
66c8719b | 605 | if (fbi->backlight_power) |
7c2f891c | 606 | fbi->backlight_power(0); |
66c8719b | 607 | if (fbi->lcd_power) |
7c2f891c SH |
608 | fbi->lcd_power(0); |
609 | ||
13aaea03 SH |
610 | clk_disable_unprepare(fbi->clk_per); |
611 | clk_disable_unprepare(fbi->clk_ipg); | |
612 | clk_disable_unprepare(fbi->clk_ahb); | |
e6b267ce | 613 | fbi->enabled = false; |
f909ef64 | 614 | |
72330b0e | 615 | writel(0, fbi->regs + LCDC_RMCR); |
7c2f891c SH |
616 | } |
617 | ||
618 | static int imxfb_blank(int blank, struct fb_info *info) | |
619 | { | |
620 | struct imxfb_info *fbi = info->par; | |
621 | ||
622 | pr_debug("imxfb_blank: blank=%d\n", blank); | |
623 | ||
624 | switch (blank) { | |
625 | case FB_BLANK_POWERDOWN: | |
626 | case FB_BLANK_VSYNC_SUSPEND: | |
627 | case FB_BLANK_HSYNC_SUSPEND: | |
628 | case FB_BLANK_NORMAL: | |
629 | imxfb_disable_controller(fbi); | |
630 | break; | |
631 | ||
632 | case FB_BLANK_UNBLANK: | |
633 | imxfb_enable_controller(fbi); | |
634 | break; | |
635 | } | |
636 | return 0; | |
637 | } | |
638 | ||
639 | static struct fb_ops imxfb_ops = { | |
640 | .owner = THIS_MODULE, | |
641 | .fb_check_var = imxfb_check_var, | |
642 | .fb_set_par = imxfb_set_par, | |
643 | .fb_setcolreg = imxfb_setcolreg, | |
644 | .fb_fillrect = cfb_fillrect, | |
645 | .fb_copyarea = cfb_copyarea, | |
646 | .fb_imageblit = cfb_imageblit, | |
647 | .fb_blank = imxfb_blank, | |
7c2f891c SH |
648 | }; |
649 | ||
650 | /* | |
651 | * imxfb_activate_var(): | |
652 | * Configures LCD Controller based on entries in var parameter. Settings are | |
653 | * only written to the controller if changes were made. | |
654 | */ | |
655 | static int imxfb_activate_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
656 | { | |
657 | struct imxfb_info *fbi = info->par; | |
e69dc9a9 | 658 | u32 ymax_mask = is_imx1_fb(fbi) ? YMAX_MASK_IMX1 : YMAX_MASK_IMX21; |
f909ef64 | 659 | |
7c2f891c SH |
660 | pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n", |
661 | var->xres, var->hsync_len, | |
662 | var->left_margin, var->right_margin); | |
663 | pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n", | |
664 | var->yres, var->vsync_len, | |
665 | var->upper_margin, var->lower_margin); | |
666 | ||
667 | #if DEBUG_VAR | |
668 | if (var->xres < 16 || var->xres > 1024) | |
669 | printk(KERN_ERR "%s: invalid xres %d\n", | |
670 | info->fix.id, var->xres); | |
671 | if (var->hsync_len < 1 || var->hsync_len > 64) | |
672 | printk(KERN_ERR "%s: invalid hsync_len %d\n", | |
673 | info->fix.id, var->hsync_len); | |
674 | if (var->left_margin > 255) | |
675 | printk(KERN_ERR "%s: invalid left_margin %d\n", | |
676 | info->fix.id, var->left_margin); | |
677 | if (var->right_margin > 255) | |
678 | printk(KERN_ERR "%s: invalid right_margin %d\n", | |
679 | info->fix.id, var->right_margin); | |
e69dc9a9 | 680 | if (var->yres < 1 || var->yres > ymax_mask) |
7c2f891c SH |
681 | printk(KERN_ERR "%s: invalid yres %d\n", |
682 | info->fix.id, var->yres); | |
683 | if (var->vsync_len > 100) | |
684 | printk(KERN_ERR "%s: invalid vsync_len %d\n", | |
685 | info->fix.id, var->vsync_len); | |
686 | if (var->upper_margin > 63) | |
687 | printk(KERN_ERR "%s: invalid upper_margin %d\n", | |
688 | info->fix.id, var->upper_margin); | |
689 | if (var->lower_margin > 255) | |
690 | printk(KERN_ERR "%s: invalid lower_margin %d\n", | |
691 | info->fix.id, var->lower_margin); | |
692 | #endif | |
693 | ||
343684ff SH |
694 | /* physical screen start address */ |
695 | writel(VPW_VPW(var->xres * var->bits_per_pixel / 8 / 4), | |
696 | fbi->regs + LCDC_VPW); | |
697 | ||
7e8549bc SH |
698 | writel(HCR_H_WIDTH(var->hsync_len - 1) | |
699 | HCR_H_WAIT_1(var->right_margin - 1) | | |
700 | HCR_H_WAIT_2(var->left_margin - 3), | |
72330b0e | 701 | fbi->regs + LCDC_HCR); |
7c2f891c | 702 | |
72330b0e | 703 | writel(VCR_V_WIDTH(var->vsync_len) | |
d6ed5755 SH |
704 | VCR_V_WAIT_1(var->lower_margin) | |
705 | VCR_V_WAIT_2(var->upper_margin), | |
72330b0e | 706 | fbi->regs + LCDC_VCR); |
7c2f891c | 707 | |
e69dc9a9 | 708 | writel(SIZE_XMAX(var->xres) | (var->yres & ymax_mask), |
72330b0e | 709 | fbi->regs + LCDC_SIZE); |
f909ef64 | 710 | |
343684ff | 711 | writel(fbi->pcr, fbi->regs + LCDC_PCR); |
81ef8061 | 712 | #ifndef PWMR_BACKLIGHT_AVAILABLE |
1b6c7936 MP |
713 | if (fbi->pwmr) |
714 | writel(fbi->pwmr, fbi->regs + LCDC_PWMR); | |
81ef8061 | 715 | #endif |
72330b0e | 716 | writel(fbi->lscr1, fbi->regs + LCDC_LSCR1); |
1b6c7936 MP |
717 | |
718 | /* dmacr = 0 is no valid value, as we need DMA control marks. */ | |
719 | if (fbi->dmacr) | |
720 | writel(fbi->dmacr, fbi->regs + LCDC_DMACR); | |
7c2f891c SH |
721 | |
722 | return 0; | |
723 | } | |
724 | ||
7c2f891c SH |
725 | #ifdef CONFIG_PM |
726 | /* | |
727 | * Power management hooks. Note that we won't be called from IRQ context, | |
728 | * unlike the blank functions above, so we may sleep. | |
729 | */ | |
3ae5eaec | 730 | static int imxfb_suspend(struct platform_device *dev, pm_message_t state) |
7c2f891c | 731 | { |
1ec56203 UKK |
732 | struct fb_info *info = platform_get_drvdata(dev); |
733 | struct imxfb_info *fbi = info->par; | |
66c8719b SH |
734 | |
735 | pr_debug("%s\n", __func__); | |
7c2f891c | 736 | |
9480e307 | 737 | imxfb_disable_controller(fbi); |
7c2f891c SH |
738 | return 0; |
739 | } | |
740 | ||
3ae5eaec | 741 | static int imxfb_resume(struct platform_device *dev) |
7c2f891c | 742 | { |
1ec56203 UKK |
743 | struct fb_info *info = platform_get_drvdata(dev); |
744 | struct imxfb_info *fbi = info->par; | |
66c8719b SH |
745 | |
746 | pr_debug("%s\n", __func__); | |
7c2f891c | 747 | |
9480e307 | 748 | imxfb_enable_controller(fbi); |
7c2f891c SH |
749 | return 0; |
750 | } | |
751 | #else | |
752 | #define imxfb_suspend NULL | |
753 | #define imxfb_resume NULL | |
754 | #endif | |
755 | ||
1b6c7936 | 756 | static int imxfb_init_fbinfo(struct platform_device *pdev) |
7c2f891c | 757 | { |
27889273 | 758 | struct imx_fb_platform_data *pdata = pdev->dev.platform_data; |
72330b0e | 759 | struct fb_info *info = dev_get_drvdata(&pdev->dev); |
7c2f891c | 760 | struct imxfb_info *fbi = info->par; |
1b6c7936 | 761 | struct device_node *np; |
7c2f891c | 762 | |
5ae12170 | 763 | pr_debug("%s\n",__func__); |
7c2f891c | 764 | |
66c8719b | 765 | info->pseudo_palette = kmalloc(sizeof(u32) * 16, GFP_KERNEL); |
7c2f891c SH |
766 | if (!info->pseudo_palette) |
767 | return -ENOMEM; | |
768 | ||
769 | memset(fbi, 0, sizeof(struct imxfb_info)); | |
7c2f891c | 770 | |
afc10301 GGM |
771 | fbi->devtype = pdev->id_entry->driver_data; |
772 | ||
7c2f891c SH |
773 | strlcpy(info->fix.id, IMX_NAME, sizeof(info->fix.id)); |
774 | ||
66c8719b | 775 | info->fix.type = FB_TYPE_PACKED_PIXELS; |
7c2f891c SH |
776 | info->fix.type_aux = 0; |
777 | info->fix.xpanstep = 0; | |
778 | info->fix.ypanstep = 0; | |
779 | info->fix.ywrapstep = 0; | |
66c8719b | 780 | info->fix.accel = FB_ACCEL_NONE; |
7c2f891c SH |
781 | |
782 | info->var.nonstd = 0; | |
783 | info->var.activate = FB_ACTIVATE_NOW; | |
784 | info->var.height = -1; | |
785 | info->var.width = -1; | |
786 | info->var.accel_flags = 0; | |
66c8719b | 787 | info->var.vmode = FB_VMODE_NONINTERLACED; |
7c2f891c SH |
788 | |
789 | info->fbops = &imxfb_ops; | |
66c8719b SH |
790 | info->flags = FBINFO_FLAG_DEFAULT | |
791 | FBINFO_READS_FAST; | |
1b6c7936 MP |
792 | if (pdata) { |
793 | info->var.grayscale = pdata->cmap_greyscale; | |
794 | fbi->cmap_inverse = pdata->cmap_inverse; | |
795 | fbi->cmap_static = pdata->cmap_static; | |
796 | fbi->lscr1 = pdata->lscr1; | |
797 | fbi->dmacr = pdata->dmacr; | |
798 | fbi->pwmr = pdata->pwmr; | |
799 | fbi->lcd_power = pdata->lcd_power; | |
800 | fbi->backlight_power = pdata->backlight_power; | |
801 | } else { | |
802 | np = pdev->dev.of_node; | |
803 | info->var.grayscale = of_property_read_bool(np, | |
804 | "cmap-greyscale"); | |
805 | fbi->cmap_inverse = of_property_read_bool(np, "cmap-inverse"); | |
806 | fbi->cmap_static = of_property_read_bool(np, "cmap-static"); | |
807 | ||
808 | fbi->lscr1 = IMXFB_LSCR1_DEFAULT; | |
809 | of_property_read_u32(np, "fsl,lscr1", &fbi->lscr1); | |
810 | ||
811 | of_property_read_u32(np, "fsl,dmacr", &fbi->dmacr); | |
812 | ||
813 | /* These two function pointers could be used by some specific | |
814 | * platforms. */ | |
815 | fbi->lcd_power = NULL; | |
816 | fbi->backlight_power = NULL; | |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
822 | static int imxfb_of_read_mode(struct device *dev, struct device_node *np, | |
823 | struct imx_fb_videomode *imxfb_mode) | |
824 | { | |
825 | int ret; | |
826 | struct fb_videomode *of_mode = &imxfb_mode->mode; | |
827 | u32 bpp; | |
828 | u32 pcr; | |
829 | ||
830 | ret = of_property_read_string(np, "model", &of_mode->name); | |
831 | if (ret) | |
832 | of_mode->name = NULL; | |
833 | ||
834 | ret = of_get_fb_videomode(np, of_mode, OF_USE_NATIVE_MODE); | |
835 | if (ret) { | |
836 | dev_err(dev, "Failed to get videomode from DT\n"); | |
837 | return ret; | |
838 | } | |
839 | ||
840 | ret = of_property_read_u32(np, "bits-per-pixel", &bpp); | |
841 | ret |= of_property_read_u32(np, "fsl,pcr", &pcr); | |
842 | ||
843 | if (ret) { | |
844 | dev_err(dev, "Failed to read bpp and pcr from DT\n"); | |
845 | return -EINVAL; | |
846 | } | |
847 | ||
848 | if (bpp < 1 || bpp > 255) { | |
849 | dev_err(dev, "Bits per pixel have to be between 1 and 255\n"); | |
850 | return -EINVAL; | |
851 | } | |
852 | ||
853 | imxfb_mode->bpp = bpp; | |
854 | imxfb_mode->pcr = pcr; | |
7c2f891c SH |
855 | |
856 | return 0; | |
857 | } | |
858 | ||
1b6c7936 | 859 | static int imxfb_probe(struct platform_device *pdev) |
7c2f891c | 860 | { |
7c2f891c SH |
861 | struct imxfb_info *fbi; |
862 | struct fb_info *info; | |
27889273 | 863 | struct imx_fb_platform_data *pdata; |
7c2f891c | 864 | struct resource *res; |
1b6c7936 MP |
865 | struct imx_fb_videomode *m; |
866 | const struct of_device_id *of_id; | |
343684ff | 867 | int ret, i; |
1b6c7936 | 868 | int bytes_per_pixel; |
7c2f891c | 869 | |
d6b51502 | 870 | dev_info(&pdev->dev, "i.MX Framebuffer driver\n"); |
7c2f891c | 871 | |
1b6c7936 MP |
872 | of_id = of_match_device(imxfb_of_dev_id, &pdev->dev); |
873 | if (of_id) | |
874 | pdev->id_entry = of_id->data; | |
875 | ||
7c2f891c | 876 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
66c8719b | 877 | if (!res) |
7c2f891c SH |
878 | return -ENODEV; |
879 | ||
27889273 | 880 | pdata = pdev->dev.platform_data; |
7c2f891c | 881 | |
3ae5eaec | 882 | info = framebuffer_alloc(sizeof(struct imxfb_info), &pdev->dev); |
66c8719b | 883 | if (!info) |
7c2f891c SH |
884 | return -ENOMEM; |
885 | ||
886 | fbi = info->par; | |
887 | ||
3ae5eaec | 888 | platform_set_drvdata(pdev, info); |
7c2f891c | 889 | |
72330b0e | 890 | ret = imxfb_init_fbinfo(pdev); |
66c8719b | 891 | if (ret < 0) |
7c2f891c SH |
892 | goto failed_init; |
893 | ||
1b6c7936 MP |
894 | if (pdata) { |
895 | if (!fb_mode) | |
896 | fb_mode = pdata->mode[0].mode.name; | |
897 | ||
898 | fbi->mode = pdata->mode; | |
899 | fbi->num_modes = pdata->num_modes; | |
900 | } else { | |
901 | struct device_node *display_np; | |
902 | fb_mode = NULL; | |
903 | ||
904 | display_np = of_parse_phandle(pdev->dev.of_node, "display", 0); | |
905 | if (!display_np) { | |
906 | dev_err(&pdev->dev, "No display defined in devicetree\n"); | |
907 | ret = -EINVAL; | |
908 | goto failed_of_parse; | |
909 | } | |
910 | ||
911 | /* | |
912 | * imxfb does not support more modes, we choose only the native | |
913 | * mode. | |
914 | */ | |
915 | fbi->num_modes = 1; | |
916 | ||
917 | fbi->mode = devm_kzalloc(&pdev->dev, | |
918 | sizeof(struct imx_fb_videomode), GFP_KERNEL); | |
919 | if (!fbi->mode) { | |
920 | ret = -ENOMEM; | |
921 | goto failed_of_parse; | |
922 | } | |
923 | ||
924 | ret = imxfb_of_read_mode(&pdev->dev, display_np, fbi->mode); | |
925 | if (ret) | |
926 | goto failed_of_parse; | |
927 | } | |
928 | ||
929 | /* Calculate maximum bytes used per pixel. In most cases this should | |
930 | * be the same as m->bpp/8 */ | |
931 | m = &fbi->mode[0]; | |
932 | bytes_per_pixel = (m->bpp + 7) / 8; | |
933 | for (i = 0; i < fbi->num_modes; i++, m++) | |
934 | info->fix.smem_len = max_t(size_t, info->fix.smem_len, | |
935 | m->mode.xres * m->mode.yres * bytes_per_pixel); | |
936 | ||
72330b0e JB |
937 | res = request_mem_region(res->start, resource_size(res), |
938 | DRIVER_NAME); | |
7c2f891c SH |
939 | if (!res) { |
940 | ret = -EBUSY; | |
72330b0e JB |
941 | goto failed_req; |
942 | } | |
943 | ||
13aaea03 SH |
944 | fbi->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); |
945 | if (IS_ERR(fbi->clk_ipg)) { | |
946 | ret = PTR_ERR(fbi->clk_ipg); | |
947 | goto failed_getclock; | |
948 | } | |
949 | ||
950 | fbi->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); | |
951 | if (IS_ERR(fbi->clk_ahb)) { | |
952 | ret = PTR_ERR(fbi->clk_ahb); | |
953 | goto failed_getclock; | |
954 | } | |
955 | ||
956 | fbi->clk_per = devm_clk_get(&pdev->dev, "per"); | |
957 | if (IS_ERR(fbi->clk_per)) { | |
958 | ret = PTR_ERR(fbi->clk_per); | |
f909ef64 SH |
959 | goto failed_getclock; |
960 | } | |
961 | ||
72330b0e JB |
962 | fbi->regs = ioremap(res->start, resource_size(res)); |
963 | if (fbi->regs == NULL) { | |
d6b51502 | 964 | dev_err(&pdev->dev, "Cannot map frame buffer registers\n"); |
caf0a5c9 | 965 | ret = -ENOMEM; |
72330b0e | 966 | goto failed_ioremap; |
7c2f891c SH |
967 | } |
968 | ||
1b6c7936 MP |
969 | /* Seems not being used by anyone, so no support for oftree */ |
970 | if (!pdata || !pdata->fixed_screen_cpu) { | |
72330b0e JB |
971 | fbi->map_size = PAGE_ALIGN(info->fix.smem_len); |
972 | fbi->map_cpu = dma_alloc_writecombine(&pdev->dev, | |
973 | fbi->map_size, &fbi->map_dma, GFP_KERNEL); | |
974 | ||
975 | if (!fbi->map_cpu) { | |
f99c8929 | 976 | dev_err(&pdev->dev, "Failed to allocate video RAM: %d\n", ret); |
7c2f891c SH |
977 | ret = -ENOMEM; |
978 | goto failed_map; | |
979 | } | |
72330b0e JB |
980 | |
981 | info->screen_base = fbi->map_cpu; | |
982 | fbi->screen_cpu = fbi->map_cpu; | |
983 | fbi->screen_dma = fbi->map_dma; | |
984 | info->fix.smem_start = fbi->screen_dma; | |
7c2f891c SH |
985 | } else { |
986 | /* Fixed framebuffer mapping enables location of the screen in eSRAM */ | |
27889273 SH |
987 | fbi->map_cpu = pdata->fixed_screen_cpu; |
988 | fbi->map_dma = pdata->fixed_screen_dma; | |
7c2f891c SH |
989 | info->screen_base = fbi->map_cpu; |
990 | fbi->screen_cpu = fbi->map_cpu; | |
991 | fbi->screen_dma = fbi->map_dma; | |
992 | info->fix.smem_start = fbi->screen_dma; | |
993 | } | |
994 | ||
1b6c7936 | 995 | if (pdata && pdata->init) { |
c0b90a31 SH |
996 | ret = pdata->init(fbi->pdev); |
997 | if (ret) | |
998 | goto failed_platform_init; | |
999 | } | |
1000 | ||
343684ff SH |
1001 | |
1002 | INIT_LIST_HEAD(&info->modelist); | |
1b6c7936 MP |
1003 | for (i = 0; i < fbi->num_modes; i++) |
1004 | fb_add_videomode(&fbi->mode[i].mode, &info->modelist); | |
343684ff | 1005 | |
7c2f891c SH |
1006 | /* |
1007 | * This makes sure that our colour bitfield | |
1008 | * descriptors are correctly initialised. | |
1009 | */ | |
1010 | imxfb_check_var(&info->var, info); | |
1011 | ||
66c8719b | 1012 | ret = fb_alloc_cmap(&info->cmap, 1 << info->var.bits_per_pixel, 0); |
7c2f891c SH |
1013 | if (ret < 0) |
1014 | goto failed_cmap; | |
1015 | ||
7c2f891c SH |
1016 | imxfb_set_par(info); |
1017 | ret = register_framebuffer(info); | |
1018 | if (ret < 0) { | |
f99c8929 | 1019 | dev_err(&pdev->dev, "failed to register framebuffer\n"); |
7c2f891c SH |
1020 | goto failed_register; |
1021 | } | |
1022 | ||
1023 | imxfb_enable_controller(fbi); | |
7a2bb23c | 1024 | fbi->pdev = pdev; |
81ef8061 | 1025 | #ifdef PWMR_BACKLIGHT_AVAILABLE |
7a2bb23c | 1026 | imxfb_init_backlight(fbi); |
81ef8061 | 1027 | #endif |
7c2f891c SH |
1028 | |
1029 | return 0; | |
1030 | ||
1031 | failed_register: | |
1032 | fb_dealloc_cmap(&info->cmap); | |
1033 | failed_cmap: | |
1b6c7936 | 1034 | if (pdata && pdata->exit) |
c0b90a31 SH |
1035 | pdata->exit(fbi->pdev); |
1036 | failed_platform_init: | |
1b6c7936 | 1037 | if (pdata && !pdata->fixed_screen_cpu) |
3ae5eaec | 1038 | dma_free_writecombine(&pdev->dev,fbi->map_size,fbi->map_cpu, |
72330b0e | 1039 | fbi->map_dma); |
7c2f891c | 1040 | failed_map: |
72330b0e JB |
1041 | iounmap(fbi->regs); |
1042 | failed_ioremap: | |
609d3bbf | 1043 | failed_getclock: |
d6b51502 | 1044 | release_mem_region(res->start, resource_size(res)); |
72330b0e | 1045 | failed_req: |
1b6c7936 | 1046 | failed_of_parse: |
72330b0e | 1047 | kfree(info->pseudo_palette); |
7c2f891c | 1048 | failed_init: |
7c2f891c SH |
1049 | framebuffer_release(info); |
1050 | return ret; | |
1051 | } | |
1052 | ||
48c68c4f | 1053 | static int imxfb_remove(struct platform_device *pdev) |
7c2f891c | 1054 | { |
c0b90a31 | 1055 | struct imx_fb_platform_data *pdata; |
3ae5eaec | 1056 | struct fb_info *info = platform_get_drvdata(pdev); |
772a9e63 | 1057 | struct imxfb_info *fbi = info->par; |
7c2f891c SH |
1058 | struct resource *res; |
1059 | ||
1060 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1061 | ||
772a9e63 | 1062 | imxfb_disable_controller(fbi); |
7c2f891c | 1063 | |
81ef8061 | 1064 | #ifdef PWMR_BACKLIGHT_AVAILABLE |
7a2bb23c | 1065 | imxfb_exit_backlight(fbi); |
81ef8061 | 1066 | #endif |
7c2f891c SH |
1067 | unregister_framebuffer(info); |
1068 | ||
c0b90a31 | 1069 | pdata = pdev->dev.platform_data; |
1b6c7936 | 1070 | if (pdata && pdata->exit) |
c0b90a31 SH |
1071 | pdata->exit(fbi->pdev); |
1072 | ||
7c2f891c SH |
1073 | fb_dealloc_cmap(&info->cmap); |
1074 | kfree(info->pseudo_palette); | |
1075 | framebuffer_release(info); | |
1076 | ||
72330b0e | 1077 | iounmap(fbi->regs); |
d6b51502 | 1078 | release_mem_region(res->start, resource_size(res)); |
f909ef64 | 1079 | |
7c2f891c SH |
1080 | return 0; |
1081 | } | |
1082 | ||
486dd6d3 | 1083 | static void imxfb_shutdown(struct platform_device *dev) |
7c2f891c | 1084 | { |
3ae5eaec | 1085 | struct fb_info *info = platform_get_drvdata(dev); |
772a9e63 SH |
1086 | struct imxfb_info *fbi = info->par; |
1087 | imxfb_disable_controller(fbi); | |
7c2f891c SH |
1088 | } |
1089 | ||
3ae5eaec | 1090 | static struct platform_driver imxfb_driver = { |
7c2f891c SH |
1091 | .suspend = imxfb_suspend, |
1092 | .resume = imxfb_resume, | |
48c68c4f | 1093 | .remove = imxfb_remove, |
7c2f891c | 1094 | .shutdown = imxfb_shutdown, |
3ae5eaec | 1095 | .driver = { |
72330b0e | 1096 | .name = DRIVER_NAME, |
1b6c7936 | 1097 | .of_match_table = imxfb_of_dev_id, |
3ae5eaec | 1098 | }, |
e69dc9a9 | 1099 | .id_table = imxfb_devtype, |
7c2f891c SH |
1100 | }; |
1101 | ||
343684ff SH |
1102 | static int imxfb_setup(void) |
1103 | { | |
1104 | #ifndef MODULE | |
1105 | char *opt, *options = NULL; | |
1106 | ||
1107 | if (fb_get_options("imxfb", &options)) | |
1108 | return -ENODEV; | |
1109 | ||
1110 | if (!options || !*options) | |
1111 | return 0; | |
1112 | ||
1113 | while ((opt = strsep(&options, ",")) != NULL) { | |
1114 | if (!*opt) | |
1115 | continue; | |
1116 | else | |
1117 | fb_mode = opt; | |
1118 | } | |
1119 | #endif | |
1120 | return 0; | |
1121 | } | |
1122 | ||
486dd6d3 | 1123 | static int __init imxfb_init(void) |
7c2f891c | 1124 | { |
343684ff SH |
1125 | int ret = imxfb_setup(); |
1126 | ||
1127 | if (ret < 0) | |
1128 | return ret; | |
1129 | ||
72330b0e | 1130 | return platform_driver_probe(&imxfb_driver, imxfb_probe); |
7c2f891c SH |
1131 | } |
1132 | ||
1133 | static void __exit imxfb_cleanup(void) | |
1134 | { | |
3ae5eaec | 1135 | platform_driver_unregister(&imxfb_driver); |
7c2f891c SH |
1136 | } |
1137 | ||
1138 | module_init(imxfb_init); | |
1139 | module_exit(imxfb_cleanup); | |
1140 | ||
e3d5fb71 | 1141 | MODULE_DESCRIPTION("Freescale i.MX framebuffer driver"); |
7c2f891c SH |
1142 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); |
1143 | MODULE_LICENSE("GPL"); |