Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * | |
3 | * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400 | |
4 | * | |
5 | * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz> | |
6 | * | |
7 | * Portions Copyright (c) 2001 Matrox Graphics Inc. | |
8 | * | |
9 | * Version: 1.65 2002/08/14 | |
10 | * | |
11 | * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org> | |
12 | * | |
13 | * Contributors: "menion?" <menion@mindless.com> | |
14 | * Betatesting, fixes, ideas | |
15 | * | |
16 | * "Kurt Garloff" <garloff@suse.de> | |
17 | * Betatesting, fixes, ideas, videomodes, videomodes timmings | |
18 | * | |
19 | * "Tom Rini" <trini@kernel.crashing.org> | |
20 | * MTRR stuff, PPC cleanups, betatesting, fixes, ideas | |
21 | * | |
22 | * "Bibek Sahu" <scorpio@dodds.net> | |
23 | * Access device through readb|w|l and write b|w|l | |
24 | * Extensive debugging stuff | |
25 | * | |
26 | * "Daniel Haun" <haund@usa.net> | |
27 | * Testing, hardware cursor fixes | |
28 | * | |
29 | * "Scott Wood" <sawst46+@pitt.edu> | |
30 | * Fixes | |
31 | * | |
32 | * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de> | |
33 | * Betatesting | |
34 | * | |
35 | * "Kelly French" <targon@hazmat.com> | |
36 | * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es> | |
37 | * Betatesting, bug reporting | |
38 | * | |
39 | * "Pablo Bianucci" <pbian@pccp.com.ar> | |
40 | * Fixes, ideas, betatesting | |
41 | * | |
42 | * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es> | |
43 | * Fixes, enhandcements, ideas, betatesting | |
44 | * | |
45 | * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp> | |
46 | * PPC betatesting, PPC support, backward compatibility | |
47 | * | |
48 | * "Paul Womar" <Paul@pwomar.demon.co.uk> | |
49 | * "Owen Waller" <O.Waller@ee.qub.ac.uk> | |
50 | * PPC betatesting | |
51 | * | |
52 | * "Thomas Pornin" <pornin@bolet.ens.fr> | |
53 | * Alpha betatesting | |
54 | * | |
55 | * "Pieter van Leuven" <pvl@iae.nl> | |
56 | * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de> | |
57 | * G100 testing | |
58 | * | |
59 | * "H. Peter Arvin" <hpa@transmeta.com> | |
60 | * Ideas | |
61 | * | |
62 | * "Cort Dougan" <cort@cs.nmt.edu> | |
63 | * CHRP fixes and PReP cleanup | |
64 | * | |
65 | * "Mark Vojkovich" <mvojkovi@ucsd.edu> | |
66 | * G400 support | |
67 | * | |
68 | * "David C. Hansen" <haveblue@us.ibm.com> | |
69 | * Fixes | |
70 | * | |
5c06e2aa IR |
71 | * "Ian Romanick" <idr@us.ibm.com> |
72 | * Find PInS data in BIOS on PowerPC systems. | |
73 | * | |
1da177e4 LT |
74 | * (following author is not in any relation with this code, but his code |
75 | * is included in this driver) | |
76 | * | |
77 | * Based on framebuffer driver for VBE 2.0 compliant graphic boards | |
78 | * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de> | |
79 | * | |
80 | * (following author is not in any relation with this code, but his ideas | |
beb7dd86 | 81 | * were used when writing this driver) |
1da177e4 LT |
82 | * |
83 | * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk> | |
84 | * | |
85 | */ | |
86 | ||
1da177e4 LT |
87 | |
88 | #include "matroxfb_misc.h" | |
89 | #include <linux/interrupt.h> | |
90 | #include <linux/matroxfb.h> | |
91 | ||
316b4d64 JD |
92 | void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val) |
93 | { | |
5ae12170 | 94 | DBG_REG(__func__) |
1da177e4 LT |
95 | mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg); |
96 | mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val); | |
97 | } | |
98 | ||
316b4d64 JD |
99 | int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg) |
100 | { | |
5ae12170 | 101 | DBG_REG(__func__) |
1da177e4 LT |
102 | mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg); |
103 | return mga_inb(M_RAMDAC_BASE+M_X_DATAREG); | |
104 | } | |
105 | ||
106 | void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) { | |
107 | unsigned int pixclock = var->pixclock; | |
108 | ||
5ae12170 | 109 | DBG(__func__) |
1da177e4 LT |
110 | |
111 | if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */ | |
112 | mt->pixclock = 1000000000 / pixclock; | |
113 | if (mt->pixclock < 1) mt->pixclock = 1; | |
114 | mt->mnp = -1; | |
115 | mt->dblscan = var->vmode & FB_VMODE_DOUBLE; | |
116 | mt->interlaced = var->vmode & FB_VMODE_INTERLACED; | |
117 | mt->HDisplay = var->xres; | |
118 | mt->HSyncStart = mt->HDisplay + var->right_margin; | |
119 | mt->HSyncEnd = mt->HSyncStart + var->hsync_len; | |
120 | mt->HTotal = mt->HSyncEnd + var->left_margin; | |
121 | mt->VDisplay = var->yres; | |
122 | mt->VSyncStart = mt->VDisplay + var->lower_margin; | |
123 | mt->VSyncEnd = mt->VSyncStart + var->vsync_len; | |
124 | mt->VTotal = mt->VSyncEnd + var->upper_margin; | |
125 | mt->sync = var->sync; | |
126 | } | |
127 | ||
128 | int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax, | |
129 | unsigned int* in, unsigned int* feed, unsigned int* post) { | |
130 | unsigned int bestdiff = ~0; | |
131 | unsigned int bestvco = 0; | |
132 | unsigned int fxtal = pll->ref_freq; | |
133 | unsigned int fwant; | |
134 | unsigned int p; | |
135 | ||
5ae12170 | 136 | DBG(__func__) |
1da177e4 LT |
137 | |
138 | fwant = freq; | |
139 | ||
140 | #ifdef DEBUG | |
141 | printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max); | |
142 | printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); | |
143 | printk(KERN_ERR "freq: %d\n", freq); | |
144 | printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min); | |
145 | printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min); | |
146 | printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max); | |
147 | printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min); | |
148 | printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max); | |
149 | printk(KERN_ERR "fmax: %d\n", fmax); | |
150 | #endif | |
151 | for (p = 1; p <= pll->post_shift_max; p++) { | |
152 | if (fwant * 2 > fmax) | |
153 | break; | |
154 | fwant *= 2; | |
155 | } | |
156 | if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min; | |
157 | if (fwant > fmax) fwant = fmax; | |
158 | for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) { | |
159 | unsigned int m; | |
160 | ||
161 | if (fwant < pll->vco_freq_min) break; | |
162 | for (m = pll->in_div_min; m <= pll->in_div_max; m++) { | |
163 | unsigned int diff, fvco; | |
164 | unsigned int n; | |
165 | ||
166 | n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1; | |
167 | if (n > pll->feed_div_max) | |
168 | break; | |
169 | if (n < pll->feed_div_min) | |
170 | n = pll->feed_div_min; | |
171 | fvco = (fxtal * (n + 1)) / (m + 1); | |
172 | if (fvco < fwant) | |
173 | diff = fwant - fvco; | |
174 | else | |
175 | diff = fvco - fwant; | |
176 | if (diff < bestdiff) { | |
177 | bestdiff = diff; | |
178 | *post = p; | |
179 | *in = m; | |
180 | *feed = n; | |
181 | bestvco = fvco; | |
182 | } | |
183 | } | |
184 | } | |
185 | dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant); | |
186 | return bestvco; | |
187 | } | |
188 | ||
316b4d64 JD |
189 | int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m) |
190 | { | |
1da177e4 LT |
191 | unsigned int hd, hs, he, hbe, ht; |
192 | unsigned int vd, vs, ve, vt, lc; | |
193 | unsigned int wd; | |
194 | unsigned int divider; | |
195 | int i; | |
fc2d10dd | 196 | struct matrox_hw_state * const hw = &minfo->hw; |
1da177e4 | 197 | |
5ae12170 | 198 | DBG(__func__) |
1da177e4 LT |
199 | |
200 | hw->SEQ[0] = 0x00; | |
67da54cf | 201 | hw->SEQ[1] = 0x01; /* or 0x09 */ |
1da177e4 LT |
202 | hw->SEQ[2] = 0x0F; /* bitplanes */ |
203 | hw->SEQ[3] = 0x00; | |
204 | hw->SEQ[4] = 0x0E; | |
205 | /* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */ | |
206 | if (m->dblscan) { | |
207 | m->VTotal <<= 1; | |
208 | m->VDisplay <<= 1; | |
209 | m->VSyncStart <<= 1; | |
210 | m->VSyncEnd <<= 1; | |
211 | } | |
212 | if (m->interlaced) { | |
213 | m->VTotal >>= 1; | |
214 | m->VDisplay >>= 1; | |
215 | m->VSyncStart >>= 1; | |
216 | m->VSyncEnd >>= 1; | |
217 | } | |
218 | ||
219 | /* GCTL is ignored when not using 0xA0000 aperture */ | |
220 | hw->GCTL[0] = 0x00; | |
221 | hw->GCTL[1] = 0x00; | |
222 | hw->GCTL[2] = 0x00; | |
223 | hw->GCTL[3] = 0x00; | |
224 | hw->GCTL[4] = 0x00; | |
225 | hw->GCTL[5] = 0x40; | |
226 | hw->GCTL[6] = 0x05; | |
227 | hw->GCTL[7] = 0x0F; | |
228 | hw->GCTL[8] = 0xFF; | |
229 | ||
230 | /* Whole ATTR is ignored in PowerGraphics mode */ | |
231 | for (i = 0; i < 16; i++) | |
232 | hw->ATTR[i] = i; | |
233 | hw->ATTR[16] = 0x41; | |
234 | hw->ATTR[17] = 0xFF; | |
235 | hw->ATTR[18] = 0x0F; | |
51d53bd3 | 236 | hw->ATTR[19] = 0x00; |
1da177e4 LT |
237 | hw->ATTR[20] = 0x00; |
238 | ||
239 | hd = m->HDisplay >> 3; | |
240 | hs = m->HSyncStart >> 3; | |
241 | he = m->HSyncEnd >> 3; | |
242 | ht = m->HTotal >> 3; | |
243 | /* standard timmings are in 8pixels, but for interleaved we cannot */ | |
244 | /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */ | |
245 | /* using 16 or more pixels per unit can save us */ | |
fc2d10dd | 246 | divider = minfo->curr.final_bppShift; |
1da177e4 LT |
247 | while (divider & 3) { |
248 | hd >>= 1; | |
249 | hs >>= 1; | |
250 | he >>= 1; | |
251 | ht >>= 1; | |
252 | divider <<= 1; | |
253 | } | |
254 | divider = divider / 4; | |
255 | /* divider can be from 1 to 8 */ | |
256 | while (divider > 8) { | |
257 | hd <<= 1; | |
258 | hs <<= 1; | |
259 | he <<= 1; | |
260 | ht <<= 1; | |
261 | divider >>= 1; | |
262 | } | |
263 | hd = hd - 1; | |
264 | hs = hs - 1; | |
265 | he = he - 1; | |
266 | ht = ht - 1; | |
267 | vd = m->VDisplay - 1; | |
268 | vs = m->VSyncStart - 1; | |
269 | ve = m->VSyncEnd - 1; | |
270 | vt = m->VTotal - 2; | |
271 | lc = vd; | |
272 | /* G200 cannot work with (ht & 7) == 6 */ | |
273 | if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04)) | |
274 | ht++; | |
275 | hbe = ht; | |
fc2d10dd | 276 | wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64; |
1da177e4 LT |
277 | |
278 | hw->CRTCEXT[0] = 0; | |
279 | hw->CRTCEXT[5] = 0; | |
280 | if (m->interlaced) { | |
281 | hw->CRTCEXT[0] = 0x80; | |
282 | hw->CRTCEXT[5] = (hs + he - ht) >> 1; | |
283 | if (!m->dblscan) | |
284 | wd <<= 1; | |
285 | vt &= ~1; | |
286 | } | |
287 | hw->CRTCEXT[0] |= (wd & 0x300) >> 4; | |
288 | hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) | | |
289 | ((hd & 0x100) >> 7) | /* blanking */ | |
290 | ((hs & 0x100) >> 6) | /* sync start */ | |
291 | (hbe & 0x040); /* end hor. blanking */ | |
292 | /* FIXME: Enable vidrst only on G400, and only if TV-out is used */ | |
fc2d10dd | 293 | if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) |
1da177e4 LT |
294 | hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */ |
295 | hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) | | |
296 | ((vd & 0x400) >> 8) | /* disp end */ | |
297 | ((vd & 0xC00) >> 7) | /* vblanking start */ | |
298 | ((vs & 0xC00) >> 5) | | |
299 | ((lc & 0x400) >> 3); | |
300 | hw->CRTCEXT[3] = (divider - 1) | 0x80; | |
301 | hw->CRTCEXT[4] = 0; | |
302 | ||
303 | hw->CRTC[0] = ht-4; | |
304 | hw->CRTC[1] = hd; | |
305 | hw->CRTC[2] = hd; | |
306 | hw->CRTC[3] = (hbe & 0x1F) | 0x80; | |
307 | hw->CRTC[4] = hs; | |
308 | hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F); | |
309 | hw->CRTC[6] = vt & 0xFF; | |
310 | hw->CRTC[7] = ((vt & 0x100) >> 8) | | |
311 | ((vd & 0x100) >> 7) | | |
312 | ((vs & 0x100) >> 6) | | |
313 | ((vd & 0x100) >> 5) | | |
314 | ((lc & 0x100) >> 4) | | |
315 | ((vt & 0x200) >> 4) | | |
316 | ((vd & 0x200) >> 3) | | |
317 | ((vs & 0x200) >> 2); | |
318 | hw->CRTC[8] = 0x00; | |
319 | hw->CRTC[9] = ((vd & 0x200) >> 4) | | |
320 | ((lc & 0x200) >> 3); | |
321 | if (m->dblscan && !m->interlaced) | |
322 | hw->CRTC[9] |= 0x80; | |
323 | for (i = 10; i < 16; i++) | |
324 | hw->CRTC[i] = 0x00; | |
325 | hw->CRTC[16] = vs /* & 0xFF */; | |
326 | hw->CRTC[17] = (ve & 0x0F) | 0x20; | |
327 | hw->CRTC[18] = vd /* & 0xFF */; | |
328 | hw->CRTC[19] = wd /* & 0xFF */; | |
329 | hw->CRTC[20] = 0x00; | |
330 | hw->CRTC[21] = vd /* & 0xFF */; | |
331 | hw->CRTC[22] = (vt + 1) /* & 0xFF */; | |
332 | hw->CRTC[23] = 0xC3; | |
333 | hw->CRTC[24] = lc; | |
334 | return 0; | |
335 | }; | |
336 | ||
316b4d64 JD |
337 | void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo) |
338 | { | |
1da177e4 | 339 | int i; |
fc2d10dd | 340 | struct matrox_hw_state * const hw = &minfo->hw; |
1da177e4 LT |
341 | CRITFLAGS |
342 | ||
5ae12170 | 343 | DBG(__func__) |
1da177e4 LT |
344 | |
345 | dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg); | |
346 | dprintk(KERN_INFO "SEQ regs: "); | |
347 | for (i = 0; i < 5; i++) | |
348 | dprintk("%02X:", hw->SEQ[i]); | |
349 | dprintk("\n"); | |
350 | dprintk(KERN_INFO "GDC regs: "); | |
351 | for (i = 0; i < 9; i++) | |
352 | dprintk("%02X:", hw->GCTL[i]); | |
353 | dprintk("\n"); | |
354 | dprintk(KERN_INFO "CRTC regs: "); | |
355 | for (i = 0; i < 25; i++) | |
356 | dprintk("%02X:", hw->CRTC[i]); | |
357 | dprintk("\n"); | |
358 | dprintk(KERN_INFO "ATTR regs: "); | |
359 | for (i = 0; i < 21; i++) | |
360 | dprintk("%02X:", hw->ATTR[i]); | |
361 | dprintk("\n"); | |
362 | ||
363 | CRITBEGIN | |
364 | ||
365 | mga_inb(M_ATTR_RESET); | |
366 | mga_outb(M_ATTR_INDEX, 0); | |
367 | mga_outb(M_MISC_REG, hw->MiscOutReg); | |
368 | for (i = 1; i < 5; i++) | |
369 | mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]); | |
370 | mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F); | |
371 | for (i = 0; i < 25; i++) | |
372 | mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]); | |
373 | for (i = 0; i < 9; i++) | |
374 | mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]); | |
375 | for (i = 0; i < 21; i++) { | |
376 | mga_inb(M_ATTR_RESET); | |
377 | mga_outb(M_ATTR_INDEX, i); | |
378 | mga_outb(M_ATTR_INDEX, hw->ATTR[i]); | |
379 | } | |
380 | mga_outb(M_PALETTE_MASK, 0xFF); | |
381 | mga_outb(M_DAC_REG, 0x00); | |
382 | for (i = 0; i < 768; i++) | |
383 | mga_outb(M_DAC_VAL, hw->DACpal[i]); | |
384 | mga_inb(M_ATTR_RESET); | |
385 | mga_outb(M_ATTR_INDEX, 0x20); | |
386 | ||
387 | CRITEND | |
388 | } | |
389 | ||
390 | static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) { | |
391 | unsigned int b0 = readb(pins); | |
392 | ||
393 | if (b0 == 0x2E && readb(pins+1) == 0x41) { | |
394 | unsigned int pins_len = readb(pins+2); | |
395 | unsigned int i; | |
396 | unsigned char cksum; | |
397 | unsigned char* dst = bd->pins; | |
398 | ||
399 | if (pins_len < 3 || pins_len > 128) { | |
400 | return; | |
401 | } | |
402 | *dst++ = 0x2E; | |
403 | *dst++ = 0x41; | |
404 | *dst++ = pins_len; | |
405 | cksum = 0x2E + 0x41 + pins_len; | |
406 | for (i = 3; i < pins_len; i++) { | |
407 | cksum += *dst++ = readb(pins+i); | |
408 | } | |
409 | if (cksum) { | |
410 | return; | |
411 | } | |
412 | bd->pins_len = pins_len; | |
413 | } else if (b0 == 0x40 && readb(pins+1) == 0x00) { | |
414 | unsigned int i; | |
415 | unsigned char* dst = bd->pins; | |
416 | ||
417 | *dst++ = 0x40; | |
418 | *dst++ = 0; | |
419 | for (i = 2; i < 0x40; i++) { | |
420 | *dst++ = readb(pins+i); | |
421 | } | |
422 | bd->pins_len = 0x40; | |
423 | } | |
424 | } | |
425 | ||
426 | static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) { | |
427 | unsigned int pcir_offset; | |
428 | ||
429 | pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8); | |
430 | if (pcir_offset >= 26 && pcir_offset < 0xFFE0 && | |
431 | readb(vbios + pcir_offset ) == 'P' && | |
432 | readb(vbios + pcir_offset + 1) == 'C' && | |
433 | readb(vbios + pcir_offset + 2) == 'I' && | |
434 | readb(vbios + pcir_offset + 3) == 'R') { | |
435 | unsigned char h; | |
436 | ||
437 | h = readb(vbios + pcir_offset + 0x12); | |
438 | bd->version.vMaj = (h >> 4) & 0xF; | |
439 | bd->version.vMin = h & 0xF; | |
440 | bd->version.vRev = readb(vbios + pcir_offset + 0x13); | |
441 | } else { | |
442 | unsigned char h; | |
443 | ||
444 | h = readb(vbios + 5); | |
445 | bd->version.vMaj = (h >> 4) & 0xF; | |
446 | bd->version.vMin = h & 0xF; | |
447 | bd->version.vRev = 0; | |
448 | } | |
449 | } | |
450 | ||
451 | static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) { | |
452 | unsigned char b; | |
453 | ||
454 | b = readb(vbios + 0x7FF1); | |
455 | if (b == 0xFF) { | |
456 | b = 0; | |
457 | } | |
458 | bd->output.state = b; | |
459 | } | |
460 | ||
461 | static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) { | |
462 | unsigned int i; | |
463 | ||
464 | /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */ | |
465 | bd->output.tvout = 0; | |
466 | if (readb(vbios + 0x1D) != 'I' || | |
467 | readb(vbios + 0x1E) != 'B' || | |
468 | readb(vbios + 0x1F) != 'M' || | |
469 | readb(vbios + 0x20) != ' ') { | |
470 | return; | |
471 | } | |
472 | for (i = 0x2D; i < 0x2D + 128; i++) { | |
473 | unsigned char b = readb(vbios + i); | |
474 | ||
475 | if (b == '(' && readb(vbios + i + 1) == 'V') { | |
476 | if (readb(vbios + i + 6) == 'T' && | |
477 | readb(vbios + i + 7) == 'V' && | |
478 | readb(vbios + i + 8) == 'O') { | |
479 | bd->output.tvout = 1; | |
480 | } | |
481 | return; | |
482 | } | |
483 | if (b == 0) | |
484 | break; | |
485 | } | |
486 | } | |
487 | ||
488 | static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) { | |
489 | unsigned int pins_offset; | |
490 | ||
491 | if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) { | |
492 | return; | |
493 | } | |
494 | bd->bios_valid = 1; | |
495 | get_bios_version(vbios, bd); | |
496 | get_bios_output(vbios, bd); | |
497 | get_bios_tvout(vbios, bd); | |
5c06e2aa IR |
498 | #if defined(__powerpc__) |
499 | /* On PowerPC cards, the PInS offset isn't stored at the end of the | |
500 | * BIOS image. Instead, you must search the entire BIOS image for | |
501 | * the magic PInS signature. | |
502 | * | |
503 | * This actually applies to all OpenFirmware base cards. Since these | |
504 | * cards could be put in a MIPS or SPARC system, should the condition | |
505 | * be something different? | |
506 | */ | |
507 | for ( pins_offset = 0 ; pins_offset <= 0xFF80 ; pins_offset++ ) { | |
508 | unsigned char header[3]; | |
509 | ||
510 | header[0] = readb(vbios + pins_offset); | |
511 | header[1] = readb(vbios + pins_offset + 1); | |
512 | header[2] = readb(vbios + pins_offset + 2); | |
513 | if ( (header[0] == 0x2E) && (header[1] == 0x41) | |
514 | && ((header[2] == 0x40) || (header[2] == 0x80)) ) { | |
515 | printk(KERN_INFO "PInS data found at offset %u\n", | |
516 | pins_offset); | |
517 | get_pins(vbios + pins_offset, bd); | |
518 | break; | |
519 | } | |
520 | } | |
521 | #else | |
1da177e4 LT |
522 | pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8); |
523 | if (pins_offset <= 0xFF80) { | |
524 | get_pins(vbios + pins_offset, bd); | |
525 | } | |
5c06e2aa | 526 | #endif |
1da177e4 LT |
527 | } |
528 | ||
316b4d64 JD |
529 | static int parse_pins1(struct matrox_fb_info *minfo, |
530 | const struct matrox_bios *bd) | |
531 | { | |
1da177e4 LT |
532 | unsigned int maxdac; |
533 | ||
534 | switch (bd->pins[22]) { | |
535 | case 0: maxdac = 175000; break; | |
536 | case 1: maxdac = 220000; break; | |
537 | default: maxdac = 240000; break; | |
538 | } | |
d15c0a4d HH |
539 | if (get_unaligned_le16(bd->pins + 24)) { |
540 | maxdac = get_unaligned_le16(bd->pins + 24) * 10; | |
1da177e4 | 541 | } |
fc2d10dd JD |
542 | minfo->limits.pixel.vcomax = maxdac; |
543 | minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ? | |
d15c0a4d | 544 | get_unaligned_le16(bd->pins + 28) * 10 : 50000; |
1da177e4 | 545 | /* ignore 4MB, 8MB, module clocks */ |
fc2d10dd JD |
546 | minfo->features.pll.ref_freq = 14318; |
547 | minfo->values.reg.mctlwtst = 0x00030101; | |
1da177e4 LT |
548 | return 0; |
549 | } | |
550 | ||
316b4d64 JD |
551 | static void default_pins1(struct matrox_fb_info *minfo) |
552 | { | |
1da177e4 | 553 | /* Millennium */ |
fc2d10dd JD |
554 | minfo->limits.pixel.vcomax = 220000; |
555 | minfo->values.pll.system = 50000; | |
556 | minfo->features.pll.ref_freq = 14318; | |
557 | minfo->values.reg.mctlwtst = 0x00030101; | |
1da177e4 LT |
558 | } |
559 | ||
316b4d64 JD |
560 | static int parse_pins2(struct matrox_fb_info *minfo, |
561 | const struct matrox_bios *bd) | |
562 | { | |
fc2d10dd JD |
563 | minfo->limits.pixel.vcomax = |
564 | minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000); | |
565 | minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) | | |
1da177e4 LT |
566 | ((bd->pins[51] & 0x02) ? 0x00000100 : 0) | |
567 | ((bd->pins[51] & 0x04) ? 0x00010000 : 0) | | |
568 | ((bd->pins[51] & 0x08) ? 0x00020000 : 0); | |
fc2d10dd JD |
569 | minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000); |
570 | minfo->features.pll.ref_freq = 14318; | |
1da177e4 LT |
571 | return 0; |
572 | } | |
573 | ||
316b4d64 JD |
574 | static void default_pins2(struct matrox_fb_info *minfo) |
575 | { | |
1da177e4 | 576 | /* Millennium II, Mystique */ |
fc2d10dd JD |
577 | minfo->limits.pixel.vcomax = |
578 | minfo->limits.system.vcomax = 230000; | |
579 | minfo->values.reg.mctlwtst = 0x00030101; | |
580 | minfo->values.pll.system = 50000; | |
581 | minfo->features.pll.ref_freq = 14318; | |
1da177e4 LT |
582 | } |
583 | ||
316b4d64 JD |
584 | static int parse_pins3(struct matrox_fb_info *minfo, |
585 | const struct matrox_bios *bd) | |
586 | { | |
fc2d10dd JD |
587 | minfo->limits.pixel.vcomax = |
588 | minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000); | |
589 | minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ? | |
d15c0a4d | 590 | 0x01250A21 : get_unaligned_le32(bd->pins + 48); |
1da177e4 | 591 | /* memory config */ |
fc2d10dd | 592 | minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) | |
1da177e4 LT |
593 | ((bd->pins[57] << 22) & 0x00C00000) | |
594 | ((bd->pins[56] << 1) & 0x000001E0) | | |
595 | ( bd->pins[56] & 0x0000000F); | |
fc2d10dd JD |
596 | minfo->values.reg.opt = (bd->pins[54] & 7) << 10; |
597 | minfo->values.reg.opt2 = bd->pins[58] << 12; | |
598 | minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000; | |
1da177e4 LT |
599 | return 0; |
600 | } | |
601 | ||
316b4d64 JD |
602 | static void default_pins3(struct matrox_fb_info *minfo) |
603 | { | |
1da177e4 | 604 | /* G100, G200 */ |
fc2d10dd JD |
605 | minfo->limits.pixel.vcomax = |
606 | minfo->limits.system.vcomax = 230000; | |
607 | minfo->values.reg.mctlwtst = 0x01250A21; | |
608 | minfo->values.reg.memrdbk = 0x00000000; | |
609 | minfo->values.reg.opt = 0x00000C00; | |
610 | minfo->values.reg.opt2 = 0x00000000; | |
611 | minfo->features.pll.ref_freq = 27000; | |
1da177e4 LT |
612 | } |
613 | ||
316b4d64 JD |
614 | static int parse_pins4(struct matrox_fb_info *minfo, |
615 | const struct matrox_bios *bd) | |
616 | { | |
fc2d10dd JD |
617 | minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000; |
618 | minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000; | |
619 | minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71); | |
620 | minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) | | |
1da177e4 LT |
621 | ((bd->pins[87] << 22) & 0x00C00000) | |
622 | ((bd->pins[86] << 1) & 0x000001E0) | | |
623 | ( bd->pins[86] & 0x0000000F); | |
fc2d10dd | 624 | minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) | |
1da177e4 LT |
625 | ((bd->pins[53] << 22) & 0x10000000) | |
626 | ((bd->pins[53] << 7) & 0x00001C00); | |
fc2d10dd JD |
627 | minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67); |
628 | minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000; | |
629 | minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000; | |
1da177e4 LT |
630 | return 0; |
631 | } | |
632 | ||
316b4d64 JD |
633 | static void default_pins4(struct matrox_fb_info *minfo) |
634 | { | |
1da177e4 | 635 | /* G400 */ |
fc2d10dd JD |
636 | minfo->limits.pixel.vcomax = |
637 | minfo->limits.system.vcomax = 252000; | |
638 | minfo->values.reg.mctlwtst = 0x04A450A1; | |
639 | minfo->values.reg.memrdbk = 0x000000E7; | |
640 | minfo->values.reg.opt = 0x10000400; | |
641 | minfo->values.reg.opt3 = 0x0190A419; | |
642 | minfo->values.pll.system = 200000; | |
643 | minfo->features.pll.ref_freq = 27000; | |
1da177e4 LT |
644 | } |
645 | ||
316b4d64 JD |
646 | static int parse_pins5(struct matrox_fb_info *minfo, |
647 | const struct matrox_bios *bd) | |
648 | { | |
1da177e4 LT |
649 | unsigned int mult; |
650 | ||
651 | mult = bd->pins[4]?8000:6000; | |
652 | ||
fc2d10dd JD |
653 | minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult; |
654 | minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult; | |
655 | minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult; | |
656 | minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult; | |
657 | minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult; | |
658 | minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult; | |
659 | minfo->values.pll.system = | |
660 | minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000; | |
661 | minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48); | |
662 | minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52); | |
663 | minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94); | |
664 | minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98); | |
665 | minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102); | |
666 | minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106); | |
667 | minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000; | |
668 | minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20; | |
669 | minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0; | |
670 | minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0; | |
671 | minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000; | |
1da177e4 | 672 | if (bd->pins[115] & 4) { |
fc2d10dd | 673 | minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst; |
1da177e4 LT |
674 | } else { |
675 | u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 }; | |
fc2d10dd JD |
676 | minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) | |
677 | wtst_xlat[minfo->values.reg.mctlwtst & 7]; | |
1da177e4 | 678 | } |
fc2d10dd | 679 | minfo->max_pixel_clock_panellink = bd->pins[47] * 4000; |
1da177e4 LT |
680 | return 0; |
681 | } | |
682 | ||
316b4d64 JD |
683 | static void default_pins5(struct matrox_fb_info *minfo) |
684 | { | |
1da177e4 | 685 | /* Mine 16MB G450 with SDRAM DDR */ |
fc2d10dd JD |
686 | minfo->limits.pixel.vcomax = |
687 | minfo->limits.system.vcomax = | |
688 | minfo->limits.video.vcomax = 600000; | |
689 | minfo->limits.pixel.vcomin = | |
690 | minfo->limits.system.vcomin = | |
691 | minfo->limits.video.vcomin = 256000; | |
692 | minfo->values.pll.system = | |
693 | minfo->values.pll.video = 284000; | |
694 | minfo->values.reg.opt = 0x404A1160; | |
695 | minfo->values.reg.opt2 = 0x0000AC00; | |
696 | minfo->values.reg.opt3 = 0x0090A409; | |
697 | minfo->values.reg.mctlwtst_core = | |
698 | minfo->values.reg.mctlwtst = 0x0C81462B; | |
699 | minfo->values.reg.memmisc = 0x80000004; | |
700 | minfo->values.reg.memrdbk = 0x01001103; | |
701 | minfo->features.pll.ref_freq = 27000; | |
702 | minfo->values.memory.ddr = 1; | |
703 | minfo->values.memory.dll = 1; | |
704 | minfo->values.memory.emrswen = 1; | |
705 | minfo->values.reg.maccess = 0x00004000; | |
1da177e4 LT |
706 | } |
707 | ||
316b4d64 JD |
708 | static int matroxfb_set_limits(struct matrox_fb_info *minfo, |
709 | const struct matrox_bios *bd) | |
710 | { | |
1da177e4 LT |
711 | unsigned int pins_version; |
712 | static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 }; | |
713 | ||
fc2d10dd | 714 | switch (minfo->chip) { |
316b4d64 | 715 | case MGA_2064: default_pins1(minfo); break; |
1da177e4 LT |
716 | case MGA_2164: |
717 | case MGA_1064: | |
316b4d64 | 718 | case MGA_1164: default_pins2(minfo); break; |
1da177e4 | 719 | case MGA_G100: |
316b4d64 JD |
720 | case MGA_G200: default_pins3(minfo); break; |
721 | case MGA_G400: default_pins4(minfo); break; | |
1da177e4 | 722 | case MGA_G450: |
316b4d64 | 723 | case MGA_G550: default_pins5(minfo); break; |
1da177e4 LT |
724 | } |
725 | if (!bd->bios_valid) { | |
726 | printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n"); | |
727 | return -1; | |
728 | } | |
729 | if (bd->pins_len < 64) { | |
730 | printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n"); | |
731 | return -1; | |
732 | } | |
733 | if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) { | |
734 | pins_version = bd->pins[5]; | |
735 | if (pins_version < 2 || pins_version > 5) { | |
736 | printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version); | |
737 | return -1; | |
738 | } | |
739 | } else { | |
740 | pins_version = 1; | |
741 | } | |
742 | if (bd->pins_len != pinslen[pins_version - 1]) { | |
743 | printk(KERN_INFO "matroxfb: Invalid powerup info\n"); | |
744 | return -1; | |
745 | } | |
746 | switch (pins_version) { | |
747 | case 1: | |
316b4d64 | 748 | return parse_pins1(minfo, bd); |
1da177e4 | 749 | case 2: |
316b4d64 | 750 | return parse_pins2(minfo, bd); |
1da177e4 | 751 | case 3: |
316b4d64 | 752 | return parse_pins3(minfo, bd); |
1da177e4 | 753 | case 4: |
316b4d64 | 754 | return parse_pins4(minfo, bd); |
1da177e4 | 755 | case 5: |
316b4d64 | 756 | return parse_pins5(minfo, bd); |
1da177e4 LT |
757 | default: |
758 | printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version); | |
759 | return -1; | |
760 | } | |
761 | } | |
762 | ||
316b4d64 JD |
763 | void matroxfb_read_pins(struct matrox_fb_info *minfo) |
764 | { | |
1da177e4 LT |
765 | u32 opt; |
766 | u32 biosbase; | |
767 | u32 fbbase; | |
fc2d10dd | 768 | struct pci_dev *pdev = minfo->pcidev; |
1da177e4 | 769 | |
fc2d10dd | 770 | memset(&minfo->bios, 0, sizeof(minfo->bios)); |
1da177e4 LT |
771 | pci_read_config_dword(pdev, PCI_OPTION_REG, &opt); |
772 | pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM); | |
773 | pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase); | |
fc2d10dd | 774 | pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase); |
1da177e4 | 775 | pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE); |
fc2d10dd | 776 | parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios); |
1da177e4 LT |
777 | pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase); |
778 | pci_write_config_dword(pdev, PCI_OPTION_REG, opt); | |
779 | #ifdef CONFIG_X86 | |
fc2d10dd | 780 | if (!minfo->bios.bios_valid) { |
1da177e4 LT |
781 | unsigned char __iomem* b; |
782 | ||
783 | b = ioremap(0x000C0000, 65536); | |
784 | if (!b) { | |
785 | printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n"); | |
786 | } else { | |
787 | unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8); | |
788 | unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8); | |
789 | ||
790 | if (ven != pdev->vendor || dev != pdev->device) { | |
791 | printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n", | |
792 | ven, dev, pdev->vendor, pdev->device); | |
793 | } else { | |
fc2d10dd | 794 | parse_bios(b, &minfo->bios); |
1da177e4 LT |
795 | } |
796 | iounmap(b); | |
797 | } | |
798 | } | |
799 | #endif | |
316b4d64 | 800 | matroxfb_set_limits(minfo, &minfo->bios); |
5c06e2aa | 801 | printk(KERN_INFO "PInS memtype = %u\n", |
fc2d10dd | 802 | (minfo->values.reg.opt & 0x1C00) >> 10); |
1da177e4 LT |
803 | } |
804 | ||
805 | EXPORT_SYMBOL(matroxfb_DAC_in); | |
806 | EXPORT_SYMBOL(matroxfb_DAC_out); | |
807 | EXPORT_SYMBOL(matroxfb_var2my); | |
808 | EXPORT_SYMBOL(matroxfb_PLL_calcclock); | |
1da177e4 LT |
809 | EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */ |
810 | EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */ | |
811 | EXPORT_SYMBOL(matroxfb_read_pins); | |
812 | ||
813 | MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>"); | |
814 | MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards"); | |
815 | MODULE_LICENSE("GPL"); |