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Merge branch 'pstore' of git://git.kernel.org/pub/scm/linux/kernel/git/aegl/linux
[deliverable/linux.git] / drivers / video / mx3fb.c
CommitLineData
86528da2
GL		 1/*
2 * Copyright (C) 2008
3 * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
4 *
5 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/platform_device.h>
15#include <linux/sched.h>
16#include <linux/errno.h>
17#include <linux/string.h>
18#include <linux/interrupt.h>
19#include <linux/slab.h>
20#include <linux/fb.h>
21#include <linux/delay.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/dma-mapping.h>
25#include <linux/dmaengine.h>
26#include <linux/console.h>
27#include <linux/clk.h>
28#include <linux/mutex.h>
29
1b346af2 30#include <mach/dma.h>
86528da2
GL		 31#include <mach/hardware.h>
32#include <mach/ipu.h>
33#include <mach/mx3fb.h>
34
35#include <asm/io.h>
36#include <asm/uaccess.h>
37
6e1588cb 38#define MX3FB_NAME "mx3_sdc_fb"
86528da2 39
6e1588cb 40#define MX3FB_REG_OFFSET 0xB4
86528da2
GL		 41
42/* SDC Registers */
6e1588cb
GL		 43#define SDC_COM_CONF (0xB4 - MX3FB_REG_OFFSET)
44#define SDC_GW_CTRL (0xB8 - MX3FB_REG_OFFSET)
45#define SDC_FG_POS (0xBC - MX3FB_REG_OFFSET)
46#define SDC_BG_POS (0xC0 - MX3FB_REG_OFFSET)
47#define SDC_CUR_POS (0xC4 - MX3FB_REG_OFFSET)
48#define SDC_PWM_CTRL (0xC8 - MX3FB_REG_OFFSET)
49#define SDC_CUR_MAP (0xCC - MX3FB_REG_OFFSET)
50#define SDC_HOR_CONF (0xD0 - MX3FB_REG_OFFSET)
51#define SDC_VER_CONF (0xD4 - MX3FB_REG_OFFSET)
52#define SDC_SHARP_CONF_1 (0xD8 - MX3FB_REG_OFFSET)
53#define SDC_SHARP_CONF_2 (0xDC - MX3FB_REG_OFFSET)
86528da2
GL		 54
55/* Register bits */
6e1588cb
GL		 56#define SDC_COM_TFT_COLOR 0x00000001UL
57#define SDC_COM_FG_EN 0x00000010UL
58#define SDC_COM_GWSEL 0x00000020UL
59#define SDC_COM_GLB_A 0x00000040UL
60#define SDC_COM_KEY_COLOR_G 0x00000080UL
61#define SDC_COM_BG_EN 0x00000200UL
62#define SDC_COM_SHARP 0x00001000UL
86528da2 63
6e1588cb 64#define SDC_V_SYNC_WIDTH_L 0x00000001UL
86528da2
GL		 65
66/* Display Interface registers */
6e1588cb
GL		 67#define DI_DISP_IF_CONF (0x0124 - MX3FB_REG_OFFSET)
68#define DI_DISP_SIG_POL (0x0128 - MX3FB_REG_OFFSET)
69#define DI_SER_DISP1_CONF (0x012C - MX3FB_REG_OFFSET)
70#define DI_SER_DISP2_CONF (0x0130 - MX3FB_REG_OFFSET)
71#define DI_HSP_CLK_PER (0x0134 - MX3FB_REG_OFFSET)
72#define DI_DISP0_TIME_CONF_1 (0x0138 - MX3FB_REG_OFFSET)
73#define DI_DISP0_TIME_CONF_2 (0x013C - MX3FB_REG_OFFSET)
74#define DI_DISP0_TIME_CONF_3 (0x0140 - MX3FB_REG_OFFSET)
75#define DI_DISP1_TIME_CONF_1 (0x0144 - MX3FB_REG_OFFSET)
76#define DI_DISP1_TIME_CONF_2 (0x0148 - MX3FB_REG_OFFSET)
77#define DI_DISP1_TIME_CONF_3 (0x014C - MX3FB_REG_OFFSET)
78#define DI_DISP2_TIME_CONF_1 (0x0150 - MX3FB_REG_OFFSET)
79#define DI_DISP2_TIME_CONF_2 (0x0154 - MX3FB_REG_OFFSET)
80#define DI_DISP2_TIME_CONF_3 (0x0158 - MX3FB_REG_OFFSET)
81#define DI_DISP3_TIME_CONF (0x015C - MX3FB_REG_OFFSET)
82#define DI_DISP0_DB0_MAP (0x0160 - MX3FB_REG_OFFSET)
83#define DI_DISP0_DB1_MAP (0x0164 - MX3FB_REG_OFFSET)
84#define DI_DISP0_DB2_MAP (0x0168 - MX3FB_REG_OFFSET)
85#define DI_DISP0_CB0_MAP (0x016C - MX3FB_REG_OFFSET)
86#define DI_DISP0_CB1_MAP (0x0170 - MX3FB_REG_OFFSET)
87#define DI_DISP0_CB2_MAP (0x0174 - MX3FB_REG_OFFSET)
88#define DI_DISP1_DB0_MAP (0x0178 - MX3FB_REG_OFFSET)
89#define DI_DISP1_DB1_MAP (0x017C - MX3FB_REG_OFFSET)
90#define DI_DISP1_DB2_MAP (0x0180 - MX3FB_REG_OFFSET)
91#define DI_DISP1_CB0_MAP (0x0184 - MX3FB_REG_OFFSET)
92#define DI_DISP1_CB1_MAP (0x0188 - MX3FB_REG_OFFSET)
93#define DI_DISP1_CB2_MAP (0x018C - MX3FB_REG_OFFSET)
94#define DI_DISP2_DB0_MAP (0x0190 - MX3FB_REG_OFFSET)
95#define DI_DISP2_DB1_MAP (0x0194 - MX3FB_REG_OFFSET)
96#define DI_DISP2_DB2_MAP (0x0198 - MX3FB_REG_OFFSET)
97#define DI_DISP2_CB0_MAP (0x019C - MX3FB_REG_OFFSET)
98#define DI_DISP2_CB1_MAP (0x01A0 - MX3FB_REG_OFFSET)
99#define DI_DISP2_CB2_MAP (0x01A4 - MX3FB_REG_OFFSET)
100#define DI_DISP3_B0_MAP (0x01A8 - MX3FB_REG_OFFSET)
101#define DI_DISP3_B1_MAP (0x01AC - MX3FB_REG_OFFSET)
102#define DI_DISP3_B2_MAP (0x01B0 - MX3FB_REG_OFFSET)
103#define DI_DISP_ACC_CC (0x01B4 - MX3FB_REG_OFFSET)
104#define DI_DISP_LLA_CONF (0x01B8 - MX3FB_REG_OFFSET)
105#define DI_DISP_LLA_DATA (0x01BC - MX3FB_REG_OFFSET)
86528da2
GL		 106
107/* DI_DISP_SIG_POL bits */
6e1588cb
GL		 108#define DI_D3_VSYNC_POL_SHIFT 28
109#define DI_D3_HSYNC_POL_SHIFT 27
110#define DI_D3_DRDY_SHARP_POL_SHIFT 26
111#define DI_D3_CLK_POL_SHIFT 25
112#define DI_D3_DATA_POL_SHIFT 24
86528da2
GL		 113
114/* DI_DISP_IF_CONF bits */
6e1588cb
GL		 115#define DI_D3_CLK_IDLE_SHIFT 26
116#define DI_D3_CLK_SEL_SHIFT 25
117#define DI_D3_DATAMSK_SHIFT 24
86528da2
GL		 118
119enum ipu_panel {
6e1588cb
GL		 120 IPU_PANEL_SHARP_TFT,
121 IPU_PANEL_TFT,
86528da2
GL		 122};
123
124struct ipu_di_signal_cfg {
6e1588cb
GL		 125 unsigned datamask_en:1;
126 unsigned clksel_en:1;
127 unsigned clkidle_en:1;
128 unsigned data_pol:1; /* true = inverted */
129 unsigned clk_pol:1; /* true = rising edge */
130 unsigned enable_pol:1;
131 unsigned Hsync_pol:1; /* true = active high */
132 unsigned Vsync_pol:1;
86528da2
GL		 133};
134
135static const struct fb_videomode mx3fb_modedb[] = {
6e1588cb
GL		 136 {
137 /* 240x320 @ 60 Hz */
138 .name = "Sharp-QVGA",
139 .refresh = 60,
140 .xres = 240,
141 .yres = 320,
142 .pixclock = 185925,
143 .left_margin = 9,
144 .right_margin = 16,
145 .upper_margin = 7,
146 .lower_margin = 9,
147 .hsync_len = 1,
148 .vsync_len = 1,
149 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
150 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
151 FB_SYNC_CLK_IDLE_EN,
152 .vmode = FB_VMODE_NONINTERLACED,
153 .flag = 0,
154 }, {
155 /* 240x33 @ 60 Hz */
156 .name = "Sharp-CLI",
157 .refresh = 60,
158 .xres = 240,
159 .yres = 33,
160 .pixclock = 185925,
161 .left_margin = 9,
162 .right_margin = 16,
163 .upper_margin = 7,
164 .lower_margin = 9 + 287,
165 .hsync_len = 1,
166 .vsync_len = 1,
167 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
168 FB_SYNC_CLK_INVERT | FB_SYNC_DATA_INVERT |
169 FB_SYNC_CLK_IDLE_EN,
170 .vmode = FB_VMODE_NONINTERLACED,
171 .flag = 0,
172 }, {
173 /* 640x480 @ 60 Hz */
174 .name = "NEC-VGA",
175 .refresh = 60,
176 .xres = 640,
177 .yres = 480,
178 .pixclock = 38255,
179 .left_margin = 144,
180 .right_margin = 0,
181 .upper_margin = 34,
182 .lower_margin = 40,
183 .hsync_len = 1,
184 .vsync_len = 1,
185 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
186 .vmode = FB_VMODE_NONINTERLACED,
187 .flag = 0,
188 }, {
189 /* NTSC TV output */
190 .name = "TV-NTSC",
191 .refresh = 60,
192 .xres = 640,
193 .yres = 480,
194 .pixclock = 37538,
195 .left_margin = 38,
196 .right_margin = 858 - 640 - 38 - 3,
197 .upper_margin = 36,
198 .lower_margin = 518 - 480 - 36 - 1,
199 .hsync_len = 3,
200 .vsync_len = 1,
201 .sync = 0,
202 .vmode = FB_VMODE_NONINTERLACED,
203 .flag = 0,
204 }, {
205 /* PAL TV output */
206 .name = "TV-PAL",
207 .refresh = 50,
208 .xres = 640,
209 .yres = 480,
210 .pixclock = 37538,
211 .left_margin = 38,
212 .right_margin = 960 - 640 - 38 - 32,
213 .upper_margin = 32,
214 .lower_margin = 555 - 480 - 32 - 3,
215 .hsync_len = 32,
216 .vsync_len = 3,
217 .sync = 0,
218 .vmode = FB_VMODE_NONINTERLACED,
219 .flag = 0,
220 }, {
221 /* TV output VGA mode, 640x480 @ 65 Hz */
222 .name = "TV-VGA",
223 .refresh = 60,
224 .xres = 640,
225 .yres = 480,
226 .pixclock = 40574,
227 .left_margin = 35,
228 .right_margin = 45,
229 .upper_margin = 9,
230 .lower_margin = 1,
231 .hsync_len = 46,
232 .vsync_len = 5,
233 .sync = 0,
234 .vmode = FB_VMODE_NONINTERLACED,
235 .flag = 0,
236 },
86528da2
GL		 237};
238
239struct mx3fb_data {
6e1588cb
GL		 240 struct fb_info *fbi;
241 int backlight_level;
242 void __iomem *reg_base;
243 spinlock_t lock;
244 struct device *dev;
245
246 uint32_t h_start_width;
247 uint32_t v_start_width;
86528da2
GL		 248};
249
250struct dma_chan_request {
6e1588cb
GL		 251 struct mx3fb_data *mx3fb;
252 enum ipu_channel id;
86528da2
GL		 253};
254
255/* MX3 specific framebuffer information. */
256struct mx3fb_info {
6e1588cb
GL		 257 int blank;
258 enum ipu_channel ipu_ch;
259 uint32_t cur_ipu_buf;
86528da2 260
6e1588cb 261 u32 pseudo_palette[16];
86528da2 262
6e1588cb
GL		 263 struct completion flip_cmpl;
264 struct mutex mutex; /* Protects fb-ops */
265 struct mx3fb_data *mx3fb;
266 struct idmac_channel *idmac_channel;
267 struct dma_async_tx_descriptor *txd;
268 dma_cookie_t cookie;
269 struct scatterlist sg[2];
86528da2 270
6e1588cb 271 u32 sync; /* preserve var->sync flags */
86528da2
GL		 272};
273
274static void mx3fb_dma_done(void *);
275
276/* Used fb-mode and bpp. Can be set on kernel command line, therefore file-static. */
277static const char *fb_mode;
278static unsigned long default_bpp = 16;
279
280static u32 mx3fb_read_reg(struct mx3fb_data *mx3fb, unsigned long reg)
281{
6e1588cb 282 return __raw_readl(mx3fb->reg_base + reg);
86528da2
GL		 283}
284
285static void mx3fb_write_reg(struct mx3fb_data *mx3fb, u32 value, unsigned long reg)
286{
6e1588cb 287 __raw_writel(value, mx3fb->reg_base + reg);
86528da2
GL		 288}
289
290static const uint32_t di_mappings[] = {
6e1588cb
GL		 291 0x1600AAAA, 0x00E05555, 0x00070000, 3, /* RGB888 */
292 0x0005000F, 0x000B000F, 0x0011000F, 1, /* RGB666 */
293 0x0011000F, 0x000B000F, 0x0005000F, 1, /* BGR666 */
294 0x0004003F, 0x000A000F, 0x000F003F, 1 /* RGB565 */
86528da2
GL		 295};
296
297static void sdc_fb_init(struct mx3fb_info *fbi)
298{
6e1588cb
GL		 299 struct mx3fb_data *mx3fb = fbi->mx3fb;
300 uint32_t reg;
86528da2 301
6e1588cb 302 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
86528da2 303
6e1588cb 304 mx3fb_write_reg(mx3fb, reg | SDC_COM_BG_EN, SDC_COM_CONF);
86528da2
GL		 305}
306
307/* Returns enabled flag before uninit */
308static uint32_t sdc_fb_uninit(struct mx3fb_info *fbi)
309{
6e1588cb
GL		 310 struct mx3fb_data *mx3fb = fbi->mx3fb;
311 uint32_t reg;
86528da2 312
6e1588cb 313 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
86528da2 314
6e1588cb 315 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_BG_EN, SDC_COM_CONF);
86528da2 316
6e1588cb 317 return reg & SDC_COM_BG_EN;
86528da2
GL		 318}
319
320static void sdc_enable_channel(struct mx3fb_info *mx3_fbi)
321{
6e1588cb
GL		 322 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
323 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
324 struct dma_chan *dma_chan = &ichan->dma_chan;
325 unsigned long flags;
326 dma_cookie_t cookie;
327
b3cb5372
AP		 328 if (mx3_fbi->txd)
329 dev_dbg(mx3fb->dev, "mx3fbi %p, desc %p, sg %p\n", mx3_fbi,
330 to_tx_desc(mx3_fbi->txd), to_tx_desc(mx3_fbi->txd)->sg);
331 else
332 dev_dbg(mx3fb->dev, "mx3fbi %p, txd = NULL\n", mx3_fbi);
6e1588cb
GL		 333
334 /* This enables the channel */
335 if (mx3_fbi->cookie < 0) {
336 mx3_fbi->txd = dma_chan->device->device_prep_slave_sg(dma_chan,
337 &mx3_fbi->sg[0], 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
338 if (!mx3_fbi->txd) {
339 dev_err(mx3fb->dev, "Cannot allocate descriptor on %d\n",
340 dma_chan->chan_id);
341 return;
342 }
343
344 mx3_fbi->txd->callback_param = mx3_fbi->txd;
345 mx3_fbi->txd->callback = mx3fb_dma_done;
346
347 cookie = mx3_fbi->txd->tx_submit(mx3_fbi->txd);
348 dev_dbg(mx3fb->dev, "%d: Submit %p #%d [%c]\n", __LINE__,
349 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
350 } else {
351 if (!mx3_fbi->txd || !mx3_fbi->txd->tx_submit) {
352 dev_err(mx3fb->dev, "Cannot enable channel %d\n",
353 dma_chan->chan_id);
354 return;
355 }
356
357 /* Just re-activate the same buffer */
358 dma_async_issue_pending(dma_chan);
359 cookie = mx3_fbi->cookie;
360 dev_dbg(mx3fb->dev, "%d: Re-submit %p #%d [%c]\n", __LINE__,
361 mx3_fbi->txd, cookie, list_empty(&ichan->queue) ? '-' : '+');
362 }
363
364 if (cookie >= 0) {
365 spin_lock_irqsave(&mx3fb->lock, flags);
366 sdc_fb_init(mx3_fbi);
367 mx3_fbi->cookie = cookie;
368 spin_unlock_irqrestore(&mx3fb->lock, flags);
369 }
370
371 /*
372 * Attention! Without this msleep the channel keeps generating
373 * interrupts. Next sdc_set_brightness() is going to be called
374 * from mx3fb_blank().
375 */
376 msleep(2);
86528da2
GL		 377}
378
379static void sdc_disable_channel(struct mx3fb_info *mx3_fbi)
380{
6e1588cb
GL		 381 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
382 uint32_t enabled;
383 unsigned long flags;
86528da2 384
8b53b7fb
WS		 385 if (mx3_fbi->txd == NULL)
386 return;
387
6e1588cb 388 spin_lock_irqsave(&mx3fb->lock, flags);
86528da2 389
6e1588cb 390 enabled = sdc_fb_uninit(mx3_fbi);
86528da2 391
6e1588cb 392 spin_unlock_irqrestore(&mx3fb->lock, flags);
86528da2 393
c3635c78 394 mx3_fbi->txd->chan->device->device_control(mx3_fbi->txd->chan,
05827630 395 DMA_TERMINATE_ALL, 0);
6e1588cb
GL		 396 mx3_fbi->txd = NULL;
397 mx3_fbi->cookie = -EINVAL;
86528da2
GL		 398}
399
400/**
401 * sdc_set_window_pos() - set window position of the respective plane.
6e1588cb
GL		 402 * @mx3fb: mx3fb context.
403 * @channel: IPU DMAC channel ID.
404 * @x_pos: X coordinate relative to the top left corner to place window at.
405 * @y_pos: Y coordinate relative to the top left corner to place window at.
406 * @return: 0 on success or negative error code on failure.
86528da2
GL		 407 */
408static int sdc_set_window_pos(struct mx3fb_data *mx3fb, enum ipu_channel channel,
6e1588cb 409 int16_t x_pos, int16_t y_pos)
86528da2 410{
6e1588cb
GL		 411 if (channel != IDMAC_SDC_0)
412 return -EINVAL;
86528da2 413
d88ca815
GL		 414 x_pos += mx3fb->h_start_width;
415 y_pos += mx3fb->v_start_width;
416
6e1588cb
GL		 417 mx3fb_write_reg(mx3fb, (x_pos << 16) | y_pos, SDC_BG_POS);
418 return 0;
86528da2
GL		 419}
420
421/**
422 * sdc_init_panel() - initialize a synchronous LCD panel.
6e1588cb
GL		 423 * @mx3fb: mx3fb context.
424 * @panel: panel type.
425 * @pixel_clk: desired pixel clock frequency in Hz.
426 * @width: width of panel in pixels.
427 * @height: height of panel in pixels.
428 * @pixel_fmt: pixel format of buffer as FOURCC ASCII code.
429 * @h_start_width: number of pixel clocks between the HSYNC signal pulse
430 * and the start of valid data.
431 * @h_sync_width: width of the HSYNC signal in units of pixel clocks.
432 * @h_end_width: number of pixel clocks between the end of valid data
433 * and the HSYNC signal for next line.
434 * @v_start_width: number of lines between the VSYNC signal pulse and the
435 * start of valid data.
436 * @v_sync_width: width of the VSYNC signal in units of lines
437 * @v_end_width: number of lines between the end of valid data and the
438 * VSYNC signal for next frame.
439 * @sig: bitfield of signal polarities for LCD interface.
440 * @return: 0 on success or negative error code on failure.
86528da2
GL		 441 */
442static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
6e1588cb
GL		 443 uint32_t pixel_clk,
444 uint16_t width, uint16_t height,
445 enum pixel_fmt pixel_fmt,
446 uint16_t h_start_width, uint16_t h_sync_width,
447 uint16_t h_end_width, uint16_t v_start_width,
448 uint16_t v_sync_width, uint16_t v_end_width,
449 struct ipu_di_signal_cfg sig)
86528da2 450{
6e1588cb
GL		 451 unsigned long lock_flags;
452 uint32_t reg;
453 uint32_t old_conf;
454 uint32_t div;
455 struct clk *ipu_clk;
86528da2 456
6e1588cb 457 dev_dbg(mx3fb->dev, "panel size = %d x %d", width, height);
86528da2 458
6e1588cb
GL		 459 if (v_sync_width == 0 || h_sync_width == 0)
460 return -EINVAL;
86528da2 461
6e1588cb
GL		 462 /* Init panel size and blanking periods */
463 reg = ((uint32_t) (h_sync_width - 1) << 26) |
464 ((uint32_t) (width + h_start_width + h_end_width - 1) << 16);
465 mx3fb_write_reg(mx3fb, reg, SDC_HOR_CONF);
86528da2
GL		 466
467#ifdef DEBUG
6e1588cb 468 printk(KERN_CONT " hor_conf %x,", reg);
86528da2
GL		 469#endif
470
6e1588cb
GL		 471 reg = ((uint32_t) (v_sync_width - 1) << 26) | SDC_V_SYNC_WIDTH_L |
472 ((uint32_t) (height + v_start_width + v_end_width - 1) << 16);
473 mx3fb_write_reg(mx3fb, reg, SDC_VER_CONF);
86528da2
GL		 474
475#ifdef DEBUG
6e1588cb 476 printk(KERN_CONT " ver_conf %x\n", reg);
86528da2
GL		 477#endif
478
6e1588cb
GL		 479 mx3fb->h_start_width = h_start_width;
480 mx3fb->v_start_width = v_start_width;
481
482 switch (panel) {
483 case IPU_PANEL_SHARP_TFT:
484 mx3fb_write_reg(mx3fb, 0x00FD0102L, SDC_SHARP_CONF_1);
485 mx3fb_write_reg(mx3fb, 0x00F500F4L, SDC_SHARP_CONF_2);
486 mx3fb_write_reg(mx3fb, SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
487 break;
488 case IPU_PANEL_TFT:
489 mx3fb_write_reg(mx3fb, SDC_COM_TFT_COLOR, SDC_COM_CONF);
490 break;
491 default:
492 return -EINVAL;
493 }
494
495 /* Init clocking */
496
497 /*
498 * Calculate divider: fractional part is 4 bits so simply multiple by
499 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
500 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
501 */
3879f5d6 502 ipu_clk = clk_get(mx3fb->dev, NULL);
d88ca815
GL		 503 if (!IS_ERR(ipu_clk)) {
504 div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
505 clk_put(ipu_clk);
506 } else {
507 div = 0;
508 }
6e1588cb
GL		 509
510 if (div < 0x40) { /* Divider less than 4 */
511 dev_dbg(mx3fb->dev,
512 "InitPanel() - Pixel clock divider less than 4\n");
513 div = 0x40;
514 }
515
d88ca815
GL		 516 dev_dbg(mx3fb->dev, "pixel clk = %u, divider %u.%u\n",
517 pixel_clk, div >> 4, (div & 7) * 125);
518
6e1588cb
GL		 519 spin_lock_irqsave(&mx3fb->lock, lock_flags);
520
521 /*
522 * DISP3_IF_CLK_DOWN_WR is half the divider value and 2 fraction bits
523 * fewer. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR based on timing
524 * debug. DISP3_IF_CLK_UP_WR is 0
525 */
526 mx3fb_write_reg(mx3fb, (((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
527
528 /* DI settings */
529 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF) & 0x78FFFFFF;
530 old_conf |= sig.datamask_en << DI_D3_DATAMSK_SHIFT |
d88ca815
GL		 531 sig.clksel_en << DI_D3_CLK_SEL_SHIFT |
532 sig.clkidle_en << DI_D3_CLK_IDLE_SHIFT;
6e1588cb
GL		 533 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_IF_CONF);
534
535 old_conf = mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL) & 0xE0FFFFFF;
536 old_conf |= sig.data_pol << DI_D3_DATA_POL_SHIFT |
d88ca815
GL		 537 sig.clk_pol << DI_D3_CLK_POL_SHIFT |
538 sig.enable_pol << DI_D3_DRDY_SHARP_POL_SHIFT |
539 sig.Hsync_pol << DI_D3_HSYNC_POL_SHIFT |
540 sig.Vsync_pol << DI_D3_VSYNC_POL_SHIFT;
6e1588cb
GL		 541 mx3fb_write_reg(mx3fb, old_conf, DI_DISP_SIG_POL);
542
543 switch (pixel_fmt) {
544 case IPU_PIX_FMT_RGB24:
545 mx3fb_write_reg(mx3fb, di_mappings[0], DI_DISP3_B0_MAP);
546 mx3fb_write_reg(mx3fb, di_mappings[1], DI_DISP3_B1_MAP);
547 mx3fb_write_reg(mx3fb, di_mappings[2], DI_DISP3_B2_MAP);
548 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
549 ((di_mappings[3] - 1) << 12), DI_DISP_ACC_CC);
550 break;
551 case IPU_PIX_FMT_RGB666:
552 mx3fb_write_reg(mx3fb, di_mappings[4], DI_DISP3_B0_MAP);
553 mx3fb_write_reg(mx3fb, di_mappings[5], DI_DISP3_B1_MAP);
554 mx3fb_write_reg(mx3fb, di_mappings[6], DI_DISP3_B2_MAP);
555 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
556 ((di_mappings[7] - 1) << 12), DI_DISP_ACC_CC);
557 break;
558 case IPU_PIX_FMT_BGR666:
559 mx3fb_write_reg(mx3fb, di_mappings[8], DI_DISP3_B0_MAP);
560 mx3fb_write_reg(mx3fb, di_mappings[9], DI_DISP3_B1_MAP);
561 mx3fb_write_reg(mx3fb, di_mappings[10], DI_DISP3_B2_MAP);
562 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
563 ((di_mappings[11] - 1) << 12), DI_DISP_ACC_CC);
564 break;
565 default:
566 mx3fb_write_reg(mx3fb, di_mappings[12], DI_DISP3_B0_MAP);
567 mx3fb_write_reg(mx3fb, di_mappings[13], DI_DISP3_B1_MAP);
568 mx3fb_write_reg(mx3fb, di_mappings[14], DI_DISP3_B2_MAP);
569 mx3fb_write_reg(mx3fb, mx3fb_read_reg(mx3fb, DI_DISP_ACC_CC) |
570 ((di_mappings[15] - 1) << 12), DI_DISP_ACC_CC);
571 break;
572 }
573
574 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
575
576 dev_dbg(mx3fb->dev, "DI_DISP_IF_CONF = 0x%08X\n",
577 mx3fb_read_reg(mx3fb, DI_DISP_IF_CONF));
578 dev_dbg(mx3fb->dev, "DI_DISP_SIG_POL = 0x%08X\n",
579 mx3fb_read_reg(mx3fb, DI_DISP_SIG_POL));
580 dev_dbg(mx3fb->dev, "DI_DISP3_TIME_CONF = 0x%08X\n",
581 mx3fb_read_reg(mx3fb, DI_DISP3_TIME_CONF));
582
583 return 0;
86528da2
GL		 584}
585
586/**
587 * sdc_set_color_key() - set the transparent color key for SDC graphic plane.
6e1588cb
GL		 588 * @mx3fb: mx3fb context.
589 * @channel: IPU DMAC channel ID.
590 * @enable: boolean to enable or disable color keyl.
591 * @color_key: 24-bit RGB color to use as transparent color key.
592 * @return: 0 on success or negative error code on failure.
86528da2
GL		 593 */
594static int sdc_set_color_key(struct mx3fb_data *mx3fb, enum ipu_channel channel,
6e1588cb 595 bool enable, uint32_t color_key)
86528da2 596{
6e1588cb
GL		 597 uint32_t reg, sdc_conf;
598 unsigned long lock_flags;
86528da2 599
6e1588cb 600 spin_lock_irqsave(&mx3fb->lock, lock_flags);
86528da2 601
6e1588cb
GL		 602 sdc_conf = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
603 if (channel == IDMAC_SDC_0)
604 sdc_conf &= ~SDC_COM_GWSEL;
605 else
606 sdc_conf |= SDC_COM_GWSEL;
86528da2 607
6e1588cb
GL		 608 if (enable) {
609 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0xFF000000L;
610 mx3fb_write_reg(mx3fb, reg | (color_key & 0x00FFFFFFL),
611 SDC_GW_CTRL);
86528da2 612
6e1588cb
GL		 613 sdc_conf |= SDC_COM_KEY_COLOR_G;
614 } else {
615 sdc_conf &= ~SDC_COM_KEY_COLOR_G;
616 }
617 mx3fb_write_reg(mx3fb, sdc_conf, SDC_COM_CONF);
86528da2 618
6e1588cb 619 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
86528da2 620
6e1588cb 621 return 0;
86528da2
GL		 622}
623
624/**
625 * sdc_set_global_alpha() - set global alpha blending modes.
6e1588cb
GL		 626 * @mx3fb: mx3fb context.
627 * @enable: boolean to enable or disable global alpha blending. If disabled,
628 * per pixel blending is used.
629 * @alpha: global alpha value.
630 * @return: 0 on success or negative error code on failure.
86528da2
GL		 631 */
632static int sdc_set_global_alpha(struct mx3fb_data *mx3fb, bool enable, uint8_t alpha)
633{
6e1588cb
GL		 634 uint32_t reg;
635 unsigned long lock_flags;
86528da2 636
6e1588cb 637 spin_lock_irqsave(&mx3fb->lock, lock_flags);
86528da2 638
6e1588cb
GL		 639 if (enable) {
640 reg = mx3fb_read_reg(mx3fb, SDC_GW_CTRL) & 0x00FFFFFFL;
641 mx3fb_write_reg(mx3fb, reg | ((uint32_t) alpha << 24), SDC_GW_CTRL);
86528da2 642
6e1588cb
GL		 643 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
644 mx3fb_write_reg(mx3fb, reg | SDC_COM_GLB_A, SDC_COM_CONF);
645 } else {
646 reg = mx3fb_read_reg(mx3fb, SDC_COM_CONF);
647 mx3fb_write_reg(mx3fb, reg & ~SDC_COM_GLB_A, SDC_COM_CONF);
648 }
86528da2 649
6e1588cb 650 spin_unlock_irqrestore(&mx3fb->lock, lock_flags);
86528da2 651
6e1588cb 652 return 0;
86528da2
GL		 653}
654
655static void sdc_set_brightness(struct mx3fb_data *mx3fb, uint8_t value)
656{
b3cb5372 657 dev_dbg(mx3fb->dev, "%s: value = %d\n", __func__, value);
6e1588cb
GL		 658 /* This might be board-specific */
659 mx3fb_write_reg(mx3fb, 0x03000000UL | value << 16, SDC_PWM_CTRL);
660 return;
86528da2
GL		 661}
662
663static uint32_t bpp_to_pixfmt(int bpp)
664{
6e1588cb
GL		 665 uint32_t pixfmt = 0;
666 switch (bpp) {
667 case 24:
668 pixfmt = IPU_PIX_FMT_BGR24;
669 break;
670 case 32:
671 pixfmt = IPU_PIX_FMT_BGR32;
672 break;
673 case 16:
674 pixfmt = IPU_PIX_FMT_RGB565;
675 break;
676 }
677 return pixfmt;
86528da2
GL		 678}
679
680static int mx3fb_blank(int blank, struct fb_info *fbi);
20de03da
GL		 681static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
682 bool lock);
86528da2
GL		 683static int mx3fb_unmap_video_memory(struct fb_info *fbi);
684
685/**
686 * mx3fb_set_fix() - set fixed framebuffer parameters from variable settings.
6e1588cb
GL		 687 * @info: framebuffer information pointer
688 * @return: 0 on success or negative error code on failure.
86528da2
GL		 689 */
690static int mx3fb_set_fix(struct fb_info *fbi)
691{
6e1588cb
GL		 692 struct fb_fix_screeninfo *fix = &fbi->fix;
693 struct fb_var_screeninfo *var = &fbi->var;
86528da2 694
6e1588cb 695 strncpy(fix->id, "DISP3 BG", 8);
86528da2 696
6e1588cb 697 fix->line_length = var->xres_virtual * var->bits_per_pixel / 8;
86528da2 698
6e1588cb
GL		 699 fix->type = FB_TYPE_PACKED_PIXELS;
700 fix->accel = FB_ACCEL_NONE;
701 fix->visual = FB_VISUAL_TRUECOLOR;
702 fix->xpanstep = 1;
703 fix->ypanstep = 1;
86528da2 704
6e1588cb 705 return 0;
86528da2
GL		 706}
707
708static void mx3fb_dma_done(void *arg)
709{
6e1588cb
GL		 710 struct idmac_tx_desc *tx_desc = to_tx_desc(arg);
711 struct dma_chan *chan = tx_desc->txd.chan;
712 struct idmac_channel *ichannel = to_idmac_chan(chan);
713 struct mx3fb_data *mx3fb = ichannel->client;
714 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 715
6e1588cb 716 dev_dbg(mx3fb->dev, "irq %d callback\n", ichannel->eof_irq);
86528da2 717
6e1588cb 718 /* We only need one interrupt, it will be re-enabled as needed */
c8a4fb47 719 disable_irq_nosync(ichannel->eof_irq);
86528da2 720
6e1588cb 721 complete(&mx3_fbi->flip_cmpl);
86528da2
GL		 722}
723
20de03da 724static int __set_par(struct fb_info *fbi, bool lock)
86528da2 725{
6e1588cb
GL		 726 u32 mem_len;
727 struct ipu_di_signal_cfg sig_cfg;
728 enum ipu_panel mode = IPU_PANEL_TFT;
729 struct mx3fb_info *mx3_fbi = fbi->par;
730 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
731 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
732 struct idmac_video_param *video = &ichan->params.video;
733 struct scatterlist *sg = mx3_fbi->sg;
6e1588cb 734
6e1588cb
GL		 735 /* Total cleanup */
736 if (mx3_fbi->txd)
737 sdc_disable_channel(mx3_fbi);
738
739 mx3fb_set_fix(fbi);
740
741 mem_len = fbi->var.yres_virtual * fbi->fix.line_length;
742 if (mem_len > fbi->fix.smem_len) {
743 if (fbi->fix.smem_start)
744 mx3fb_unmap_video_memory(fbi);
745
20de03da 746 if (mx3fb_map_video_memory(fbi, mem_len, lock) < 0)
6e1588cb 747 return -ENOMEM;
6e1588cb
GL		 748 }
749
6e1588cb
GL		 750 sg_init_table(&sg[0], 1);
751 sg_init_table(&sg[1], 1);
752
d88ca815 753 sg_dma_address(&sg[0]) = fbi->fix.smem_start;
6e1588cb
GL		 754 sg_set_page(&sg[0], virt_to_page(fbi->screen_base),
755 fbi->fix.smem_len,
756 offset_in_page(fbi->screen_base));
757
758 if (mx3_fbi->ipu_ch == IDMAC_SDC_0) {
759 memset(&sig_cfg, 0, sizeof(sig_cfg));
760 if (fbi->var.sync & FB_SYNC_HOR_HIGH_ACT)
761 sig_cfg.Hsync_pol = true;
762 if (fbi->var.sync & FB_SYNC_VERT_HIGH_ACT)
763 sig_cfg.Vsync_pol = true;
764 if (fbi->var.sync & FB_SYNC_CLK_INVERT)
765 sig_cfg.clk_pol = true;
766 if (fbi->var.sync & FB_SYNC_DATA_INVERT)
767 sig_cfg.data_pol = true;
768 if (fbi->var.sync & FB_SYNC_OE_ACT_HIGH)
769 sig_cfg.enable_pol = true;
770 if (fbi->var.sync & FB_SYNC_CLK_IDLE_EN)
771 sig_cfg.clkidle_en = true;
772 if (fbi->var.sync & FB_SYNC_CLK_SEL_EN)
773 sig_cfg.clksel_en = true;
774 if (fbi->var.sync & FB_SYNC_SHARP_MODE)
775 mode = IPU_PANEL_SHARP_TFT;
776
777 dev_dbg(fbi->device, "pixclock = %ul Hz\n",
778 (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
779
780 if (sdc_init_panel(mx3fb, mode,
781 (PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
782 fbi->var.xres, fbi->var.yres,
783 (fbi->var.sync & FB_SYNC_SWAP_RGB) ?
784 IPU_PIX_FMT_BGR666 : IPU_PIX_FMT_RGB666,
785 fbi->var.left_margin,
786 fbi->var.hsync_len,
787 fbi->var.right_margin +
788 fbi->var.hsync_len,
789 fbi->var.upper_margin,
790 fbi->var.vsync_len,
791 fbi->var.lower_margin +
792 fbi->var.vsync_len, sig_cfg) != 0) {
6e1588cb
GL		 793 dev_err(fbi->device,
794 "mx3fb: Error initializing panel.\n");
795 return -EINVAL;
796 }
797 }
798
799 sdc_set_window_pos(mx3fb, mx3_fbi->ipu_ch, 0, 0);
800
801 mx3_fbi->cur_ipu_buf = 0;
802
803 video->out_pixel_fmt = bpp_to_pixfmt(fbi->var.bits_per_pixel);
804 video->out_width = fbi->var.xres;
805 video->out_height = fbi->var.yres;
806 video->out_stride = fbi->var.xres_virtual;
807
808 if (mx3_fbi->blank == FB_BLANK_UNBLANK)
809 sdc_enable_channel(mx3_fbi);
810
20de03da
GL		 811 return 0;
812}
813
814/**
815 * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
816 * @fbi: framebuffer information pointer.
817 * @return: 0 on success or negative error code on failure.
818 */
819static int mx3fb_set_par(struct fb_info *fbi)
820{
821 struct mx3fb_info *mx3_fbi = fbi->par;
822 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
823 struct idmac_channel *ichan = mx3_fbi->idmac_channel;
824 int ret;
825
826 dev_dbg(mx3fb->dev, "%s [%c]\n", __func__, list_empty(&ichan->queue) ? '-' : '+');
827
828 mutex_lock(&mx3_fbi->mutex);
829
830 ret = __set_par(fbi, true);
831
6e1588cb
GL		 832 mutex_unlock(&mx3_fbi->mutex);
833
20de03da 834 return ret;
86528da2
GL		 835}
836
837/**
838 * mx3fb_check_var() - check and adjust framebuffer variable parameters.
6e1588cb
GL		 839 * @var: framebuffer variable parameters
840 * @fbi: framebuffer information pointer
86528da2
GL		 841 */
842static int mx3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *fbi)
843{
6e1588cb
GL		 844 struct mx3fb_info *mx3_fbi = fbi->par;
845 u32 vtotal;
846 u32 htotal;
847
848 dev_dbg(fbi->device, "%s\n", __func__);
849
850 if (var->xres_virtual < var->xres)
851 var->xres_virtual = var->xres;
852 if (var->yres_virtual < var->yres)
853 var->yres_virtual = var->yres;
854
855 if ((var->bits_per_pixel != 32) && (var->bits_per_pixel != 24) &&
856 (var->bits_per_pixel != 16))
857 var->bits_per_pixel = default_bpp;
858
859 switch (var->bits_per_pixel) {
860 case 16:
861 var->red.length = 5;
862 var->red.offset = 11;
863 var->red.msb_right = 0;
864
865 var->green.length = 6;
866 var->green.offset = 5;
867 var->green.msb_right = 0;
868
869 var->blue.length = 5;
870 var->blue.offset = 0;
871 var->blue.msb_right = 0;
872
873 var->transp.length = 0;
874 var->transp.offset = 0;
875 var->transp.msb_right = 0;
876 break;
877 case 24:
878 var->red.length = 8;
879 var->red.offset = 16;
880 var->red.msb_right = 0;
881
882 var->green.length = 8;
883 var->green.offset = 8;
884 var->green.msb_right = 0;
885
886 var->blue.length = 8;
887 var->blue.offset = 0;
888 var->blue.msb_right = 0;
889
890 var->transp.length = 0;
891 var->transp.offset = 0;
892 var->transp.msb_right = 0;
893 break;
894 case 32:
895 var->red.length = 8;
896 var->red.offset = 16;
897 var->red.msb_right = 0;
898
899 var->green.length = 8;
900 var->green.offset = 8;
901 var->green.msb_right = 0;
902
903 var->blue.length = 8;
904 var->blue.offset = 0;
905 var->blue.msb_right = 0;
906
907 var->transp.length = 8;
908 var->transp.offset = 24;
909 var->transp.msb_right = 0;
910 break;
911 }
912
913 if (var->pixclock < 1000) {
914 htotal = var->xres + var->right_margin + var->hsync_len +
915 var->left_margin;
916 vtotal = var->yres + var->lower_margin + var->vsync_len +
917 var->upper_margin;
918 var->pixclock = (vtotal * htotal * 6UL) / 100UL;
919 var->pixclock = KHZ2PICOS(var->pixclock);
920 dev_dbg(fbi->device, "pixclock set for 60Hz refresh = %u ps\n",
921 var->pixclock);
922 }
923
924 var->height = -1;
925 var->width = -1;
926 var->grayscale = 0;
927
928 /* Preserve sync flags */
929 var->sync |= mx3_fbi->sync;
930 mx3_fbi->sync |= var->sync;
931
932 return 0;
86528da2
GL		 933}
934
935static u32 chan_to_field(unsigned int chan, struct fb_bitfield *bf)
936{
6e1588cb
GL		 937 chan &= 0xffff;
938 chan >>= 16 - bf->length;
939 return chan << bf->offset;
86528da2
GL		 940}
941
942static int mx3fb_setcolreg(unsigned int regno, unsigned int red,
6e1588cb
GL		 943 unsigned int green, unsigned int blue,
944 unsigned int trans, struct fb_info *fbi)
86528da2 945{
6e1588cb
GL		 946 struct mx3fb_info *mx3_fbi = fbi->par;
947 u32 val;
948 int ret = 1;
949
d88ca815 950 dev_dbg(fbi->device, "%s, regno = %u\n", __func__, regno);
6e1588cb
GL		 951
952 mutex_lock(&mx3_fbi->mutex);
953 /*
954 * If greyscale is true, then we convert the RGB value
955 * to greyscale no matter what visual we are using.
956 */
957 if (fbi->var.grayscale)
958 red = green = blue = (19595 * red + 38470 * green +
959 7471 * blue) >> 16;
960 switch (fbi->fix.visual) {
961 case FB_VISUAL_TRUECOLOR:
962 /*
963 * 16-bit True Colour. We encode the RGB value
964 * according to the RGB bitfield information.
965 */
966 if (regno < 16) {
967 u32 *pal = fbi->pseudo_palette;
968
969 val = chan_to_field(red, &fbi->var.red);
970 val |= chan_to_field(green, &fbi->var.green);
971 val |= chan_to_field(blue, &fbi->var.blue);
972
973 pal[regno] = val;
974
975 ret = 0;
976 }
977 break;
978
979 case FB_VISUAL_STATIC_PSEUDOCOLOR:
980 case FB_VISUAL_PSEUDOCOLOR:
981 break;
982 }
983 mutex_unlock(&mx3_fbi->mutex);
984
985 return ret;
86528da2
GL		 986}
987
20de03da 988static void __blank(int blank, struct fb_info *fbi)
86528da2 989{
6e1588cb
GL		 990 struct mx3fb_info *mx3_fbi = fbi->par;
991 struct mx3fb_data *mx3fb = mx3_fbi->mx3fb;
8b53b7fb 992 int was_blank = mx3_fbi->blank;
6e1588cb 993
6e1588cb
GL		 994 mx3_fbi->blank = blank;
995
8b53b7fb
WS		 996 /* Attention!
997 * Do not call sdc_disable_channel() for a channel that is disabled
998 * already! This will result in a kernel NULL pointer dereference
999 * (mx3_fbi->txd is NULL). Hide the fact, that all blank modes are
1000 * handled equally by this driver.
1001 */
1002 if (blank > FB_BLANK_UNBLANK && was_blank > FB_BLANK_UNBLANK)
1003 return;
1004
6e1588cb
GL		 1005 switch (blank) {
1006 case FB_BLANK_POWERDOWN:
1007 case FB_BLANK_VSYNC_SUSPEND:
1008 case FB_BLANK_HSYNC_SUSPEND:
1009 case FB_BLANK_NORMAL:
6e1588cb 1010 sdc_set_brightness(mx3fb, 0);
d88ca815
GL		 1011 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
1012 /* Give LCD time to update - enough for 50 and 60 Hz */
1013 msleep(25);
1014 sdc_disable_channel(mx3_fbi);
6e1588cb
GL		 1015 break;
1016 case FB_BLANK_UNBLANK:
1017 sdc_enable_channel(mx3_fbi);
1018 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
1019 break;
1020 }
20de03da
GL		 1021}
1022
1023/**
1024 * mx3fb_blank() - blank the display.
1025 */
1026static int mx3fb_blank(int blank, struct fb_info *fbi)
1027{
1028 struct mx3fb_info *mx3_fbi = fbi->par;
1029
1030 dev_dbg(fbi->device, "%s, blank = %d, base %p, len %u\n", __func__,
1031 blank, fbi->screen_base, fbi->fix.smem_len);
1032
1033 if (mx3_fbi->blank == blank)
1034 return 0;
1035
1036 mutex_lock(&mx3_fbi->mutex);
1037 __blank(blank, fbi);
6e1588cb
GL		 1038 mutex_unlock(&mx3_fbi->mutex);
1039
1040 return 0;
86528da2
GL		 1041}
1042
1043/**
1044 * mx3fb_pan_display() - pan or wrap the display
6e1588cb
GL		 1045 * @var: variable screen buffer information.
1046 * @info: framebuffer information pointer.
86528da2
GL		 1047 *
1048 * We look only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1049 */
1050static int mx3fb_pan_display(struct fb_var_screeninfo *var,
6e1588cb 1051 struct fb_info *fbi)
86528da2 1052{
6e1588cb
GL		 1053 struct mx3fb_info *mx3_fbi = fbi->par;
1054 u32 y_bottom;
1055 unsigned long base;
1056 off_t offset;
1057 dma_cookie_t cookie;
1058 struct scatterlist *sg = mx3_fbi->sg;
1059 struct dma_chan *dma_chan = &mx3_fbi->idmac_channel->dma_chan;
1060 struct dma_async_tx_descriptor *txd;
1061 int ret;
1062
1063 dev_dbg(fbi->device, "%s [%c]\n", __func__,
1064 list_empty(&mx3_fbi->idmac_channel->queue) ? '-' : '+');
1065
1066 if (var->xoffset > 0) {
1067 dev_dbg(fbi->device, "x panning not supported\n");
1068 return -EINVAL;
1069 }
1070
1071 if (fbi->var.xoffset == var->xoffset &&
1072 fbi->var.yoffset == var->yoffset)
1073 return 0; /* No change, do nothing */
1074
1075 y_bottom = var->yoffset;
1076
1077 if (!(var->vmode & FB_VMODE_YWRAP))
9f1b3ebb 1078 y_bottom += fbi->var.yres;
6e1588cb
GL		 1079
1080 if (y_bottom > fbi->var.yres_virtual)
1081 return -EINVAL;
1082
1083 mutex_lock(&mx3_fbi->mutex);
1084
9f1b3ebb
LP		 1085 offset = var->yoffset * fbi->fix.line_length
1086 + var->xoffset * (fbi->var.bits_per_pixel / 8);
6e1588cb
GL		 1087 base = fbi->fix.smem_start + offset;
1088
1089 dev_dbg(fbi->device, "Updating SDC BG buf %d address=0x%08lX\n",
1090 mx3_fbi->cur_ipu_buf, base);
1091
1092 /*
1093 * We enable the End of Frame interrupt, which will free a tx-descriptor,
1094 * which we will need for the next device_prep_slave_sg(). The
1095 * IRQ-handler will disable the IRQ again.
1096 */
1097 init_completion(&mx3_fbi->flip_cmpl);
1098 enable_irq(mx3_fbi->idmac_channel->eof_irq);
1099
1100 ret = wait_for_completion_timeout(&mx3_fbi->flip_cmpl, HZ / 10);
1101 if (ret <= 0) {
1102 mutex_unlock(&mx3_fbi->mutex);
1103 dev_info(fbi->device, "Panning failed due to %s\n", ret < 0 ?
1104 "user interrupt" : "timeout");
d88ca815 1105 disable_irq(mx3_fbi->idmac_channel->eof_irq);
6e1588cb
GL		 1106 return ret ? : -ETIMEDOUT;
1107 }
1108
1109 mx3_fbi->cur_ipu_buf = !mx3_fbi->cur_ipu_buf;
1110
1111 sg_dma_address(&sg[mx3_fbi->cur_ipu_buf]) = base;
1112 sg_set_page(&sg[mx3_fbi->cur_ipu_buf],
1113 virt_to_page(fbi->screen_base + offset), fbi->fix.smem_len,
1114 offset_in_page(fbi->screen_base + offset));
1115
d88ca815
GL		 1116 if (mx3_fbi->txd)
1117 async_tx_ack(mx3_fbi->txd);
1118
6e1588cb
GL		 1119 txd = dma_chan->device->device_prep_slave_sg(dma_chan, sg +
1120 mx3_fbi->cur_ipu_buf, 1, DMA_TO_DEVICE, DMA_PREP_INTERRUPT);
1121 if (!txd) {
1122 dev_err(fbi->device,
1123 "Error preparing a DMA transaction descriptor.\n");
1124 mutex_unlock(&mx3_fbi->mutex);
1125 return -EIO;
1126 }
1127
1128 txd->callback_param = txd;
1129 txd->callback = mx3fb_dma_done;
1130
1131 /*
1132 * Emulate original mx3fb behaviour: each new call to idmac_tx_submit()
1133 * should switch to another buffer
1134 */
1135 cookie = txd->tx_submit(txd);
1136 dev_dbg(fbi->device, "%d: Submit %p #%d\n", __LINE__, txd, cookie);
1137 if (cookie < 0) {
1138 dev_err(fbi->device,
1139 "Error updating SDC buf %d to address=0x%08lX\n",
1140 mx3_fbi->cur_ipu_buf, base);
1141 mutex_unlock(&mx3_fbi->mutex);
1142 return -EIO;
1143 }
1144
6e1588cb
GL		 1145 mx3_fbi->txd = txd;
1146
1147 fbi->var.xoffset = var->xoffset;
1148 fbi->var.yoffset = var->yoffset;
1149
1150 if (var->vmode & FB_VMODE_YWRAP)
1151 fbi->var.vmode |= FB_VMODE_YWRAP;
1152 else
1153 fbi->var.vmode &= ~FB_VMODE_YWRAP;
1154
1155 mutex_unlock(&mx3_fbi->mutex);
1156
1157 dev_dbg(fbi->device, "Update complete\n");
1158
1159 return 0;
86528da2
GL		 1160}
1161
1162/*
1163 * This structure contains the pointers to the control functions that are
1164 * invoked by the core framebuffer driver to perform operations like
1165 * blitting, rectangle filling, copy regions and cursor definition.
1166 */
1167static struct fb_ops mx3fb_ops = {
6e1588cb
GL		 1168 .owner = THIS_MODULE,
1169 .fb_set_par = mx3fb_set_par,
1170 .fb_check_var = mx3fb_check_var,
1171 .fb_setcolreg = mx3fb_setcolreg,
1172 .fb_pan_display = mx3fb_pan_display,
1173 .fb_fillrect = cfb_fillrect,
1174 .fb_copyarea = cfb_copyarea,
1175 .fb_imageblit = cfb_imageblit,
1176 .fb_blank = mx3fb_blank,
86528da2
GL		 1177};
1178
1179#ifdef CONFIG_PM
1180/*
1181 * Power management hooks. Note that we won't be called from IRQ context,
1182 * unlike the blank functions above, so we may sleep.
1183 */
1184
1185/*
1186 * Suspends the framebuffer and blanks the screen. Power management support
1187 */
1188static int mx3fb_suspend(struct platform_device *pdev, pm_message_t state)
1189{
b09de420
SH		 1190 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1191 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 1192
ac751efa 1193 console_lock();
b09de420 1194 fb_set_suspend(mx3fb->fbi, 1);
ac751efa 1195 console_unlock();
86528da2 1196
6e1588cb
GL		 1197 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1198 sdc_disable_channel(mx3_fbi);
1199 sdc_set_brightness(mx3fb, 0);
86528da2 1200
6e1588cb
GL		 1201 }
1202 return 0;
86528da2
GL		 1203}
1204
1205/*
1206 * Resumes the framebuffer and unblanks the screen. Power management support
1207 */
1208static int mx3fb_resume(struct platform_device *pdev)
1209{
b09de420
SH		 1210 struct mx3fb_data *mx3fb = platform_get_drvdata(pdev);
1211 struct mx3fb_info *mx3_fbi = mx3fb->fbi->par;
86528da2 1212
6e1588cb
GL		 1213 if (mx3_fbi->blank == FB_BLANK_UNBLANK) {
1214 sdc_enable_channel(mx3_fbi);
b09de420 1215 sdc_set_brightness(mx3fb, mx3fb->backlight_level);
6e1588cb 1216 }
86528da2 1217
ac751efa 1218 console_lock();
b09de420 1219 fb_set_suspend(mx3fb->fbi, 0);
ac751efa 1220 console_unlock();
86528da2 1221
6e1588cb 1222 return 0;
86528da2
GL		 1223}
1224#else
1225#define mx3fb_suspend NULL
1226#define mx3fb_resume NULL
1227#endif
1228
1229/*
1230 * Main framebuffer functions
1231 */
1232
1233/**
1234 * mx3fb_map_video_memory() - allocates the DRAM memory for the frame buffer.
6e1588cb 1235 * @fbi: framebuffer information pointer
537a1bf0 1236 * @mem_len: length of mapped memory
20de03da 1237 * @lock: do not lock during initialisation
6e1588cb 1238 * @return: Error code indicating success or failure
86528da2
GL		 1239 *
1240 * This buffer is remapped into a non-cached, non-buffered, memory region to
1241 * allow palette and pixel writes to occur without flushing the cache. Once this
1242 * area is remapped, all virtual memory access to the video memory should occur
1243 * at the new region.
1244 */
20de03da
GL		 1245static int mx3fb_map_video_memory(struct fb_info *fbi, unsigned int mem_len,
1246 bool lock)
86528da2 1247{
6e1588cb
GL		 1248 int retval = 0;
1249 dma_addr_t addr;
86528da2 1250
6e1588cb 1251 fbi->screen_base = dma_alloc_writecombine(fbi->device,
537a1bf0 1252 mem_len,
6e1588cb 1253 &addr, GFP_DMA);
86528da2 1254
6e1588cb
GL		 1255 if (!fbi->screen_base) {
1256 dev_err(fbi->device, "Cannot allocate %u bytes framebuffer memory\n",
537a1bf0 1257 mem_len);
6e1588cb
GL		 1258 retval = -EBUSY;
1259 goto err0;
1260 }
86528da2 1261
20de03da
GL		 1262 if (lock)
1263 mutex_lock(&fbi->mm_lock);
6e1588cb 1264 fbi->fix.smem_start = addr;
537a1bf0 1265 fbi->fix.smem_len = mem_len;
20de03da
GL		 1266 if (lock)
1267 mutex_unlock(&fbi->mm_lock);
86528da2 1268
6e1588cb
GL		 1269 dev_dbg(fbi->device, "allocated fb @ p=0x%08x, v=0x%p, size=%d.\n",
1270 (uint32_t) fbi->fix.smem_start, fbi->screen_base, fbi->fix.smem_len);
86528da2 1271
6e1588cb 1272 fbi->screen_size = fbi->fix.smem_len;
86528da2 1273
6e1588cb
GL		 1274 /* Clear the screen */
1275 memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
86528da2 1276
6e1588cb 1277 return 0;
86528da2
GL		 1278
1279err0:
6e1588cb
GL		 1280 fbi->fix.smem_len = 0;
1281 fbi->fix.smem_start = 0;
1282 fbi->screen_base = NULL;
1283 return retval;
86528da2
GL		 1284}
1285
1286/**
1287 * mx3fb_unmap_video_memory() - de-allocate frame buffer memory.
6e1588cb
GL		 1288 * @fbi: framebuffer information pointer
1289 * @return: error code indicating success or failure
86528da2
GL		 1290 */
1291static int mx3fb_unmap_video_memory(struct fb_info *fbi)
1292{
6e1588cb
GL		 1293 dma_free_writecombine(fbi->device, fbi->fix.smem_len,
1294 fbi->screen_base, fbi->fix.smem_start);
86528da2 1295
6e1588cb 1296 fbi->screen_base = 0;
537a1bf0 1297 mutex_lock(&fbi->mm_lock);
6e1588cb
GL		 1298 fbi->fix.smem_start = 0;
1299 fbi->fix.smem_len = 0;
537a1bf0 1300 mutex_unlock(&fbi->mm_lock);
6e1588cb 1301 return 0;
86528da2
GL		 1302}
1303
1304/**
1305 * mx3fb_init_fbinfo() - initialize framebuffer information object.
6e1588cb 1306 * @return: initialized framebuffer structure.
86528da2
GL		 1307 */
1308static struct fb_info *mx3fb_init_fbinfo(struct device *dev, struct fb_ops *ops)
1309{
6e1588cb
GL		 1310 struct fb_info *fbi;
1311 struct mx3fb_info *mx3fbi;
1312 int ret;
86528da2 1313
6e1588cb
GL		 1314 /* Allocate sufficient memory for the fb structure */
1315 fbi = framebuffer_alloc(sizeof(struct mx3fb_info), dev);
1316 if (!fbi)
1317 return NULL;
86528da2 1318
6e1588cb
GL		 1319 mx3fbi = fbi->par;
1320 mx3fbi->cookie = -EINVAL;
1321 mx3fbi->cur_ipu_buf = 0;
86528da2 1322
6e1588cb 1323 fbi->var.activate = FB_ACTIVATE_NOW;
86528da2 1324
6e1588cb
GL		 1325 fbi->fbops = ops;
1326 fbi->flags = FBINFO_FLAG_DEFAULT;
1327 fbi->pseudo_palette = mx3fbi->pseudo_palette;
86528da2 1328
6e1588cb 1329 mutex_init(&mx3fbi->mutex);
86528da2 1330
6e1588cb
GL		 1331 /* Allocate colormap */
1332 ret = fb_alloc_cmap(&fbi->cmap, 16, 0);
1333 if (ret < 0) {
1334 framebuffer_release(fbi);
1335 return NULL;
1336 }
86528da2 1337
6e1588cb 1338 return fbi;
86528da2
GL		 1339}
1340
1341static int init_fb_chan(struct mx3fb_data *mx3fb, struct idmac_channel *ichan)
1342{
6e1588cb
GL		 1343 struct device *dev = mx3fb->dev;
1344 struct mx3fb_platform_data *mx3fb_pdata = dev->platform_data;
1345 const char *name = mx3fb_pdata->name;
1346 unsigned int irq;
1347 struct fb_info *fbi;
1348 struct mx3fb_info *mx3fbi;
1349 const struct fb_videomode *mode;
1350 int ret, num_modes;
86528da2 1351
6e1588cb
GL		 1352 ichan->client = mx3fb;
1353 irq = ichan->eof_irq;
86528da2 1354
6e1588cb
GL		 1355 if (ichan->dma_chan.chan_id != IDMAC_SDC_0)
1356 return -EINVAL;
86528da2 1357
6e1588cb
GL		 1358 fbi = mx3fb_init_fbinfo(dev, &mx3fb_ops);
1359 if (!fbi)
1360 return -ENOMEM;
86528da2 1361
6e1588cb
GL		 1362 if (!fb_mode)
1363 fb_mode = name;
86528da2 1364
6e1588cb
GL		 1365 if (!fb_mode) {
1366 ret = -EINVAL;
1367 goto emode;
1368 }
86528da2 1369
6e1588cb
GL		 1370 if (mx3fb_pdata->mode && mx3fb_pdata->num_modes) {
1371 mode = mx3fb_pdata->mode;
1372 num_modes = mx3fb_pdata->num_modes;
1373 } else {
1374 mode = mx3fb_modedb;
1375 num_modes = ARRAY_SIZE(mx3fb_modedb);
1376 }
86528da2 1377
6e1588cb
GL		 1378 if (!fb_find_mode(&fbi->var, fbi, fb_mode, mode,
1379 num_modes, NULL, default_bpp)) {
1380 ret = -EBUSY;
1381 goto emode;
1382 }
86528da2 1383
6e1588cb 1384 fb_videomode_to_modelist(mode, num_modes, &fbi->modelist);
86528da2 1385
6e1588cb
GL		 1386 /* Default Y virtual size is 2x panel size */
1387 fbi->var.yres_virtual = fbi->var.yres * 2;
86528da2 1388
6e1588cb 1389 mx3fb->fbi = fbi;
86528da2 1390
6e1588cb
GL		 1391 /* set Display Interface clock period */
1392 mx3fb_write_reg(mx3fb, 0x00100010L, DI_HSP_CLK_PER);
1393 /* Might need to trigger HSP clock change - see 44.3.3.8.5 */
86528da2 1394
6e1588cb
GL		 1395 sdc_set_brightness(mx3fb, 255);
1396 sdc_set_global_alpha(mx3fb, true, 0xFF);
1397 sdc_set_color_key(mx3fb, IDMAC_SDC_0, false, 0);
86528da2 1398
6e1588cb
GL		 1399 mx3fbi = fbi->par;
1400 mx3fbi->idmac_channel = ichan;
1401 mx3fbi->ipu_ch = ichan->dma_chan.chan_id;
1402 mx3fbi->mx3fb = mx3fb;
1403 mx3fbi->blank = FB_BLANK_NORMAL;
86528da2 1404
6e1588cb
GL		 1405 init_completion(&mx3fbi->flip_cmpl);
1406 disable_irq(ichan->eof_irq);
1407 dev_dbg(mx3fb->dev, "disabling irq %d\n", ichan->eof_irq);
20de03da
GL		 1408 ret = __set_par(fbi, false);
1409 if (ret < 0)
1410 goto esetpar;
1411
1412 __blank(FB_BLANK_UNBLANK, fbi);
86528da2 1413
2eec8c31 1414 dev_info(dev, "registered, using mode %s\n", fb_mode);
86528da2 1415
6e1588cb
GL		 1416 ret = register_framebuffer(fbi);
1417 if (ret < 0)
1418 goto erfb;
86528da2 1419
6e1588cb 1420 return 0;
86528da2
GL		 1421
1422erfb:
1423esetpar:
1424emode:
6e1588cb
GL		 1425 fb_dealloc_cmap(&fbi->cmap);
1426 framebuffer_release(fbi);
86528da2 1427
6e1588cb 1428 return ret;
86528da2
GL		 1429}
1430
1431static bool chan_filter(struct dma_chan *chan, void *arg)
1432{
6e1588cb
GL		 1433 struct dma_chan_request *rq = arg;
1434 struct device *dev;
1435 struct mx3fb_platform_data *mx3fb_pdata;
86528da2 1436
1b346af2
SH		 1437 if (!imx_dma_is_ipu(chan))
1438 return false;
1439
6e1588cb
GL		 1440 if (!rq)
1441 return false;
86528da2 1442
6e1588cb
GL		 1443 dev = rq->mx3fb->dev;
1444 mx3fb_pdata = dev->platform_data;
86528da2 1445
6e1588cb
GL		 1446 return rq->id == chan->chan_id &&
1447 mx3fb_pdata->dma_dev == chan->device->dev;
86528da2
GL		 1448}
1449
1450static void release_fbi(struct fb_info *fbi)
1451{
6e1588cb 1452 mx3fb_unmap_video_memory(fbi);
86528da2 1453
6e1588cb 1454 fb_dealloc_cmap(&fbi->cmap);
86528da2 1455
6e1588cb
GL		 1456 unregister_framebuffer(fbi);
1457 framebuffer_release(fbi);
86528da2
GL		 1458}
1459
1460static int mx3fb_probe(struct platform_device *pdev)
1461{
6e1588cb
GL		 1462 struct device *dev = &pdev->dev;
1463 int ret;
1464 struct resource *sdc_reg;
1465 struct mx3fb_data *mx3fb;
1466 dma_cap_mask_t mask;
1467 struct dma_chan *chan;
1468 struct dma_chan_request rq;
1469
1470 /*
1471 * Display Interface (DI) and Synchronous Display Controller (SDC)
1472 * registers
1473 */
1474 sdc_reg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1475 if (!sdc_reg)
1476 return -EINVAL;
1477
1478 mx3fb = kzalloc(sizeof(*mx3fb), GFP_KERNEL);
1479 if (!mx3fb)
1480 return -ENOMEM;
1481
1482 spin_lock_init(&mx3fb->lock);
1483
1484 mx3fb->reg_base = ioremap(sdc_reg->start, resource_size(sdc_reg));
1485 if (!mx3fb->reg_base) {
1486 ret = -ENOMEM;
1487 goto eremap;
1488 }
1489
3b80ffde 1490 pr_debug("Remapped %pR at %p\n", sdc_reg, mx3fb->reg_base);
6e1588cb
GL		 1491
1492 /* IDMAC interface */
1493 dmaengine_get();
1494
1495 mx3fb->dev = dev;
1496 platform_set_drvdata(pdev, mx3fb);
1497
1498 rq.mx3fb = mx3fb;
1499
1500 dma_cap_zero(mask);
1501 dma_cap_set(DMA_SLAVE, mask);
1502 dma_cap_set(DMA_PRIVATE, mask);
1503 rq.id = IDMAC_SDC_0;
1504 chan = dma_request_channel(mask, chan_filter, &rq);
1505 if (!chan) {
1506 ret = -EBUSY;
1507 goto ersdc0;
1508 }
1509
b3cb5372
AP		 1510 mx3fb->backlight_level = 255;
1511
6e1588cb
GL		 1512 ret = init_fb_chan(mx3fb, to_idmac_chan(chan));
1513 if (ret < 0)
1514 goto eisdc0;
1515
6e1588cb 1516 return 0;
86528da2
GL		 1517
1518eisdc0:
6e1588cb 1519 dma_release_channel(chan);
86528da2 1520ersdc0:
6e1588cb
GL		 1521 dmaengine_put();
1522 iounmap(mx3fb->reg_base);
86528da2 1523eremap:
6e1588cb
GL		 1524 kfree(mx3fb);
1525 dev_err(dev, "mx3fb: failed to register fb\n");
1526 return ret;
86528da2
GL		 1527}
1528
1529static int mx3fb_remove(struct platform_device *dev)
1530{
6e1588cb
GL		 1531 struct mx3fb_data *mx3fb = platform_get_drvdata(dev);
1532 struct fb_info *fbi = mx3fb->fbi;
1533 struct mx3fb_info *mx3_fbi = fbi->par;
1534 struct dma_chan *chan;
86528da2 1535
6e1588cb
GL		 1536 chan = &mx3_fbi->idmac_channel->dma_chan;
1537 release_fbi(fbi);
86528da2 1538
6e1588cb
GL		 1539 dma_release_channel(chan);
1540 dmaengine_put();
86528da2 1541
6e1588cb
GL		 1542 iounmap(mx3fb->reg_base);
1543 kfree(mx3fb);
1544 return 0;
86528da2
GL		 1545}
1546
1547static struct platform_driver mx3fb_driver = {
6e1588cb
GL		 1548 .driver = {
1549 .name = MX3FB_NAME,
1550 },
1551 .probe = mx3fb_probe,
1552 .remove = mx3fb_remove,
1553 .suspend = mx3fb_suspend,
1554 .resume = mx3fb_resume,
86528da2
GL		 1555};
1556
1557/*
1558 * Parse user specified options (`video=mx3fb:')
1559 * example:
6e1588cb 1560 * video=mx3fb:bpp=16
86528da2 1561 */
d88ca815 1562static int __init mx3fb_setup(void)
86528da2
GL		 1563{
1564#ifndef MODULE
6e1588cb
GL		 1565 char *opt, *options = NULL;
1566
1567 if (fb_get_options("mx3fb", &options))
1568 return -ENODEV;
1569
1570 if (!options || !*options)
1571 return 0;
1572
1573 while ((opt = strsep(&options, ",")) != NULL) {
1574 if (!*opt)
1575 continue;
1576 if (!strncmp(opt, "bpp=", 4))
1577 default_bpp = simple_strtoul(opt + 4, NULL, 0);
1578 else
1579 fb_mode = opt;
1580 }
86528da2
GL		 1581#endif
1582
6e1588cb 1583 return 0;
86528da2
GL		 1584}
1585
1586static int __init mx3fb_init(void)
1587{
6e1588cb 1588 int ret = mx3fb_setup();
86528da2 1589
6e1588cb
GL		 1590 if (ret < 0)
1591 return ret;
86528da2 1592
6e1588cb
GL		 1593 ret = platform_driver_register(&mx3fb_driver);
1594 return ret;
86528da2
GL		 1595}
1596
1597static void __exit mx3fb_exit(void)
1598{
6e1588cb 1599 platform_driver_unregister(&mx3fb_driver);
86528da2
GL		 1600}
1601
1602module_init(mx3fb_init);
1603module_exit(mx3fb_exit);
1604
1605MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1606MODULE_DESCRIPTION("MX3 framebuffer driver");
1607MODULE_ALIAS("platform:" MX3FB_NAME);
1608MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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