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1da177e4 LT |
1 | #ifndef __NV_TYPE_H__ |
2 | #define __NV_TYPE_H__ | |
3 | ||
4 | #include <linux/fb.h> | |
5 | #include <linux/types.h> | |
6 | #include <linux/i2c.h> | |
1da177e4 | 7 | #include <linux/i2c-algo-bit.h> |
7dfe50b3 | 8 | #include <video/vga.h> |
1da177e4 LT |
9 | |
10 | #define NV_ARCH_04 0x04 | |
11 | #define NV_ARCH_10 0x10 | |
12 | #define NV_ARCH_20 0x20 | |
13 | #define NV_ARCH_30 0x30 | |
14 | #define NV_ARCH_40 0x40 | |
15 | ||
16 | #define BITMASK(t,b) (((unsigned)(1U << (((t)-(b)+1)))-1) << (b)) | |
17 | #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) | |
18 | #define SetBF(mask,value) ((value) << (0?mask)) | |
19 | #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) | |
20 | #define SetBitField(value,from,to) SetBF(to, GetBF(value,from)) | |
21 | #define SetBit(n) (1<<(n)) | |
22 | #define Set8Bits(value) ((value)&0xff) | |
23 | ||
24 | #define V_DBLSCAN 1 | |
25 | ||
26 | typedef struct { | |
27 | int bitsPerPixel; | |
28 | int depth; | |
29 | int displayWidth; | |
30 | int weight; | |
31 | } NVFBLayout; | |
32 | ||
33 | #define NUM_SEQ_REGS 0x05 | |
34 | #define NUM_CRT_REGS 0x41 | |
35 | #define NUM_GRC_REGS 0x09 | |
36 | #define NUM_ATC_REGS 0x15 | |
37 | ||
38 | struct nvidia_par; | |
39 | ||
40 | struct nvidia_i2c_chan { | |
41 | struct nvidia_par *par; | |
42 | unsigned long ddc_base; | |
43 | struct i2c_adapter adapter; | |
44 | struct i2c_algo_bit_data algo; | |
45 | }; | |
46 | ||
47 | typedef struct _riva_hw_state { | |
48 | u8 attr[NUM_ATC_REGS]; | |
49 | u8 crtc[NUM_CRT_REGS]; | |
50 | u8 gra[NUM_GRC_REGS]; | |
51 | u8 seq[NUM_SEQ_REGS]; | |
52 | u8 misc_output; | |
53 | u32 bpp; | |
54 | u32 width; | |
55 | u32 height; | |
56 | u32 interlace; | |
57 | u32 repaint0; | |
58 | u32 repaint1; | |
59 | u32 screen; | |
60 | u32 scale; | |
61 | u32 dither; | |
62 | u32 extra; | |
63 | u32 fifo; | |
64 | u32 pixel; | |
65 | u32 horiz; | |
66 | u32 arbitration0; | |
67 | u32 arbitration1; | |
68 | u32 pll; | |
69 | u32 pllB; | |
70 | u32 vpll; | |
71 | u32 vpll2; | |
72 | u32 vpllB; | |
73 | u32 vpll2B; | |
74 | u32 pllsel; | |
75 | u32 general; | |
76 | u32 crtcOwner; | |
77 | u32 head; | |
78 | u32 head2; | |
79 | u32 config; | |
80 | u32 cursorConfig; | |
81 | u32 cursor0; | |
82 | u32 cursor1; | |
83 | u32 cursor2; | |
84 | u32 timingH; | |
85 | u32 timingV; | |
86 | u32 displayV; | |
87 | u32 crtcSync; | |
ac1ae162 | 88 | u32 control; |
1da177e4 LT |
89 | } RIVA_HW_STATE; |
90 | ||
91 | struct riva_regs { | |
92 | RIVA_HW_STATE ext; | |
93 | }; | |
94 | ||
95 | struct nvidia_par { | |
96 | RIVA_HW_STATE SavedReg; | |
97 | RIVA_HW_STATE ModeReg; | |
7dfe50b3 | 98 | RIVA_HW_STATE initial_state; |
1da177e4 | 99 | RIVA_HW_STATE *CurrentState; |
7dfe50b3 | 100 | struct vgastate vgastate; |
1da177e4 LT |
101 | u32 pseudo_palette[16]; |
102 | struct pci_dev *pci_dev; | |
103 | u32 Architecture; | |
104 | u32 CursorStart; | |
105 | int Chipset; | |
1da177e4 LT |
106 | unsigned long FbAddress; |
107 | u8 __iomem *FbStart; | |
108 | u32 FbMapSize; | |
109 | u32 FbUsableSize; | |
110 | u32 ScratchBufferSize; | |
111 | u32 ScratchBufferStart; | |
112 | int FpScale; | |
113 | u32 MinVClockFreqKHz; | |
114 | u32 MaxVClockFreqKHz; | |
115 | u32 CrystalFreqKHz; | |
116 | u32 RamAmountKBytes; | |
117 | u32 IOBase; | |
118 | NVFBLayout CurrentLayout; | |
119 | int cursor_reset; | |
120 | int lockup; | |
121 | int videoKey; | |
122 | int FlatPanel; | |
123 | int FPDither; | |
124 | int Television; | |
125 | int CRTCnumber; | |
126 | int alphaCursor; | |
127 | int twoHeads; | |
128 | int twoStagePLL; | |
129 | int fpScaler; | |
130 | int fpWidth; | |
131 | int fpHeight; | |
132 | int PanelTweak; | |
133 | int paneltweak; | |
e40c6759 | 134 | int LVDS; |
7a07cd78 | 135 | int pm_state; |
3c03ec20 | 136 | int reverse_i2c; |
1da177e4 LT |
137 | u32 crtcSync_read; |
138 | u32 fpSyncs; | |
139 | u32 dmaPut; | |
140 | u32 dmaCurrent; | |
141 | u32 dmaFree; | |
142 | u32 dmaMax; | |
143 | u32 __iomem *dmaBase; | |
144 | u32 currentRop; | |
145 | int WaitVSyncPossible; | |
146 | int BlendingPossible; | |
147 | u32 paletteEnabled; | |
148 | u32 forceCRTC; | |
7dfe50b3 | 149 | u32 open_count; |
1da177e4 LT |
150 | u8 DDCBase; |
151 | #ifdef CONFIG_MTRR | |
152 | struct { | |
153 | int vram; | |
154 | int vram_valid; | |
155 | } mtrr; | |
156 | #endif | |
157 | struct nvidia_i2c_chan chan[3]; | |
158 | ||
159 | volatile u32 __iomem *REGS; | |
160 | volatile u32 __iomem *PCRTC0; | |
161 | volatile u32 __iomem *PCRTC; | |
162 | volatile u32 __iomem *PRAMDAC0; | |
163 | volatile u32 __iomem *PFB; | |
164 | volatile u32 __iomem *PFIFO; | |
165 | volatile u32 __iomem *PGRAPH; | |
166 | volatile u32 __iomem *PEXTDEV; | |
167 | volatile u32 __iomem *PTIMER; | |
168 | volatile u32 __iomem *PMC; | |
169 | volatile u32 __iomem *PRAMIN; | |
170 | volatile u32 __iomem *FIFO; | |
171 | volatile u32 __iomem *CURSOR; | |
172 | volatile u8 __iomem *PCIO0; | |
173 | volatile u8 __iomem *PCIO; | |
174 | volatile u8 __iomem *PVIO; | |
175 | volatile u8 __iomem *PDIO0; | |
176 | volatile u8 __iomem *PDIO; | |
177 | volatile u32 __iomem *PRAMDAC; | |
178 | }; | |
179 | ||
180 | #endif /* __NV_TYPE_H__ */ |