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OMAPDSS: use DSI_FIFO_BUG workaround only for manual update displays
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
80c39712
TV		 122static void _omap_dispc_set_irqs(void);
123
55978cc2 124static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 125{
55978cc2 126 __raw_writel(val, dispc.base + idx);
80c39712
TV		 127}
128
55978cc2 129static inline u32 dispc_read_reg(const u16 idx)
80c39712 130{
55978cc2 131 return __raw_readl(dispc.base + idx);
80c39712
TV		 132}
133
134#define SR(reg) \
55978cc2 135 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 136#define RR(reg) \
55978cc2 137 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 138
4fbafaf3 139static void dispc_save_context(void)
80c39712 140{
c6104b8e 141 int i, j;
80c39712 142
4fbafaf3
TV		 143 DSSDBG("dispc_save_context\n");
144
80c39712
TV		 145 SR(IRQENABLE);
146 SR(CONTROL);
147 SR(CONFIG);
80c39712 148 SR(LINE_NUMBER);
11354dd5
AT		 149 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
150 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 151 SR(GLOBAL_ALPHA);
2a205f34
SS		 152 if (dss_has_feature(FEAT_MGR_LCD2)) {
153 SR(CONTROL2);
2a205f34
SS		 154 SR(CONFIG2);
155 }
80c39712 156
c6104b8e
AT		 157 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
158 SR(DEFAULT_COLOR(i));
159 SR(TRANS_COLOR(i));
160 SR(SIZE_MGR(i));
161 if (i == OMAP_DSS_CHANNEL_DIGIT)
162 continue;
163 SR(TIMING_H(i));
164 SR(TIMING_V(i));
165 SR(POL_FREQ(i));
166 SR(DIVISORo(i));
167
168 SR(DATA_CYCLE1(i));
169 SR(DATA_CYCLE2(i));
170 SR(DATA_CYCLE3(i));
171
332e9d70 172 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 173 SR(CPR_COEF_R(i));
174 SR(CPR_COEF_G(i));
175 SR(CPR_COEF_B(i));
332e9d70 176 }
2a205f34 177 }
80c39712 178
c6104b8e
AT		 179 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
180 SR(OVL_BA0(i));
181 SR(OVL_BA1(i));
182 SR(OVL_POSITION(i));
183 SR(OVL_SIZE(i));
184 SR(OVL_ATTRIBUTES(i));
185 SR(OVL_FIFO_THRESHOLD(i));
186 SR(OVL_ROW_INC(i));
187 SR(OVL_PIXEL_INC(i));
188 if (dss_has_feature(FEAT_PRELOAD))
189 SR(OVL_PRELOAD(i));
190 if (i == OMAP_DSS_GFX) {
191 SR(OVL_WINDOW_SKIP(i));
192 SR(OVL_TABLE_BA(i));
193 continue;
194 }
195 SR(OVL_FIR(i));
196 SR(OVL_PICTURE_SIZE(i));
197 SR(OVL_ACCU0(i));
198 SR(OVL_ACCU1(i));
9b372c2d 199
c6104b8e
AT		 200 for (j = 0; j < 8; j++)
201 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 202
c6104b8e
AT		 203 for (j = 0; j < 8; j++)
204 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 205
c6104b8e
AT		 206 for (j = 0; j < 5; j++)
207 SR(OVL_CONV_COEF(i, j));
ab5ca071 208
c6104b8e
AT		 209 if (dss_has_feature(FEAT_FIR_COEF_V)) {
210 for (j = 0; j < 8; j++)
211 SR(OVL_FIR_COEF_V(i, j));
212 }
9b372c2d 213
c6104b8e
AT		 214 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
215 SR(OVL_BA0_UV(i));
216 SR(OVL_BA1_UV(i));
217 SR(OVL_FIR2(i));
218 SR(OVL_ACCU2_0(i));
219 SR(OVL_ACCU2_1(i));
ab5ca071 220
c6104b8e
AT		 221 for (j = 0; j < 8; j++)
222 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 223
c6104b8e
AT		 224 for (j = 0; j < 8; j++)
225 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 226
c6104b8e
AT		 227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V2(i, j));
229 }
230 if (dss_has_feature(FEAT_ATTR2))
231 SR(OVL_ATTRIBUTES2(i));
ab5ca071 232 }
0cf35df3
MR		 233
234 if (dss_has_feature(FEAT_CORE_CLK_DIV))
235 SR(DIVISOR);
49ea86f3 236
00928eaf 237 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 238 dispc.ctx_valid = true;
239
240 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 241}
242
4fbafaf3 243static void dispc_restore_context(void)
80c39712 244{
c6104b8e 245 int i, j, ctx;
4fbafaf3
TV		 246
247 DSSDBG("dispc_restore_context\n");
248
49ea86f3
TV		 249 if (!dispc.ctx_valid)
250 return;
251
00928eaf 252 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 253
254 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
255 return;
256
257 DSSDBG("ctx_loss_count: saved %d, current %d\n",
258 dispc.ctx_loss_cnt, ctx);
259
75c7d59d 260 /*RR(IRQENABLE);*/
80c39712
TV		 261 /*RR(CONTROL);*/
262 RR(CONFIG);
80c39712 263 RR(LINE_NUMBER);
11354dd5
AT		 264 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
265 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 266 RR(GLOBAL_ALPHA);
c6104b8e 267 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 268 RR(CONFIG2);
80c39712 269
c6104b8e
AT		 270 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
271 RR(DEFAULT_COLOR(i));
272 RR(TRANS_COLOR(i));
273 RR(SIZE_MGR(i));
274 if (i == OMAP_DSS_CHANNEL_DIGIT)
275 continue;
276 RR(TIMING_H(i));
277 RR(TIMING_V(i));
278 RR(POL_FREQ(i));
279 RR(DIVISORo(i));
280
281 RR(DATA_CYCLE1(i));
282 RR(DATA_CYCLE2(i));
283 RR(DATA_CYCLE3(i));
2a205f34 284
332e9d70 285 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 286 RR(CPR_COEF_R(i));
287 RR(CPR_COEF_G(i));
288 RR(CPR_COEF_B(i));
332e9d70 289 }
2a205f34 290 }
80c39712 291
c6104b8e
AT		 292 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
293 RR(OVL_BA0(i));
294 RR(OVL_BA1(i));
295 RR(OVL_POSITION(i));
296 RR(OVL_SIZE(i));
297 RR(OVL_ATTRIBUTES(i));
298 RR(OVL_FIFO_THRESHOLD(i));
299 RR(OVL_ROW_INC(i));
300 RR(OVL_PIXEL_INC(i));
301 if (dss_has_feature(FEAT_PRELOAD))
302 RR(OVL_PRELOAD(i));
303 if (i == OMAP_DSS_GFX) {
304 RR(OVL_WINDOW_SKIP(i));
305 RR(OVL_TABLE_BA(i));
306 continue;
307 }
308 RR(OVL_FIR(i));
309 RR(OVL_PICTURE_SIZE(i));
310 RR(OVL_ACCU0(i));
311 RR(OVL_ACCU1(i));
9b372c2d 312
c6104b8e
AT		 313 for (j = 0; j < 8; j++)
314 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 315
c6104b8e
AT		 316 for (j = 0; j < 8; j++)
317 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 318
c6104b8e
AT		 319 for (j = 0; j < 5; j++)
320 RR(OVL_CONV_COEF(i, j));
ab5ca071 321
c6104b8e
AT		 322 if (dss_has_feature(FEAT_FIR_COEF_V)) {
323 for (j = 0; j < 8; j++)
324 RR(OVL_FIR_COEF_V(i, j));
325 }
9b372c2d 326
c6104b8e
AT		 327 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
328 RR(OVL_BA0_UV(i));
329 RR(OVL_BA1_UV(i));
330 RR(OVL_FIR2(i));
331 RR(OVL_ACCU2_0(i));
332 RR(OVL_ACCU2_1(i));
ab5ca071 333
c6104b8e
AT		 334 for (j = 0; j < 8; j++)
335 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 336
c6104b8e
AT		 337 for (j = 0; j < 8; j++)
338 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 339
c6104b8e
AT		 340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V2(i, j));
342 }
343 if (dss_has_feature(FEAT_ATTR2))
344 RR(OVL_ATTRIBUTES2(i));
ab5ca071 345 }
80c39712 346
0cf35df3
MR		 347 if (dss_has_feature(FEAT_CORE_CLK_DIV))
348 RR(DIVISOR);
349
80c39712
TV		 350 /* enable last, because LCD & DIGIT enable are here */
351 RR(CONTROL);
2a205f34
SS		 352 if (dss_has_feature(FEAT_MGR_LCD2))
353 RR(CONTROL2);
75c7d59d
VS		 354 /* clear spurious SYNC_LOST_DIGIT interrupts */
355 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
356
357 /*
358 * enable last so IRQs won't trigger before
359 * the context is fully restored
360 */
361 RR(IRQENABLE);
49ea86f3
TV		 362
363 DSSDBG("context restored\n");
80c39712
TV		 364}
365
366#undef SR
367#undef RR
368
4fbafaf3
TV		 369int dispc_runtime_get(void)
370{
371 int r;
372
373 DSSDBG("dispc_runtime_get\n");
374
375 r = pm_runtime_get_sync(&dispc.pdev->dev);
376 WARN_ON(r < 0);
377 return r < 0 ? r : 0;
378}
379
380void dispc_runtime_put(void)
381{
382 int r;
383
384 DSSDBG("dispc_runtime_put\n");
385
0eaf9f52 386 r = pm_runtime_put_sync(&dispc.pdev->dev);
4fbafaf3 387 WARN_ON(r < 0);
80c39712
TV		 388}
389
dac57a05
AT		 390static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
391{
392 if (channel == OMAP_DSS_CHANNEL_LCD ||
393 channel == OMAP_DSS_CHANNEL_LCD2)
394 return true;
395 else
396 return false;
397}
4fbafaf3 398
3dcec4d6
TV		 399u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
400{
401 switch (channel) {
402 case OMAP_DSS_CHANNEL_LCD:
403 return DISPC_IRQ_VSYNC;
404 case OMAP_DSS_CHANNEL_LCD2:
405 return DISPC_IRQ_VSYNC2;
406 case OMAP_DSS_CHANNEL_DIGIT:
407 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
408 default:
409 BUG();
410 }
411}
412
7d1365c9
TV		 413u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
414{
415 switch (channel) {
416 case OMAP_DSS_CHANNEL_LCD:
417 return DISPC_IRQ_FRAMEDONE;
418 case OMAP_DSS_CHANNEL_LCD2:
419 return DISPC_IRQ_FRAMEDONE2;
420 case OMAP_DSS_CHANNEL_DIGIT:
421 return 0;
422 default:
423 BUG();
424 }
425}
426
26d9dd0d 427bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 428{
429 int bit;
430
dac57a05 431 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 432 bit = 5; /* GOLCD */
433 else
434 bit = 6; /* GODIGIT */
435
2a205f34
SS		 436 if (channel == OMAP_DSS_CHANNEL_LCD2)
437 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
438 else
439 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 440}
441
26d9dd0d 442void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 443{
444 int bit;
2a205f34 445 bool enable_bit, go_bit;
80c39712 446
dac57a05 447 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 448 bit = 0; /* LCDENABLE */
449 else
450 bit = 1; /* DIGITALENABLE */
451
452 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 453 if (channel == OMAP_DSS_CHANNEL_LCD2)
454 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
455 else
456 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
457
458 if (!enable_bit)
e6d80f95 459 return;
80c39712 460
dac57a05 461 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 462 bit = 5; /* GOLCD */
463 else
464 bit = 6; /* GODIGIT */
465
2a205f34
SS		 466 if (channel == OMAP_DSS_CHANNEL_LCD2)
467 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
468 else
469 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
470
471 if (go_bit) {
80c39712 472 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 473 return;
80c39712
TV		 474 }
475
2a205f34
SS		 476 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
477 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 478
2a205f34
SS		 479 if (channel == OMAP_DSS_CHANNEL_LCD2)
480 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
481 else
482 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 483}
484
f0e5caab 485static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 486{
9b372c2d 487 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 488}
489
f0e5caab 490static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 491{
9b372c2d 492 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 493}
494
f0e5caab 495static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 496{
9b372c2d 497 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 498}
499
f0e5caab 500static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 501{
502 BUG_ON(plane == OMAP_DSS_GFX);
503
504 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
505}
506
f0e5caab
TV		 507static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
508 u32 value)
ab5ca071
AJ		 509{
510 BUG_ON(plane == OMAP_DSS_GFX);
511
512 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
513}
514
f0e5caab 515static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 516{
517 BUG_ON(plane == OMAP_DSS_GFX);
518
519 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
520}
521
debd9074
CM		 522static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
523 int fir_vinc, int five_taps,
524 enum omap_color_component color_comp)
80c39712 525{
debd9074 526 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 527 int i;
528
debd9074
CM		 529 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
530 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 531
532 for (i = 0; i < 8; i++) {
533 u32 h, hv;
534
debd9074
CM		 535 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
536 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
537 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
538 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
539 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
540 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
541 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
542 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 543
0d66cbb5 544 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 545 dispc_ovl_write_firh_reg(plane, i, h);
546 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 547 } else {
f0e5caab
TV		 548 dispc_ovl_write_firh2_reg(plane, i, h);
549 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 550 }
551
80c39712
TV		 552 }
553
66be8f6c
GI		 554 if (five_taps) {
555 for (i = 0; i < 8; i++) {
556 u32 v;
debd9074
CM		 557 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
558 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 559 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 560 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 561 else
f0e5caab 562 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 563 }
80c39712
TV		 564 }
565}
566
567static void _dispc_setup_color_conv_coef(void)
568{
ac01c29e 569 int i;
80c39712
TV		 570 const struct color_conv_coef {
571 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
572 int full_range;
573 } ctbl_bt601_5 = {
574 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
575 };
576
577 const struct color_conv_coef *ct;
578
579#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
580
581 ct = &ctbl_bt601_5;
582
ac01c29e
AT		 583 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
584 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
585 CVAL(ct->rcr, ct->ry));
586 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
587 CVAL(ct->gy, ct->rcb));
588 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
589 CVAL(ct->gcb, ct->gcr));
590 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
591 CVAL(ct->bcr, ct->by));
592 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
593 CVAL(0, ct->bcb));
594
595 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
596 11, 11);
597 }
80c39712
TV		 598
599#undef CVAL
80c39712
TV		 600}
601
602
f0e5caab 603static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 604{
9b372c2d 605 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 606}
607
f0e5caab 608static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 609{
9b372c2d 610 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 611}
612
f0e5caab 613static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 614{
615 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
616}
617
f0e5caab 618static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 619{
620 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
621}
622
f0e5caab 623static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 624{
80c39712 625 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 626
627 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 628}
629
f0e5caab 630static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 631{
80c39712 632 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 633
634 if (plane == OMAP_DSS_GFX)
635 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
636 else
637 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 638}
639
f0e5caab 640static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 641{
642 u32 val;
80c39712
TV		 643
644 BUG_ON(plane == OMAP_DSS_GFX);
645
646 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 647
648 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 649}
650
54128701
AT		 651static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
652{
653 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
654
655 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
656 return;
657
658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
659}
660
661static void dispc_ovl_enable_zorder_planes(void)
662{
663 int i;
664
665 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
666 return;
667
668 for (i = 0; i < dss_feat_get_num_ovls(); i++)
669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
670}
671
f0e5caab 672static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 673{
f6dc8150 674 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 675
f6dc8150 676 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 677 return;
678
9b372c2d 679 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 680}
681
f0e5caab 682static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 683{
b8c095b4 684 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 685 int shift;
f6dc8150 686 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 687
f6dc8150 688 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 689 return;
a0acb557 690
fe3cc9d6
TV		 691 shift = shifts[plane];
692 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 693}
694
f0e5caab 695static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 696{
9b372c2d 697 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 698}
699
f0e5caab 700static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 701{
9b372c2d 702 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 703}
704
f0e5caab 705static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 706 enum omap_color_mode color_mode)
707{
708 u32 m = 0;
f20e4220
AJ		 709 if (plane != OMAP_DSS_GFX) {
710 switch (color_mode) {
711 case OMAP_DSS_COLOR_NV12:
712 m = 0x0; break;
08f3267e 713 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 714 m = 0x1; break;
715 case OMAP_DSS_COLOR_RGBA16:
716 m = 0x2; break;
08f3267e 717 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 718 m = 0x4; break;
719 case OMAP_DSS_COLOR_ARGB16:
720 m = 0x5; break;
721 case OMAP_DSS_COLOR_RGB16:
722 m = 0x6; break;
723 case OMAP_DSS_COLOR_ARGB16_1555:
724 m = 0x7; break;
725 case OMAP_DSS_COLOR_RGB24U:
726 m = 0x8; break;
727 case OMAP_DSS_COLOR_RGB24P:
728 m = 0x9; break;
729 case OMAP_DSS_COLOR_YUV2:
730 m = 0xa; break;
731 case OMAP_DSS_COLOR_UYVY:
732 m = 0xb; break;
733 case OMAP_DSS_COLOR_ARGB32:
734 m = 0xc; break;
735 case OMAP_DSS_COLOR_RGBA32:
736 m = 0xd; break;
737 case OMAP_DSS_COLOR_RGBX32:
738 m = 0xe; break;
739 case OMAP_DSS_COLOR_XRGB16_1555:
740 m = 0xf; break;
741 default:
742 BUG(); break;
743 }
744 } else {
745 switch (color_mode) {
746 case OMAP_DSS_COLOR_CLUT1:
747 m = 0x0; break;
748 case OMAP_DSS_COLOR_CLUT2:
749 m = 0x1; break;
750 case OMAP_DSS_COLOR_CLUT4:
751 m = 0x2; break;
752 case OMAP_DSS_COLOR_CLUT8:
753 m = 0x3; break;
754 case OMAP_DSS_COLOR_RGB12U:
755 m = 0x4; break;
756 case OMAP_DSS_COLOR_ARGB16:
757 m = 0x5; break;
758 case OMAP_DSS_COLOR_RGB16:
759 m = 0x6; break;
760 case OMAP_DSS_COLOR_ARGB16_1555:
761 m = 0x7; break;
762 case OMAP_DSS_COLOR_RGB24U:
763 m = 0x8; break;
764 case OMAP_DSS_COLOR_RGB24P:
765 m = 0x9; break;
08f3267e 766 case OMAP_DSS_COLOR_RGBX16:
f20e4220 767 m = 0xa; break;
08f3267e 768 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 769 m = 0xb; break;
770 case OMAP_DSS_COLOR_ARGB32:
771 m = 0xc; break;
772 case OMAP_DSS_COLOR_RGBA32:
773 m = 0xd; break;
774 case OMAP_DSS_COLOR_RGBX32:
775 m = 0xe; break;
776 case OMAP_DSS_COLOR_XRGB16_1555:
777 m = 0xf; break;
778 default:
779 BUG(); break;
780 }
80c39712
TV		 781 }
782
9b372c2d 783 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 784}
785
f427984e 786void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 787{
788 int shift;
789 u32 val;
2a205f34 790 int chan = 0, chan2 = 0;
80c39712
TV		 791
792 switch (plane) {
793 case OMAP_DSS_GFX:
794 shift = 8;
795 break;
796 case OMAP_DSS_VIDEO1:
797 case OMAP_DSS_VIDEO2:
b8c095b4 798 case OMAP_DSS_VIDEO3:
80c39712
TV		 799 shift = 16;
800 break;
801 default:
802 BUG();
803 return;
804 }
805
9b372c2d 806 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 807 if (dss_has_feature(FEAT_MGR_LCD2)) {
808 switch (channel) {
809 case OMAP_DSS_CHANNEL_LCD:
810 chan = 0;
811 chan2 = 0;
812 break;
813 case OMAP_DSS_CHANNEL_DIGIT:
814 chan = 1;
815 chan2 = 0;
816 break;
817 case OMAP_DSS_CHANNEL_LCD2:
818 chan = 0;
819 chan2 = 1;
820 break;
821 default:
822 BUG();
823 }
824
825 val = FLD_MOD(val, chan, shift, shift);
826 val = FLD_MOD(val, chan2, 31, 30);
827 } else {
828 val = FLD_MOD(val, channel, shift, shift);
829 }
9b372c2d 830 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 831}
832
2cc5d1af
TV		 833static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
834{
835 int shift;
836 u32 val;
837 enum omap_channel channel;
838
839 switch (plane) {
840 case OMAP_DSS_GFX:
841 shift = 8;
842 break;
843 case OMAP_DSS_VIDEO1:
844 case OMAP_DSS_VIDEO2:
845 case OMAP_DSS_VIDEO3:
846 shift = 16;
847 break;
848 default:
849 BUG();
850 }
851
852 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
853
854 if (dss_has_feature(FEAT_MGR_LCD2)) {
855 if (FLD_GET(val, 31, 30) == 0)
856 channel = FLD_GET(val, shift, shift);
857 else
858 channel = OMAP_DSS_CHANNEL_LCD2;
859 } else {
860 channel = FLD_GET(val, shift, shift);
861 }
862
863 return channel;
864}
865
f0e5caab 866static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 867 enum omap_burst_size burst_size)
868{
b8c095b4 869 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 870 int shift;
80c39712 871
fe3cc9d6 872 shift = shifts[plane];
5ed8cf5b 873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 874}
875
5ed8cf5b
TV		 876static void dispc_configure_burst_sizes(void)
877{
878 int i;
879 const int burst_size = BURST_SIZE_X8;
880
881 /* Configure burst size always to maximum size */
882 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 883 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 884}
885
83fa2f2e 886static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 887{
888 unsigned unit = dss_feat_get_burst_size_unit();
889 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
890 return unit * 8;
891}
892
d3862610
M		 893void dispc_enable_gamma_table(bool enable)
894{
895 /*
896 * This is partially implemented to support only disabling of
897 * the gamma table.
898 */
899 if (enable) {
900 DSSWARN("Gamma table enabling for TV not yet supported");
901 return;
902 }
903
904 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
905}
906
c64dca40 907static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 908{
909 u16 reg;
910
911 if (channel == OMAP_DSS_CHANNEL_LCD)
912 reg = DISPC_CONFIG;
913 else if (channel == OMAP_DSS_CHANNEL_LCD2)
914 reg = DISPC_CONFIG2;
915 else
916 return;
917
918 REG_FLD_MOD(reg, enable, 15, 15);
919}
920
c64dca40 921static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 922 struct omap_dss_cpr_coefs *coefs)
923{
924 u32 coef_r, coef_g, coef_b;
925
dac57a05 926 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 927 return;
928
929 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
930 FLD_VAL(coefs->rb, 9, 0);
931 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
932 FLD_VAL(coefs->gb, 9, 0);
933 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
934 FLD_VAL(coefs->bb, 9, 0);
935
936 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
937 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
938 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
939}
940
f0e5caab 941static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 942{
943 u32 val;
944
945 BUG_ON(plane == OMAP_DSS_GFX);
946
9b372c2d 947 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 948 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 949 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 950}
951
c3d92529 952static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 953{
b8c095b4 954 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 955 int shift;
80c39712 956
fe3cc9d6
TV		 957 shift = shifts[plane];
958 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 959}
960
8f366162 961static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 962 u16 height)
80c39712
TV		 963{
964 u32 val;
80c39712 965
80c39712 966 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 967 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 968}
969
970static void dispc_read_plane_fifo_sizes(void)
971{
80c39712
TV		 972 u32 size;
973 int plane;
a0acb557 974 u8 start, end;
5ed8cf5b
TV		 975 u32 unit;
976
977 unit = dss_feat_get_buffer_size_unit();
80c39712 978
a0acb557 979 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 980
e13a138b 981 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 982 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
983 size *= unit;
80c39712
TV		 984 dispc.fifo_size[plane] = size;
985 }
80c39712
TV		 986}
987
83fa2f2e 988static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 989{
990 return dispc.fifo_size[plane];
991}
992
6f04e1bf 993void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 994{
a0acb557 995 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 996 u32 unit;
997
998 unit = dss_feat_get_buffer_size_unit();
999
1000 WARN_ON(low % unit != 0);
1001 WARN_ON(high % unit != 0);
1002
1003 low /= unit;
1004 high /= unit;
a0acb557 1005
9b372c2d
AT		 1006 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1007 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1008
3cb5d966 1009 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1010 plane,
9b372c2d 1011 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1012 lo_start, lo_end) * unit,
9b372c2d 1013 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1014 hi_start, hi_end) * unit,
1015 low * unit, high * unit);
80c39712 1016
9b372c2d 1017 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1018 FLD_VAL(high, hi_start, hi_end) |
1019 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1020}
1021
1022void dispc_enable_fifomerge(bool enable)
1023{
e6b0f884
TV		 1024 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1025 WARN_ON(enable);
1026 return;
1027 }
1028
80c39712
TV		 1029 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1030 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1031}
1032
83fa2f2e 1033void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1034 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1035 bool manual_update)
83fa2f2e
TV		 1036{
1037 /*
1038 * All sizes are in bytes. Both the buffer and burst are made of
1039 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1040 */
1041
1042 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1043 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1044 int i;
83fa2f2e
TV		 1045
1046 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1047 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1048
e0e405b9
TV		 1049 if (use_fifomerge) {
1050 total_fifo_size = 0;
1051 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1052 total_fifo_size += dispc_ovl_get_fifo_size(i);
1053 } else {
1054 total_fifo_size = ovl_fifo_size;
1055 }
1056
1057 /*
1058 * We use the same low threshold for both fifomerge and non-fifomerge
1059 * cases, but for fifomerge we calculate the high threshold using the
1060 * combined fifo size
1061 */
1062
3568f2a4 1063 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1064 *fifo_low = ovl_fifo_size - burst_size * 2;
1065 *fifo_high = total_fifo_size - burst_size;
1066 } else {
1067 *fifo_low = ovl_fifo_size - burst_size;
1068 *fifo_high = total_fifo_size - buf_unit;
1069 }
83fa2f2e
TV		 1070}
1071
f0e5caab 1072static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1073 int hinc, int vinc,
1074 enum omap_color_component color_comp)
80c39712
TV		 1075{
1076 u32 val;
80c39712 1077
0d66cbb5
AJ		 1078 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1079 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1080
0d66cbb5
AJ		 1081 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1082 &hinc_start, &hinc_end);
1083 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1084 &vinc_start, &vinc_end);
1085 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1086 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1087
0d66cbb5
AJ		 1088 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1089 } else {
1090 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1091 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1092 }
80c39712
TV		 1093}
1094
f0e5caab 1095static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1096{
1097 u32 val;
87a7484b 1098 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1099
87a7484b
AT		 1100 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1101 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1102
1103 val = FLD_VAL(vaccu, vert_start, vert_end) |
1104 FLD_VAL(haccu, hor_start, hor_end);
1105
9b372c2d 1106 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1107}
1108
f0e5caab 1109static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1110{
1111 u32 val;
87a7484b 1112 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1113
87a7484b
AT		 1114 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1115 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1116
1117 val = FLD_VAL(vaccu, vert_start, vert_end) |
1118 FLD_VAL(haccu, hor_start, hor_end);
1119
9b372c2d 1120 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1121}
1122
f0e5caab
TV		 1123static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1124 int vaccu)
ab5ca071
AJ		 1125{
1126 u32 val;
1127
1128 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1129 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1130}
1131
f0e5caab
TV		 1132static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1133 int vaccu)
ab5ca071
AJ		 1134{
1135 u32 val;
1136
1137 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1138 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1139}
80c39712 1140
f0e5caab 1141static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1142 u16 orig_width, u16 orig_height,
1143 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1144 bool five_taps, u8 rotation,
1145 enum omap_color_component color_comp)
80c39712 1146{
0d66cbb5 1147 int fir_hinc, fir_vinc;
80c39712 1148
ed14a3ce
AJ		 1149 fir_hinc = 1024 * orig_width / out_width;
1150 fir_vinc = 1024 * orig_height / out_height;
80c39712 1151
debd9074
CM		 1152 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1153 color_comp);
f0e5caab 1154 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1155}
1156
05dd0f53
CM		 1157static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1158 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1159 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1160{
1161 int h_accu2_0, h_accu2_1;
1162 int v_accu2_0, v_accu2_1;
1163 int chroma_hinc, chroma_vinc;
1164 int idx;
1165
1166 struct accu {
1167 s8 h0_m, h0_n;
1168 s8 h1_m, h1_n;
1169 s8 v0_m, v0_n;
1170 s8 v1_m, v1_n;
1171 };
1172
1173 const struct accu *accu_table;
1174 const struct accu *accu_val;
1175
1176 static const struct accu accu_nv12[4] = {
1177 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1178 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1179 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1180 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1181 };
1182
1183 static const struct accu accu_nv12_ilace[4] = {
1184 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1185 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1186 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1187 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1188 };
1189
1190 static const struct accu accu_yuv[4] = {
1191 { 0, 1, 0, 1, 0, 1, 0, 1 },
1192 { 0, 1, 0, 1, 0, 1, 0, 1 },
1193 { -1, 1, 0, 1, 0, 1, 0, 1 },
1194 { 0, 1, 0, 1, -1, 1, 0, 1 },
1195 };
1196
1197 switch (rotation) {
1198 case OMAP_DSS_ROT_0:
1199 idx = 0;
1200 break;
1201 case OMAP_DSS_ROT_90:
1202 idx = 1;
1203 break;
1204 case OMAP_DSS_ROT_180:
1205 idx = 2;
1206 break;
1207 case OMAP_DSS_ROT_270:
1208 idx = 3;
1209 break;
1210 default:
1211 BUG();
1212 }
1213
1214 switch (color_mode) {
1215 case OMAP_DSS_COLOR_NV12:
1216 if (ilace)
1217 accu_table = accu_nv12_ilace;
1218 else
1219 accu_table = accu_nv12;
1220 break;
1221 case OMAP_DSS_COLOR_YUV2:
1222 case OMAP_DSS_COLOR_UYVY:
1223 accu_table = accu_yuv;
1224 break;
1225 default:
1226 BUG();
1227 }
1228
1229 accu_val = &accu_table[idx];
1230
1231 chroma_hinc = 1024 * orig_width / out_width;
1232 chroma_vinc = 1024 * orig_height / out_height;
1233
1234 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1235 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1236 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1237 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1238
1239 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1240 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1241}
1242
f0e5caab 1243static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1244 u16 orig_width, u16 orig_height,
1245 u16 out_width, u16 out_height,
1246 bool ilace, bool five_taps,
1247 bool fieldmode, enum omap_color_mode color_mode,
1248 u8 rotation)
1249{
1250 int accu0 = 0;
1251 int accu1 = 0;
1252 u32 l;
80c39712 1253
f0e5caab 1254 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1255 out_width, out_height, five_taps,
1256 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1257 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1258
87a7484b
AT		 1259 /* RESIZEENABLE and VERTICALTAPS */
1260 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1261 l |= (orig_width != out_width) ? (1 << 5) : 0;
1262 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1263 l |= five_taps ? (1 << 21) : 0;
80c39712 1264
87a7484b
AT		 1265 /* VRESIZECONF and HRESIZECONF */
1266 if (dss_has_feature(FEAT_RESIZECONF)) {
1267 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1268 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1269 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1270 }
80c39712 1271
87a7484b
AT		 1272 /* LINEBUFFERSPLIT */
1273 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1274 l &= ~(0x1 << 22);
1275 l |= five_taps ? (1 << 22) : 0;
1276 }
80c39712 1277
9b372c2d 1278 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1279
1280 /*
1281 * field 0 = even field = bottom field
1282 * field 1 = odd field = top field
1283 */
1284 if (ilace && !fieldmode) {
1285 accu1 = 0;
0d66cbb5 1286 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1287 if (accu0 >= 1024/2) {
1288 accu1 = 1024/2;
1289 accu0 -= accu1;
1290 }
1291 }
1292
f0e5caab
TV		 1293 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1294 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1295}
1296
f0e5caab 1297static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1298 u16 orig_width, u16 orig_height,
1299 u16 out_width, u16 out_height,
1300 bool ilace, bool five_taps,
1301 bool fieldmode, enum omap_color_mode color_mode,
1302 u8 rotation)
1303{
1304 int scale_x = out_width != orig_width;
1305 int scale_y = out_height != orig_height;
1306
05dd0f53
CM		 1307 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1308 out_height, ilace, color_mode, rotation);
1309
0d66cbb5
AJ		 1310 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1311 return;
1312 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1313 color_mode != OMAP_DSS_COLOR_UYVY &&
1314 color_mode != OMAP_DSS_COLOR_NV12)) {
1315 /* reset chroma resampling for RGB formats */
1316 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1317 return;
1318 }
1319 switch (color_mode) {
1320 case OMAP_DSS_COLOR_NV12:
1321 /* UV is subsampled by 2 vertically*/
1322 orig_height >>= 1;
1323 /* UV is subsampled by 2 horz.*/
1324 orig_width >>= 1;
1325 break;
1326 case OMAP_DSS_COLOR_YUV2:
1327 case OMAP_DSS_COLOR_UYVY:
1328 /*For YUV422 with 90/270 rotation,
1329 *we don't upsample chroma
1330 */
1331 if (rotation == OMAP_DSS_ROT_0 ||
1332 rotation == OMAP_DSS_ROT_180)
1333 /* UV is subsampled by 2 hrz*/
1334 orig_width >>= 1;
1335 /* must use FIR for YUV422 if rotated */
1336 if (rotation != OMAP_DSS_ROT_0)
1337 scale_x = scale_y = true;
1338 break;
1339 default:
1340 BUG();
1341 }
1342
1343 if (out_width != orig_width)
1344 scale_x = true;
1345 if (out_height != orig_height)
1346 scale_y = true;
1347
f0e5caab 1348 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1349 out_width, out_height, five_taps,
1350 rotation, DISPC_COLOR_COMPONENT_UV);
1351
1352 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1353 (scale_x || scale_y) ? 1 : 0, 8, 8);
1354 /* set H scaling */
1355 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1356 /* set V scaling */
1357 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1358}
1359
f0e5caab 1360static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1361 u16 orig_width, u16 orig_height,
1362 u16 out_width, u16 out_height,
1363 bool ilace, bool five_taps,
1364 bool fieldmode, enum omap_color_mode color_mode,
1365 u8 rotation)
1366{
1367 BUG_ON(plane == OMAP_DSS_GFX);
1368
f0e5caab 1369 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1370 orig_width, orig_height,
1371 out_width, out_height,
1372 ilace, five_taps,
1373 fieldmode, color_mode,
1374 rotation);
1375
f0e5caab 1376 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1377 orig_width, orig_height,
1378 out_width, out_height,
1379 ilace, five_taps,
1380 fieldmode, color_mode,
1381 rotation);
1382}
1383
f0e5caab 1384static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1385 bool mirroring, enum omap_color_mode color_mode)
1386{
87a7484b
AT		 1387 bool row_repeat = false;
1388 int vidrot = 0;
1389
80c39712
TV		 1390 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1391 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1392
1393 if (mirroring) {
1394 switch (rotation) {
1395 case OMAP_DSS_ROT_0:
1396 vidrot = 2;
1397 break;
1398 case OMAP_DSS_ROT_90:
1399 vidrot = 1;
1400 break;
1401 case OMAP_DSS_ROT_180:
1402 vidrot = 0;
1403 break;
1404 case OMAP_DSS_ROT_270:
1405 vidrot = 3;
1406 break;
1407 }
1408 } else {
1409 switch (rotation) {
1410 case OMAP_DSS_ROT_0:
1411 vidrot = 0;
1412 break;
1413 case OMAP_DSS_ROT_90:
1414 vidrot = 1;
1415 break;
1416 case OMAP_DSS_ROT_180:
1417 vidrot = 2;
1418 break;
1419 case OMAP_DSS_ROT_270:
1420 vidrot = 3;
1421 break;
1422 }
1423 }
1424
80c39712 1425 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1426 row_repeat = true;
80c39712 1427 else
87a7484b 1428 row_repeat = false;
80c39712 1429 }
87a7484b 1430
9b372c2d 1431 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1432 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1433 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1434 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1435}
1436
1437static int color_mode_to_bpp(enum omap_color_mode color_mode)
1438{
1439 switch (color_mode) {
1440 case OMAP_DSS_COLOR_CLUT1:
1441 return 1;
1442 case OMAP_DSS_COLOR_CLUT2:
1443 return 2;
1444 case OMAP_DSS_COLOR_CLUT4:
1445 return 4;
1446 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1447 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1448 return 8;
1449 case OMAP_DSS_COLOR_RGB12U:
1450 case OMAP_DSS_COLOR_RGB16:
1451 case OMAP_DSS_COLOR_ARGB16:
1452 case OMAP_DSS_COLOR_YUV2:
1453 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1454 case OMAP_DSS_COLOR_RGBA16:
1455 case OMAP_DSS_COLOR_RGBX16:
1456 case OMAP_DSS_COLOR_ARGB16_1555:
1457 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1458 return 16;
1459 case OMAP_DSS_COLOR_RGB24P:
1460 return 24;
1461 case OMAP_DSS_COLOR_RGB24U:
1462 case OMAP_DSS_COLOR_ARGB32:
1463 case OMAP_DSS_COLOR_RGBA32:
1464 case OMAP_DSS_COLOR_RGBX32:
1465 return 32;
1466 default:
1467 BUG();
1468 }
1469}
1470
1471static s32 pixinc(int pixels, u8 ps)
1472{
1473 if (pixels == 1)
1474 return 1;
1475 else if (pixels > 1)
1476 return 1 + (pixels - 1) * ps;
1477 else if (pixels < 0)
1478 return 1 - (-pixels + 1) * ps;
1479 else
1480 BUG();
1481}
1482
1483static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1484 u16 screen_width,
1485 u16 width, u16 height,
1486 enum omap_color_mode color_mode, bool fieldmode,
1487 unsigned int field_offset,
1488 unsigned *offset0, unsigned *offset1,
aed74b55 1489 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1490{
1491 u8 ps;
1492
1493 /* FIXME CLUT formats */
1494 switch (color_mode) {
1495 case OMAP_DSS_COLOR_CLUT1:
1496 case OMAP_DSS_COLOR_CLUT2:
1497 case OMAP_DSS_COLOR_CLUT4:
1498 case OMAP_DSS_COLOR_CLUT8:
1499 BUG();
1500 return;
1501 case OMAP_DSS_COLOR_YUV2:
1502 case OMAP_DSS_COLOR_UYVY:
1503 ps = 4;
1504 break;
1505 default:
1506 ps = color_mode_to_bpp(color_mode) / 8;
1507 break;
1508 }
1509
1510 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1511 width, height);
1512
1513 /*
1514 * field 0 = even field = bottom field
1515 * field 1 = odd field = top field
1516 */
1517 switch (rotation + mirror * 4) {
1518 case OMAP_DSS_ROT_0:
1519 case OMAP_DSS_ROT_180:
1520 /*
1521 * If the pixel format is YUV or UYVY divide the width
1522 * of the image by 2 for 0 and 180 degree rotation.
1523 */
1524 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1525 color_mode == OMAP_DSS_COLOR_UYVY)
1526 width = width >> 1;
1527 case OMAP_DSS_ROT_90:
1528 case OMAP_DSS_ROT_270:
1529 *offset1 = 0;
1530 if (field_offset)
1531 *offset0 = field_offset * screen_width * ps;
1532 else
1533 *offset0 = 0;
1534
aed74b55
CM		 1535 *row_inc = pixinc(1 +
1536 (y_predecim * screen_width - x_predecim * width) +
1537 (fieldmode ? screen_width : 0), ps);
1538 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1539 break;
1540
1541 case OMAP_DSS_ROT_0 + 4:
1542 case OMAP_DSS_ROT_180 + 4:
1543 /* If the pixel format is YUV or UYVY divide the width
1544 * of the image by 2 for 0 degree and 180 degree
1545 */
1546 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1547 color_mode == OMAP_DSS_COLOR_UYVY)
1548 width = width >> 1;
1549 case OMAP_DSS_ROT_90 + 4:
1550 case OMAP_DSS_ROT_270 + 4:
1551 *offset1 = 0;
1552 if (field_offset)
1553 *offset0 = field_offset * screen_width * ps;
1554 else
1555 *offset0 = 0;
aed74b55
CM		 1556 *row_inc = pixinc(1 -
1557 (y_predecim * screen_width + x_predecim * width) -
1558 (fieldmode ? screen_width : 0), ps);
1559 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1560 break;
1561
1562 default:
1563 BUG();
1564 }
1565}
1566
1567static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1568 u16 screen_width,
1569 u16 width, u16 height,
1570 enum omap_color_mode color_mode, bool fieldmode,
1571 unsigned int field_offset,
1572 unsigned *offset0, unsigned *offset1,
aed74b55 1573 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1574{
1575 u8 ps;
1576 u16 fbw, fbh;
1577
1578 /* FIXME CLUT formats */
1579 switch (color_mode) {
1580 case OMAP_DSS_COLOR_CLUT1:
1581 case OMAP_DSS_COLOR_CLUT2:
1582 case OMAP_DSS_COLOR_CLUT4:
1583 case OMAP_DSS_COLOR_CLUT8:
1584 BUG();
1585 return;
1586 default:
1587 ps = color_mode_to_bpp(color_mode) / 8;
1588 break;
1589 }
1590
1591 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1592 width, height);
1593
1594 /* width & height are overlay sizes, convert to fb sizes */
1595
1596 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1597 fbw = width;
1598 fbh = height;
1599 } else {
1600 fbw = height;
1601 fbh = width;
1602 }
1603
1604 /*
1605 * field 0 = even field = bottom field
1606 * field 1 = odd field = top field
1607 */
1608 switch (rotation + mirror * 4) {
1609 case OMAP_DSS_ROT_0:
1610 *offset1 = 0;
1611 if (field_offset)
1612 *offset0 = *offset1 + field_offset * screen_width * ps;
1613 else
1614 *offset0 = *offset1;
aed74b55
CM		 1615 *row_inc = pixinc(1 +
1616 (y_predecim * screen_width - fbw * x_predecim) +
1617 (fieldmode ? screen_width : 0), ps);
1618 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1619 color_mode == OMAP_DSS_COLOR_UYVY)
1620 *pix_inc = pixinc(x_predecim, 2 * ps);
1621 else
1622 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1623 break;
1624 case OMAP_DSS_ROT_90:
1625 *offset1 = screen_width * (fbh - 1) * ps;
1626 if (field_offset)
1627 *offset0 = *offset1 + field_offset * ps;
1628 else
1629 *offset0 = *offset1;
aed74b55
CM		 1630 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1631 y_predecim + (fieldmode ? 1 : 0), ps);
1632 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1633 break;
1634 case OMAP_DSS_ROT_180:
1635 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1636 if (field_offset)
1637 *offset0 = *offset1 - field_offset * screen_width * ps;
1638 else
1639 *offset0 = *offset1;
1640 *row_inc = pixinc(-1 -
aed74b55
CM		 1641 (y_predecim * screen_width - fbw * x_predecim) -
1642 (fieldmode ? screen_width : 0), ps);
1643 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1644 color_mode == OMAP_DSS_COLOR_UYVY)
1645 *pix_inc = pixinc(-x_predecim, 2 * ps);
1646 else
1647 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1648 break;
1649 case OMAP_DSS_ROT_270:
1650 *offset1 = (fbw - 1) * ps;
1651 if (field_offset)
1652 *offset0 = *offset1 - field_offset * ps;
1653 else
1654 *offset0 = *offset1;
aed74b55
CM		 1655 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1656 y_predecim - (fieldmode ? 1 : 0), ps);
1657 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1658 break;
1659
1660 /* mirroring */
1661 case OMAP_DSS_ROT_0 + 4:
1662 *offset1 = (fbw - 1) * ps;
1663 if (field_offset)
1664 *offset0 = *offset1 + field_offset * screen_width * ps;
1665 else
1666 *offset0 = *offset1;
aed74b55 1667 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1668 (fieldmode ? screen_width : 0),
1669 ps);
aed74b55
CM		 1670 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1671 color_mode == OMAP_DSS_COLOR_UYVY)
1672 *pix_inc = pixinc(-x_predecim, 2 * ps);
1673 else
1674 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1675 break;
1676
1677 case OMAP_DSS_ROT_90 + 4:
1678 *offset1 = 0;
1679 if (field_offset)
1680 *offset0 = *offset1 + field_offset * ps;
1681 else
1682 *offset0 = *offset1;
aed74b55
CM		 1683 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1684 y_predecim + (fieldmode ? 1 : 0),
80c39712 1685 ps);
aed74b55 1686 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1687 break;
1688
1689 case OMAP_DSS_ROT_180 + 4:
1690 *offset1 = screen_width * (fbh - 1) * ps;
1691 if (field_offset)
1692 *offset0 = *offset1 - field_offset * screen_width * ps;
1693 else
1694 *offset0 = *offset1;
aed74b55 1695 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1696 (fieldmode ? screen_width : 0),
1697 ps);
aed74b55
CM		 1698 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1699 color_mode == OMAP_DSS_COLOR_UYVY)
1700 *pix_inc = pixinc(x_predecim, 2 * ps);
1701 else
1702 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1703 break;
1704
1705 case OMAP_DSS_ROT_270 + 4:
1706 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1707 if (field_offset)
1708 *offset0 = *offset1 - field_offset * ps;
1709 else
1710 *offset0 = *offset1;
aed74b55
CM		 1711 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1712 y_predecim - (fieldmode ? 1 : 0),
80c39712 1713 ps);
aed74b55 1714 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1715 break;
1716
1717 default:
1718 BUG();
1719 }
1720}
1721
7faa9233
CM		 1722/*
1723 * This function is used to avoid synclosts in OMAP3, because of some
1724 * undocumented horizontal position and timing related limitations.
1725 */
81ab95b7
AT		 1726static int check_horiz_timing_omap3(enum omap_channel channel,
1727 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1728 u16 width, u16 height, u16 out_width, u16 out_height)
1729{
1730 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1731 unsigned long nonactive, lclk, pclk;
1732 static const u8 limits[3] = { 8, 10, 20 };
1733 u64 val, blank;
1734 int i;
1735
81ab95b7 1736 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 1737 pclk = dispc_mgr_pclk_rate(channel);
1738 if (dispc_mgr_is_lcd(channel))
1739 lclk = dispc_mgr_lclk_rate(channel);
1740 else
1741 lclk = dispc_fclk_rate();
1742
1743 i = 0;
1744 if (out_height < height)
1745 i++;
1746 if (out_width < width)
1747 i++;
81ab95b7 1748 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1749 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1750 if (blank <= limits[i])
1751 return -EINVAL;
1752
1753 /*
1754 * Pixel data should be prepared before visible display point starts.
1755 * So, atleast DS-2 lines must have already been fetched by DISPC
1756 * during nonactive - pos_x period.
1757 */
1758 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1759 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1760 val, max(0, DS - 2) * width);
1761 if (val < max(0, DS - 2) * width)
1762 return -EINVAL;
1763
1764 /*
1765 * All lines need to be refilled during the nonactive period of which
1766 * only one line can be loaded during the active period. So, atleast
1767 * DS - 1 lines should be loaded during nonactive period.
1768 */
1769 val = div_u64((u64)nonactive * lclk, pclk);
1770 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1771 val, max(0, DS - 1) * width);
1772 if (val < max(0, DS - 1) * width)
1773 return -EINVAL;
1774
1775 return 0;
1776}
1777
8b53d991 1778static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1779 const struct omap_video_timings *mgr_timings, u16 width,
1780 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1781 enum omap_color_mode color_mode)
80c39712 1782{
8b53d991 1783 u32 core_clk = 0;
26d9dd0d 1784 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1785
7282f1b7
CM		 1786 if (height <= out_height && width <= out_width)
1787 return (unsigned long) pclk;
1788
80c39712 1789 if (height > out_height) {
81ab95b7 1790 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1791
1792 tmp = pclk * height * out_width;
1793 do_div(tmp, 2 * out_height * ppl);
8b53d991 1794 core_clk = tmp;
80c39712 1795
2d9c5597
VS		 1796 if (height > 2 * out_height) {
1797 if (ppl == out_width)
1798 return 0;
1799
80c39712
TV		 1800 tmp = pclk * (height - 2 * out_height) * out_width;
1801 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1802 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1803 }
1804 }
1805
1806 if (width > out_width) {
1807 tmp = pclk * width;
1808 do_div(tmp, out_width);
8b53d991 1809 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1810
1811 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1812 core_clk <<= 1;
80c39712
TV		 1813 }
1814
8b53d991 1815 return core_clk;
80c39712
TV		 1816}
1817
8b53d991 1818static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
ff1b2cde 1819 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1820{
1821 unsigned int hf, vf;
79ee89cd 1822 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1823
1824 /*
1825 * FIXME how to determine the 'A' factor
1826 * for the no downscaling case ?
1827 */
1828
1829 if (width > 3 * out_width)
1830 hf = 4;
1831 else if (width > 2 * out_width)
1832 hf = 3;
1833 else if (width > out_width)
1834 hf = 2;
1835 else
1836 hf = 1;
1837
1838 if (height > out_height)
1839 vf = 2;
1840 else
1841 vf = 1;
1842
7282f1b7
CM		 1843 if (cpu_is_omap24xx()) {
1844 if (vf > 1 && hf > 1)
79ee89cd 1845 return pclk * 4;
7282f1b7 1846 else
79ee89cd 1847 return pclk * 2;
7282f1b7 1848 } else if (cpu_is_omap34xx()) {
79ee89cd 1849 return pclk * vf * hf;
7282f1b7 1850 } else {
79ee89cd
AT		 1851 if (hf > 1)
1852 return DIV_ROUND_UP(pclk, out_width) * width;
1853 else
1854 return pclk;
7282f1b7 1855 }
80c39712
TV		 1856}
1857
79ad75f2 1858static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 1859 enum omap_channel channel,
1860 const struct omap_video_timings *mgr_timings,
1861 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 1862 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 1863 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 1864{
1865 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1866 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1867 const int maxsinglelinewidth =
1868 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
aed74b55 1869 const int max_decim_limit = 16;
8b53d991 1870 unsigned long core_clk = 0;
aed74b55
CM		 1871 int decim_x, decim_y, error, min_factor;
1872 u16 in_width, in_height, in_width_max = 0;
79ad75f2 1873
f95cb5eb
TV		 1874 if (width == out_width && height == out_height)
1875 return 0;
1876
1877 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1878 return -EINVAL;
79ad75f2 1879
aed74b55
CM		 1880 *x_predecim = max_decim_limit;
1881 *y_predecim = max_decim_limit;
1882
1883 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
1884 color_mode == OMAP_DSS_COLOR_CLUT2 ||
1885 color_mode == OMAP_DSS_COLOR_CLUT4 ||
1886 color_mode == OMAP_DSS_COLOR_CLUT8) {
1887 *x_predecim = 1;
1888 *y_predecim = 1;
1889 *five_taps = false;
1890 return 0;
1891 }
1892
1893 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
1894 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
1895
1896 min_factor = min(decim_x, decim_y);
1897
1898 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 1899 return -EINVAL;
1900
aed74b55 1901 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 1902 return -EINVAL;
1903
7282f1b7 1904 if (cpu_is_omap24xx()) {
7282f1b7 1905 *five_taps = false;
aed74b55
CM		 1906
1907 do {
1908 in_height = DIV_ROUND_UP(height, decim_y);
1909 in_width = DIV_ROUND_UP(width, decim_x);
8b53d991 1910 core_clk = calc_core_clk(channel, in_width, in_height,
aed74b55 1911 out_width, out_height);
8b53d991
CM		 1912 error = (in_width > maxsinglelinewidth || !core_clk ||
1913 core_clk > dispc_core_clk_rate());
aed74b55
CM		 1914 if (error) {
1915 if (decim_x == decim_y) {
1916 decim_x = min_factor;
1917 decim_y++;
1918 } else {
1919 swap(decim_x, decim_y);
1920 if (decim_x < decim_y)
1921 decim_x++;
1922 }
1923 }
1924 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
1925 error);
1926
1927 if (in_width > maxsinglelinewidth) {
1928 DSSERR("Cannot scale max input width exceeded");
1929 return -EINVAL;
1930 }
7282f1b7 1931 } else if (cpu_is_omap34xx()) {
aed74b55
CM		 1932
1933 do {
1934 in_height = DIV_ROUND_UP(height, decim_y);
1935 in_width = DIV_ROUND_UP(width, decim_x);
81ab95b7
AT		 1936 core_clk = calc_core_clk_five_taps(channel, mgr_timings,
1937 in_width, in_height, out_width, out_height,
1938 color_mode);
aed74b55 1939
81ab95b7
AT		 1940 error = check_horiz_timing_omap3(channel, mgr_timings,
1941 pos_x, in_width, in_height, out_width,
1942 out_height);
7faa9233 1943
aed74b55
CM		 1944 if (in_width > maxsinglelinewidth)
1945 if (in_height > out_height &&
1946 in_height < out_height * 2)
1947 *five_taps = false;
1948 if (!*five_taps)
8b53d991
CM		 1949 core_clk = calc_core_clk(channel, in_width,
1950 in_height, out_width, out_height);
7faa9233 1951 error = (error || in_width > maxsinglelinewidth * 2 ||
aed74b55 1952 (in_width > maxsinglelinewidth && *five_taps) ||
8b53d991 1953 !core_clk || core_clk > dispc_core_clk_rate());
aed74b55
CM		 1954 if (error) {
1955 if (decim_x == decim_y) {
1956 decim_x = min_factor;
1957 decim_y++;
1958 } else {
1959 swap(decim_x, decim_y);
1960 if (decim_x < decim_y)
1961 decim_x++;
1962 }
1963 }
1964 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
1965 && error);
1966
81ab95b7
AT		 1967 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
1968 height, out_width, out_height)){
7faa9233
CM		 1969 DSSERR("horizontal timing too tight\n");
1970 return -EINVAL;
1971 }
1972
aed74b55 1973 if (in_width > (maxsinglelinewidth * 2)) {
7282f1b7
CM		 1974 DSSERR("Cannot setup scaling");
1975 DSSERR("width exceeds maximum width possible");
1976 return -EINVAL;
1977 }
aed74b55
CM		 1978
1979 if (in_width > maxsinglelinewidth && *five_taps) {
1980 DSSERR("cannot setup scaling with five taps");
1981 return -EINVAL;
7282f1b7 1982 }
7282f1b7 1983 } else {
aed74b55
CM		 1984 int decim_x_min = decim_x;
1985 in_height = DIV_ROUND_UP(height, decim_y);
8b53d991 1986 in_width_max = dispc_core_clk_rate() /
aed74b55
CM		 1987 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
1988 out_width);
1989 decim_x = DIV_ROUND_UP(width, in_width_max);
1990
1991 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
1992 if (decim_x > *x_predecim)
1993 return -EINVAL;
1994
1995 do {
1996 in_width = DIV_ROUND_UP(width, decim_x);
1997 } while (decim_x <= *x_predecim &&
1998 in_width > maxsinglelinewidth && decim_x++);
1999
2000 if (in_width > maxsinglelinewidth) {
7282f1b7
CM		 2001 DSSERR("Cannot scale width exceeds max line width");
2002 return -EINVAL;
2003 }
aed74b55 2004
8b53d991
CM		 2005 core_clk = calc_core_clk(channel, in_width, in_height,
2006 out_width, out_height);
79ad75f2
AT		 2007 }
2008
8b53d991
CM		 2009 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2010 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2011
8b53d991 2012 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2013 DSSERR("failed to set up scaling, "
8b53d991
CM		 2014 "required core clk rate = %lu Hz, "
2015 "current core clk rate = %lu Hz\n",
2016 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2017 return -EINVAL;
2018 }
2019
aed74b55
CM		 2020 *x_predecim = decim_x;
2021 *y_predecim = decim_y;
79ad75f2
AT		 2022 return 0;
2023}
2024
a4273b7c 2025int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
81ab95b7
AT		 2026 bool ilace, bool replication,
2027 const struct omap_video_timings *mgr_timings)
80c39712 2028{
79ad75f2 2029 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 2030 bool five_taps = true;
80c39712 2031 bool fieldmode = 0;
79ad75f2 2032 int r, cconv = 0;
80c39712
TV		 2033 unsigned offset0, offset1;
2034 s32 row_inc;
2035 s32 pix_inc;
a4273b7c 2036 u16 frame_height = oi->height;
80c39712 2037 unsigned int field_offset = 0;
aed74b55
CM		 2038 u16 in_height = oi->height;
2039 u16 in_width = oi->width;
2040 u16 out_width, out_height;
2cc5d1af 2041 enum omap_channel channel;
aed74b55 2042 int x_predecim = 1, y_predecim = 1;
2cc5d1af
TV		 2043
2044 channel = dispc_ovl_get_channel_out(plane);
80c39712 2045
a4273b7c 2046 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 2047 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2048 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 2049 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2050 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 2051 oi->mirror, ilace, channel, replication);
e6d80f95 2052
a4273b7c 2053 if (oi->paddr == 0)
80c39712
TV		 2054 return -EINVAL;
2055
aed74b55
CM		 2056 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2057 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 2058
aed74b55 2059 if (ilace && oi->height == out_height)
80c39712
TV		 2060 fieldmode = 1;
2061
2062 if (ilace) {
2063 if (fieldmode)
aed74b55 2064 in_height /= 2;
a4273b7c 2065 oi->pos_y /= 2;
aed74b55 2066 out_height /= 2;
80c39712
TV		 2067
2068 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2069 "out_height %d\n",
aed74b55 2070 in_height, oi->pos_y, out_height);
80c39712
TV		 2071 }
2072
a4273b7c 2073 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2074 return -EINVAL;
2075
81ab95b7
AT		 2076 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2077 in_height, out_width, out_height, oi->color_mode,
2078 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 2079 if (r)
2080 return r;
80c39712 2081
aed74b55
CM		 2082 in_width = DIV_ROUND_UP(in_width, x_predecim);
2083 in_height = DIV_ROUND_UP(in_height, y_predecim);
2084
79ad75f2
AT		 2085 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2086 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2087 oi->color_mode == OMAP_DSS_COLOR_NV12)
2088 cconv = 1;
80c39712
TV		 2089
2090 if (ilace && !fieldmode) {
2091 /*
2092 * when downscaling the bottom field may have to start several
2093 * source lines below the top field. Unfortunately ACCUI
2094 * registers will only hold the fractional part of the offset
2095 * so the integer part must be added to the base address of the
2096 * bottom field.
2097 */
aed74b55 2098 if (!in_height || in_height == out_height)
80c39712
TV		 2099 field_offset = 0;
2100 else
aed74b55 2101 field_offset = in_height / out_height / 2;
80c39712
TV		 2102 }
2103
2104 /* Fields are independent but interleaved in memory. */
2105 if (fieldmode)
2106 field_offset = 1;
2107
a4273b7c
AT		 2108 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
2109 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2110 oi->screen_width, in_width, frame_height,
a4273b7c 2111 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2112 &offset0, &offset1, &row_inc, &pix_inc,
2113 x_predecim, y_predecim);
80c39712 2114 else
a4273b7c 2115 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2116 oi->screen_width, in_width, frame_height,
a4273b7c 2117 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2118 &offset0, &offset1, &row_inc, &pix_inc,
2119 x_predecim, y_predecim);
80c39712
TV		 2120
2121 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2122 offset0, offset1, row_inc, pix_inc);
2123
a4273b7c 2124 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2125
a4273b7c
AT		 2126 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2127 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2128
a4273b7c
AT		 2129 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2130 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2131 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2132 }
2133
2134
f0e5caab
TV		 2135 dispc_ovl_set_row_inc(plane, row_inc);
2136 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2137
aed74b55
CM		 2138 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2139 in_height, out_width, out_height);
80c39712 2140
a4273b7c 2141 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2142
aed74b55 2143 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2144
79ad75f2 2145 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2146 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2147 out_height, ilace, five_taps, fieldmode,
a4273b7c 2148 oi->color_mode, oi->rotation);
aed74b55 2149 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2150 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2151 }
2152
a4273b7c
AT		 2153 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2154 oi->color_mode);
80c39712 2155
54128701 2156 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2157 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2158 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2159
c3d92529 2160 dispc_ovl_enable_replication(plane, replication);
c3d92529 2161
80c39712
TV		 2162 return 0;
2163}
2164
f0e5caab 2165int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2166{
e6d80f95
TV		 2167 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2168
9b372c2d 2169 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2170
2171 return 0;
80c39712
TV		 2172}
2173
2174static void dispc_disable_isr(void *data, u32 mask)
2175{
2176 struct completion *compl = data;
2177 complete(compl);
2178}
2179
2a205f34 2180static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2181{
b6a44e77 2182 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 2183 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2184 /* flush posted write */
2185 dispc_read_reg(DISPC_CONTROL2);
2186 } else {
2a205f34 2187 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2188 dispc_read_reg(DISPC_CONTROL);
2189 }
80c39712
TV		 2190}
2191
26d9dd0d 2192static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2193{
2194 struct completion frame_done_completion;
2195 bool is_on;
2196 int r;
2a205f34 2197 u32 irq;
80c39712 2198
80c39712
TV		 2199 /* When we disable LCD output, we need to wait until frame is done.
2200 * Otherwise the DSS is still working, and turning off the clocks
2201 * prevents DSS from going to OFF mode */
2a205f34
SS		 2202 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2203 REG_GET(DISPC_CONTROL2, 0, 0) :
2204 REG_GET(DISPC_CONTROL, 0, 0);
2205
2206 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2207 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2208
2209 if (!enable && is_on) {
2210 init_completion(&frame_done_completion);
2211
2212 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2213 &frame_done_completion, irq);
80c39712
TV		 2214
2215 if (r)
2216 DSSERR("failed to register FRAMEDONE isr\n");
2217 }
2218
2a205f34 2219 _enable_lcd_out(channel, enable);
80c39712
TV		 2220
2221 if (!enable && is_on) {
2222 if (!wait_for_completion_timeout(&frame_done_completion,
2223 msecs_to_jiffies(100)))
2224 DSSERR("timeout waiting for FRAME DONE\n");
2225
2226 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2227 &frame_done_completion, irq);
80c39712
TV		 2228
2229 if (r)
2230 DSSERR("failed to unregister FRAMEDONE isr\n");
2231 }
80c39712
TV		 2232}
2233
2234static void _enable_digit_out(bool enable)
2235{
2236 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2237 /* flush posted write */
2238 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2239}
2240
26d9dd0d 2241static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2242{
2243 struct completion frame_done_completion;
e82b090b
TV		 2244 enum dss_hdmi_venc_clk_source_select src;
2245 int r, i;
2246 u32 irq_mask;
2247 int num_irqs;
80c39712 2248
e6d80f95 2249 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2250 return;
80c39712 2251
e82b090b
TV		 2252 src = dss_get_hdmi_venc_clk_source();
2253
80c39712
TV		 2254 if (enable) {
2255 unsigned long flags;
2256 /* When we enable digit output, we'll get an extra digit
2257 * sync lost interrupt, that we need to ignore */
2258 spin_lock_irqsave(&dispc.irq_lock, flags);
2259 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2260 _omap_dispc_set_irqs();
2261 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2262 }
2263
2264 /* When we disable digit output, we need to wait until fields are done.
2265 * Otherwise the DSS is still working, and turning off the clocks
2266 * prevents DSS from going to OFF mode. And when enabling, we need to
2267 * wait for the extra sync losts */
2268 init_completion(&frame_done_completion);
2269
e82b090b
TV		 2270 if (src == DSS_HDMI_M_PCLK && enable == false) {
2271 irq_mask = DISPC_IRQ_FRAMEDONETV;
2272 num_irqs = 1;
2273 } else {
2274 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2275 /* XXX I understand from TRM that we should only wait for the
2276 * current field to complete. But it seems we have to wait for
2277 * both fields */
2278 num_irqs = 2;
2279 }
2280
80c39712 2281 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2282 irq_mask);
80c39712 2283 if (r)
e82b090b 2284 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2285
2286 _enable_digit_out(enable);
2287
e82b090b
TV		 2288 for (i = 0; i < num_irqs; ++i) {
2289 if (!wait_for_completion_timeout(&frame_done_completion,
2290 msecs_to_jiffies(100)))
2291 DSSERR("timeout waiting for digit out to %s\n",
2292 enable ? "start" : "stop");
2293 }
80c39712 2294
e82b090b
TV		 2295 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2296 irq_mask);
80c39712 2297 if (r)
e82b090b 2298 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2299
2300 if (enable) {
2301 unsigned long flags;
2302 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2303 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2304 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2305 _omap_dispc_set_irqs();
2306 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2307 }
80c39712
TV		 2308}
2309
26d9dd0d 2310bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2311{
2312 if (channel == OMAP_DSS_CHANNEL_LCD)
2313 return !!REG_GET(DISPC_CONTROL, 0, 0);
2314 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2315 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2316 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2317 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2318 else
2319 BUG();
2320}
2321
26d9dd0d 2322void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2323{
dac57a05 2324 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2325 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2326 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2327 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2328 else
2329 BUG();
2330}
2331
80c39712
TV		 2332void dispc_lcd_enable_signal_polarity(bool act_high)
2333{
6ced40bf
AT		 2334 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2335 return;
2336
80c39712 2337 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2338}
2339
2340void dispc_lcd_enable_signal(bool enable)
2341{
6ced40bf
AT		 2342 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2343 return;
2344
80c39712 2345 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2346}
2347
2348void dispc_pck_free_enable(bool enable)
2349{
6ced40bf
AT		 2350 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2351 return;
2352
80c39712 2353 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2354}
2355
26d9dd0d 2356void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2357{
2a205f34
SS		 2358 if (channel == OMAP_DSS_CHANNEL_LCD2)
2359 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2360 else
2361 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2362}
2363
2364
26d9dd0d 2365void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2366 enum omap_lcd_display_type type)
80c39712
TV		 2367{
2368 int mode;
2369
2370 switch (type) {
2371 case OMAP_DSS_LCD_DISPLAY_STN:
2372 mode = 0;
2373 break;
2374
2375 case OMAP_DSS_LCD_DISPLAY_TFT:
2376 mode = 1;
2377 break;
2378
2379 default:
2380 BUG();
2381 return;
2382 }
2383
2a205f34
SS		 2384 if (channel == OMAP_DSS_CHANNEL_LCD2)
2385 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2386 else
2387 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2388}
2389
2390void dispc_set_loadmode(enum omap_dss_load_mode mode)
2391{
80c39712 2392 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2393}
2394
2395
c64dca40 2396static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2397{
8613b000 2398 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2399}
2400
c64dca40 2401static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2402 enum omap_dss_trans_key_type type,
2403 u32 trans_key)
2404{
80c39712
TV		 2405 if (ch == OMAP_DSS_CHANNEL_LCD)
2406 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2407 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2408 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2409 else /* OMAP_DSS_CHANNEL_LCD2 */
2410 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2411
8613b000 2412 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2413}
2414
c64dca40 2415static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2416{
80c39712
TV		 2417 if (ch == OMAP_DSS_CHANNEL_LCD)
2418 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2419 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2420 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2421 else /* OMAP_DSS_CHANNEL_LCD2 */
2422 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2423}
11354dd5 2424
c64dca40
TV		 2425static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2426 bool enable)
80c39712 2427{
11354dd5 2428 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2429 return;
2430
80c39712
TV		 2431 if (ch == OMAP_DSS_CHANNEL_LCD)
2432 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2433 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2434 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2435}
11354dd5 2436
c64dca40
TV		 2437void dispc_mgr_setup(enum omap_channel channel,
2438 struct omap_overlay_manager_info *info)
2439{
2440 dispc_mgr_set_default_color(channel, info->default_color);
2441 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2442 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2443 dispc_mgr_enable_alpha_fixed_zorder(channel,
2444 info->partial_alpha_enabled);
2445 if (dss_has_feature(FEAT_CPR)) {
2446 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2447 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2448 }
2449}
80c39712 2450
26d9dd0d 2451void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2452{
2453 int code;
2454
2455 switch (data_lines) {
2456 case 12:
2457 code = 0;
2458 break;
2459 case 16:
2460 code = 1;
2461 break;
2462 case 18:
2463 code = 2;
2464 break;
2465 case 24:
2466 code = 3;
2467 break;
2468 default:
2469 BUG();
2470 return;
2471 }
2472
2a205f34
SS		 2473 if (channel == OMAP_DSS_CHANNEL_LCD2)
2474 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2475 else
2476 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2477}
2478
569969d6 2479void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2480{
2481 u32 l;
569969d6 2482 int gpout0, gpout1;
80c39712
TV		 2483
2484 switch (mode) {
569969d6
AT		 2485 case DSS_IO_PAD_MODE_RESET:
2486 gpout0 = 0;
2487 gpout1 = 0;
80c39712 2488 break;
569969d6
AT		 2489 case DSS_IO_PAD_MODE_RFBI:
2490 gpout0 = 1;
80c39712
TV		 2491 gpout1 = 0;
2492 break;
569969d6
AT		 2493 case DSS_IO_PAD_MODE_BYPASS:
2494 gpout0 = 1;
80c39712
TV		 2495 gpout1 = 1;
2496 break;
80c39712
TV		 2497 default:
2498 BUG();
2499 return;
2500 }
2501
569969d6
AT		 2502 l = dispc_read_reg(DISPC_CONTROL);
2503 l = FLD_MOD(l, gpout0, 15, 15);
2504 l = FLD_MOD(l, gpout1, 16, 16);
2505 dispc_write_reg(DISPC_CONTROL, l);
2506}
2507
2508void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2509{
2510 if (channel == OMAP_DSS_CHANNEL_LCD2)
2511 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2512 else
2513 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2514}
2515
8f366162
AT		 2516static bool _dispc_mgr_size_ok(u16 width, u16 height)
2517{
2518 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2519 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2520}
2521
80c39712
TV		 2522static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2523 int vsw, int vfp, int vbp)
2524{
2525 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2526 if (hsw < 1 || hsw > 64 ||
2527 hfp < 1 || hfp > 256 ||
2528 hbp < 1 || hbp > 256 ||
2529 vsw < 1 || vsw > 64 ||
2530 vfp < 0 || vfp > 255 ||
2531 vbp < 0 || vbp > 255)
2532 return false;
2533 } else {
2534 if (hsw < 1 || hsw > 256 ||
2535 hfp < 1 || hfp > 4096 ||
2536 hbp < 1 || hbp > 4096 ||
2537 vsw < 1 || vsw > 256 ||
2538 vfp < 0 || vfp > 4095 ||
2539 vbp < 0 || vbp > 4095)
2540 return false;
2541 }
2542
2543 return true;
2544}
2545
8f366162 2546bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2547 const struct omap_video_timings *timings)
80c39712 2548{
8f366162
AT		 2549 bool timings_ok;
2550
2551 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2552
2553 if (dispc_mgr_is_lcd(channel))
2554 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2555 timings->hfp, timings->hbp,
2556 timings->vsw, timings->vfp,
2557 timings->vbp);
2558
2559 return timings_ok;
80c39712
TV		 2560}
2561
26d9dd0d 2562static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2563 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2564{
2565 u32 timing_h, timing_v;
2566
2567 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2568 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2569 FLD_VAL(hbp-1, 27, 20);
2570
2571 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2572 FLD_VAL(vbp, 27, 20);
2573 } else {
2574 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2575 FLD_VAL(hbp-1, 31, 20);
2576
2577 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2578 FLD_VAL(vbp, 31, 20);
2579 }
2580
64ba4f74
SS		 2581 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2582 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2583}
2584
2585/* change name to mode? */
c51d921a 2586void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2587 struct omap_video_timings *timings)
80c39712
TV		 2588{
2589 unsigned xtot, ytot;
2590 unsigned long ht, vt;
2591
c51d921a
AT		 2592 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2593 timings->y_res);
80c39712 2594
8f366162
AT		 2595 if (!dispc_mgr_timings_ok(channel, timings))
2596 BUG();
80c39712 2597
8f366162 2598 if (dispc_mgr_is_lcd(channel)) {
c51d921a
AT		 2599 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2600 timings->hbp, timings->vsw, timings->vfp,
2601 timings->vbp);
80c39712 2602
c51d921a
AT		 2603 xtot = timings->x_res + timings->hfp + timings->hsw +
2604 timings->hbp;
2605 ytot = timings->y_res + timings->vfp + timings->vsw +
2606 timings->vbp;
80c39712 2607
c51d921a
AT		 2608 ht = (timings->pixel_clock * 1000) / xtot;
2609 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2610
2611 DSSDBG("pck %u\n", timings->pixel_clock);
2612 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
80c39712
TV		 2613 timings->hsw, timings->hfp, timings->hbp,
2614 timings->vsw, timings->vfp, timings->vbp);
2615
c51d921a 2616 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
c51d921a 2617 }
8f366162
AT		 2618
2619 dispc_mgr_set_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2620}
2621
26d9dd0d 2622static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2623 u16 pck_div)
80c39712
TV		 2624{
2625 BUG_ON(lck_div < 1);
9eaaf207 2626 BUG_ON(pck_div < 1);
80c39712 2627
ce7fa5eb 2628 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2629 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2630}
2631
26d9dd0d 2632static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2633 int *pck_div)
80c39712
TV		 2634{
2635 u32 l;
ce7fa5eb 2636 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2637 *lck_div = FLD_GET(l, 23, 16);
2638 *pck_div = FLD_GET(l, 7, 0);
2639}
2640
2641unsigned long dispc_fclk_rate(void)
2642{
a72b64b9 2643 struct platform_device *dsidev;
80c39712
TV		 2644 unsigned long r = 0;
2645
66534e8e 2646 switch (dss_get_dispc_clk_source()) {
89a35e51 2647 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2648 r = clk_get_rate(dispc.dss_clk);
66534e8e 2649 break;
89a35e51 2650 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2651 dsidev = dsi_get_dsidev_from_id(0);
2652 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2653 break;
5a8b572d
AT		 2654 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2655 dsidev = dsi_get_dsidev_from_id(1);
2656 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2657 break;
66534e8e
TA		 2658 default:
2659 BUG();
2660 }
2661
80c39712
TV		 2662 return r;
2663}
2664
26d9dd0d 2665unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2666{
a72b64b9 2667 struct platform_device *dsidev;
80c39712
TV		 2668 int lcd;
2669 unsigned long r;
2670 u32 l;
2671
ce7fa5eb 2672 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2673
2674 lcd = FLD_GET(l, 23, 16);
2675
ea75159e 2676 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2677 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2678 r = clk_get_rate(dispc.dss_clk);
ea75159e 2679 break;
89a35e51 2680 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2681 dsidev = dsi_get_dsidev_from_id(0);
2682 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2683 break;
5a8b572d
AT		 2684 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2685 dsidev = dsi_get_dsidev_from_id(1);
2686 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2687 break;
ea75159e
TA		 2688 default:
2689 BUG();
2690 }
80c39712
TV		 2691
2692 return r / lcd;
2693}
2694
26d9dd0d 2695unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2696{
80c39712 2697 unsigned long r;
80c39712 2698
c3dc6a7a
AT		 2699 if (dispc_mgr_is_lcd(channel)) {
2700 int pcd;
2701 u32 l;
80c39712 2702
c3dc6a7a 2703 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2704
c3dc6a7a 2705 pcd = FLD_GET(l, 7, 0);
80c39712 2706
c3dc6a7a
AT		 2707 r = dispc_mgr_lclk_rate(channel);
2708
2709 return r / pcd;
2710 } else {
3fa03ba8 2711 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2712
3fa03ba8
AT		 2713 source = dss_get_hdmi_venc_clk_source();
2714
2715 switch (source) {
2716 case DSS_VENC_TV_CLK:
c3dc6a7a 2717 return venc_get_pixel_clock();
3fa03ba8 2718 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2719 return hdmi_get_pixel_clock();
2720 default:
2721 BUG();
2722 }
2723 }
80c39712
TV		 2724}
2725
8b53d991
CM		 2726unsigned long dispc_core_clk_rate(void)
2727{
2728 int lcd;
2729 unsigned long fclk = dispc_fclk_rate();
2730
2731 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2732 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2733 else
2734 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2735
2736 return fclk / lcd;
2737}
2738
80c39712
TV		 2739void dispc_dump_clocks(struct seq_file *s)
2740{
2741 int lcd, pcd;
0cf35df3 2742 u32 l;
89a35e51
AT		 2743 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2744 enum omap_dss_clk_source lcd_clk_src;
80c39712 2745
4fbafaf3
TV		 2746 if (dispc_runtime_get())
2747 return;
80c39712 2748
80c39712
TV		 2749 seq_printf(s, "- DISPC -\n");
2750
067a57e4
AT		 2751 seq_printf(s, "dispc fclk source = %s (%s)\n",
2752 dss_get_generic_clk_source_name(dispc_clk_src),
2753 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2754
2755 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2756
0cf35df3
MR		 2757 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2758 seq_printf(s, "- DISPC-CORE-CLK -\n");
2759 l = dispc_read_reg(DISPC_DIVISOR);
2760 lcd = FLD_GET(l, 23, 16);
2761
2762 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2763 (dispc_fclk_rate()/lcd), lcd);
2764 }
2a205f34
SS		 2765 seq_printf(s, "- LCD1 -\n");
2766
ea75159e
TA		 2767 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2768
2769 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2770 dss_get_generic_clk_source_name(lcd_clk_src),
2771 dss_feat_get_clk_source_name(lcd_clk_src));
2772
26d9dd0d 2773 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2774
ff1b2cde 2775 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2776 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2777 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2778 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2779 if (dss_has_feature(FEAT_MGR_LCD2)) {
2780 seq_printf(s, "- LCD2 -\n");
2781
ea75159e
TA		 2782 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2783
2784 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2785 dss_get_generic_clk_source_name(lcd_clk_src),
2786 dss_feat_get_clk_source_name(lcd_clk_src));
2787
26d9dd0d 2788 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2789
2a205f34 2790 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2791 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2792 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2793 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2794 }
4fbafaf3
TV		 2795
2796 dispc_runtime_put();
80c39712
TV		 2797}
2798
dfc0fd8d
TV		 2799#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2800void dispc_dump_irqs(struct seq_file *s)
2801{
2802 unsigned long flags;
2803 struct dispc_irq_stats stats;
2804
2805 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2806
2807 stats = dispc.irq_stats;
2808 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2809 dispc.irq_stats.last_reset = jiffies;
2810
2811 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2812
2813 seq_printf(s, "period %u ms\n",
2814 jiffies_to_msecs(jiffies - stats.last_reset));
2815
2816 seq_printf(s, "irqs %d\n", stats.irq_count);
2817#define PIS(x) \
2818 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2819
2820 PIS(FRAMEDONE);
2821 PIS(VSYNC);
2822 PIS(EVSYNC_EVEN);
2823 PIS(EVSYNC_ODD);
2824 PIS(ACBIAS_COUNT_STAT);
2825 PIS(PROG_LINE_NUM);
2826 PIS(GFX_FIFO_UNDERFLOW);
2827 PIS(GFX_END_WIN);
2828 PIS(PAL_GAMMA_MASK);
2829 PIS(OCP_ERR);
2830 PIS(VID1_FIFO_UNDERFLOW);
2831 PIS(VID1_END_WIN);
2832 PIS(VID2_FIFO_UNDERFLOW);
2833 PIS(VID2_END_WIN);
b8c095b4
AT		 2834 if (dss_feat_get_num_ovls() > 3) {
2835 PIS(VID3_FIFO_UNDERFLOW);
2836 PIS(VID3_END_WIN);
2837 }
dfc0fd8d
TV		 2838 PIS(SYNC_LOST);
2839 PIS(SYNC_LOST_DIGIT);
2840 PIS(WAKEUP);
2a205f34
SS		 2841 if (dss_has_feature(FEAT_MGR_LCD2)) {
2842 PIS(FRAMEDONE2);
2843 PIS(VSYNC2);
2844 PIS(ACBIAS_COUNT_STAT2);
2845 PIS(SYNC_LOST2);
2846 }
dfc0fd8d
TV		 2847#undef PIS
2848}
dfc0fd8d
TV		 2849#endif
2850
e40402cf 2851static void dispc_dump_regs(struct seq_file *s)
80c39712 2852{
4dd2da15
AT		 2853 int i, j;
2854 const char *mgr_names[] = {
2855 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2856 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2857 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2858 };
2859 const char *ovl_names[] = {
2860 [OMAP_DSS_GFX] = "GFX",
2861 [OMAP_DSS_VIDEO1] = "VID1",
2862 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2863 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2864 };
2865 const char **p_names;
2866
9b372c2d 2867#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2868
4fbafaf3
TV		 2869 if (dispc_runtime_get())
2870 return;
80c39712 2871
5010be80 2872 /* DISPC common registers */
80c39712
TV		 2873 DUMPREG(DISPC_REVISION);
2874 DUMPREG(DISPC_SYSCONFIG);
2875 DUMPREG(DISPC_SYSSTATUS);
2876 DUMPREG(DISPC_IRQSTATUS);
2877 DUMPREG(DISPC_IRQENABLE);
2878 DUMPREG(DISPC_CONTROL);
2879 DUMPREG(DISPC_CONFIG);
2880 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2881 DUMPREG(DISPC_LINE_STATUS);
2882 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2883 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2884 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2885 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2886 if (dss_has_feature(FEAT_MGR_LCD2)) {
2887 DUMPREG(DISPC_CONTROL2);
2888 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2889 }
2890
2891#undef DUMPREG
2892
2893#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2894#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2895 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2896 dispc_read_reg(DISPC_REG(i, r)))
2897
4dd2da15 2898 p_names = mgr_names;
5010be80 2899
4dd2da15
AT		 2900 /* DISPC channel specific registers */
2901 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2902 DUMPREG(i, DISPC_DEFAULT_COLOR);
2903 DUMPREG(i, DISPC_TRANS_COLOR);
2904 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2905
4dd2da15
AT		 2906 if (i == OMAP_DSS_CHANNEL_DIGIT)
2907 continue;
5010be80 2908
4dd2da15
AT		 2909 DUMPREG(i, DISPC_DEFAULT_COLOR);
2910 DUMPREG(i, DISPC_TRANS_COLOR);
2911 DUMPREG(i, DISPC_TIMING_H);
2912 DUMPREG(i, DISPC_TIMING_V);
2913 DUMPREG(i, DISPC_POL_FREQ);
2914 DUMPREG(i, DISPC_DIVISORo);
2915 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2916
4dd2da15
AT		 2917 DUMPREG(i, DISPC_DATA_CYCLE1);
2918 DUMPREG(i, DISPC_DATA_CYCLE2);
2919 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2920
332e9d70 2921 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2922 DUMPREG(i, DISPC_CPR_COEF_R);
2923 DUMPREG(i, DISPC_CPR_COEF_G);
2924 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2925 }
2a205f34 2926 }
80c39712 2927
4dd2da15
AT		 2928 p_names = ovl_names;
2929
2930 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2931 DUMPREG(i, DISPC_OVL_BA0);
2932 DUMPREG(i, DISPC_OVL_BA1);
2933 DUMPREG(i, DISPC_OVL_POSITION);
2934 DUMPREG(i, DISPC_OVL_SIZE);
2935 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2936 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2937 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2938 DUMPREG(i, DISPC_OVL_ROW_INC);
2939 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2940 if (dss_has_feature(FEAT_PRELOAD))
2941 DUMPREG(i, DISPC_OVL_PRELOAD);
2942
2943 if (i == OMAP_DSS_GFX) {
2944 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2945 DUMPREG(i, DISPC_OVL_TABLE_BA);
2946 continue;
2947 }
2948
2949 DUMPREG(i, DISPC_OVL_FIR);
2950 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2951 DUMPREG(i, DISPC_OVL_ACCU0);
2952 DUMPREG(i, DISPC_OVL_ACCU1);
2953 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2954 DUMPREG(i, DISPC_OVL_BA0_UV);
2955 DUMPREG(i, DISPC_OVL_BA1_UV);
2956 DUMPREG(i, DISPC_OVL_FIR2);
2957 DUMPREG(i, DISPC_OVL_ACCU2_0);
2958 DUMPREG(i, DISPC_OVL_ACCU2_1);
2959 }
2960 if (dss_has_feature(FEAT_ATTR2))
2961 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2962 if (dss_has_feature(FEAT_PRELOAD))
2963 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2964 }
5010be80
AT		 2965
2966#undef DISPC_REG
2967#undef DUMPREG
2968
2969#define DISPC_REG(plane, name, i) name(plane, i)
2970#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2971 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2972 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2973 dispc_read_reg(DISPC_REG(plane, name, i)))
2974
4dd2da15 2975 /* Video pipeline coefficient registers */
332e9d70 2976
4dd2da15
AT		 2977 /* start from OMAP_DSS_VIDEO1 */
2978 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2979 for (j = 0; j < 8; j++)
2980 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2981
4dd2da15
AT		 2982 for (j = 0; j < 8; j++)
2983 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2984
4dd2da15
AT		 2985 for (j = 0; j < 5; j++)
2986 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2987
4dd2da15
AT		 2988 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2989 for (j = 0; j < 8; j++)
2990 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2991 }
2992
2993 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2994 for (j = 0; j < 8; j++)
2995 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2996
2997 for (j = 0; j < 8; j++)
2998 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2999
3000 for (j = 0; j < 8; j++)
3001 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3002 }
332e9d70 3003 }
80c39712 3004
4fbafaf3 3005 dispc_runtime_put();
5010be80
AT		 3006
3007#undef DISPC_REG
80c39712
TV		 3008#undef DUMPREG
3009}
3010
26d9dd0d
TV		 3011static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
3012 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
3013 u8 acb)
80c39712
TV		 3014{
3015 u32 l = 0;
3016
3017 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
3018 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
3019
3020 l |= FLD_VAL(onoff, 17, 17);
3021 l |= FLD_VAL(rf, 16, 16);
3022 l |= FLD_VAL(ieo, 15, 15);
3023 l |= FLD_VAL(ipc, 14, 14);
3024 l |= FLD_VAL(ihs, 13, 13);
3025 l |= FLD_VAL(ivs, 12, 12);
3026 l |= FLD_VAL(acbi, 11, 8);
3027 l |= FLD_VAL(acb, 7, 0);
3028
ff1b2cde 3029 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3030}
3031
26d9dd0d 3032void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 3033 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 3034{
26d9dd0d 3035 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 3036 (config & OMAP_DSS_LCD_RF) != 0,
3037 (config & OMAP_DSS_LCD_IEO) != 0,
3038 (config & OMAP_DSS_LCD_IPC) != 0,
3039 (config & OMAP_DSS_LCD_IHS) != 0,
3040 (config & OMAP_DSS_LCD_IVS) != 0,
3041 acbi, acb);
3042}
3043
3044/* with fck as input clock rate, find dispc dividers that produce req_pck */
3045void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3046 struct dispc_clock_info *cinfo)
3047{
9eaaf207 3048 u16 pcd_min, pcd_max;
80c39712
TV		 3049 unsigned long best_pck;
3050 u16 best_ld, cur_ld;
3051 u16 best_pd, cur_pd;
3052
9eaaf207
TV		 3053 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3054 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3055
3056 if (!is_tft)
3057 pcd_min = 3;
3058
80c39712
TV		 3059 best_pck = 0;
3060 best_ld = 0;
3061 best_pd = 0;
3062
3063 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3064 unsigned long lck = fck / cur_ld;
3065
9eaaf207 3066 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3067 unsigned long pck = lck / cur_pd;
3068 long old_delta = abs(best_pck - req_pck);
3069 long new_delta = abs(pck - req_pck);
3070
3071 if (best_pck == 0 || new_delta < old_delta) {
3072 best_pck = pck;
3073 best_ld = cur_ld;
3074 best_pd = cur_pd;
3075
3076 if (pck == req_pck)
3077 goto found;
3078 }
3079
3080 if (pck < req_pck)
3081 break;
3082 }
3083
3084 if (lck / pcd_min < req_pck)
3085 break;
3086 }
3087
3088found:
3089 cinfo->lck_div = best_ld;
3090 cinfo->pck_div = best_pd;
3091 cinfo->lck = fck / cinfo->lck_div;
3092 cinfo->pck = cinfo->lck / cinfo->pck_div;
3093}
3094
3095/* calculate clock rates using dividers in cinfo */
3096int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3097 struct dispc_clock_info *cinfo)
3098{
3099 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3100 return -EINVAL;
9eaaf207 3101 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3102 return -EINVAL;
3103
3104 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3105 cinfo->pck = cinfo->lck / cinfo->pck_div;
3106
3107 return 0;
3108}
3109
26d9dd0d 3110int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3111 struct dispc_clock_info *cinfo)
80c39712
TV		 3112{
3113 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3114 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3115
26d9dd0d 3116 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3117
3118 return 0;
3119}
3120
26d9dd0d 3121int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3122 struct dispc_clock_info *cinfo)
80c39712
TV		 3123{
3124 unsigned long fck;
3125
3126 fck = dispc_fclk_rate();
3127
ce7fa5eb
MR		 3128 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3129 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3130
3131 cinfo->lck = fck / cinfo->lck_div;
3132 cinfo->pck = cinfo->lck / cinfo->pck_div;
3133
3134 return 0;
3135}
3136
3137/* dispc.irq_lock has to be locked by the caller */
3138static void _omap_dispc_set_irqs(void)
3139{
3140 u32 mask;
3141 u32 old_mask;
3142 int i;
3143 struct omap_dispc_isr_data *isr_data;
3144
3145 mask = dispc.irq_error_mask;
3146
3147 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3148 isr_data = &dispc.registered_isr[i];
3149
3150 if (isr_data->isr == NULL)
3151 continue;
3152
3153 mask |= isr_data->mask;
3154 }
3155
80c39712
TV		 3156 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3157 /* clear the irqstatus for newly enabled irqs */
3158 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3159
3160 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3161}
3162
3163int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3164{
3165 int i;
3166 int ret;
3167 unsigned long flags;
3168 struct omap_dispc_isr_data *isr_data;
3169
3170 if (isr == NULL)
3171 return -EINVAL;
3172
3173 spin_lock_irqsave(&dispc.irq_lock, flags);
3174
3175 /* check for duplicate entry */
3176 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3177 isr_data = &dispc.registered_isr[i];
3178 if (isr_data->isr == isr && isr_data->arg == arg &&
3179 isr_data->mask == mask) {
3180 ret = -EINVAL;
3181 goto err;
3182 }
3183 }
3184
3185 isr_data = NULL;
3186 ret = -EBUSY;
3187
3188 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3189 isr_data = &dispc.registered_isr[i];
3190
3191 if (isr_data->isr != NULL)
3192 continue;
3193
3194 isr_data->isr = isr;
3195 isr_data->arg = arg;
3196 isr_data->mask = mask;
3197 ret = 0;
3198
3199 break;
3200 }
3201
b9cb0984
TV		 3202 if (ret)
3203 goto err;
3204
80c39712
TV		 3205 _omap_dispc_set_irqs();
3206
3207 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3208
3209 return 0;
3210err:
3211 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3212
3213 return ret;
3214}
3215EXPORT_SYMBOL(omap_dispc_register_isr);
3216
3217int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3218{
3219 int i;
3220 unsigned long flags;
3221 int ret = -EINVAL;
3222 struct omap_dispc_isr_data *isr_data;
3223
3224 spin_lock_irqsave(&dispc.irq_lock, flags);
3225
3226 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3227 isr_data = &dispc.registered_isr[i];
3228 if (isr_data->isr != isr || isr_data->arg != arg ||
3229 isr_data->mask != mask)
3230 continue;
3231
3232 /* found the correct isr */
3233
3234 isr_data->isr = NULL;
3235 isr_data->arg = NULL;
3236 isr_data->mask = 0;
3237
3238 ret = 0;
3239 break;
3240 }
3241
3242 if (ret == 0)
3243 _omap_dispc_set_irqs();
3244
3245 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3246
3247 return ret;
3248}
3249EXPORT_SYMBOL(omap_dispc_unregister_isr);
3250
3251#ifdef DEBUG
3252static void print_irq_status(u32 status)
3253{
3254 if ((status & dispc.irq_error_mask) == 0)
3255 return;
3256
3257 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3258
3259#define PIS(x) \
3260 if (status & DISPC_IRQ_##x) \
3261 printk(#x " ");
3262 PIS(GFX_FIFO_UNDERFLOW);
3263 PIS(OCP_ERR);
3264 PIS(VID1_FIFO_UNDERFLOW);
3265 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3266 if (dss_feat_get_num_ovls() > 3)
3267 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3268 PIS(SYNC_LOST);
3269 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3270 if (dss_has_feature(FEAT_MGR_LCD2))
3271 PIS(SYNC_LOST2);
80c39712
TV		 3272#undef PIS
3273
3274 printk("\n");
3275}
3276#endif
3277
3278/* Called from dss.c. Note that we don't touch clocks here,
3279 * but we presume they are on because we got an IRQ. However,
3280 * an irq handler may turn the clocks off, so we may not have
3281 * clock later in the function. */
affe360d 3282static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3283{
3284 int i;
affe360d 3285 u32 irqstatus, irqenable;
80c39712
TV		 3286 u32 handledirqs = 0;
3287 u32 unhandled_errors;
3288 struct omap_dispc_isr_data *isr_data;
3289 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3290
3291 spin_lock(&dispc.irq_lock);
3292
3293 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3294 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3295
3296 /* IRQ is not for us */
3297 if (!(irqstatus & irqenable)) {
3298 spin_unlock(&dispc.irq_lock);
3299 return IRQ_NONE;
3300 }
80c39712 3301
dfc0fd8d
TV		 3302#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3303 spin_lock(&dispc.irq_stats_lock);
3304 dispc.irq_stats.irq_count++;
3305 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3306 spin_unlock(&dispc.irq_stats_lock);
3307#endif
3308
80c39712
TV		 3309#ifdef DEBUG
3310 if (dss_debug)
3311 print_irq_status(irqstatus);
3312#endif
3313 /* Ack the interrupt. Do it here before clocks are possibly turned
3314 * off */
3315 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3316 /* flush posted write */
3317 dispc_read_reg(DISPC_IRQSTATUS);
3318
3319 /* make a copy and unlock, so that isrs can unregister
3320 * themselves */
3321 memcpy(registered_isr, dispc.registered_isr,
3322 sizeof(registered_isr));
3323
3324 spin_unlock(&dispc.irq_lock);
3325
3326 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3327 isr_data = &registered_isr[i];
3328
3329 if (!isr_data->isr)
3330 continue;
3331
3332 if (isr_data->mask & irqstatus) {
3333 isr_data->isr(isr_data->arg, irqstatus);
3334 handledirqs |= isr_data->mask;
3335 }
3336 }
3337
3338 spin_lock(&dispc.irq_lock);
3339
3340 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3341
3342 if (unhandled_errors) {
3343 dispc.error_irqs |= unhandled_errors;
3344
3345 dispc.irq_error_mask &= ~unhandled_errors;
3346 _omap_dispc_set_irqs();
3347
3348 schedule_work(&dispc.error_work);
3349 }
3350
3351 spin_unlock(&dispc.irq_lock);
affe360d 3352
3353 return IRQ_HANDLED;
80c39712
TV		 3354}
3355
3356static void dispc_error_worker(struct work_struct *work)
3357{
3358 int i;
3359 u32 errors;
3360 unsigned long flags;
fe3cc9d6
TV		 3361 static const unsigned fifo_underflow_bits[] = {
3362 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3363 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3364 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3365 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3366 };
3367
3368 static const unsigned sync_lost_bits[] = {
3369 DISPC_IRQ_SYNC_LOST,
3370 DISPC_IRQ_SYNC_LOST_DIGIT,
3371 DISPC_IRQ_SYNC_LOST2,
3372 };
80c39712
TV		 3373
3374 spin_lock_irqsave(&dispc.irq_lock, flags);
3375 errors = dispc.error_irqs;
3376 dispc.error_irqs = 0;
3377 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3378
13eae1f9
DZ		 3379 dispc_runtime_get();
3380
fe3cc9d6
TV		 3381 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3382 struct omap_overlay *ovl;
3383 unsigned bit;
80c39712 3384
fe3cc9d6
TV		 3385 ovl = omap_dss_get_overlay(i);
3386 bit = fifo_underflow_bits[i];
80c39712 3387
fe3cc9d6
TV		 3388 if (bit & errors) {
3389 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3390 ovl->name);
f0e5caab 3391 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3392 dispc_mgr_go(ovl->manager->id);
80c39712 3393 mdelay(50);
80c39712
TV		 3394 }
3395 }
3396
fe3cc9d6
TV		 3397 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3398 struct omap_overlay_manager *mgr;
3399 unsigned bit;
80c39712 3400
fe3cc9d6
TV		 3401 mgr = omap_dss_get_overlay_manager(i);
3402 bit = sync_lost_bits[i];
80c39712 3403
fe3cc9d6
TV		 3404 if (bit & errors) {
3405 struct omap_dss_device *dssdev = mgr->device;
3406 bool enable;
80c39712 3407
fe3cc9d6
TV		 3408 DSSERR("SYNC_LOST on channel %s, restarting the output "
3409 "with video overlays disabled\n",
3410 mgr->name);
2a205f34 3411
fe3cc9d6
TV		 3412 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3413 dssdev->driver->disable(dssdev);
2a205f34 3414
2a205f34
SS		 3415 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3416 struct omap_overlay *ovl;
3417 ovl = omap_dss_get_overlay(i);
3418
fe3cc9d6
TV		 3419 if (ovl->id != OMAP_DSS_GFX &&
3420 ovl->manager == mgr)
f0e5caab 3421 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3422 }
3423
26d9dd0d 3424 dispc_mgr_go(mgr->id);
2a205f34 3425 mdelay(50);
fe3cc9d6 3426
2a205f34
SS		 3427 if (enable)
3428 dssdev->driver->enable(dssdev);
3429 }
3430 }
3431
80c39712
TV		 3432 if (errors & DISPC_IRQ_OCP_ERR) {
3433 DSSERR("OCP_ERR\n");
3434 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3435 struct omap_overlay_manager *mgr;
3436 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3437 if (mgr->device && mgr->device->driver)
3438 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3439 }
3440 }
3441
3442 spin_lock_irqsave(&dispc.irq_lock, flags);
3443 dispc.irq_error_mask |= errors;
3444 _omap_dispc_set_irqs();
3445 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3446
3447 dispc_runtime_put();
80c39712
TV		 3448}
3449
3450int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3451{
3452 void dispc_irq_wait_handler(void *data, u32 mask)
3453 {
3454 complete((struct completion *)data);
3455 }
3456
3457 int r;
3458 DECLARE_COMPLETION_ONSTACK(completion);
3459
3460 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3461 irqmask);
3462
3463 if (r)
3464 return r;
3465
3466 timeout = wait_for_completion_timeout(&completion, timeout);
3467
3468 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3469
3470 if (timeout == 0)
3471 return -ETIMEDOUT;
3472
3473 if (timeout == -ERESTARTSYS)
3474 return -ERESTARTSYS;
3475
3476 return 0;
3477}
3478
3479int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3480 unsigned long timeout)
3481{
3482 void dispc_irq_wait_handler(void *data, u32 mask)
3483 {
3484 complete((struct completion *)data);
3485 }
3486
3487 int r;
3488 DECLARE_COMPLETION_ONSTACK(completion);
3489
3490 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3491 irqmask);
3492
3493 if (r)
3494 return r;
3495
3496 timeout = wait_for_completion_interruptible_timeout(&completion,
3497 timeout);
3498
3499 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3500
3501 if (timeout == 0)
3502 return -ETIMEDOUT;
3503
3504 if (timeout == -ERESTARTSYS)
3505 return -ERESTARTSYS;
3506
3507 return 0;
3508}
3509
80c39712
TV		 3510static void _omap_dispc_initialize_irq(void)
3511{
3512 unsigned long flags;
3513
3514 spin_lock_irqsave(&dispc.irq_lock, flags);
3515
3516 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3517
3518 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3519 if (dss_has_feature(FEAT_MGR_LCD2))
3520 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3521 if (dss_feat_get_num_ovls() > 3)
3522 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3523
3524 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3525 * so clear it */
3526 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3527
3528 _omap_dispc_set_irqs();
3529
3530 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3531}
3532
3533void dispc_enable_sidle(void)
3534{
3535 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3536}
3537
3538void dispc_disable_sidle(void)
3539{
3540 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3541}
3542
3543static void _omap_dispc_initial_config(void)
3544{
3545 u32 l;
3546
0cf35df3
MR		 3547 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3548 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3549 l = dispc_read_reg(DISPC_DIVISOR);
3550 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3551 l = FLD_MOD(l, 1, 0, 0);
3552 l = FLD_MOD(l, 1, 23, 16);
3553 dispc_write_reg(DISPC_DIVISOR, l);
3554 }
3555
80c39712 3556 /* FUNCGATED */
6ced40bf
AT		 3557 if (dss_has_feature(FEAT_FUNCGATED))
3558 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3559
80c39712
TV		 3560 _dispc_setup_color_conv_coef();
3561
3562 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3563
3564 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3565
3566 dispc_configure_burst_sizes();
54128701
AT		 3567
3568 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3569}
3570
060b6d9c 3571/* DISPC HW IP initialisation */
6e7e8f06 3572static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3573{
3574 u32 rev;
affe360d 3575 int r = 0;
ea9da36a 3576 struct resource *dispc_mem;
4fbafaf3 3577 struct clk *clk;
ea9da36a 3578
060b6d9c
SG		 3579 dispc.pdev = pdev;
3580
3581 spin_lock_init(&dispc.irq_lock);
3582
3583#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3584 spin_lock_init(&dispc.irq_stats_lock);
3585 dispc.irq_stats.last_reset = jiffies;
3586#endif
3587
3588 INIT_WORK(&dispc.error_work, dispc_error_worker);
3589
ea9da36a
SG		 3590 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3591 if (!dispc_mem) {
3592 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3593 return -EINVAL;
ea9da36a 3594 }
cd3b3449 3595
6e2a14d2
JL		 3596 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3597 resource_size(dispc_mem));
060b6d9c
SG		 3598 if (!dispc.base) {
3599 DSSERR("can't ioremap DISPC\n");
cd3b3449 3600 return -ENOMEM;
affe360d 3601 }
cd3b3449 3602
affe360d 3603 dispc.irq = platform_get_irq(dispc.pdev, 0);
3604 if (dispc.irq < 0) {
3605 DSSERR("platform_get_irq failed\n");
cd3b3449 3606 return -ENODEV;
affe360d 3607 }
3608
6e2a14d2
JL		 3609 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3610 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3611 if (r < 0) {
3612 DSSERR("request_irq failed\n");
cd3b3449
TV		 3613 return r;
3614 }
3615
3616 clk = clk_get(&pdev->dev, "fck");
3617 if (IS_ERR(clk)) {
3618 DSSERR("can't get fck\n");
3619 r = PTR_ERR(clk);
3620 return r;
060b6d9c
SG		 3621 }
3622
cd3b3449
TV		 3623 dispc.dss_clk = clk;
3624
4fbafaf3
TV		 3625 pm_runtime_enable(&pdev->dev);
3626
3627 r = dispc_runtime_get();
3628 if (r)
3629 goto err_runtime_get;
060b6d9c
SG		 3630
3631 _omap_dispc_initial_config();
3632
3633 _omap_dispc_initialize_irq();
3634
060b6d9c 3635 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3636 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3637 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3638
4fbafaf3 3639 dispc_runtime_put();
060b6d9c 3640
e40402cf
TV		 3641 dss_debugfs_create_file("dispc", dispc_dump_regs);
3642
3643#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3644 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3645#endif
060b6d9c 3646 return 0;
4fbafaf3
TV		 3647
3648err_runtime_get:
3649 pm_runtime_disable(&pdev->dev);
4fbafaf3 3650 clk_put(dispc.dss_clk);
affe360d 3651 return r;
060b6d9c
SG		 3652}
3653
6e7e8f06 3654static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3655{
4fbafaf3
TV		 3656 pm_runtime_disable(&pdev->dev);
3657
3658 clk_put(dispc.dss_clk);
3659
060b6d9c
SG		 3660 return 0;
3661}
3662
4fbafaf3
TV		 3663static int dispc_runtime_suspend(struct device *dev)
3664{
3665 dispc_save_context();
4fbafaf3
TV		 3666
3667 return 0;
3668}
3669
3670static int dispc_runtime_resume(struct device *dev)
3671{
49ea86f3 3672 dispc_restore_context();
4fbafaf3
TV		 3673
3674 return 0;
3675}
3676
3677static const struct dev_pm_ops dispc_pm_ops = {
3678 .runtime_suspend = dispc_runtime_suspend,
3679 .runtime_resume = dispc_runtime_resume,
3680};
3681
060b6d9c 3682static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3683 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3684 .driver = {
3685 .name = "omapdss_dispc",
3686 .owner = THIS_MODULE,
4fbafaf3 3687 .pm = &dispc_pm_ops,
060b6d9c
SG		 3688 },
3689};
3690
6e7e8f06 3691int __init dispc_init_platform_driver(void)
060b6d9c 3692{
11436e1d 3693 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3694}
3695
6e7e8f06 3696void __exit dispc_uninit_platform_driver(void)
060b6d9c 3697{
04c742c3 3698 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3699}
Linux kernel - Deliverables
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