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OMAPDSS: DISPC: fix usage of dispc_ovl_set_accu_uv
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
80c39712
TV		 122static void _omap_dispc_set_irqs(void);
123
55978cc2 124static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 125{
55978cc2 126 __raw_writel(val, dispc.base + idx);
80c39712
TV		 127}
128
55978cc2 129static inline u32 dispc_read_reg(const u16 idx)
80c39712 130{
55978cc2 131 return __raw_readl(dispc.base + idx);
80c39712
TV		 132}
133
134#define SR(reg) \
55978cc2 135 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 136#define RR(reg) \
55978cc2 137 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 138
4fbafaf3 139static void dispc_save_context(void)
80c39712 140{
c6104b8e 141 int i, j;
80c39712 142
4fbafaf3
TV		 143 DSSDBG("dispc_save_context\n");
144
80c39712
TV		 145 SR(IRQENABLE);
146 SR(CONTROL);
147 SR(CONFIG);
80c39712 148 SR(LINE_NUMBER);
11354dd5
AT		 149 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
150 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 151 SR(GLOBAL_ALPHA);
2a205f34
SS		 152 if (dss_has_feature(FEAT_MGR_LCD2)) {
153 SR(CONTROL2);
2a205f34
SS		 154 SR(CONFIG2);
155 }
80c39712 156
c6104b8e
AT		 157 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
158 SR(DEFAULT_COLOR(i));
159 SR(TRANS_COLOR(i));
160 SR(SIZE_MGR(i));
161 if (i == OMAP_DSS_CHANNEL_DIGIT)
162 continue;
163 SR(TIMING_H(i));
164 SR(TIMING_V(i));
165 SR(POL_FREQ(i));
166 SR(DIVISORo(i));
167
168 SR(DATA_CYCLE1(i));
169 SR(DATA_CYCLE2(i));
170 SR(DATA_CYCLE3(i));
171
332e9d70 172 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 173 SR(CPR_COEF_R(i));
174 SR(CPR_COEF_G(i));
175 SR(CPR_COEF_B(i));
332e9d70 176 }
2a205f34 177 }
80c39712 178
c6104b8e
AT		 179 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
180 SR(OVL_BA0(i));
181 SR(OVL_BA1(i));
182 SR(OVL_POSITION(i));
183 SR(OVL_SIZE(i));
184 SR(OVL_ATTRIBUTES(i));
185 SR(OVL_FIFO_THRESHOLD(i));
186 SR(OVL_ROW_INC(i));
187 SR(OVL_PIXEL_INC(i));
188 if (dss_has_feature(FEAT_PRELOAD))
189 SR(OVL_PRELOAD(i));
190 if (i == OMAP_DSS_GFX) {
191 SR(OVL_WINDOW_SKIP(i));
192 SR(OVL_TABLE_BA(i));
193 continue;
194 }
195 SR(OVL_FIR(i));
196 SR(OVL_PICTURE_SIZE(i));
197 SR(OVL_ACCU0(i));
198 SR(OVL_ACCU1(i));
9b372c2d 199
c6104b8e
AT		 200 for (j = 0; j < 8; j++)
201 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 202
c6104b8e
AT		 203 for (j = 0; j < 8; j++)
204 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 205
c6104b8e
AT		 206 for (j = 0; j < 5; j++)
207 SR(OVL_CONV_COEF(i, j));
ab5ca071 208
c6104b8e
AT		 209 if (dss_has_feature(FEAT_FIR_COEF_V)) {
210 for (j = 0; j < 8; j++)
211 SR(OVL_FIR_COEF_V(i, j));
212 }
9b372c2d 213
c6104b8e
AT		 214 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
215 SR(OVL_BA0_UV(i));
216 SR(OVL_BA1_UV(i));
217 SR(OVL_FIR2(i));
218 SR(OVL_ACCU2_0(i));
219 SR(OVL_ACCU2_1(i));
ab5ca071 220
c6104b8e
AT		 221 for (j = 0; j < 8; j++)
222 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 223
c6104b8e
AT		 224 for (j = 0; j < 8; j++)
225 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 226
c6104b8e
AT		 227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V2(i, j));
229 }
230 if (dss_has_feature(FEAT_ATTR2))
231 SR(OVL_ATTRIBUTES2(i));
ab5ca071 232 }
0cf35df3
MR		 233
234 if (dss_has_feature(FEAT_CORE_CLK_DIV))
235 SR(DIVISOR);
49ea86f3 236
00928eaf 237 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 238 dispc.ctx_valid = true;
239
240 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 241}
242
4fbafaf3 243static void dispc_restore_context(void)
80c39712 244{
c6104b8e 245 int i, j, ctx;
4fbafaf3
TV		 246
247 DSSDBG("dispc_restore_context\n");
248
49ea86f3
TV		 249 if (!dispc.ctx_valid)
250 return;
251
00928eaf 252 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 253
254 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
255 return;
256
257 DSSDBG("ctx_loss_count: saved %d, current %d\n",
258 dispc.ctx_loss_cnt, ctx);
259
75c7d59d 260 /*RR(IRQENABLE);*/
80c39712
TV		 261 /*RR(CONTROL);*/
262 RR(CONFIG);
80c39712 263 RR(LINE_NUMBER);
11354dd5
AT		 264 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
265 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 266 RR(GLOBAL_ALPHA);
c6104b8e 267 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 268 RR(CONFIG2);
80c39712 269
c6104b8e
AT		 270 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
271 RR(DEFAULT_COLOR(i));
272 RR(TRANS_COLOR(i));
273 RR(SIZE_MGR(i));
274 if (i == OMAP_DSS_CHANNEL_DIGIT)
275 continue;
276 RR(TIMING_H(i));
277 RR(TIMING_V(i));
278 RR(POL_FREQ(i));
279 RR(DIVISORo(i));
280
281 RR(DATA_CYCLE1(i));
282 RR(DATA_CYCLE2(i));
283 RR(DATA_CYCLE3(i));
2a205f34 284
332e9d70 285 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 286 RR(CPR_COEF_R(i));
287 RR(CPR_COEF_G(i));
288 RR(CPR_COEF_B(i));
332e9d70 289 }
2a205f34 290 }
80c39712 291
c6104b8e
AT		 292 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
293 RR(OVL_BA0(i));
294 RR(OVL_BA1(i));
295 RR(OVL_POSITION(i));
296 RR(OVL_SIZE(i));
297 RR(OVL_ATTRIBUTES(i));
298 RR(OVL_FIFO_THRESHOLD(i));
299 RR(OVL_ROW_INC(i));
300 RR(OVL_PIXEL_INC(i));
301 if (dss_has_feature(FEAT_PRELOAD))
302 RR(OVL_PRELOAD(i));
303 if (i == OMAP_DSS_GFX) {
304 RR(OVL_WINDOW_SKIP(i));
305 RR(OVL_TABLE_BA(i));
306 continue;
307 }
308 RR(OVL_FIR(i));
309 RR(OVL_PICTURE_SIZE(i));
310 RR(OVL_ACCU0(i));
311 RR(OVL_ACCU1(i));
9b372c2d 312
c6104b8e
AT		 313 for (j = 0; j < 8; j++)
314 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 315
c6104b8e
AT		 316 for (j = 0; j < 8; j++)
317 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 318
c6104b8e
AT		 319 for (j = 0; j < 5; j++)
320 RR(OVL_CONV_COEF(i, j));
ab5ca071 321
c6104b8e
AT		 322 if (dss_has_feature(FEAT_FIR_COEF_V)) {
323 for (j = 0; j < 8; j++)
324 RR(OVL_FIR_COEF_V(i, j));
325 }
9b372c2d 326
c6104b8e
AT		 327 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
328 RR(OVL_BA0_UV(i));
329 RR(OVL_BA1_UV(i));
330 RR(OVL_FIR2(i));
331 RR(OVL_ACCU2_0(i));
332 RR(OVL_ACCU2_1(i));
ab5ca071 333
c6104b8e
AT		 334 for (j = 0; j < 8; j++)
335 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 336
c6104b8e
AT		 337 for (j = 0; j < 8; j++)
338 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 339
c6104b8e
AT		 340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V2(i, j));
342 }
343 if (dss_has_feature(FEAT_ATTR2))
344 RR(OVL_ATTRIBUTES2(i));
ab5ca071 345 }
80c39712 346
0cf35df3
MR		 347 if (dss_has_feature(FEAT_CORE_CLK_DIV))
348 RR(DIVISOR);
349
80c39712
TV		 350 /* enable last, because LCD & DIGIT enable are here */
351 RR(CONTROL);
2a205f34
SS		 352 if (dss_has_feature(FEAT_MGR_LCD2))
353 RR(CONTROL2);
75c7d59d
VS		 354 /* clear spurious SYNC_LOST_DIGIT interrupts */
355 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
356
357 /*
358 * enable last so IRQs won't trigger before
359 * the context is fully restored
360 */
361 RR(IRQENABLE);
49ea86f3
TV		 362
363 DSSDBG("context restored\n");
80c39712
TV		 364}
365
366#undef SR
367#undef RR
368
4fbafaf3
TV		 369int dispc_runtime_get(void)
370{
371 int r;
372
373 DSSDBG("dispc_runtime_get\n");
374
375 r = pm_runtime_get_sync(&dispc.pdev->dev);
376 WARN_ON(r < 0);
377 return r < 0 ? r : 0;
378}
379
380void dispc_runtime_put(void)
381{
382 int r;
383
384 DSSDBG("dispc_runtime_put\n");
385
0eaf9f52 386 r = pm_runtime_put_sync(&dispc.pdev->dev);
4fbafaf3 387 WARN_ON(r < 0);
80c39712
TV		 388}
389
dac57a05
AT		 390static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
391{
392 if (channel == OMAP_DSS_CHANNEL_LCD ||
393 channel == OMAP_DSS_CHANNEL_LCD2)
394 return true;
395 else
396 return false;
397}
4fbafaf3 398
3dcec4d6
TV		 399u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
400{
401 switch (channel) {
402 case OMAP_DSS_CHANNEL_LCD:
403 return DISPC_IRQ_VSYNC;
404 case OMAP_DSS_CHANNEL_LCD2:
405 return DISPC_IRQ_VSYNC2;
406 case OMAP_DSS_CHANNEL_DIGIT:
407 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
408 default:
409 BUG();
410 }
411}
412
7d1365c9
TV		 413u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
414{
415 switch (channel) {
416 case OMAP_DSS_CHANNEL_LCD:
417 return DISPC_IRQ_FRAMEDONE;
418 case OMAP_DSS_CHANNEL_LCD2:
419 return DISPC_IRQ_FRAMEDONE2;
420 case OMAP_DSS_CHANNEL_DIGIT:
421 return 0;
422 default:
423 BUG();
424 }
425}
426
26d9dd0d 427bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 428{
429 int bit;
430
dac57a05 431 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 432 bit = 5; /* GOLCD */
433 else
434 bit = 6; /* GODIGIT */
435
2a205f34
SS		 436 if (channel == OMAP_DSS_CHANNEL_LCD2)
437 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
438 else
439 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 440}
441
26d9dd0d 442void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 443{
444 int bit;
2a205f34 445 bool enable_bit, go_bit;
80c39712 446
dac57a05 447 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 448 bit = 0; /* LCDENABLE */
449 else
450 bit = 1; /* DIGITALENABLE */
451
452 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 453 if (channel == OMAP_DSS_CHANNEL_LCD2)
454 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
455 else
456 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
457
458 if (!enable_bit)
e6d80f95 459 return;
80c39712 460
dac57a05 461 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 462 bit = 5; /* GOLCD */
463 else
464 bit = 6; /* GODIGIT */
465
2a205f34
SS		 466 if (channel == OMAP_DSS_CHANNEL_LCD2)
467 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
468 else
469 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
470
471 if (go_bit) {
80c39712 472 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 473 return;
80c39712
TV		 474 }
475
2a205f34
SS		 476 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
477 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 478
2a205f34
SS		 479 if (channel == OMAP_DSS_CHANNEL_LCD2)
480 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
481 else
482 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 483}
484
f0e5caab 485static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 486{
9b372c2d 487 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 488}
489
f0e5caab 490static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 491{
9b372c2d 492 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 493}
494
f0e5caab 495static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 496{
9b372c2d 497 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 498}
499
f0e5caab 500static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 501{
502 BUG_ON(plane == OMAP_DSS_GFX);
503
504 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
505}
506
f0e5caab
TV		 507static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
508 u32 value)
ab5ca071
AJ		 509{
510 BUG_ON(plane == OMAP_DSS_GFX);
511
512 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
513}
514
f0e5caab 515static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 516{
517 BUG_ON(plane == OMAP_DSS_GFX);
518
519 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
520}
521
debd9074
CM		 522static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
523 int fir_vinc, int five_taps,
524 enum omap_color_component color_comp)
80c39712 525{
debd9074 526 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 527 int i;
528
debd9074
CM		 529 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
530 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 531
532 for (i = 0; i < 8; i++) {
533 u32 h, hv;
534
debd9074
CM		 535 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
536 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
537 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
538 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
539 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
540 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
541 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
542 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 543
0d66cbb5 544 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 545 dispc_ovl_write_firh_reg(plane, i, h);
546 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 547 } else {
f0e5caab
TV		 548 dispc_ovl_write_firh2_reg(plane, i, h);
549 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 550 }
551
80c39712
TV		 552 }
553
66be8f6c
GI		 554 if (five_taps) {
555 for (i = 0; i < 8; i++) {
556 u32 v;
debd9074
CM		 557 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
558 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 559 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 560 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 561 else
f0e5caab 562 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 563 }
80c39712
TV		 564 }
565}
566
567static void _dispc_setup_color_conv_coef(void)
568{
ac01c29e 569 int i;
80c39712
TV		 570 const struct color_conv_coef {
571 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
572 int full_range;
573 } ctbl_bt601_5 = {
574 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
575 };
576
577 const struct color_conv_coef *ct;
578
579#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
580
581 ct = &ctbl_bt601_5;
582
ac01c29e
AT		 583 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
584 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
585 CVAL(ct->rcr, ct->ry));
586 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
587 CVAL(ct->gy, ct->rcb));
588 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
589 CVAL(ct->gcb, ct->gcr));
590 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
591 CVAL(ct->bcr, ct->by));
592 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
593 CVAL(0, ct->bcb));
594
595 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
596 11, 11);
597 }
80c39712
TV		 598
599#undef CVAL
80c39712
TV		 600}
601
602
f0e5caab 603static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 604{
9b372c2d 605 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 606}
607
f0e5caab 608static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 609{
9b372c2d 610 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 611}
612
f0e5caab 613static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 614{
615 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
616}
617
f0e5caab 618static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 619{
620 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
621}
622
f0e5caab 623static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 624{
80c39712 625 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 626
627 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 628}
629
f0e5caab 630static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 631{
80c39712 632 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 633
634 if (plane == OMAP_DSS_GFX)
635 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
636 else
637 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 638}
639
f0e5caab 640static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 641{
642 u32 val;
80c39712
TV		 643
644 BUG_ON(plane == OMAP_DSS_GFX);
645
646 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 647
648 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 649}
650
54128701
AT		 651static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
652{
653 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
654
655 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
656 return;
657
658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
659}
660
661static void dispc_ovl_enable_zorder_planes(void)
662{
663 int i;
664
665 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
666 return;
667
668 for (i = 0; i < dss_feat_get_num_ovls(); i++)
669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
670}
671
f0e5caab 672static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 673{
f6dc8150 674 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 675
f6dc8150 676 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 677 return;
678
9b372c2d 679 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 680}
681
f0e5caab 682static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 683{
b8c095b4 684 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 685 int shift;
f6dc8150 686 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 687
f6dc8150 688 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 689 return;
a0acb557 690
fe3cc9d6
TV		 691 shift = shifts[plane];
692 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 693}
694
f0e5caab 695static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 696{
9b372c2d 697 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 698}
699
f0e5caab 700static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 701{
9b372c2d 702 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 703}
704
f0e5caab 705static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 706 enum omap_color_mode color_mode)
707{
708 u32 m = 0;
f20e4220
AJ		 709 if (plane != OMAP_DSS_GFX) {
710 switch (color_mode) {
711 case OMAP_DSS_COLOR_NV12:
712 m = 0x0; break;
08f3267e 713 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 714 m = 0x1; break;
715 case OMAP_DSS_COLOR_RGBA16:
716 m = 0x2; break;
08f3267e 717 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 718 m = 0x4; break;
719 case OMAP_DSS_COLOR_ARGB16:
720 m = 0x5; break;
721 case OMAP_DSS_COLOR_RGB16:
722 m = 0x6; break;
723 case OMAP_DSS_COLOR_ARGB16_1555:
724 m = 0x7; break;
725 case OMAP_DSS_COLOR_RGB24U:
726 m = 0x8; break;
727 case OMAP_DSS_COLOR_RGB24P:
728 m = 0x9; break;
729 case OMAP_DSS_COLOR_YUV2:
730 m = 0xa; break;
731 case OMAP_DSS_COLOR_UYVY:
732 m = 0xb; break;
733 case OMAP_DSS_COLOR_ARGB32:
734 m = 0xc; break;
735 case OMAP_DSS_COLOR_RGBA32:
736 m = 0xd; break;
737 case OMAP_DSS_COLOR_RGBX32:
738 m = 0xe; break;
739 case OMAP_DSS_COLOR_XRGB16_1555:
740 m = 0xf; break;
741 default:
742 BUG(); break;
743 }
744 } else {
745 switch (color_mode) {
746 case OMAP_DSS_COLOR_CLUT1:
747 m = 0x0; break;
748 case OMAP_DSS_COLOR_CLUT2:
749 m = 0x1; break;
750 case OMAP_DSS_COLOR_CLUT4:
751 m = 0x2; break;
752 case OMAP_DSS_COLOR_CLUT8:
753 m = 0x3; break;
754 case OMAP_DSS_COLOR_RGB12U:
755 m = 0x4; break;
756 case OMAP_DSS_COLOR_ARGB16:
757 m = 0x5; break;
758 case OMAP_DSS_COLOR_RGB16:
759 m = 0x6; break;
760 case OMAP_DSS_COLOR_ARGB16_1555:
761 m = 0x7; break;
762 case OMAP_DSS_COLOR_RGB24U:
763 m = 0x8; break;
764 case OMAP_DSS_COLOR_RGB24P:
765 m = 0x9; break;
08f3267e 766 case OMAP_DSS_COLOR_RGBX16:
f20e4220 767 m = 0xa; break;
08f3267e 768 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 769 m = 0xb; break;
770 case OMAP_DSS_COLOR_ARGB32:
771 m = 0xc; break;
772 case OMAP_DSS_COLOR_RGBA32:
773 m = 0xd; break;
774 case OMAP_DSS_COLOR_RGBX32:
775 m = 0xe; break;
776 case OMAP_DSS_COLOR_XRGB16_1555:
777 m = 0xf; break;
778 default:
779 BUG(); break;
780 }
80c39712
TV		 781 }
782
9b372c2d 783 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 784}
785
f427984e 786void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 787{
788 int shift;
789 u32 val;
2a205f34 790 int chan = 0, chan2 = 0;
80c39712
TV		 791
792 switch (plane) {
793 case OMAP_DSS_GFX:
794 shift = 8;
795 break;
796 case OMAP_DSS_VIDEO1:
797 case OMAP_DSS_VIDEO2:
b8c095b4 798 case OMAP_DSS_VIDEO3:
80c39712
TV		 799 shift = 16;
800 break;
801 default:
802 BUG();
803 return;
804 }
805
9b372c2d 806 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 807 if (dss_has_feature(FEAT_MGR_LCD2)) {
808 switch (channel) {
809 case OMAP_DSS_CHANNEL_LCD:
810 chan = 0;
811 chan2 = 0;
812 break;
813 case OMAP_DSS_CHANNEL_DIGIT:
814 chan = 1;
815 chan2 = 0;
816 break;
817 case OMAP_DSS_CHANNEL_LCD2:
818 chan = 0;
819 chan2 = 1;
820 break;
821 default:
822 BUG();
823 }
824
825 val = FLD_MOD(val, chan, shift, shift);
826 val = FLD_MOD(val, chan2, 31, 30);
827 } else {
828 val = FLD_MOD(val, channel, shift, shift);
829 }
9b372c2d 830 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 831}
832
2cc5d1af
TV		 833static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
834{
835 int shift;
836 u32 val;
837 enum omap_channel channel;
838
839 switch (plane) {
840 case OMAP_DSS_GFX:
841 shift = 8;
842 break;
843 case OMAP_DSS_VIDEO1:
844 case OMAP_DSS_VIDEO2:
845 case OMAP_DSS_VIDEO3:
846 shift = 16;
847 break;
848 default:
849 BUG();
850 }
851
852 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
853
854 if (dss_has_feature(FEAT_MGR_LCD2)) {
855 if (FLD_GET(val, 31, 30) == 0)
856 channel = FLD_GET(val, shift, shift);
857 else
858 channel = OMAP_DSS_CHANNEL_LCD2;
859 } else {
860 channel = FLD_GET(val, shift, shift);
861 }
862
863 return channel;
864}
865
f0e5caab 866static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 867 enum omap_burst_size burst_size)
868{
b8c095b4 869 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 870 int shift;
80c39712 871
fe3cc9d6 872 shift = shifts[plane];
5ed8cf5b 873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 874}
875
5ed8cf5b
TV		 876static void dispc_configure_burst_sizes(void)
877{
878 int i;
879 const int burst_size = BURST_SIZE_X8;
880
881 /* Configure burst size always to maximum size */
882 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 883 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 884}
885
83fa2f2e 886static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 887{
888 unsigned unit = dss_feat_get_burst_size_unit();
889 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
890 return unit * 8;
891}
892
d3862610
M		 893void dispc_enable_gamma_table(bool enable)
894{
895 /*
896 * This is partially implemented to support only disabling of
897 * the gamma table.
898 */
899 if (enable) {
900 DSSWARN("Gamma table enabling for TV not yet supported");
901 return;
902 }
903
904 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
905}
906
c64dca40 907static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 908{
909 u16 reg;
910
911 if (channel == OMAP_DSS_CHANNEL_LCD)
912 reg = DISPC_CONFIG;
913 else if (channel == OMAP_DSS_CHANNEL_LCD2)
914 reg = DISPC_CONFIG2;
915 else
916 return;
917
918 REG_FLD_MOD(reg, enable, 15, 15);
919}
920
c64dca40 921static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 922 struct omap_dss_cpr_coefs *coefs)
923{
924 u32 coef_r, coef_g, coef_b;
925
dac57a05 926 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 927 return;
928
929 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
930 FLD_VAL(coefs->rb, 9, 0);
931 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
932 FLD_VAL(coefs->gb, 9, 0);
933 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
934 FLD_VAL(coefs->bb, 9, 0);
935
936 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
937 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
938 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
939}
940
f0e5caab 941static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 942{
943 u32 val;
944
945 BUG_ON(plane == OMAP_DSS_GFX);
946
9b372c2d 947 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 948 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 949 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 950}
951
c3d92529 952static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 953{
b8c095b4 954 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 955 int shift;
80c39712 956
fe3cc9d6
TV		 957 shift = shifts[plane];
958 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 959}
960
8f366162 961static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 962 u16 height)
80c39712
TV		 963{
964 u32 val;
80c39712 965
80c39712 966 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 967 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 968}
969
970static void dispc_read_plane_fifo_sizes(void)
971{
80c39712
TV		 972 u32 size;
973 int plane;
a0acb557 974 u8 start, end;
5ed8cf5b
TV		 975 u32 unit;
976
977 unit = dss_feat_get_buffer_size_unit();
80c39712 978
a0acb557 979 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 980
e13a138b 981 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 982 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
983 size *= unit;
80c39712
TV		 984 dispc.fifo_size[plane] = size;
985 }
80c39712
TV		 986}
987
83fa2f2e 988static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 989{
990 return dispc.fifo_size[plane];
991}
992
6f04e1bf 993void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 994{
a0acb557 995 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 996 u32 unit;
997
998 unit = dss_feat_get_buffer_size_unit();
999
1000 WARN_ON(low % unit != 0);
1001 WARN_ON(high % unit != 0);
1002
1003 low /= unit;
1004 high /= unit;
a0acb557 1005
9b372c2d
AT		 1006 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1007 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1008
3cb5d966 1009 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1010 plane,
9b372c2d 1011 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1012 lo_start, lo_end) * unit,
9b372c2d 1013 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1014 hi_start, hi_end) * unit,
1015 low * unit, high * unit);
80c39712 1016
9b372c2d 1017 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1018 FLD_VAL(high, hi_start, hi_end) |
1019 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1020}
1021
1022void dispc_enable_fifomerge(bool enable)
1023{
e6b0f884
TV		 1024 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1025 WARN_ON(enable);
1026 return;
1027 }
1028
80c39712
TV		 1029 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1030 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1031}
1032
83fa2f2e 1033void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1034 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1035 bool manual_update)
83fa2f2e
TV		 1036{
1037 /*
1038 * All sizes are in bytes. Both the buffer and burst are made of
1039 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1040 */
1041
1042 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1043 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1044 int i;
83fa2f2e
TV		 1045
1046 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1047 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1048
e0e405b9
TV		 1049 if (use_fifomerge) {
1050 total_fifo_size = 0;
1051 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1052 total_fifo_size += dispc_ovl_get_fifo_size(i);
1053 } else {
1054 total_fifo_size = ovl_fifo_size;
1055 }
1056
1057 /*
1058 * We use the same low threshold for both fifomerge and non-fifomerge
1059 * cases, but for fifomerge we calculate the high threshold using the
1060 * combined fifo size
1061 */
1062
3568f2a4 1063 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1064 *fifo_low = ovl_fifo_size - burst_size * 2;
1065 *fifo_high = total_fifo_size - burst_size;
1066 } else {
1067 *fifo_low = ovl_fifo_size - burst_size;
1068 *fifo_high = total_fifo_size - buf_unit;
1069 }
83fa2f2e
TV		 1070}
1071
f0e5caab 1072static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1073 int hinc, int vinc,
1074 enum omap_color_component color_comp)
80c39712
TV		 1075{
1076 u32 val;
80c39712 1077
0d66cbb5
AJ		 1078 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1079 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1080
0d66cbb5
AJ		 1081 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1082 &hinc_start, &hinc_end);
1083 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1084 &vinc_start, &vinc_end);
1085 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1086 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1087
0d66cbb5
AJ		 1088 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1089 } else {
1090 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1091 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1092 }
80c39712
TV		 1093}
1094
f0e5caab 1095static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1096{
1097 u32 val;
87a7484b 1098 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1099
87a7484b
AT		 1100 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1101 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1102
1103 val = FLD_VAL(vaccu, vert_start, vert_end) |
1104 FLD_VAL(haccu, hor_start, hor_end);
1105
9b372c2d 1106 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1107}
1108
f0e5caab 1109static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1110{
1111 u32 val;
87a7484b 1112 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1113
87a7484b
AT		 1114 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1115 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1116
1117 val = FLD_VAL(vaccu, vert_start, vert_end) |
1118 FLD_VAL(haccu, hor_start, hor_end);
1119
9b372c2d 1120 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1121}
1122
f0e5caab
TV		 1123static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1124 int vaccu)
ab5ca071
AJ		 1125{
1126 u32 val;
1127
1128 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1129 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1130}
1131
f0e5caab
TV		 1132static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1133 int vaccu)
ab5ca071
AJ		 1134{
1135 u32 val;
1136
1137 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1138 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1139}
80c39712 1140
f0e5caab 1141static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1142 u16 orig_width, u16 orig_height,
1143 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1144 bool five_taps, u8 rotation,
1145 enum omap_color_component color_comp)
80c39712 1146{
0d66cbb5 1147 int fir_hinc, fir_vinc;
80c39712 1148
ed14a3ce
AJ		 1149 fir_hinc = 1024 * orig_width / out_width;
1150 fir_vinc = 1024 * orig_height / out_height;
80c39712 1151
debd9074
CM		 1152 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1153 color_comp);
f0e5caab 1154 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1155}
1156
05dd0f53
CM		 1157static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1158 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1159 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1160{
1161 int h_accu2_0, h_accu2_1;
1162 int v_accu2_0, v_accu2_1;
1163 int chroma_hinc, chroma_vinc;
1164 int idx;
1165
1166 struct accu {
1167 s8 h0_m, h0_n;
1168 s8 h1_m, h1_n;
1169 s8 v0_m, v0_n;
1170 s8 v1_m, v1_n;
1171 };
1172
1173 const struct accu *accu_table;
1174 const struct accu *accu_val;
1175
1176 static const struct accu accu_nv12[4] = {
1177 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1178 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1179 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1180 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1181 };
1182
1183 static const struct accu accu_nv12_ilace[4] = {
1184 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1185 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1186 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1187 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1188 };
1189
1190 static const struct accu accu_yuv[4] = {
1191 { 0, 1, 0, 1, 0, 1, 0, 1 },
1192 { 0, 1, 0, 1, 0, 1, 0, 1 },
1193 { -1, 1, 0, 1, 0, 1, 0, 1 },
1194 { 0, 1, 0, 1, -1, 1, 0, 1 },
1195 };
1196
1197 switch (rotation) {
1198 case OMAP_DSS_ROT_0:
1199 idx = 0;
1200 break;
1201 case OMAP_DSS_ROT_90:
1202 idx = 1;
1203 break;
1204 case OMAP_DSS_ROT_180:
1205 idx = 2;
1206 break;
1207 case OMAP_DSS_ROT_270:
1208 idx = 3;
1209 break;
1210 default:
1211 BUG();
1212 }
1213
1214 switch (color_mode) {
1215 case OMAP_DSS_COLOR_NV12:
1216 if (ilace)
1217 accu_table = accu_nv12_ilace;
1218 else
1219 accu_table = accu_nv12;
1220 break;
1221 case OMAP_DSS_COLOR_YUV2:
1222 case OMAP_DSS_COLOR_UYVY:
1223 accu_table = accu_yuv;
1224 break;
1225 default:
1226 BUG();
1227 }
1228
1229 accu_val = &accu_table[idx];
1230
1231 chroma_hinc = 1024 * orig_width / out_width;
1232 chroma_vinc = 1024 * orig_height / out_height;
1233
1234 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1235 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1236 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1237 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1238
1239 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1240 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1241}
1242
f0e5caab 1243static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1244 u16 orig_width, u16 orig_height,
1245 u16 out_width, u16 out_height,
1246 bool ilace, bool five_taps,
1247 bool fieldmode, enum omap_color_mode color_mode,
1248 u8 rotation)
1249{
1250 int accu0 = 0;
1251 int accu1 = 0;
1252 u32 l;
80c39712 1253
f0e5caab 1254 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1255 out_width, out_height, five_taps,
1256 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1257 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1258
87a7484b
AT		 1259 /* RESIZEENABLE and VERTICALTAPS */
1260 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1261 l |= (orig_width != out_width) ? (1 << 5) : 0;
1262 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1263 l |= five_taps ? (1 << 21) : 0;
80c39712 1264
87a7484b
AT		 1265 /* VRESIZECONF and HRESIZECONF */
1266 if (dss_has_feature(FEAT_RESIZECONF)) {
1267 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1268 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1269 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1270 }
80c39712 1271
87a7484b
AT		 1272 /* LINEBUFFERSPLIT */
1273 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1274 l &= ~(0x1 << 22);
1275 l |= five_taps ? (1 << 22) : 0;
1276 }
80c39712 1277
9b372c2d 1278 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1279
1280 /*
1281 * field 0 = even field = bottom field
1282 * field 1 = odd field = top field
1283 */
1284 if (ilace && !fieldmode) {
1285 accu1 = 0;
0d66cbb5 1286 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1287 if (accu0 >= 1024/2) {
1288 accu1 = 1024/2;
1289 accu0 -= accu1;
1290 }
1291 }
1292
f0e5caab
TV		 1293 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1294 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1295}
1296
f0e5caab 1297static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1298 u16 orig_width, u16 orig_height,
1299 u16 out_width, u16 out_height,
1300 bool ilace, bool five_taps,
1301 bool fieldmode, enum omap_color_mode color_mode,
1302 u8 rotation)
1303{
1304 int scale_x = out_width != orig_width;
1305 int scale_y = out_height != orig_height;
1306
1307 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1308 return;
1309 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1310 color_mode != OMAP_DSS_COLOR_UYVY &&
1311 color_mode != OMAP_DSS_COLOR_NV12)) {
1312 /* reset chroma resampling for RGB formats */
1313 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1314 return;
1315 }
36377357
TV		 1316
1317 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1318 out_height, ilace, color_mode, rotation);
1319
0d66cbb5
AJ		 1320 switch (color_mode) {
1321 case OMAP_DSS_COLOR_NV12:
1322 /* UV is subsampled by 2 vertically*/
1323 orig_height >>= 1;
1324 /* UV is subsampled by 2 horz.*/
1325 orig_width >>= 1;
1326 break;
1327 case OMAP_DSS_COLOR_YUV2:
1328 case OMAP_DSS_COLOR_UYVY:
1329 /*For YUV422 with 90/270 rotation,
1330 *we don't upsample chroma
1331 */
1332 if (rotation == OMAP_DSS_ROT_0 ||
1333 rotation == OMAP_DSS_ROT_180)
1334 /* UV is subsampled by 2 hrz*/
1335 orig_width >>= 1;
1336 /* must use FIR for YUV422 if rotated */
1337 if (rotation != OMAP_DSS_ROT_0)
1338 scale_x = scale_y = true;
1339 break;
1340 default:
1341 BUG();
1342 }
1343
1344 if (out_width != orig_width)
1345 scale_x = true;
1346 if (out_height != orig_height)
1347 scale_y = true;
1348
f0e5caab 1349 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1350 out_width, out_height, five_taps,
1351 rotation, DISPC_COLOR_COMPONENT_UV);
1352
1353 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1354 (scale_x || scale_y) ? 1 : 0, 8, 8);
1355 /* set H scaling */
1356 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1357 /* set V scaling */
1358 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1359}
1360
f0e5caab 1361static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1362 u16 orig_width, u16 orig_height,
1363 u16 out_width, u16 out_height,
1364 bool ilace, bool five_taps,
1365 bool fieldmode, enum omap_color_mode color_mode,
1366 u8 rotation)
1367{
1368 BUG_ON(plane == OMAP_DSS_GFX);
1369
f0e5caab 1370 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1371 orig_width, orig_height,
1372 out_width, out_height,
1373 ilace, five_taps,
1374 fieldmode, color_mode,
1375 rotation);
1376
f0e5caab 1377 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1378 orig_width, orig_height,
1379 out_width, out_height,
1380 ilace, five_taps,
1381 fieldmode, color_mode,
1382 rotation);
1383}
1384
f0e5caab 1385static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1386 bool mirroring, enum omap_color_mode color_mode)
1387{
87a7484b
AT		 1388 bool row_repeat = false;
1389 int vidrot = 0;
1390
80c39712
TV		 1391 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1392 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1393
1394 if (mirroring) {
1395 switch (rotation) {
1396 case OMAP_DSS_ROT_0:
1397 vidrot = 2;
1398 break;
1399 case OMAP_DSS_ROT_90:
1400 vidrot = 1;
1401 break;
1402 case OMAP_DSS_ROT_180:
1403 vidrot = 0;
1404 break;
1405 case OMAP_DSS_ROT_270:
1406 vidrot = 3;
1407 break;
1408 }
1409 } else {
1410 switch (rotation) {
1411 case OMAP_DSS_ROT_0:
1412 vidrot = 0;
1413 break;
1414 case OMAP_DSS_ROT_90:
1415 vidrot = 1;
1416 break;
1417 case OMAP_DSS_ROT_180:
1418 vidrot = 2;
1419 break;
1420 case OMAP_DSS_ROT_270:
1421 vidrot = 3;
1422 break;
1423 }
1424 }
1425
80c39712 1426 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1427 row_repeat = true;
80c39712 1428 else
87a7484b 1429 row_repeat = false;
80c39712 1430 }
87a7484b 1431
9b372c2d 1432 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1433 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1434 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1435 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1436}
1437
1438static int color_mode_to_bpp(enum omap_color_mode color_mode)
1439{
1440 switch (color_mode) {
1441 case OMAP_DSS_COLOR_CLUT1:
1442 return 1;
1443 case OMAP_DSS_COLOR_CLUT2:
1444 return 2;
1445 case OMAP_DSS_COLOR_CLUT4:
1446 return 4;
1447 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1448 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1449 return 8;
1450 case OMAP_DSS_COLOR_RGB12U:
1451 case OMAP_DSS_COLOR_RGB16:
1452 case OMAP_DSS_COLOR_ARGB16:
1453 case OMAP_DSS_COLOR_YUV2:
1454 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1455 case OMAP_DSS_COLOR_RGBA16:
1456 case OMAP_DSS_COLOR_RGBX16:
1457 case OMAP_DSS_COLOR_ARGB16_1555:
1458 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1459 return 16;
1460 case OMAP_DSS_COLOR_RGB24P:
1461 return 24;
1462 case OMAP_DSS_COLOR_RGB24U:
1463 case OMAP_DSS_COLOR_ARGB32:
1464 case OMAP_DSS_COLOR_RGBA32:
1465 case OMAP_DSS_COLOR_RGBX32:
1466 return 32;
1467 default:
1468 BUG();
1469 }
1470}
1471
1472static s32 pixinc(int pixels, u8 ps)
1473{
1474 if (pixels == 1)
1475 return 1;
1476 else if (pixels > 1)
1477 return 1 + (pixels - 1) * ps;
1478 else if (pixels < 0)
1479 return 1 - (-pixels + 1) * ps;
1480 else
1481 BUG();
1482}
1483
1484static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1485 u16 screen_width,
1486 u16 width, u16 height,
1487 enum omap_color_mode color_mode, bool fieldmode,
1488 unsigned int field_offset,
1489 unsigned *offset0, unsigned *offset1,
aed74b55 1490 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1491{
1492 u8 ps;
1493
1494 /* FIXME CLUT formats */
1495 switch (color_mode) {
1496 case OMAP_DSS_COLOR_CLUT1:
1497 case OMAP_DSS_COLOR_CLUT2:
1498 case OMAP_DSS_COLOR_CLUT4:
1499 case OMAP_DSS_COLOR_CLUT8:
1500 BUG();
1501 return;
1502 case OMAP_DSS_COLOR_YUV2:
1503 case OMAP_DSS_COLOR_UYVY:
1504 ps = 4;
1505 break;
1506 default:
1507 ps = color_mode_to_bpp(color_mode) / 8;
1508 break;
1509 }
1510
1511 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1512 width, height);
1513
1514 /*
1515 * field 0 = even field = bottom field
1516 * field 1 = odd field = top field
1517 */
1518 switch (rotation + mirror * 4) {
1519 case OMAP_DSS_ROT_0:
1520 case OMAP_DSS_ROT_180:
1521 /*
1522 * If the pixel format is YUV or UYVY divide the width
1523 * of the image by 2 for 0 and 180 degree rotation.
1524 */
1525 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1526 color_mode == OMAP_DSS_COLOR_UYVY)
1527 width = width >> 1;
1528 case OMAP_DSS_ROT_90:
1529 case OMAP_DSS_ROT_270:
1530 *offset1 = 0;
1531 if (field_offset)
1532 *offset0 = field_offset * screen_width * ps;
1533 else
1534 *offset0 = 0;
1535
aed74b55
CM		 1536 *row_inc = pixinc(1 +
1537 (y_predecim * screen_width - x_predecim * width) +
1538 (fieldmode ? screen_width : 0), ps);
1539 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1540 break;
1541
1542 case OMAP_DSS_ROT_0 + 4:
1543 case OMAP_DSS_ROT_180 + 4:
1544 /* If the pixel format is YUV or UYVY divide the width
1545 * of the image by 2 for 0 degree and 180 degree
1546 */
1547 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1548 color_mode == OMAP_DSS_COLOR_UYVY)
1549 width = width >> 1;
1550 case OMAP_DSS_ROT_90 + 4:
1551 case OMAP_DSS_ROT_270 + 4:
1552 *offset1 = 0;
1553 if (field_offset)
1554 *offset0 = field_offset * screen_width * ps;
1555 else
1556 *offset0 = 0;
aed74b55
CM		 1557 *row_inc = pixinc(1 -
1558 (y_predecim * screen_width + x_predecim * width) -
1559 (fieldmode ? screen_width : 0), ps);
1560 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1561 break;
1562
1563 default:
1564 BUG();
1565 }
1566}
1567
1568static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1569 u16 screen_width,
1570 u16 width, u16 height,
1571 enum omap_color_mode color_mode, bool fieldmode,
1572 unsigned int field_offset,
1573 unsigned *offset0, unsigned *offset1,
aed74b55 1574 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1575{
1576 u8 ps;
1577 u16 fbw, fbh;
1578
1579 /* FIXME CLUT formats */
1580 switch (color_mode) {
1581 case OMAP_DSS_COLOR_CLUT1:
1582 case OMAP_DSS_COLOR_CLUT2:
1583 case OMAP_DSS_COLOR_CLUT4:
1584 case OMAP_DSS_COLOR_CLUT8:
1585 BUG();
1586 return;
1587 default:
1588 ps = color_mode_to_bpp(color_mode) / 8;
1589 break;
1590 }
1591
1592 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1593 width, height);
1594
1595 /* width & height are overlay sizes, convert to fb sizes */
1596
1597 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1598 fbw = width;
1599 fbh = height;
1600 } else {
1601 fbw = height;
1602 fbh = width;
1603 }
1604
1605 /*
1606 * field 0 = even field = bottom field
1607 * field 1 = odd field = top field
1608 */
1609 switch (rotation + mirror * 4) {
1610 case OMAP_DSS_ROT_0:
1611 *offset1 = 0;
1612 if (field_offset)
1613 *offset0 = *offset1 + field_offset * screen_width * ps;
1614 else
1615 *offset0 = *offset1;
aed74b55
CM		 1616 *row_inc = pixinc(1 +
1617 (y_predecim * screen_width - fbw * x_predecim) +
1618 (fieldmode ? screen_width : 0), ps);
1619 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620 color_mode == OMAP_DSS_COLOR_UYVY)
1621 *pix_inc = pixinc(x_predecim, 2 * ps);
1622 else
1623 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1624 break;
1625 case OMAP_DSS_ROT_90:
1626 *offset1 = screen_width * (fbh - 1) * ps;
1627 if (field_offset)
1628 *offset0 = *offset1 + field_offset * ps;
1629 else
1630 *offset0 = *offset1;
aed74b55
CM		 1631 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1632 y_predecim + (fieldmode ? 1 : 0), ps);
1633 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1634 break;
1635 case OMAP_DSS_ROT_180:
1636 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1637 if (field_offset)
1638 *offset0 = *offset1 - field_offset * screen_width * ps;
1639 else
1640 *offset0 = *offset1;
1641 *row_inc = pixinc(-1 -
aed74b55
CM		 1642 (y_predecim * screen_width - fbw * x_predecim) -
1643 (fieldmode ? screen_width : 0), ps);
1644 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1645 color_mode == OMAP_DSS_COLOR_UYVY)
1646 *pix_inc = pixinc(-x_predecim, 2 * ps);
1647 else
1648 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1649 break;
1650 case OMAP_DSS_ROT_270:
1651 *offset1 = (fbw - 1) * ps;
1652 if (field_offset)
1653 *offset0 = *offset1 - field_offset * ps;
1654 else
1655 *offset0 = *offset1;
aed74b55
CM		 1656 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1657 y_predecim - (fieldmode ? 1 : 0), ps);
1658 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1659 break;
1660
1661 /* mirroring */
1662 case OMAP_DSS_ROT_0 + 4:
1663 *offset1 = (fbw - 1) * ps;
1664 if (field_offset)
1665 *offset0 = *offset1 + field_offset * screen_width * ps;
1666 else
1667 *offset0 = *offset1;
aed74b55 1668 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1669 (fieldmode ? screen_width : 0),
1670 ps);
aed74b55
CM		 1671 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1672 color_mode == OMAP_DSS_COLOR_UYVY)
1673 *pix_inc = pixinc(-x_predecim, 2 * ps);
1674 else
1675 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1676 break;
1677
1678 case OMAP_DSS_ROT_90 + 4:
1679 *offset1 = 0;
1680 if (field_offset)
1681 *offset0 = *offset1 + field_offset * ps;
1682 else
1683 *offset0 = *offset1;
aed74b55
CM		 1684 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1685 y_predecim + (fieldmode ? 1 : 0),
80c39712 1686 ps);
aed74b55 1687 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1688 break;
1689
1690 case OMAP_DSS_ROT_180 + 4:
1691 *offset1 = screen_width * (fbh - 1) * ps;
1692 if (field_offset)
1693 *offset0 = *offset1 - field_offset * screen_width * ps;
1694 else
1695 *offset0 = *offset1;
aed74b55 1696 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1697 (fieldmode ? screen_width : 0),
1698 ps);
aed74b55
CM		 1699 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1700 color_mode == OMAP_DSS_COLOR_UYVY)
1701 *pix_inc = pixinc(x_predecim, 2 * ps);
1702 else
1703 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1704 break;
1705
1706 case OMAP_DSS_ROT_270 + 4:
1707 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1708 if (field_offset)
1709 *offset0 = *offset1 - field_offset * ps;
1710 else
1711 *offset0 = *offset1;
aed74b55
CM		 1712 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1713 y_predecim - (fieldmode ? 1 : 0),
80c39712 1714 ps);
aed74b55 1715 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1716 break;
1717
1718 default:
1719 BUG();
1720 }
1721}
1722
7faa9233
CM		 1723/*
1724 * This function is used to avoid synclosts in OMAP3, because of some
1725 * undocumented horizontal position and timing related limitations.
1726 */
81ab95b7
AT		 1727static int check_horiz_timing_omap3(enum omap_channel channel,
1728 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1729 u16 width, u16 height, u16 out_width, u16 out_height)
1730{
1731 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1732 unsigned long nonactive, lclk, pclk;
1733 static const u8 limits[3] = { 8, 10, 20 };
1734 u64 val, blank;
1735 int i;
1736
81ab95b7 1737 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 1738 pclk = dispc_mgr_pclk_rate(channel);
1739 if (dispc_mgr_is_lcd(channel))
1740 lclk = dispc_mgr_lclk_rate(channel);
1741 else
1742 lclk = dispc_fclk_rate();
1743
1744 i = 0;
1745 if (out_height < height)
1746 i++;
1747 if (out_width < width)
1748 i++;
81ab95b7 1749 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1750 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1751 if (blank <= limits[i])
1752 return -EINVAL;
1753
1754 /*
1755 * Pixel data should be prepared before visible display point starts.
1756 * So, atleast DS-2 lines must have already been fetched by DISPC
1757 * during nonactive - pos_x period.
1758 */
1759 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1760 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1761 val, max(0, DS - 2) * width);
1762 if (val < max(0, DS - 2) * width)
1763 return -EINVAL;
1764
1765 /*
1766 * All lines need to be refilled during the nonactive period of which
1767 * only one line can be loaded during the active period. So, atleast
1768 * DS - 1 lines should be loaded during nonactive period.
1769 */
1770 val = div_u64((u64)nonactive * lclk, pclk);
1771 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1772 val, max(0, DS - 1) * width);
1773 if (val < max(0, DS - 1) * width)
1774 return -EINVAL;
1775
1776 return 0;
1777}
1778
8b53d991 1779static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1780 const struct omap_video_timings *mgr_timings, u16 width,
1781 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1782 enum omap_color_mode color_mode)
80c39712 1783{
8b53d991 1784 u32 core_clk = 0;
26d9dd0d 1785 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1786
7282f1b7
CM		 1787 if (height <= out_height && width <= out_width)
1788 return (unsigned long) pclk;
1789
80c39712 1790 if (height > out_height) {
81ab95b7 1791 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1792
1793 tmp = pclk * height * out_width;
1794 do_div(tmp, 2 * out_height * ppl);
8b53d991 1795 core_clk = tmp;
80c39712 1796
2d9c5597
VS		 1797 if (height > 2 * out_height) {
1798 if (ppl == out_width)
1799 return 0;
1800
80c39712
TV		 1801 tmp = pclk * (height - 2 * out_height) * out_width;
1802 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1803 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1804 }
1805 }
1806
1807 if (width > out_width) {
1808 tmp = pclk * width;
1809 do_div(tmp, out_width);
8b53d991 1810 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1811
1812 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1813 core_clk <<= 1;
80c39712
TV		 1814 }
1815
8b53d991 1816 return core_clk;
80c39712
TV		 1817}
1818
8b53d991 1819static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
ff1b2cde 1820 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1821{
1822 unsigned int hf, vf;
79ee89cd 1823 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1824
1825 /*
1826 * FIXME how to determine the 'A' factor
1827 * for the no downscaling case ?
1828 */
1829
1830 if (width > 3 * out_width)
1831 hf = 4;
1832 else if (width > 2 * out_width)
1833 hf = 3;
1834 else if (width > out_width)
1835 hf = 2;
1836 else
1837 hf = 1;
1838
1839 if (height > out_height)
1840 vf = 2;
1841 else
1842 vf = 1;
1843
7282f1b7
CM		 1844 if (cpu_is_omap24xx()) {
1845 if (vf > 1 && hf > 1)
79ee89cd 1846 return pclk * 4;
7282f1b7 1847 else
79ee89cd 1848 return pclk * 2;
7282f1b7 1849 } else if (cpu_is_omap34xx()) {
79ee89cd 1850 return pclk * vf * hf;
7282f1b7 1851 } else {
79ee89cd
AT		 1852 if (hf > 1)
1853 return DIV_ROUND_UP(pclk, out_width) * width;
1854 else
1855 return pclk;
7282f1b7 1856 }
80c39712
TV		 1857}
1858
79ad75f2 1859static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 1860 enum omap_channel channel,
1861 const struct omap_video_timings *mgr_timings,
1862 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 1863 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 1864 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 1865{
1866 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1867 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1868 const int maxsinglelinewidth =
1869 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
aed74b55 1870 const int max_decim_limit = 16;
8b53d991 1871 unsigned long core_clk = 0;
aed74b55
CM		 1872 int decim_x, decim_y, error, min_factor;
1873 u16 in_width, in_height, in_width_max = 0;
79ad75f2 1874
f95cb5eb
TV		 1875 if (width == out_width && height == out_height)
1876 return 0;
1877
1878 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1879 return -EINVAL;
79ad75f2 1880
aed74b55
CM		 1881 *x_predecim = max_decim_limit;
1882 *y_predecim = max_decim_limit;
1883
1884 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
1885 color_mode == OMAP_DSS_COLOR_CLUT2 ||
1886 color_mode == OMAP_DSS_COLOR_CLUT4 ||
1887 color_mode == OMAP_DSS_COLOR_CLUT8) {
1888 *x_predecim = 1;
1889 *y_predecim = 1;
1890 *five_taps = false;
1891 return 0;
1892 }
1893
1894 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
1895 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
1896
1897 min_factor = min(decim_x, decim_y);
1898
1899 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 1900 return -EINVAL;
1901
aed74b55 1902 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 1903 return -EINVAL;
1904
7282f1b7 1905 if (cpu_is_omap24xx()) {
7282f1b7 1906 *five_taps = false;
aed74b55
CM		 1907
1908 do {
1909 in_height = DIV_ROUND_UP(height, decim_y);
1910 in_width = DIV_ROUND_UP(width, decim_x);
8b53d991 1911 core_clk = calc_core_clk(channel, in_width, in_height,
aed74b55 1912 out_width, out_height);
8b53d991
CM		 1913 error = (in_width > maxsinglelinewidth || !core_clk ||
1914 core_clk > dispc_core_clk_rate());
aed74b55
CM		 1915 if (error) {
1916 if (decim_x == decim_y) {
1917 decim_x = min_factor;
1918 decim_y++;
1919 } else {
1920 swap(decim_x, decim_y);
1921 if (decim_x < decim_y)
1922 decim_x++;
1923 }
1924 }
1925 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
1926 error);
1927
1928 if (in_width > maxsinglelinewidth) {
1929 DSSERR("Cannot scale max input width exceeded");
1930 return -EINVAL;
1931 }
7282f1b7 1932 } else if (cpu_is_omap34xx()) {
aed74b55
CM		 1933
1934 do {
1935 in_height = DIV_ROUND_UP(height, decim_y);
1936 in_width = DIV_ROUND_UP(width, decim_x);
81ab95b7
AT		 1937 core_clk = calc_core_clk_five_taps(channel, mgr_timings,
1938 in_width, in_height, out_width, out_height,
1939 color_mode);
aed74b55 1940
81ab95b7
AT		 1941 error = check_horiz_timing_omap3(channel, mgr_timings,
1942 pos_x, in_width, in_height, out_width,
1943 out_height);
7faa9233 1944
aed74b55
CM		 1945 if (in_width > maxsinglelinewidth)
1946 if (in_height > out_height &&
1947 in_height < out_height * 2)
1948 *five_taps = false;
1949 if (!*five_taps)
8b53d991
CM		 1950 core_clk = calc_core_clk(channel, in_width,
1951 in_height, out_width, out_height);
7faa9233 1952 error = (error || in_width > maxsinglelinewidth * 2 ||
aed74b55 1953 (in_width > maxsinglelinewidth && *five_taps) ||
8b53d991 1954 !core_clk || core_clk > dispc_core_clk_rate());
aed74b55
CM		 1955 if (error) {
1956 if (decim_x == decim_y) {
1957 decim_x = min_factor;
1958 decim_y++;
1959 } else {
1960 swap(decim_x, decim_y);
1961 if (decim_x < decim_y)
1962 decim_x++;
1963 }
1964 }
1965 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
1966 && error);
1967
81ab95b7
AT		 1968 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
1969 height, out_width, out_height)){
7faa9233
CM		 1970 DSSERR("horizontal timing too tight\n");
1971 return -EINVAL;
1972 }
1973
aed74b55 1974 if (in_width > (maxsinglelinewidth * 2)) {
7282f1b7
CM		 1975 DSSERR("Cannot setup scaling");
1976 DSSERR("width exceeds maximum width possible");
1977 return -EINVAL;
1978 }
aed74b55
CM		 1979
1980 if (in_width > maxsinglelinewidth && *five_taps) {
1981 DSSERR("cannot setup scaling with five taps");
1982 return -EINVAL;
7282f1b7 1983 }
7282f1b7 1984 } else {
aed74b55
CM		 1985 int decim_x_min = decim_x;
1986 in_height = DIV_ROUND_UP(height, decim_y);
8b53d991 1987 in_width_max = dispc_core_clk_rate() /
aed74b55
CM		 1988 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
1989 out_width);
1990 decim_x = DIV_ROUND_UP(width, in_width_max);
1991
1992 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
1993 if (decim_x > *x_predecim)
1994 return -EINVAL;
1995
1996 do {
1997 in_width = DIV_ROUND_UP(width, decim_x);
1998 } while (decim_x <= *x_predecim &&
1999 in_width > maxsinglelinewidth && decim_x++);
2000
2001 if (in_width > maxsinglelinewidth) {
7282f1b7
CM		 2002 DSSERR("Cannot scale width exceeds max line width");
2003 return -EINVAL;
2004 }
aed74b55 2005
8b53d991
CM		 2006 core_clk = calc_core_clk(channel, in_width, in_height,
2007 out_width, out_height);
79ad75f2
AT		 2008 }
2009
8b53d991
CM		 2010 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2011 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2012
8b53d991 2013 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2014 DSSERR("failed to set up scaling, "
8b53d991
CM		 2015 "required core clk rate = %lu Hz, "
2016 "current core clk rate = %lu Hz\n",
2017 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2018 return -EINVAL;
2019 }
2020
aed74b55
CM		 2021 *x_predecim = decim_x;
2022 *y_predecim = decim_y;
79ad75f2
AT		 2023 return 0;
2024}
2025
a4273b7c 2026int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
81ab95b7
AT		 2027 bool ilace, bool replication,
2028 const struct omap_video_timings *mgr_timings)
80c39712 2029{
79ad75f2 2030 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 2031 bool five_taps = true;
80c39712 2032 bool fieldmode = 0;
79ad75f2 2033 int r, cconv = 0;
80c39712
TV		 2034 unsigned offset0, offset1;
2035 s32 row_inc;
2036 s32 pix_inc;
a4273b7c 2037 u16 frame_height = oi->height;
80c39712 2038 unsigned int field_offset = 0;
aed74b55
CM		 2039 u16 in_height = oi->height;
2040 u16 in_width = oi->width;
2041 u16 out_width, out_height;
2cc5d1af 2042 enum omap_channel channel;
aed74b55 2043 int x_predecim = 1, y_predecim = 1;
2cc5d1af
TV		 2044
2045 channel = dispc_ovl_get_channel_out(plane);
80c39712 2046
a4273b7c 2047 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 2048 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2049 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 2050 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2051 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 2052 oi->mirror, ilace, channel, replication);
e6d80f95 2053
a4273b7c 2054 if (oi->paddr == 0)
80c39712
TV		 2055 return -EINVAL;
2056
aed74b55
CM		 2057 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2058 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 2059
aed74b55 2060 if (ilace && oi->height == out_height)
80c39712
TV		 2061 fieldmode = 1;
2062
2063 if (ilace) {
2064 if (fieldmode)
aed74b55 2065 in_height /= 2;
a4273b7c 2066 oi->pos_y /= 2;
aed74b55 2067 out_height /= 2;
80c39712
TV		 2068
2069 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2070 "out_height %d\n",
aed74b55 2071 in_height, oi->pos_y, out_height);
80c39712
TV		 2072 }
2073
a4273b7c 2074 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2075 return -EINVAL;
2076
81ab95b7
AT		 2077 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2078 in_height, out_width, out_height, oi->color_mode,
2079 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 2080 if (r)
2081 return r;
80c39712 2082
aed74b55
CM		 2083 in_width = DIV_ROUND_UP(in_width, x_predecim);
2084 in_height = DIV_ROUND_UP(in_height, y_predecim);
2085
79ad75f2
AT		 2086 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2087 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2088 oi->color_mode == OMAP_DSS_COLOR_NV12)
2089 cconv = 1;
80c39712
TV		 2090
2091 if (ilace && !fieldmode) {
2092 /*
2093 * when downscaling the bottom field may have to start several
2094 * source lines below the top field. Unfortunately ACCUI
2095 * registers will only hold the fractional part of the offset
2096 * so the integer part must be added to the base address of the
2097 * bottom field.
2098 */
aed74b55 2099 if (!in_height || in_height == out_height)
80c39712
TV		 2100 field_offset = 0;
2101 else
aed74b55 2102 field_offset = in_height / out_height / 2;
80c39712
TV		 2103 }
2104
2105 /* Fields are independent but interleaved in memory. */
2106 if (fieldmode)
2107 field_offset = 1;
2108
a4273b7c
AT		 2109 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
2110 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2111 oi->screen_width, in_width, frame_height,
a4273b7c 2112 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2113 &offset0, &offset1, &row_inc, &pix_inc,
2114 x_predecim, y_predecim);
80c39712 2115 else
a4273b7c 2116 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2117 oi->screen_width, in_width, frame_height,
a4273b7c 2118 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2119 &offset0, &offset1, &row_inc, &pix_inc,
2120 x_predecim, y_predecim);
80c39712
TV		 2121
2122 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2123 offset0, offset1, row_inc, pix_inc);
2124
a4273b7c 2125 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2126
a4273b7c
AT		 2127 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2128 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2129
a4273b7c
AT		 2130 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2131 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2132 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2133 }
2134
2135
f0e5caab
TV		 2136 dispc_ovl_set_row_inc(plane, row_inc);
2137 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2138
aed74b55
CM		 2139 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2140 in_height, out_width, out_height);
80c39712 2141
a4273b7c 2142 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2143
aed74b55 2144 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2145
79ad75f2 2146 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2147 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2148 out_height, ilace, five_taps, fieldmode,
a4273b7c 2149 oi->color_mode, oi->rotation);
aed74b55 2150 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2151 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2152 }
2153
a4273b7c
AT		 2154 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2155 oi->color_mode);
80c39712 2156
54128701 2157 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2158 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2159 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2160
c3d92529 2161 dispc_ovl_enable_replication(plane, replication);
c3d92529 2162
80c39712
TV		 2163 return 0;
2164}
2165
f0e5caab 2166int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2167{
e6d80f95
TV		 2168 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2169
9b372c2d 2170 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2171
2172 return 0;
80c39712
TV		 2173}
2174
2175static void dispc_disable_isr(void *data, u32 mask)
2176{
2177 struct completion *compl = data;
2178 complete(compl);
2179}
2180
2a205f34 2181static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2182{
b6a44e77 2183 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 2184 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2185 /* flush posted write */
2186 dispc_read_reg(DISPC_CONTROL2);
2187 } else {
2a205f34 2188 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2189 dispc_read_reg(DISPC_CONTROL);
2190 }
80c39712
TV		 2191}
2192
26d9dd0d 2193static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2194{
2195 struct completion frame_done_completion;
2196 bool is_on;
2197 int r;
2a205f34 2198 u32 irq;
80c39712 2199
80c39712
TV		 2200 /* When we disable LCD output, we need to wait until frame is done.
2201 * Otherwise the DSS is still working, and turning off the clocks
2202 * prevents DSS from going to OFF mode */
2a205f34
SS		 2203 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2204 REG_GET(DISPC_CONTROL2, 0, 0) :
2205 REG_GET(DISPC_CONTROL, 0, 0);
2206
2207 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2208 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2209
2210 if (!enable && is_on) {
2211 init_completion(&frame_done_completion);
2212
2213 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2214 &frame_done_completion, irq);
80c39712
TV		 2215
2216 if (r)
2217 DSSERR("failed to register FRAMEDONE isr\n");
2218 }
2219
2a205f34 2220 _enable_lcd_out(channel, enable);
80c39712
TV		 2221
2222 if (!enable && is_on) {
2223 if (!wait_for_completion_timeout(&frame_done_completion,
2224 msecs_to_jiffies(100)))
2225 DSSERR("timeout waiting for FRAME DONE\n");
2226
2227 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2228 &frame_done_completion, irq);
80c39712
TV		 2229
2230 if (r)
2231 DSSERR("failed to unregister FRAMEDONE isr\n");
2232 }
80c39712
TV		 2233}
2234
2235static void _enable_digit_out(bool enable)
2236{
2237 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2238 /* flush posted write */
2239 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2240}
2241
26d9dd0d 2242static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2243{
2244 struct completion frame_done_completion;
e82b090b
TV		 2245 enum dss_hdmi_venc_clk_source_select src;
2246 int r, i;
2247 u32 irq_mask;
2248 int num_irqs;
80c39712 2249
e6d80f95 2250 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2251 return;
80c39712 2252
e82b090b
TV		 2253 src = dss_get_hdmi_venc_clk_source();
2254
80c39712
TV		 2255 if (enable) {
2256 unsigned long flags;
2257 /* When we enable digit output, we'll get an extra digit
2258 * sync lost interrupt, that we need to ignore */
2259 spin_lock_irqsave(&dispc.irq_lock, flags);
2260 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2261 _omap_dispc_set_irqs();
2262 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2263 }
2264
2265 /* When we disable digit output, we need to wait until fields are done.
2266 * Otherwise the DSS is still working, and turning off the clocks
2267 * prevents DSS from going to OFF mode. And when enabling, we need to
2268 * wait for the extra sync losts */
2269 init_completion(&frame_done_completion);
2270
e82b090b
TV		 2271 if (src == DSS_HDMI_M_PCLK && enable == false) {
2272 irq_mask = DISPC_IRQ_FRAMEDONETV;
2273 num_irqs = 1;
2274 } else {
2275 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2276 /* XXX I understand from TRM that we should only wait for the
2277 * current field to complete. But it seems we have to wait for
2278 * both fields */
2279 num_irqs = 2;
2280 }
2281
80c39712 2282 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2283 irq_mask);
80c39712 2284 if (r)
e82b090b 2285 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2286
2287 _enable_digit_out(enable);
2288
e82b090b
TV		 2289 for (i = 0; i < num_irqs; ++i) {
2290 if (!wait_for_completion_timeout(&frame_done_completion,
2291 msecs_to_jiffies(100)))
2292 DSSERR("timeout waiting for digit out to %s\n",
2293 enable ? "start" : "stop");
2294 }
80c39712 2295
e82b090b
TV		 2296 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2297 irq_mask);
80c39712 2298 if (r)
e82b090b 2299 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2300
2301 if (enable) {
2302 unsigned long flags;
2303 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2304 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2305 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2306 _omap_dispc_set_irqs();
2307 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2308 }
80c39712
TV		 2309}
2310
26d9dd0d 2311bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2312{
2313 if (channel == OMAP_DSS_CHANNEL_LCD)
2314 return !!REG_GET(DISPC_CONTROL, 0, 0);
2315 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2316 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2317 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2318 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2319 else
2320 BUG();
2321}
2322
26d9dd0d 2323void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2324{
dac57a05 2325 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2326 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2327 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2328 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2329 else
2330 BUG();
2331}
2332
80c39712
TV		 2333void dispc_lcd_enable_signal_polarity(bool act_high)
2334{
6ced40bf
AT		 2335 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2336 return;
2337
80c39712 2338 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2339}
2340
2341void dispc_lcd_enable_signal(bool enable)
2342{
6ced40bf
AT		 2343 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2344 return;
2345
80c39712 2346 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2347}
2348
2349void dispc_pck_free_enable(bool enable)
2350{
6ced40bf
AT		 2351 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2352 return;
2353
80c39712 2354 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2355}
2356
26d9dd0d 2357void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2358{
2a205f34
SS		 2359 if (channel == OMAP_DSS_CHANNEL_LCD2)
2360 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2361 else
2362 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2363}
2364
2365
26d9dd0d 2366void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2367 enum omap_lcd_display_type type)
80c39712
TV		 2368{
2369 int mode;
2370
2371 switch (type) {
2372 case OMAP_DSS_LCD_DISPLAY_STN:
2373 mode = 0;
2374 break;
2375
2376 case OMAP_DSS_LCD_DISPLAY_TFT:
2377 mode = 1;
2378 break;
2379
2380 default:
2381 BUG();
2382 return;
2383 }
2384
2a205f34
SS		 2385 if (channel == OMAP_DSS_CHANNEL_LCD2)
2386 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2387 else
2388 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2389}
2390
2391void dispc_set_loadmode(enum omap_dss_load_mode mode)
2392{
80c39712 2393 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2394}
2395
2396
c64dca40 2397static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2398{
8613b000 2399 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2400}
2401
c64dca40 2402static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2403 enum omap_dss_trans_key_type type,
2404 u32 trans_key)
2405{
80c39712
TV		 2406 if (ch == OMAP_DSS_CHANNEL_LCD)
2407 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2408 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2409 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2410 else /* OMAP_DSS_CHANNEL_LCD2 */
2411 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2412
8613b000 2413 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2414}
2415
c64dca40 2416static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2417{
80c39712
TV		 2418 if (ch == OMAP_DSS_CHANNEL_LCD)
2419 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2420 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2421 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2422 else /* OMAP_DSS_CHANNEL_LCD2 */
2423 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2424}
11354dd5 2425
c64dca40
TV		 2426static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2427 bool enable)
80c39712 2428{
11354dd5 2429 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2430 return;
2431
80c39712
TV		 2432 if (ch == OMAP_DSS_CHANNEL_LCD)
2433 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2434 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2435 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2436}
11354dd5 2437
c64dca40
TV		 2438void dispc_mgr_setup(enum omap_channel channel,
2439 struct omap_overlay_manager_info *info)
2440{
2441 dispc_mgr_set_default_color(channel, info->default_color);
2442 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2443 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2444 dispc_mgr_enable_alpha_fixed_zorder(channel,
2445 info->partial_alpha_enabled);
2446 if (dss_has_feature(FEAT_CPR)) {
2447 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2448 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2449 }
2450}
80c39712 2451
26d9dd0d 2452void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2453{
2454 int code;
2455
2456 switch (data_lines) {
2457 case 12:
2458 code = 0;
2459 break;
2460 case 16:
2461 code = 1;
2462 break;
2463 case 18:
2464 code = 2;
2465 break;
2466 case 24:
2467 code = 3;
2468 break;
2469 default:
2470 BUG();
2471 return;
2472 }
2473
2a205f34
SS		 2474 if (channel == OMAP_DSS_CHANNEL_LCD2)
2475 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2476 else
2477 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2478}
2479
569969d6 2480void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2481{
2482 u32 l;
569969d6 2483 int gpout0, gpout1;
80c39712
TV		 2484
2485 switch (mode) {
569969d6
AT		 2486 case DSS_IO_PAD_MODE_RESET:
2487 gpout0 = 0;
2488 gpout1 = 0;
80c39712 2489 break;
569969d6
AT		 2490 case DSS_IO_PAD_MODE_RFBI:
2491 gpout0 = 1;
80c39712
TV		 2492 gpout1 = 0;
2493 break;
569969d6
AT		 2494 case DSS_IO_PAD_MODE_BYPASS:
2495 gpout0 = 1;
80c39712
TV		 2496 gpout1 = 1;
2497 break;
80c39712
TV		 2498 default:
2499 BUG();
2500 return;
2501 }
2502
569969d6
AT		 2503 l = dispc_read_reg(DISPC_CONTROL);
2504 l = FLD_MOD(l, gpout0, 15, 15);
2505 l = FLD_MOD(l, gpout1, 16, 16);
2506 dispc_write_reg(DISPC_CONTROL, l);
2507}
2508
2509void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2510{
2511 if (channel == OMAP_DSS_CHANNEL_LCD2)
2512 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2513 else
2514 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2515}
2516
8f366162
AT		 2517static bool _dispc_mgr_size_ok(u16 width, u16 height)
2518{
2519 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2520 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2521}
2522
80c39712
TV		 2523static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2524 int vsw, int vfp, int vbp)
2525{
2526 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2527 if (hsw < 1 || hsw > 64 ||
2528 hfp < 1 || hfp > 256 ||
2529 hbp < 1 || hbp > 256 ||
2530 vsw < 1 || vsw > 64 ||
2531 vfp < 0 || vfp > 255 ||
2532 vbp < 0 || vbp > 255)
2533 return false;
2534 } else {
2535 if (hsw < 1 || hsw > 256 ||
2536 hfp < 1 || hfp > 4096 ||
2537 hbp < 1 || hbp > 4096 ||
2538 vsw < 1 || vsw > 256 ||
2539 vfp < 0 || vfp > 4095 ||
2540 vbp < 0 || vbp > 4095)
2541 return false;
2542 }
2543
2544 return true;
2545}
2546
8f366162 2547bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2548 const struct omap_video_timings *timings)
80c39712 2549{
8f366162
AT		 2550 bool timings_ok;
2551
2552 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2553
2554 if (dispc_mgr_is_lcd(channel))
2555 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2556 timings->hfp, timings->hbp,
2557 timings->vsw, timings->vfp,
2558 timings->vbp);
2559
2560 return timings_ok;
80c39712
TV		 2561}
2562
26d9dd0d 2563static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2564 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2565{
2566 u32 timing_h, timing_v;
2567
2568 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2569 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2570 FLD_VAL(hbp-1, 27, 20);
2571
2572 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2573 FLD_VAL(vbp, 27, 20);
2574 } else {
2575 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2576 FLD_VAL(hbp-1, 31, 20);
2577
2578 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2579 FLD_VAL(vbp, 31, 20);
2580 }
2581
64ba4f74
SS		 2582 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2583 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2584}
2585
2586/* change name to mode? */
c51d921a 2587void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2588 struct omap_video_timings *timings)
80c39712
TV		 2589{
2590 unsigned xtot, ytot;
2591 unsigned long ht, vt;
2592
c51d921a
AT		 2593 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2594 timings->y_res);
80c39712 2595
8f366162
AT		 2596 if (!dispc_mgr_timings_ok(channel, timings))
2597 BUG();
80c39712 2598
8f366162 2599 if (dispc_mgr_is_lcd(channel)) {
c51d921a
AT		 2600 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2601 timings->hbp, timings->vsw, timings->vfp,
2602 timings->vbp);
80c39712 2603
c51d921a
AT		 2604 xtot = timings->x_res + timings->hfp + timings->hsw +
2605 timings->hbp;
2606 ytot = timings->y_res + timings->vfp + timings->vsw +
2607 timings->vbp;
80c39712 2608
c51d921a
AT		 2609 ht = (timings->pixel_clock * 1000) / xtot;
2610 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2611
2612 DSSDBG("pck %u\n", timings->pixel_clock);
2613 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
80c39712
TV		 2614 timings->hsw, timings->hfp, timings->hbp,
2615 timings->vsw, timings->vfp, timings->vbp);
2616
c51d921a 2617 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
c51d921a 2618 }
8f366162
AT		 2619
2620 dispc_mgr_set_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2621}
2622
26d9dd0d 2623static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2624 u16 pck_div)
80c39712
TV		 2625{
2626 BUG_ON(lck_div < 1);
9eaaf207 2627 BUG_ON(pck_div < 1);
80c39712 2628
ce7fa5eb 2629 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2630 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2631}
2632
26d9dd0d 2633static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2634 int *pck_div)
80c39712
TV		 2635{
2636 u32 l;
ce7fa5eb 2637 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2638 *lck_div = FLD_GET(l, 23, 16);
2639 *pck_div = FLD_GET(l, 7, 0);
2640}
2641
2642unsigned long dispc_fclk_rate(void)
2643{
a72b64b9 2644 struct platform_device *dsidev;
80c39712
TV		 2645 unsigned long r = 0;
2646
66534e8e 2647 switch (dss_get_dispc_clk_source()) {
89a35e51 2648 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2649 r = clk_get_rate(dispc.dss_clk);
66534e8e 2650 break;
89a35e51 2651 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2652 dsidev = dsi_get_dsidev_from_id(0);
2653 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2654 break;
5a8b572d
AT		 2655 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2656 dsidev = dsi_get_dsidev_from_id(1);
2657 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2658 break;
66534e8e
TA		 2659 default:
2660 BUG();
2661 }
2662
80c39712
TV		 2663 return r;
2664}
2665
26d9dd0d 2666unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2667{
a72b64b9 2668 struct platform_device *dsidev;
80c39712
TV		 2669 int lcd;
2670 unsigned long r;
2671 u32 l;
2672
ce7fa5eb 2673 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2674
2675 lcd = FLD_GET(l, 23, 16);
2676
ea75159e 2677 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2678 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2679 r = clk_get_rate(dispc.dss_clk);
ea75159e 2680 break;
89a35e51 2681 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2682 dsidev = dsi_get_dsidev_from_id(0);
2683 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2684 break;
5a8b572d
AT		 2685 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2686 dsidev = dsi_get_dsidev_from_id(1);
2687 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2688 break;
ea75159e
TA		 2689 default:
2690 BUG();
2691 }
80c39712
TV		 2692
2693 return r / lcd;
2694}
2695
26d9dd0d 2696unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2697{
80c39712 2698 unsigned long r;
80c39712 2699
c3dc6a7a
AT		 2700 if (dispc_mgr_is_lcd(channel)) {
2701 int pcd;
2702 u32 l;
80c39712 2703
c3dc6a7a 2704 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2705
c3dc6a7a 2706 pcd = FLD_GET(l, 7, 0);
80c39712 2707
c3dc6a7a
AT		 2708 r = dispc_mgr_lclk_rate(channel);
2709
2710 return r / pcd;
2711 } else {
3fa03ba8 2712 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2713
3fa03ba8
AT		 2714 source = dss_get_hdmi_venc_clk_source();
2715
2716 switch (source) {
2717 case DSS_VENC_TV_CLK:
c3dc6a7a 2718 return venc_get_pixel_clock();
3fa03ba8 2719 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2720 return hdmi_get_pixel_clock();
2721 default:
2722 BUG();
2723 }
2724 }
80c39712
TV		 2725}
2726
8b53d991
CM		 2727unsigned long dispc_core_clk_rate(void)
2728{
2729 int lcd;
2730 unsigned long fclk = dispc_fclk_rate();
2731
2732 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2733 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2734 else
2735 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2736
2737 return fclk / lcd;
2738}
2739
80c39712
TV		 2740void dispc_dump_clocks(struct seq_file *s)
2741{
2742 int lcd, pcd;
0cf35df3 2743 u32 l;
89a35e51
AT		 2744 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2745 enum omap_dss_clk_source lcd_clk_src;
80c39712 2746
4fbafaf3
TV		 2747 if (dispc_runtime_get())
2748 return;
80c39712 2749
80c39712
TV		 2750 seq_printf(s, "- DISPC -\n");
2751
067a57e4
AT		 2752 seq_printf(s, "dispc fclk source = %s (%s)\n",
2753 dss_get_generic_clk_source_name(dispc_clk_src),
2754 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2755
2756 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2757
0cf35df3
MR		 2758 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2759 seq_printf(s, "- DISPC-CORE-CLK -\n");
2760 l = dispc_read_reg(DISPC_DIVISOR);
2761 lcd = FLD_GET(l, 23, 16);
2762
2763 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2764 (dispc_fclk_rate()/lcd), lcd);
2765 }
2a205f34
SS		 2766 seq_printf(s, "- LCD1 -\n");
2767
ea75159e
TA		 2768 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2769
2770 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2771 dss_get_generic_clk_source_name(lcd_clk_src),
2772 dss_feat_get_clk_source_name(lcd_clk_src));
2773
26d9dd0d 2774 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2775
ff1b2cde 2776 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2777 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2778 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2779 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2780 if (dss_has_feature(FEAT_MGR_LCD2)) {
2781 seq_printf(s, "- LCD2 -\n");
2782
ea75159e
TA		 2783 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2784
2785 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2786 dss_get_generic_clk_source_name(lcd_clk_src),
2787 dss_feat_get_clk_source_name(lcd_clk_src));
2788
26d9dd0d 2789 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2790
2a205f34 2791 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2792 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2793 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2794 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2795 }
4fbafaf3
TV		 2796
2797 dispc_runtime_put();
80c39712
TV		 2798}
2799
dfc0fd8d
TV		 2800#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2801void dispc_dump_irqs(struct seq_file *s)
2802{
2803 unsigned long flags;
2804 struct dispc_irq_stats stats;
2805
2806 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2807
2808 stats = dispc.irq_stats;
2809 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2810 dispc.irq_stats.last_reset = jiffies;
2811
2812 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2813
2814 seq_printf(s, "period %u ms\n",
2815 jiffies_to_msecs(jiffies - stats.last_reset));
2816
2817 seq_printf(s, "irqs %d\n", stats.irq_count);
2818#define PIS(x) \
2819 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2820
2821 PIS(FRAMEDONE);
2822 PIS(VSYNC);
2823 PIS(EVSYNC_EVEN);
2824 PIS(EVSYNC_ODD);
2825 PIS(ACBIAS_COUNT_STAT);
2826 PIS(PROG_LINE_NUM);
2827 PIS(GFX_FIFO_UNDERFLOW);
2828 PIS(GFX_END_WIN);
2829 PIS(PAL_GAMMA_MASK);
2830 PIS(OCP_ERR);
2831 PIS(VID1_FIFO_UNDERFLOW);
2832 PIS(VID1_END_WIN);
2833 PIS(VID2_FIFO_UNDERFLOW);
2834 PIS(VID2_END_WIN);
b8c095b4
AT		 2835 if (dss_feat_get_num_ovls() > 3) {
2836 PIS(VID3_FIFO_UNDERFLOW);
2837 PIS(VID3_END_WIN);
2838 }
dfc0fd8d
TV		 2839 PIS(SYNC_LOST);
2840 PIS(SYNC_LOST_DIGIT);
2841 PIS(WAKEUP);
2a205f34
SS		 2842 if (dss_has_feature(FEAT_MGR_LCD2)) {
2843 PIS(FRAMEDONE2);
2844 PIS(VSYNC2);
2845 PIS(ACBIAS_COUNT_STAT2);
2846 PIS(SYNC_LOST2);
2847 }
dfc0fd8d
TV		 2848#undef PIS
2849}
dfc0fd8d
TV		 2850#endif
2851
e40402cf 2852static void dispc_dump_regs(struct seq_file *s)
80c39712 2853{
4dd2da15
AT		 2854 int i, j;
2855 const char *mgr_names[] = {
2856 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2857 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2858 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2859 };
2860 const char *ovl_names[] = {
2861 [OMAP_DSS_GFX] = "GFX",
2862 [OMAP_DSS_VIDEO1] = "VID1",
2863 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2864 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2865 };
2866 const char **p_names;
2867
9b372c2d 2868#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2869
4fbafaf3
TV		 2870 if (dispc_runtime_get())
2871 return;
80c39712 2872
5010be80 2873 /* DISPC common registers */
80c39712
TV		 2874 DUMPREG(DISPC_REVISION);
2875 DUMPREG(DISPC_SYSCONFIG);
2876 DUMPREG(DISPC_SYSSTATUS);
2877 DUMPREG(DISPC_IRQSTATUS);
2878 DUMPREG(DISPC_IRQENABLE);
2879 DUMPREG(DISPC_CONTROL);
2880 DUMPREG(DISPC_CONFIG);
2881 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2882 DUMPREG(DISPC_LINE_STATUS);
2883 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2884 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2885 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2886 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2887 if (dss_has_feature(FEAT_MGR_LCD2)) {
2888 DUMPREG(DISPC_CONTROL2);
2889 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2890 }
2891
2892#undef DUMPREG
2893
2894#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2895#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2896 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2897 dispc_read_reg(DISPC_REG(i, r)))
2898
4dd2da15 2899 p_names = mgr_names;
5010be80 2900
4dd2da15
AT		 2901 /* DISPC channel specific registers */
2902 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2903 DUMPREG(i, DISPC_DEFAULT_COLOR);
2904 DUMPREG(i, DISPC_TRANS_COLOR);
2905 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2906
4dd2da15
AT		 2907 if (i == OMAP_DSS_CHANNEL_DIGIT)
2908 continue;
5010be80 2909
4dd2da15
AT		 2910 DUMPREG(i, DISPC_DEFAULT_COLOR);
2911 DUMPREG(i, DISPC_TRANS_COLOR);
2912 DUMPREG(i, DISPC_TIMING_H);
2913 DUMPREG(i, DISPC_TIMING_V);
2914 DUMPREG(i, DISPC_POL_FREQ);
2915 DUMPREG(i, DISPC_DIVISORo);
2916 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2917
4dd2da15
AT		 2918 DUMPREG(i, DISPC_DATA_CYCLE1);
2919 DUMPREG(i, DISPC_DATA_CYCLE2);
2920 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2921
332e9d70 2922 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2923 DUMPREG(i, DISPC_CPR_COEF_R);
2924 DUMPREG(i, DISPC_CPR_COEF_G);
2925 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2926 }
2a205f34 2927 }
80c39712 2928
4dd2da15
AT		 2929 p_names = ovl_names;
2930
2931 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2932 DUMPREG(i, DISPC_OVL_BA0);
2933 DUMPREG(i, DISPC_OVL_BA1);
2934 DUMPREG(i, DISPC_OVL_POSITION);
2935 DUMPREG(i, DISPC_OVL_SIZE);
2936 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2937 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2938 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2939 DUMPREG(i, DISPC_OVL_ROW_INC);
2940 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2941 if (dss_has_feature(FEAT_PRELOAD))
2942 DUMPREG(i, DISPC_OVL_PRELOAD);
2943
2944 if (i == OMAP_DSS_GFX) {
2945 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2946 DUMPREG(i, DISPC_OVL_TABLE_BA);
2947 continue;
2948 }
2949
2950 DUMPREG(i, DISPC_OVL_FIR);
2951 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2952 DUMPREG(i, DISPC_OVL_ACCU0);
2953 DUMPREG(i, DISPC_OVL_ACCU1);
2954 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2955 DUMPREG(i, DISPC_OVL_BA0_UV);
2956 DUMPREG(i, DISPC_OVL_BA1_UV);
2957 DUMPREG(i, DISPC_OVL_FIR2);
2958 DUMPREG(i, DISPC_OVL_ACCU2_0);
2959 DUMPREG(i, DISPC_OVL_ACCU2_1);
2960 }
2961 if (dss_has_feature(FEAT_ATTR2))
2962 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2963 if (dss_has_feature(FEAT_PRELOAD))
2964 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2965 }
5010be80
AT		 2966
2967#undef DISPC_REG
2968#undef DUMPREG
2969
2970#define DISPC_REG(plane, name, i) name(plane, i)
2971#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2972 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2973 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2974 dispc_read_reg(DISPC_REG(plane, name, i)))
2975
4dd2da15 2976 /* Video pipeline coefficient registers */
332e9d70 2977
4dd2da15
AT		 2978 /* start from OMAP_DSS_VIDEO1 */
2979 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2980 for (j = 0; j < 8; j++)
2981 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2982
4dd2da15
AT		 2983 for (j = 0; j < 8; j++)
2984 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2985
4dd2da15
AT		 2986 for (j = 0; j < 5; j++)
2987 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2988
4dd2da15
AT		 2989 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2990 for (j = 0; j < 8; j++)
2991 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2992 }
2993
2994 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2995 for (j = 0; j < 8; j++)
2996 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2997
2998 for (j = 0; j < 8; j++)
2999 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3000
3001 for (j = 0; j < 8; j++)
3002 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3003 }
332e9d70 3004 }
80c39712 3005
4fbafaf3 3006 dispc_runtime_put();
5010be80
AT		 3007
3008#undef DISPC_REG
80c39712
TV		 3009#undef DUMPREG
3010}
3011
26d9dd0d
TV		 3012static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
3013 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
3014 u8 acb)
80c39712
TV		 3015{
3016 u32 l = 0;
3017
3018 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
3019 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
3020
3021 l |= FLD_VAL(onoff, 17, 17);
3022 l |= FLD_VAL(rf, 16, 16);
3023 l |= FLD_VAL(ieo, 15, 15);
3024 l |= FLD_VAL(ipc, 14, 14);
3025 l |= FLD_VAL(ihs, 13, 13);
3026 l |= FLD_VAL(ivs, 12, 12);
3027 l |= FLD_VAL(acbi, 11, 8);
3028 l |= FLD_VAL(acb, 7, 0);
3029
ff1b2cde 3030 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3031}
3032
26d9dd0d 3033void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 3034 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 3035{
26d9dd0d 3036 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 3037 (config & OMAP_DSS_LCD_RF) != 0,
3038 (config & OMAP_DSS_LCD_IEO) != 0,
3039 (config & OMAP_DSS_LCD_IPC) != 0,
3040 (config & OMAP_DSS_LCD_IHS) != 0,
3041 (config & OMAP_DSS_LCD_IVS) != 0,
3042 acbi, acb);
3043}
3044
3045/* with fck as input clock rate, find dispc dividers that produce req_pck */
3046void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3047 struct dispc_clock_info *cinfo)
3048{
9eaaf207 3049 u16 pcd_min, pcd_max;
80c39712
TV		 3050 unsigned long best_pck;
3051 u16 best_ld, cur_ld;
3052 u16 best_pd, cur_pd;
3053
9eaaf207
TV		 3054 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3055 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3056
3057 if (!is_tft)
3058 pcd_min = 3;
3059
80c39712
TV		 3060 best_pck = 0;
3061 best_ld = 0;
3062 best_pd = 0;
3063
3064 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3065 unsigned long lck = fck / cur_ld;
3066
9eaaf207 3067 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3068 unsigned long pck = lck / cur_pd;
3069 long old_delta = abs(best_pck - req_pck);
3070 long new_delta = abs(pck - req_pck);
3071
3072 if (best_pck == 0 || new_delta < old_delta) {
3073 best_pck = pck;
3074 best_ld = cur_ld;
3075 best_pd = cur_pd;
3076
3077 if (pck == req_pck)
3078 goto found;
3079 }
3080
3081 if (pck < req_pck)
3082 break;
3083 }
3084
3085 if (lck / pcd_min < req_pck)
3086 break;
3087 }
3088
3089found:
3090 cinfo->lck_div = best_ld;
3091 cinfo->pck_div = best_pd;
3092 cinfo->lck = fck / cinfo->lck_div;
3093 cinfo->pck = cinfo->lck / cinfo->pck_div;
3094}
3095
3096/* calculate clock rates using dividers in cinfo */
3097int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3098 struct dispc_clock_info *cinfo)
3099{
3100 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3101 return -EINVAL;
9eaaf207 3102 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3103 return -EINVAL;
3104
3105 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3106 cinfo->pck = cinfo->lck / cinfo->pck_div;
3107
3108 return 0;
3109}
3110
26d9dd0d 3111int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3112 struct dispc_clock_info *cinfo)
80c39712
TV		 3113{
3114 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3115 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3116
26d9dd0d 3117 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3118
3119 return 0;
3120}
3121
26d9dd0d 3122int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3123 struct dispc_clock_info *cinfo)
80c39712
TV		 3124{
3125 unsigned long fck;
3126
3127 fck = dispc_fclk_rate();
3128
ce7fa5eb
MR		 3129 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3130 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3131
3132 cinfo->lck = fck / cinfo->lck_div;
3133 cinfo->pck = cinfo->lck / cinfo->pck_div;
3134
3135 return 0;
3136}
3137
3138/* dispc.irq_lock has to be locked by the caller */
3139static void _omap_dispc_set_irqs(void)
3140{
3141 u32 mask;
3142 u32 old_mask;
3143 int i;
3144 struct omap_dispc_isr_data *isr_data;
3145
3146 mask = dispc.irq_error_mask;
3147
3148 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3149 isr_data = &dispc.registered_isr[i];
3150
3151 if (isr_data->isr == NULL)
3152 continue;
3153
3154 mask |= isr_data->mask;
3155 }
3156
80c39712
TV		 3157 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3158 /* clear the irqstatus for newly enabled irqs */
3159 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3160
3161 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3162}
3163
3164int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3165{
3166 int i;
3167 int ret;
3168 unsigned long flags;
3169 struct omap_dispc_isr_data *isr_data;
3170
3171 if (isr == NULL)
3172 return -EINVAL;
3173
3174 spin_lock_irqsave(&dispc.irq_lock, flags);
3175
3176 /* check for duplicate entry */
3177 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3178 isr_data = &dispc.registered_isr[i];
3179 if (isr_data->isr == isr && isr_data->arg == arg &&
3180 isr_data->mask == mask) {
3181 ret = -EINVAL;
3182 goto err;
3183 }
3184 }
3185
3186 isr_data = NULL;
3187 ret = -EBUSY;
3188
3189 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3190 isr_data = &dispc.registered_isr[i];
3191
3192 if (isr_data->isr != NULL)
3193 continue;
3194
3195 isr_data->isr = isr;
3196 isr_data->arg = arg;
3197 isr_data->mask = mask;
3198 ret = 0;
3199
3200 break;
3201 }
3202
b9cb0984
TV		 3203 if (ret)
3204 goto err;
3205
80c39712
TV		 3206 _omap_dispc_set_irqs();
3207
3208 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3209
3210 return 0;
3211err:
3212 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3213
3214 return ret;
3215}
3216EXPORT_SYMBOL(omap_dispc_register_isr);
3217
3218int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3219{
3220 int i;
3221 unsigned long flags;
3222 int ret = -EINVAL;
3223 struct omap_dispc_isr_data *isr_data;
3224
3225 spin_lock_irqsave(&dispc.irq_lock, flags);
3226
3227 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3228 isr_data = &dispc.registered_isr[i];
3229 if (isr_data->isr != isr || isr_data->arg != arg ||
3230 isr_data->mask != mask)
3231 continue;
3232
3233 /* found the correct isr */
3234
3235 isr_data->isr = NULL;
3236 isr_data->arg = NULL;
3237 isr_data->mask = 0;
3238
3239 ret = 0;
3240 break;
3241 }
3242
3243 if (ret == 0)
3244 _omap_dispc_set_irqs();
3245
3246 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3247
3248 return ret;
3249}
3250EXPORT_SYMBOL(omap_dispc_unregister_isr);
3251
3252#ifdef DEBUG
3253static void print_irq_status(u32 status)
3254{
3255 if ((status & dispc.irq_error_mask) == 0)
3256 return;
3257
3258 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3259
3260#define PIS(x) \
3261 if (status & DISPC_IRQ_##x) \
3262 printk(#x " ");
3263 PIS(GFX_FIFO_UNDERFLOW);
3264 PIS(OCP_ERR);
3265 PIS(VID1_FIFO_UNDERFLOW);
3266 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3267 if (dss_feat_get_num_ovls() > 3)
3268 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3269 PIS(SYNC_LOST);
3270 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3271 if (dss_has_feature(FEAT_MGR_LCD2))
3272 PIS(SYNC_LOST2);
80c39712
TV		 3273#undef PIS
3274
3275 printk("\n");
3276}
3277#endif
3278
3279/* Called from dss.c. Note that we don't touch clocks here,
3280 * but we presume they are on because we got an IRQ. However,
3281 * an irq handler may turn the clocks off, so we may not have
3282 * clock later in the function. */
affe360d 3283static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3284{
3285 int i;
affe360d 3286 u32 irqstatus, irqenable;
80c39712
TV		 3287 u32 handledirqs = 0;
3288 u32 unhandled_errors;
3289 struct omap_dispc_isr_data *isr_data;
3290 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3291
3292 spin_lock(&dispc.irq_lock);
3293
3294 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3295 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3296
3297 /* IRQ is not for us */
3298 if (!(irqstatus & irqenable)) {
3299 spin_unlock(&dispc.irq_lock);
3300 return IRQ_NONE;
3301 }
80c39712 3302
dfc0fd8d
TV		 3303#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3304 spin_lock(&dispc.irq_stats_lock);
3305 dispc.irq_stats.irq_count++;
3306 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3307 spin_unlock(&dispc.irq_stats_lock);
3308#endif
3309
80c39712
TV		 3310#ifdef DEBUG
3311 if (dss_debug)
3312 print_irq_status(irqstatus);
3313#endif
3314 /* Ack the interrupt. Do it here before clocks are possibly turned
3315 * off */
3316 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3317 /* flush posted write */
3318 dispc_read_reg(DISPC_IRQSTATUS);
3319
3320 /* make a copy and unlock, so that isrs can unregister
3321 * themselves */
3322 memcpy(registered_isr, dispc.registered_isr,
3323 sizeof(registered_isr));
3324
3325 spin_unlock(&dispc.irq_lock);
3326
3327 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3328 isr_data = &registered_isr[i];
3329
3330 if (!isr_data->isr)
3331 continue;
3332
3333 if (isr_data->mask & irqstatus) {
3334 isr_data->isr(isr_data->arg, irqstatus);
3335 handledirqs |= isr_data->mask;
3336 }
3337 }
3338
3339 spin_lock(&dispc.irq_lock);
3340
3341 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3342
3343 if (unhandled_errors) {
3344 dispc.error_irqs |= unhandled_errors;
3345
3346 dispc.irq_error_mask &= ~unhandled_errors;
3347 _omap_dispc_set_irqs();
3348
3349 schedule_work(&dispc.error_work);
3350 }
3351
3352 spin_unlock(&dispc.irq_lock);
affe360d 3353
3354 return IRQ_HANDLED;
80c39712
TV		 3355}
3356
3357static void dispc_error_worker(struct work_struct *work)
3358{
3359 int i;
3360 u32 errors;
3361 unsigned long flags;
fe3cc9d6
TV		 3362 static const unsigned fifo_underflow_bits[] = {
3363 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3364 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3365 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3366 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3367 };
3368
3369 static const unsigned sync_lost_bits[] = {
3370 DISPC_IRQ_SYNC_LOST,
3371 DISPC_IRQ_SYNC_LOST_DIGIT,
3372 DISPC_IRQ_SYNC_LOST2,
3373 };
80c39712
TV		 3374
3375 spin_lock_irqsave(&dispc.irq_lock, flags);
3376 errors = dispc.error_irqs;
3377 dispc.error_irqs = 0;
3378 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3379
13eae1f9
DZ		 3380 dispc_runtime_get();
3381
fe3cc9d6
TV		 3382 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3383 struct omap_overlay *ovl;
3384 unsigned bit;
80c39712 3385
fe3cc9d6
TV		 3386 ovl = omap_dss_get_overlay(i);
3387 bit = fifo_underflow_bits[i];
80c39712 3388
fe3cc9d6
TV		 3389 if (bit & errors) {
3390 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3391 ovl->name);
f0e5caab 3392 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3393 dispc_mgr_go(ovl->manager->id);
80c39712 3394 mdelay(50);
80c39712
TV		 3395 }
3396 }
3397
fe3cc9d6
TV		 3398 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3399 struct omap_overlay_manager *mgr;
3400 unsigned bit;
80c39712 3401
fe3cc9d6
TV		 3402 mgr = omap_dss_get_overlay_manager(i);
3403 bit = sync_lost_bits[i];
80c39712 3404
fe3cc9d6
TV		 3405 if (bit & errors) {
3406 struct omap_dss_device *dssdev = mgr->device;
3407 bool enable;
80c39712 3408
fe3cc9d6
TV		 3409 DSSERR("SYNC_LOST on channel %s, restarting the output "
3410 "with video overlays disabled\n",
3411 mgr->name);
2a205f34 3412
fe3cc9d6
TV		 3413 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3414 dssdev->driver->disable(dssdev);
2a205f34 3415
2a205f34
SS		 3416 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3417 struct omap_overlay *ovl;
3418 ovl = omap_dss_get_overlay(i);
3419
fe3cc9d6
TV		 3420 if (ovl->id != OMAP_DSS_GFX &&
3421 ovl->manager == mgr)
f0e5caab 3422 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3423 }
3424
26d9dd0d 3425 dispc_mgr_go(mgr->id);
2a205f34 3426 mdelay(50);
fe3cc9d6 3427
2a205f34
SS		 3428 if (enable)
3429 dssdev->driver->enable(dssdev);
3430 }
3431 }
3432
80c39712
TV		 3433 if (errors & DISPC_IRQ_OCP_ERR) {
3434 DSSERR("OCP_ERR\n");
3435 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3436 struct omap_overlay_manager *mgr;
3437 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3438 if (mgr->device && mgr->device->driver)
3439 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3440 }
3441 }
3442
3443 spin_lock_irqsave(&dispc.irq_lock, flags);
3444 dispc.irq_error_mask |= errors;
3445 _omap_dispc_set_irqs();
3446 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3447
3448 dispc_runtime_put();
80c39712
TV		 3449}
3450
3451int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3452{
3453 void dispc_irq_wait_handler(void *data, u32 mask)
3454 {
3455 complete((struct completion *)data);
3456 }
3457
3458 int r;
3459 DECLARE_COMPLETION_ONSTACK(completion);
3460
3461 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3462 irqmask);
3463
3464 if (r)
3465 return r;
3466
3467 timeout = wait_for_completion_timeout(&completion, timeout);
3468
3469 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3470
3471 if (timeout == 0)
3472 return -ETIMEDOUT;
3473
3474 if (timeout == -ERESTARTSYS)
3475 return -ERESTARTSYS;
3476
3477 return 0;
3478}
3479
3480int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3481 unsigned long timeout)
3482{
3483 void dispc_irq_wait_handler(void *data, u32 mask)
3484 {
3485 complete((struct completion *)data);
3486 }
3487
3488 int r;
3489 DECLARE_COMPLETION_ONSTACK(completion);
3490
3491 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3492 irqmask);
3493
3494 if (r)
3495 return r;
3496
3497 timeout = wait_for_completion_interruptible_timeout(&completion,
3498 timeout);
3499
3500 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3501
3502 if (timeout == 0)
3503 return -ETIMEDOUT;
3504
3505 if (timeout == -ERESTARTSYS)
3506 return -ERESTARTSYS;
3507
3508 return 0;
3509}
3510
80c39712
TV		 3511static void _omap_dispc_initialize_irq(void)
3512{
3513 unsigned long flags;
3514
3515 spin_lock_irqsave(&dispc.irq_lock, flags);
3516
3517 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3518
3519 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3520 if (dss_has_feature(FEAT_MGR_LCD2))
3521 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3522 if (dss_feat_get_num_ovls() > 3)
3523 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3524
3525 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3526 * so clear it */
3527 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3528
3529 _omap_dispc_set_irqs();
3530
3531 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3532}
3533
3534void dispc_enable_sidle(void)
3535{
3536 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3537}
3538
3539void dispc_disable_sidle(void)
3540{
3541 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3542}
3543
3544static void _omap_dispc_initial_config(void)
3545{
3546 u32 l;
3547
0cf35df3
MR		 3548 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3549 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3550 l = dispc_read_reg(DISPC_DIVISOR);
3551 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3552 l = FLD_MOD(l, 1, 0, 0);
3553 l = FLD_MOD(l, 1, 23, 16);
3554 dispc_write_reg(DISPC_DIVISOR, l);
3555 }
3556
80c39712 3557 /* FUNCGATED */
6ced40bf
AT		 3558 if (dss_has_feature(FEAT_FUNCGATED))
3559 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3560
80c39712
TV		 3561 _dispc_setup_color_conv_coef();
3562
3563 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3564
3565 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3566
3567 dispc_configure_burst_sizes();
54128701
AT		 3568
3569 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3570}
3571
060b6d9c 3572/* DISPC HW IP initialisation */
6e7e8f06 3573static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3574{
3575 u32 rev;
affe360d 3576 int r = 0;
ea9da36a 3577 struct resource *dispc_mem;
4fbafaf3 3578 struct clk *clk;
ea9da36a 3579
060b6d9c
SG		 3580 dispc.pdev = pdev;
3581
3582 spin_lock_init(&dispc.irq_lock);
3583
3584#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3585 spin_lock_init(&dispc.irq_stats_lock);
3586 dispc.irq_stats.last_reset = jiffies;
3587#endif
3588
3589 INIT_WORK(&dispc.error_work, dispc_error_worker);
3590
ea9da36a
SG		 3591 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3592 if (!dispc_mem) {
3593 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3594 return -EINVAL;
ea9da36a 3595 }
cd3b3449 3596
6e2a14d2
JL		 3597 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3598 resource_size(dispc_mem));
060b6d9c
SG		 3599 if (!dispc.base) {
3600 DSSERR("can't ioremap DISPC\n");
cd3b3449 3601 return -ENOMEM;
affe360d 3602 }
cd3b3449 3603
affe360d 3604 dispc.irq = platform_get_irq(dispc.pdev, 0);
3605 if (dispc.irq < 0) {
3606 DSSERR("platform_get_irq failed\n");
cd3b3449 3607 return -ENODEV;
affe360d 3608 }
3609
6e2a14d2
JL		 3610 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3611 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3612 if (r < 0) {
3613 DSSERR("request_irq failed\n");
cd3b3449
TV		 3614 return r;
3615 }
3616
3617 clk = clk_get(&pdev->dev, "fck");
3618 if (IS_ERR(clk)) {
3619 DSSERR("can't get fck\n");
3620 r = PTR_ERR(clk);
3621 return r;
060b6d9c
SG		 3622 }
3623
cd3b3449
TV		 3624 dispc.dss_clk = clk;
3625
4fbafaf3
TV		 3626 pm_runtime_enable(&pdev->dev);
3627
3628 r = dispc_runtime_get();
3629 if (r)
3630 goto err_runtime_get;
060b6d9c
SG		 3631
3632 _omap_dispc_initial_config();
3633
3634 _omap_dispc_initialize_irq();
3635
060b6d9c 3636 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3637 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3638 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3639
4fbafaf3 3640 dispc_runtime_put();
060b6d9c 3641
e40402cf
TV		 3642 dss_debugfs_create_file("dispc", dispc_dump_regs);
3643
3644#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3645 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3646#endif
060b6d9c 3647 return 0;
4fbafaf3
TV		 3648
3649err_runtime_get:
3650 pm_runtime_disable(&pdev->dev);
4fbafaf3 3651 clk_put(dispc.dss_clk);
affe360d 3652 return r;
060b6d9c
SG		 3653}
3654
6e7e8f06 3655static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3656{
4fbafaf3
TV		 3657 pm_runtime_disable(&pdev->dev);
3658
3659 clk_put(dispc.dss_clk);
3660
060b6d9c
SG		 3661 return 0;
3662}
3663
4fbafaf3
TV		 3664static int dispc_runtime_suspend(struct device *dev)
3665{
3666 dispc_save_context();
4fbafaf3
TV		 3667
3668 return 0;
3669}
3670
3671static int dispc_runtime_resume(struct device *dev)
3672{
49ea86f3 3673 dispc_restore_context();
4fbafaf3
TV		 3674
3675 return 0;
3676}
3677
3678static const struct dev_pm_ops dispc_pm_ops = {
3679 .runtime_suspend = dispc_runtime_suspend,
3680 .runtime_resume = dispc_runtime_resume,
3681};
3682
060b6d9c 3683static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3684 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3685 .driver = {
3686 .name = "omapdss_dispc",
3687 .owner = THIS_MODULE,
4fbafaf3 3688 .pm = &dispc_pm_ops,
060b6d9c
SG		 3689 },
3690};
3691
6e7e8f06 3692int __init dispc_init_platform_driver(void)
060b6d9c 3693{
11436e1d 3694 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3695}
3696
6e7e8f06 3697void __exit dispc_uninit_platform_driver(void)
060b6d9c 3698{
04c742c3 3699 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3700}
Linux kernel - Deliverables
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