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80c39712 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dispc.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DISPC" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/vmalloc.h> | |
a8a35931 | 28 | #include <linux/export.h> |
80c39712 TV |
29 | #include <linux/clk.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/jiffies.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/workqueue.h> | |
ab83b14c | 35 | #include <linux/hardirq.h> |
affe360d | 36 | #include <linux/interrupt.h> |
24e6289c | 37 | #include <linux/platform_device.h> |
4fbafaf3 | 38 | #include <linux/pm_runtime.h> |
80c39712 TV |
39 | |
40 | #include <plat/sram.h> | |
41 | #include <plat/clock.h> | |
42 | ||
a0b38cc4 | 43 | #include <video/omapdss.h> |
80c39712 TV |
44 | |
45 | #include "dss.h" | |
a0acb557 | 46 | #include "dss_features.h" |
9b372c2d | 47 | #include "dispc.h" |
80c39712 TV |
48 | |
49 | /* DISPC */ | |
8613b000 | 50 | #define DISPC_SZ_REGS SZ_4K |
80c39712 | 51 | |
80c39712 TV |
52 | #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ |
53 | DISPC_IRQ_OCP_ERR | \ | |
54 | DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ | |
55 | DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ | |
56 | DISPC_IRQ_SYNC_LOST | \ | |
57 | DISPC_IRQ_SYNC_LOST_DIGIT) | |
58 | ||
59 | #define DISPC_MAX_NR_ISRS 8 | |
60 | ||
61 | struct omap_dispc_isr_data { | |
62 | omap_dispc_isr_t isr; | |
63 | void *arg; | |
64 | u32 mask; | |
65 | }; | |
66 | ||
5ed8cf5b TV |
67 | enum omap_burst_size { |
68 | BURST_SIZE_X2 = 0, | |
69 | BURST_SIZE_X4 = 1, | |
70 | BURST_SIZE_X8 = 2, | |
71 | }; | |
72 | ||
80c39712 TV |
73 | #define REG_GET(idx, start, end) \ |
74 | FLD_GET(dispc_read_reg(idx), start, end) | |
75 | ||
76 | #define REG_FLD_MOD(idx, val, start, end) \ | |
77 | dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) | |
78 | ||
dfc0fd8d TV |
79 | struct dispc_irq_stats { |
80 | unsigned long last_reset; | |
81 | unsigned irq_count; | |
82 | unsigned irqs[32]; | |
83 | }; | |
84 | ||
80c39712 | 85 | static struct { |
060b6d9c | 86 | struct platform_device *pdev; |
80c39712 | 87 | void __iomem *base; |
4fbafaf3 TV |
88 | |
89 | int ctx_loss_cnt; | |
90 | ||
affe360d | 91 | int irq; |
4fbafaf3 | 92 | struct clk *dss_clk; |
80c39712 | 93 | |
e13a138b | 94 | u32 fifo_size[MAX_DSS_OVERLAYS]; |
80c39712 TV |
95 | |
96 | spinlock_t irq_lock; | |
97 | u32 irq_error_mask; | |
98 | struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; | |
99 | u32 error_irqs; | |
100 | struct work_struct error_work; | |
101 | ||
49ea86f3 | 102 | bool ctx_valid; |
80c39712 | 103 | u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; |
dfc0fd8d TV |
104 | |
105 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
106 | spinlock_t irq_stats_lock; | |
107 | struct dispc_irq_stats irq_stats; | |
108 | #endif | |
80c39712 TV |
109 | } dispc; |
110 | ||
0d66cbb5 AJ |
111 | enum omap_color_component { |
112 | /* used for all color formats for OMAP3 and earlier | |
113 | * and for RGB and Y color component on OMAP4 | |
114 | */ | |
115 | DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, | |
116 | /* used for UV component for | |
117 | * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 | |
118 | * color formats on OMAP4 | |
119 | */ | |
120 | DISPC_COLOR_COMPONENT_UV = 1 << 1, | |
121 | }; | |
122 | ||
80c39712 TV |
123 | static void _omap_dispc_set_irqs(void); |
124 | ||
55978cc2 | 125 | static inline void dispc_write_reg(const u16 idx, u32 val) |
80c39712 | 126 | { |
55978cc2 | 127 | __raw_writel(val, dispc.base + idx); |
80c39712 TV |
128 | } |
129 | ||
55978cc2 | 130 | static inline u32 dispc_read_reg(const u16 idx) |
80c39712 | 131 | { |
55978cc2 | 132 | return __raw_readl(dispc.base + idx); |
80c39712 TV |
133 | } |
134 | ||
49ea86f3 TV |
135 | static int dispc_get_ctx_loss_count(void) |
136 | { | |
137 | struct device *dev = &dispc.pdev->dev; | |
138 | struct omap_display_platform_data *pdata = dev->platform_data; | |
139 | struct omap_dss_board_info *board_data = pdata->board_data; | |
140 | int cnt; | |
141 | ||
142 | if (!board_data->get_context_loss_count) | |
143 | return -ENOENT; | |
144 | ||
145 | cnt = board_data->get_context_loss_count(dev); | |
146 | ||
147 | WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt); | |
148 | ||
149 | return cnt; | |
150 | } | |
151 | ||
80c39712 | 152 | #define SR(reg) \ |
55978cc2 | 153 | dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) |
80c39712 | 154 | #define RR(reg) \ |
55978cc2 | 155 | dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) |
80c39712 | 156 | |
4fbafaf3 | 157 | static void dispc_save_context(void) |
80c39712 | 158 | { |
c6104b8e | 159 | int i, j; |
80c39712 | 160 | |
4fbafaf3 TV |
161 | DSSDBG("dispc_save_context\n"); |
162 | ||
80c39712 TV |
163 | SR(IRQENABLE); |
164 | SR(CONTROL); | |
165 | SR(CONFIG); | |
80c39712 | 166 | SR(LINE_NUMBER); |
11354dd5 AT |
167 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
168 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 169 | SR(GLOBAL_ALPHA); |
2a205f34 SS |
170 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
171 | SR(CONTROL2); | |
2a205f34 SS |
172 | SR(CONFIG2); |
173 | } | |
80c39712 | 174 | |
c6104b8e AT |
175 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
176 | SR(DEFAULT_COLOR(i)); | |
177 | SR(TRANS_COLOR(i)); | |
178 | SR(SIZE_MGR(i)); | |
179 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
180 | continue; | |
181 | SR(TIMING_H(i)); | |
182 | SR(TIMING_V(i)); | |
183 | SR(POL_FREQ(i)); | |
184 | SR(DIVISORo(i)); | |
185 | ||
186 | SR(DATA_CYCLE1(i)); | |
187 | SR(DATA_CYCLE2(i)); | |
188 | SR(DATA_CYCLE3(i)); | |
189 | ||
332e9d70 | 190 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
191 | SR(CPR_COEF_R(i)); |
192 | SR(CPR_COEF_G(i)); | |
193 | SR(CPR_COEF_B(i)); | |
332e9d70 | 194 | } |
2a205f34 | 195 | } |
80c39712 | 196 | |
c6104b8e AT |
197 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
198 | SR(OVL_BA0(i)); | |
199 | SR(OVL_BA1(i)); | |
200 | SR(OVL_POSITION(i)); | |
201 | SR(OVL_SIZE(i)); | |
202 | SR(OVL_ATTRIBUTES(i)); | |
203 | SR(OVL_FIFO_THRESHOLD(i)); | |
204 | SR(OVL_ROW_INC(i)); | |
205 | SR(OVL_PIXEL_INC(i)); | |
206 | if (dss_has_feature(FEAT_PRELOAD)) | |
207 | SR(OVL_PRELOAD(i)); | |
208 | if (i == OMAP_DSS_GFX) { | |
209 | SR(OVL_WINDOW_SKIP(i)); | |
210 | SR(OVL_TABLE_BA(i)); | |
211 | continue; | |
212 | } | |
213 | SR(OVL_FIR(i)); | |
214 | SR(OVL_PICTURE_SIZE(i)); | |
215 | SR(OVL_ACCU0(i)); | |
216 | SR(OVL_ACCU1(i)); | |
9b372c2d | 217 | |
c6104b8e AT |
218 | for (j = 0; j < 8; j++) |
219 | SR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 220 | |
c6104b8e AT |
221 | for (j = 0; j < 8; j++) |
222 | SR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 223 | |
c6104b8e AT |
224 | for (j = 0; j < 5; j++) |
225 | SR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 226 | |
c6104b8e AT |
227 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
228 | for (j = 0; j < 8; j++) | |
229 | SR(OVL_FIR_COEF_V(i, j)); | |
230 | } | |
9b372c2d | 231 | |
c6104b8e AT |
232 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
233 | SR(OVL_BA0_UV(i)); | |
234 | SR(OVL_BA1_UV(i)); | |
235 | SR(OVL_FIR2(i)); | |
236 | SR(OVL_ACCU2_0(i)); | |
237 | SR(OVL_ACCU2_1(i)); | |
ab5ca071 | 238 | |
c6104b8e AT |
239 | for (j = 0; j < 8; j++) |
240 | SR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 241 | |
c6104b8e AT |
242 | for (j = 0; j < 8; j++) |
243 | SR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 244 | |
c6104b8e AT |
245 | for (j = 0; j < 8; j++) |
246 | SR(OVL_FIR_COEF_V2(i, j)); | |
247 | } | |
248 | if (dss_has_feature(FEAT_ATTR2)) | |
249 | SR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 250 | } |
0cf35df3 MR |
251 | |
252 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
253 | SR(DIVISOR); | |
49ea86f3 TV |
254 | |
255 | dispc.ctx_loss_cnt = dispc_get_ctx_loss_count(); | |
256 | dispc.ctx_valid = true; | |
257 | ||
258 | DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt); | |
80c39712 TV |
259 | } |
260 | ||
4fbafaf3 | 261 | static void dispc_restore_context(void) |
80c39712 | 262 | { |
c6104b8e | 263 | int i, j, ctx; |
4fbafaf3 TV |
264 | |
265 | DSSDBG("dispc_restore_context\n"); | |
266 | ||
49ea86f3 TV |
267 | if (!dispc.ctx_valid) |
268 | return; | |
269 | ||
270 | ctx = dispc_get_ctx_loss_count(); | |
271 | ||
272 | if (ctx >= 0 && ctx == dispc.ctx_loss_cnt) | |
273 | return; | |
274 | ||
275 | DSSDBG("ctx_loss_count: saved %d, current %d\n", | |
276 | dispc.ctx_loss_cnt, ctx); | |
277 | ||
75c7d59d | 278 | /*RR(IRQENABLE);*/ |
80c39712 TV |
279 | /*RR(CONTROL);*/ |
280 | RR(CONFIG); | |
80c39712 | 281 | RR(LINE_NUMBER); |
11354dd5 AT |
282 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
283 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 284 | RR(GLOBAL_ALPHA); |
c6104b8e | 285 | if (dss_has_feature(FEAT_MGR_LCD2)) |
2a205f34 | 286 | RR(CONFIG2); |
80c39712 | 287 | |
c6104b8e AT |
288 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
289 | RR(DEFAULT_COLOR(i)); | |
290 | RR(TRANS_COLOR(i)); | |
291 | RR(SIZE_MGR(i)); | |
292 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
293 | continue; | |
294 | RR(TIMING_H(i)); | |
295 | RR(TIMING_V(i)); | |
296 | RR(POL_FREQ(i)); | |
297 | RR(DIVISORo(i)); | |
298 | ||
299 | RR(DATA_CYCLE1(i)); | |
300 | RR(DATA_CYCLE2(i)); | |
301 | RR(DATA_CYCLE3(i)); | |
2a205f34 | 302 | |
332e9d70 | 303 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
304 | RR(CPR_COEF_R(i)); |
305 | RR(CPR_COEF_G(i)); | |
306 | RR(CPR_COEF_B(i)); | |
332e9d70 | 307 | } |
2a205f34 | 308 | } |
80c39712 | 309 | |
c6104b8e AT |
310 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
311 | RR(OVL_BA0(i)); | |
312 | RR(OVL_BA1(i)); | |
313 | RR(OVL_POSITION(i)); | |
314 | RR(OVL_SIZE(i)); | |
315 | RR(OVL_ATTRIBUTES(i)); | |
316 | RR(OVL_FIFO_THRESHOLD(i)); | |
317 | RR(OVL_ROW_INC(i)); | |
318 | RR(OVL_PIXEL_INC(i)); | |
319 | if (dss_has_feature(FEAT_PRELOAD)) | |
320 | RR(OVL_PRELOAD(i)); | |
321 | if (i == OMAP_DSS_GFX) { | |
322 | RR(OVL_WINDOW_SKIP(i)); | |
323 | RR(OVL_TABLE_BA(i)); | |
324 | continue; | |
325 | } | |
326 | RR(OVL_FIR(i)); | |
327 | RR(OVL_PICTURE_SIZE(i)); | |
328 | RR(OVL_ACCU0(i)); | |
329 | RR(OVL_ACCU1(i)); | |
9b372c2d | 330 | |
c6104b8e AT |
331 | for (j = 0; j < 8; j++) |
332 | RR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 333 | |
c6104b8e AT |
334 | for (j = 0; j < 8; j++) |
335 | RR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 336 | |
c6104b8e AT |
337 | for (j = 0; j < 5; j++) |
338 | RR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 339 | |
c6104b8e AT |
340 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
341 | for (j = 0; j < 8; j++) | |
342 | RR(OVL_FIR_COEF_V(i, j)); | |
343 | } | |
9b372c2d | 344 | |
c6104b8e AT |
345 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
346 | RR(OVL_BA0_UV(i)); | |
347 | RR(OVL_BA1_UV(i)); | |
348 | RR(OVL_FIR2(i)); | |
349 | RR(OVL_ACCU2_0(i)); | |
350 | RR(OVL_ACCU2_1(i)); | |
ab5ca071 | 351 | |
c6104b8e AT |
352 | for (j = 0; j < 8; j++) |
353 | RR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 354 | |
c6104b8e AT |
355 | for (j = 0; j < 8; j++) |
356 | RR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 357 | |
c6104b8e AT |
358 | for (j = 0; j < 8; j++) |
359 | RR(OVL_FIR_COEF_V2(i, j)); | |
360 | } | |
361 | if (dss_has_feature(FEAT_ATTR2)) | |
362 | RR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 363 | } |
80c39712 | 364 | |
0cf35df3 MR |
365 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) |
366 | RR(DIVISOR); | |
367 | ||
80c39712 TV |
368 | /* enable last, because LCD & DIGIT enable are here */ |
369 | RR(CONTROL); | |
2a205f34 SS |
370 | if (dss_has_feature(FEAT_MGR_LCD2)) |
371 | RR(CONTROL2); | |
75c7d59d VS |
372 | /* clear spurious SYNC_LOST_DIGIT interrupts */ |
373 | dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); | |
374 | ||
375 | /* | |
376 | * enable last so IRQs won't trigger before | |
377 | * the context is fully restored | |
378 | */ | |
379 | RR(IRQENABLE); | |
49ea86f3 TV |
380 | |
381 | DSSDBG("context restored\n"); | |
80c39712 TV |
382 | } |
383 | ||
384 | #undef SR | |
385 | #undef RR | |
386 | ||
4fbafaf3 TV |
387 | int dispc_runtime_get(void) |
388 | { | |
389 | int r; | |
390 | ||
391 | DSSDBG("dispc_runtime_get\n"); | |
392 | ||
393 | r = pm_runtime_get_sync(&dispc.pdev->dev); | |
394 | WARN_ON(r < 0); | |
395 | return r < 0 ? r : 0; | |
396 | } | |
397 | ||
398 | void dispc_runtime_put(void) | |
399 | { | |
400 | int r; | |
401 | ||
402 | DSSDBG("dispc_runtime_put\n"); | |
403 | ||
404 | r = pm_runtime_put(&dispc.pdev->dev); | |
405 | WARN_ON(r < 0); | |
80c39712 TV |
406 | } |
407 | ||
dac57a05 AT |
408 | static inline bool dispc_mgr_is_lcd(enum omap_channel channel) |
409 | { | |
410 | if (channel == OMAP_DSS_CHANNEL_LCD || | |
411 | channel == OMAP_DSS_CHANNEL_LCD2) | |
412 | return true; | |
413 | else | |
414 | return false; | |
415 | } | |
4fbafaf3 | 416 | |
c3dc6a7a AT |
417 | static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel) |
418 | { | |
419 | struct omap_overlay_manager *mgr = | |
420 | omap_dss_get_overlay_manager(channel); | |
421 | ||
422 | return mgr ? mgr->device : NULL; | |
423 | } | |
424 | ||
3dcec4d6 TV |
425 | u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) |
426 | { | |
427 | switch (channel) { | |
428 | case OMAP_DSS_CHANNEL_LCD: | |
429 | return DISPC_IRQ_VSYNC; | |
430 | case OMAP_DSS_CHANNEL_LCD2: | |
431 | return DISPC_IRQ_VSYNC2; | |
432 | case OMAP_DSS_CHANNEL_DIGIT: | |
433 | return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN; | |
434 | default: | |
435 | BUG(); | |
436 | } | |
437 | } | |
438 | ||
7d1365c9 TV |
439 | u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) |
440 | { | |
441 | switch (channel) { | |
442 | case OMAP_DSS_CHANNEL_LCD: | |
443 | return DISPC_IRQ_FRAMEDONE; | |
444 | case OMAP_DSS_CHANNEL_LCD2: | |
445 | return DISPC_IRQ_FRAMEDONE2; | |
446 | case OMAP_DSS_CHANNEL_DIGIT: | |
447 | return 0; | |
448 | default: | |
449 | BUG(); | |
450 | } | |
451 | } | |
452 | ||
26d9dd0d | 453 | bool dispc_mgr_go_busy(enum omap_channel channel) |
80c39712 TV |
454 | { |
455 | int bit; | |
456 | ||
dac57a05 | 457 | if (dispc_mgr_is_lcd(channel)) |
80c39712 TV |
458 | bit = 5; /* GOLCD */ |
459 | else | |
460 | bit = 6; /* GODIGIT */ | |
461 | ||
2a205f34 SS |
462 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
463 | return REG_GET(DISPC_CONTROL2, bit, bit) == 1; | |
464 | else | |
465 | return REG_GET(DISPC_CONTROL, bit, bit) == 1; | |
80c39712 TV |
466 | } |
467 | ||
26d9dd0d | 468 | void dispc_mgr_go(enum omap_channel channel) |
80c39712 TV |
469 | { |
470 | int bit; | |
2a205f34 | 471 | bool enable_bit, go_bit; |
80c39712 | 472 | |
dac57a05 | 473 | if (dispc_mgr_is_lcd(channel)) |
80c39712 TV |
474 | bit = 0; /* LCDENABLE */ |
475 | else | |
476 | bit = 1; /* DIGITALENABLE */ | |
477 | ||
478 | /* if the channel is not enabled, we don't need GO */ | |
2a205f34 SS |
479 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
480 | enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1; | |
481 | else | |
482 | enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; | |
483 | ||
484 | if (!enable_bit) | |
e6d80f95 | 485 | return; |
80c39712 | 486 | |
dac57a05 | 487 | if (dispc_mgr_is_lcd(channel)) |
80c39712 TV |
488 | bit = 5; /* GOLCD */ |
489 | else | |
490 | bit = 6; /* GODIGIT */ | |
491 | ||
2a205f34 SS |
492 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
493 | go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1; | |
494 | else | |
495 | go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1; | |
496 | ||
497 | if (go_bit) { | |
80c39712 | 498 | DSSERR("GO bit not down for channel %d\n", channel); |
e6d80f95 | 499 | return; |
80c39712 TV |
500 | } |
501 | ||
2a205f34 SS |
502 | DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : |
503 | (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT")); | |
80c39712 | 504 | |
2a205f34 SS |
505 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
506 | REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit); | |
507 | else | |
508 | REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit); | |
80c39712 TV |
509 | } |
510 | ||
f0e5caab | 511 | static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 512 | { |
9b372c2d | 513 | dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); |
80c39712 TV |
514 | } |
515 | ||
f0e5caab | 516 | static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 517 | { |
9b372c2d | 518 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); |
80c39712 TV |
519 | } |
520 | ||
f0e5caab | 521 | static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 522 | { |
9b372c2d | 523 | dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); |
80c39712 TV |
524 | } |
525 | ||
f0e5caab | 526 | static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
527 | { |
528 | BUG_ON(plane == OMAP_DSS_GFX); | |
529 | ||
530 | dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); | |
531 | } | |
532 | ||
f0e5caab TV |
533 | static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, |
534 | u32 value) | |
ab5ca071 AJ |
535 | { |
536 | BUG_ON(plane == OMAP_DSS_GFX); | |
537 | ||
538 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); | |
539 | } | |
540 | ||
f0e5caab | 541 | static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
542 | { |
543 | BUG_ON(plane == OMAP_DSS_GFX); | |
544 | ||
545 | dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); | |
546 | } | |
547 | ||
debd9074 CM |
548 | static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, |
549 | int fir_vinc, int five_taps, | |
550 | enum omap_color_component color_comp) | |
80c39712 | 551 | { |
debd9074 | 552 | const struct dispc_coef *h_coef, *v_coef; |
80c39712 TV |
553 | int i; |
554 | ||
debd9074 CM |
555 | h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); |
556 | v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); | |
80c39712 TV |
557 | |
558 | for (i = 0; i < 8; i++) { | |
559 | u32 h, hv; | |
560 | ||
debd9074 CM |
561 | h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) |
562 | | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) | |
563 | | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) | |
564 | | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); | |
565 | hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) | |
566 | | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) | |
567 | | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) | |
568 | | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); | |
80c39712 | 569 | |
0d66cbb5 | 570 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
f0e5caab TV |
571 | dispc_ovl_write_firh_reg(plane, i, h); |
572 | dispc_ovl_write_firhv_reg(plane, i, hv); | |
0d66cbb5 | 573 | } else { |
f0e5caab TV |
574 | dispc_ovl_write_firh2_reg(plane, i, h); |
575 | dispc_ovl_write_firhv2_reg(plane, i, hv); | |
0d66cbb5 AJ |
576 | } |
577 | ||
80c39712 TV |
578 | } |
579 | ||
66be8f6c GI |
580 | if (five_taps) { |
581 | for (i = 0; i < 8; i++) { | |
582 | u32 v; | |
debd9074 CM |
583 | v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) |
584 | | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); | |
0d66cbb5 | 585 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) |
f0e5caab | 586 | dispc_ovl_write_firv_reg(plane, i, v); |
0d66cbb5 | 587 | else |
f0e5caab | 588 | dispc_ovl_write_firv2_reg(plane, i, v); |
66be8f6c | 589 | } |
80c39712 TV |
590 | } |
591 | } | |
592 | ||
593 | static void _dispc_setup_color_conv_coef(void) | |
594 | { | |
ac01c29e | 595 | int i; |
80c39712 TV |
596 | const struct color_conv_coef { |
597 | int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; | |
598 | int full_range; | |
599 | } ctbl_bt601_5 = { | |
600 | 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, | |
601 | }; | |
602 | ||
603 | const struct color_conv_coef *ct; | |
604 | ||
605 | #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) | |
606 | ||
607 | ct = &ctbl_bt601_5; | |
608 | ||
ac01c29e AT |
609 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { |
610 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0), | |
611 | CVAL(ct->rcr, ct->ry)); | |
612 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1), | |
613 | CVAL(ct->gy, ct->rcb)); | |
614 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2), | |
615 | CVAL(ct->gcb, ct->gcr)); | |
616 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3), | |
617 | CVAL(ct->bcr, ct->by)); | |
618 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4), | |
619 | CVAL(0, ct->bcb)); | |
620 | ||
621 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range, | |
622 | 11, 11); | |
623 | } | |
80c39712 TV |
624 | |
625 | #undef CVAL | |
80c39712 TV |
626 | } |
627 | ||
628 | ||
f0e5caab | 629 | static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) |
80c39712 | 630 | { |
9b372c2d | 631 | dispc_write_reg(DISPC_OVL_BA0(plane), paddr); |
80c39712 TV |
632 | } |
633 | ||
f0e5caab | 634 | static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) |
80c39712 | 635 | { |
9b372c2d | 636 | dispc_write_reg(DISPC_OVL_BA1(plane), paddr); |
80c39712 TV |
637 | } |
638 | ||
f0e5caab | 639 | static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
640 | { |
641 | dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); | |
642 | } | |
643 | ||
f0e5caab | 644 | static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
645 | { |
646 | dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); | |
647 | } | |
648 | ||
f0e5caab | 649 | static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y) |
80c39712 | 650 | { |
80c39712 | 651 | u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); |
9b372c2d AT |
652 | |
653 | dispc_write_reg(DISPC_OVL_POSITION(plane), val); | |
80c39712 TV |
654 | } |
655 | ||
f0e5caab | 656 | static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height) |
80c39712 | 657 | { |
80c39712 | 658 | u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
9b372c2d AT |
659 | |
660 | if (plane == OMAP_DSS_GFX) | |
661 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); | |
662 | else | |
663 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); | |
80c39712 TV |
664 | } |
665 | ||
f0e5caab | 666 | static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height) |
80c39712 TV |
667 | { |
668 | u32 val; | |
80c39712 TV |
669 | |
670 | BUG_ON(plane == OMAP_DSS_GFX); | |
671 | ||
672 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); | |
9b372c2d AT |
673 | |
674 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); | |
80c39712 TV |
675 | } |
676 | ||
54128701 AT |
677 | static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder) |
678 | { | |
679 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); | |
680 | ||
681 | if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) | |
682 | return; | |
683 | ||
684 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); | |
685 | } | |
686 | ||
687 | static void dispc_ovl_enable_zorder_planes(void) | |
688 | { | |
689 | int i; | |
690 | ||
691 | if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
692 | return; | |
693 | ||
694 | for (i = 0; i < dss_feat_get_num_ovls(); i++) | |
695 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); | |
696 | } | |
697 | ||
f0e5caab | 698 | static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable) |
fd28a390 | 699 | { |
f6dc8150 | 700 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); |
fd28a390 | 701 | |
f6dc8150 | 702 | if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) |
fd28a390 R |
703 | return; |
704 | ||
9b372c2d | 705 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); |
fd28a390 R |
706 | } |
707 | ||
f0e5caab | 708 | static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha) |
80c39712 | 709 | { |
b8c095b4 | 710 | static const unsigned shifts[] = { 0, 8, 16, 24, }; |
fe3cc9d6 | 711 | int shift; |
f6dc8150 | 712 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); |
fe3cc9d6 | 713 | |
f6dc8150 | 714 | if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) |
fd28a390 | 715 | return; |
a0acb557 | 716 | |
fe3cc9d6 TV |
717 | shift = shifts[plane]; |
718 | REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); | |
80c39712 TV |
719 | } |
720 | ||
f0e5caab | 721 | static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) |
80c39712 | 722 | { |
9b372c2d | 723 | dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); |
80c39712 TV |
724 | } |
725 | ||
f0e5caab | 726 | static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) |
80c39712 | 727 | { |
9b372c2d | 728 | dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); |
80c39712 TV |
729 | } |
730 | ||
f0e5caab | 731 | static void dispc_ovl_set_color_mode(enum omap_plane plane, |
80c39712 TV |
732 | enum omap_color_mode color_mode) |
733 | { | |
734 | u32 m = 0; | |
f20e4220 AJ |
735 | if (plane != OMAP_DSS_GFX) { |
736 | switch (color_mode) { | |
737 | case OMAP_DSS_COLOR_NV12: | |
738 | m = 0x0; break; | |
739 | case OMAP_DSS_COLOR_RGB12U: | |
740 | m = 0x1; break; | |
741 | case OMAP_DSS_COLOR_RGBA16: | |
742 | m = 0x2; break; | |
743 | case OMAP_DSS_COLOR_RGBX16: | |
744 | m = 0x4; break; | |
745 | case OMAP_DSS_COLOR_ARGB16: | |
746 | m = 0x5; break; | |
747 | case OMAP_DSS_COLOR_RGB16: | |
748 | m = 0x6; break; | |
749 | case OMAP_DSS_COLOR_ARGB16_1555: | |
750 | m = 0x7; break; | |
751 | case OMAP_DSS_COLOR_RGB24U: | |
752 | m = 0x8; break; | |
753 | case OMAP_DSS_COLOR_RGB24P: | |
754 | m = 0x9; break; | |
755 | case OMAP_DSS_COLOR_YUV2: | |
756 | m = 0xa; break; | |
757 | case OMAP_DSS_COLOR_UYVY: | |
758 | m = 0xb; break; | |
759 | case OMAP_DSS_COLOR_ARGB32: | |
760 | m = 0xc; break; | |
761 | case OMAP_DSS_COLOR_RGBA32: | |
762 | m = 0xd; break; | |
763 | case OMAP_DSS_COLOR_RGBX32: | |
764 | m = 0xe; break; | |
765 | case OMAP_DSS_COLOR_XRGB16_1555: | |
766 | m = 0xf; break; | |
767 | default: | |
768 | BUG(); break; | |
769 | } | |
770 | } else { | |
771 | switch (color_mode) { | |
772 | case OMAP_DSS_COLOR_CLUT1: | |
773 | m = 0x0; break; | |
774 | case OMAP_DSS_COLOR_CLUT2: | |
775 | m = 0x1; break; | |
776 | case OMAP_DSS_COLOR_CLUT4: | |
777 | m = 0x2; break; | |
778 | case OMAP_DSS_COLOR_CLUT8: | |
779 | m = 0x3; break; | |
780 | case OMAP_DSS_COLOR_RGB12U: | |
781 | m = 0x4; break; | |
782 | case OMAP_DSS_COLOR_ARGB16: | |
783 | m = 0x5; break; | |
784 | case OMAP_DSS_COLOR_RGB16: | |
785 | m = 0x6; break; | |
786 | case OMAP_DSS_COLOR_ARGB16_1555: | |
787 | m = 0x7; break; | |
788 | case OMAP_DSS_COLOR_RGB24U: | |
789 | m = 0x8; break; | |
790 | case OMAP_DSS_COLOR_RGB24P: | |
791 | m = 0x9; break; | |
792 | case OMAP_DSS_COLOR_YUV2: | |
793 | m = 0xa; break; | |
794 | case OMAP_DSS_COLOR_UYVY: | |
795 | m = 0xb; break; | |
796 | case OMAP_DSS_COLOR_ARGB32: | |
797 | m = 0xc; break; | |
798 | case OMAP_DSS_COLOR_RGBA32: | |
799 | m = 0xd; break; | |
800 | case OMAP_DSS_COLOR_RGBX32: | |
801 | m = 0xe; break; | |
802 | case OMAP_DSS_COLOR_XRGB16_1555: | |
803 | m = 0xf; break; | |
804 | default: | |
805 | BUG(); break; | |
806 | } | |
80c39712 TV |
807 | } |
808 | ||
9b372c2d | 809 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); |
80c39712 TV |
810 | } |
811 | ||
f427984e | 812 | void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) |
80c39712 TV |
813 | { |
814 | int shift; | |
815 | u32 val; | |
2a205f34 | 816 | int chan = 0, chan2 = 0; |
80c39712 TV |
817 | |
818 | switch (plane) { | |
819 | case OMAP_DSS_GFX: | |
820 | shift = 8; | |
821 | break; | |
822 | case OMAP_DSS_VIDEO1: | |
823 | case OMAP_DSS_VIDEO2: | |
b8c095b4 | 824 | case OMAP_DSS_VIDEO3: |
80c39712 TV |
825 | shift = 16; |
826 | break; | |
827 | default: | |
828 | BUG(); | |
829 | return; | |
830 | } | |
831 | ||
9b372c2d | 832 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
2a205f34 SS |
833 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
834 | switch (channel) { | |
835 | case OMAP_DSS_CHANNEL_LCD: | |
836 | chan = 0; | |
837 | chan2 = 0; | |
838 | break; | |
839 | case OMAP_DSS_CHANNEL_DIGIT: | |
840 | chan = 1; | |
841 | chan2 = 0; | |
842 | break; | |
843 | case OMAP_DSS_CHANNEL_LCD2: | |
844 | chan = 0; | |
845 | chan2 = 1; | |
846 | break; | |
847 | default: | |
848 | BUG(); | |
849 | } | |
850 | ||
851 | val = FLD_MOD(val, chan, shift, shift); | |
852 | val = FLD_MOD(val, chan2, 31, 30); | |
853 | } else { | |
854 | val = FLD_MOD(val, channel, shift, shift); | |
855 | } | |
9b372c2d | 856 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 TV |
857 | } |
858 | ||
2cc5d1af TV |
859 | static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) |
860 | { | |
861 | int shift; | |
862 | u32 val; | |
863 | enum omap_channel channel; | |
864 | ||
865 | switch (plane) { | |
866 | case OMAP_DSS_GFX: | |
867 | shift = 8; | |
868 | break; | |
869 | case OMAP_DSS_VIDEO1: | |
870 | case OMAP_DSS_VIDEO2: | |
871 | case OMAP_DSS_VIDEO3: | |
872 | shift = 16; | |
873 | break; | |
874 | default: | |
875 | BUG(); | |
876 | } | |
877 | ||
878 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); | |
879 | ||
880 | if (dss_has_feature(FEAT_MGR_LCD2)) { | |
881 | if (FLD_GET(val, 31, 30) == 0) | |
882 | channel = FLD_GET(val, shift, shift); | |
883 | else | |
884 | channel = OMAP_DSS_CHANNEL_LCD2; | |
885 | } else { | |
886 | channel = FLD_GET(val, shift, shift); | |
887 | } | |
888 | ||
889 | return channel; | |
890 | } | |
891 | ||
f0e5caab | 892 | static void dispc_ovl_set_burst_size(enum omap_plane plane, |
80c39712 TV |
893 | enum omap_burst_size burst_size) |
894 | { | |
b8c095b4 | 895 | static const unsigned shifts[] = { 6, 14, 14, 14, }; |
80c39712 | 896 | int shift; |
80c39712 | 897 | |
fe3cc9d6 | 898 | shift = shifts[plane]; |
5ed8cf5b | 899 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); |
80c39712 TV |
900 | } |
901 | ||
5ed8cf5b TV |
902 | static void dispc_configure_burst_sizes(void) |
903 | { | |
904 | int i; | |
905 | const int burst_size = BURST_SIZE_X8; | |
906 | ||
907 | /* Configure burst size always to maximum size */ | |
908 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) | |
f0e5caab | 909 | dispc_ovl_set_burst_size(i, burst_size); |
5ed8cf5b TV |
910 | } |
911 | ||
f0e5caab | 912 | u32 dispc_ovl_get_burst_size(enum omap_plane plane) |
5ed8cf5b TV |
913 | { |
914 | unsigned unit = dss_feat_get_burst_size_unit(); | |
915 | /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ | |
916 | return unit * 8; | |
917 | } | |
918 | ||
d3862610 M |
919 | void dispc_enable_gamma_table(bool enable) |
920 | { | |
921 | /* | |
922 | * This is partially implemented to support only disabling of | |
923 | * the gamma table. | |
924 | */ | |
925 | if (enable) { | |
926 | DSSWARN("Gamma table enabling for TV not yet supported"); | |
927 | return; | |
928 | } | |
929 | ||
930 | REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); | |
931 | } | |
932 | ||
c64dca40 | 933 | static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) |
3c07cae2 TV |
934 | { |
935 | u16 reg; | |
936 | ||
937 | if (channel == OMAP_DSS_CHANNEL_LCD) | |
938 | reg = DISPC_CONFIG; | |
939 | else if (channel == OMAP_DSS_CHANNEL_LCD2) | |
940 | reg = DISPC_CONFIG2; | |
941 | else | |
942 | return; | |
943 | ||
944 | REG_FLD_MOD(reg, enable, 15, 15); | |
945 | } | |
946 | ||
c64dca40 | 947 | static void dispc_mgr_set_cpr_coef(enum omap_channel channel, |
3c07cae2 TV |
948 | struct omap_dss_cpr_coefs *coefs) |
949 | { | |
950 | u32 coef_r, coef_g, coef_b; | |
951 | ||
dac57a05 | 952 | if (!dispc_mgr_is_lcd(channel)) |
3c07cae2 TV |
953 | return; |
954 | ||
955 | coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | | |
956 | FLD_VAL(coefs->rb, 9, 0); | |
957 | coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | | |
958 | FLD_VAL(coefs->gb, 9, 0); | |
959 | coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | | |
960 | FLD_VAL(coefs->bb, 9, 0); | |
961 | ||
962 | dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); | |
963 | dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); | |
964 | dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); | |
965 | } | |
966 | ||
f0e5caab | 967 | static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) |
80c39712 TV |
968 | { |
969 | u32 val; | |
970 | ||
971 | BUG_ON(plane == OMAP_DSS_GFX); | |
972 | ||
9b372c2d | 973 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 974 | val = FLD_MOD(val, enable, 9, 9); |
9b372c2d | 975 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 TV |
976 | } |
977 | ||
c3d92529 | 978 | static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable) |
80c39712 | 979 | { |
b8c095b4 | 980 | static const unsigned shifts[] = { 5, 10, 10, 10 }; |
fe3cc9d6 | 981 | int shift; |
80c39712 | 982 | |
fe3cc9d6 TV |
983 | shift = shifts[plane]; |
984 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); | |
80c39712 TV |
985 | } |
986 | ||
26d9dd0d | 987 | void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height) |
80c39712 TV |
988 | { |
989 | u32 val; | |
990 | BUG_ON((width > (1 << 11)) || (height > (1 << 11))); | |
991 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); | |
702d1448 | 992 | dispc_write_reg(DISPC_SIZE_MGR(channel), val); |
80c39712 TV |
993 | } |
994 | ||
995 | void dispc_set_digit_size(u16 width, u16 height) | |
996 | { | |
997 | u32 val; | |
998 | BUG_ON((width > (1 << 11)) || (height > (1 << 11))); | |
999 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); | |
702d1448 | 1000 | dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val); |
80c39712 TV |
1001 | } |
1002 | ||
1003 | static void dispc_read_plane_fifo_sizes(void) | |
1004 | { | |
80c39712 TV |
1005 | u32 size; |
1006 | int plane; | |
a0acb557 | 1007 | u8 start, end; |
5ed8cf5b TV |
1008 | u32 unit; |
1009 | ||
1010 | unit = dss_feat_get_buffer_size_unit(); | |
80c39712 | 1011 | |
a0acb557 | 1012 | dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); |
80c39712 | 1013 | |
e13a138b | 1014 | for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) { |
5ed8cf5b TV |
1015 | size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end); |
1016 | size *= unit; | |
80c39712 TV |
1017 | dispc.fifo_size[plane] = size; |
1018 | } | |
80c39712 TV |
1019 | } |
1020 | ||
f0e5caab | 1021 | u32 dispc_ovl_get_fifo_size(enum omap_plane plane) |
80c39712 TV |
1022 | { |
1023 | return dispc.fifo_size[plane]; | |
1024 | } | |
1025 | ||
6f04e1bf | 1026 | void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) |
80c39712 | 1027 | { |
a0acb557 | 1028 | u8 hi_start, hi_end, lo_start, lo_end; |
5ed8cf5b TV |
1029 | u32 unit; |
1030 | ||
1031 | unit = dss_feat_get_buffer_size_unit(); | |
1032 | ||
1033 | WARN_ON(low % unit != 0); | |
1034 | WARN_ON(high % unit != 0); | |
1035 | ||
1036 | low /= unit; | |
1037 | high /= unit; | |
a0acb557 | 1038 | |
9b372c2d AT |
1039 | dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); |
1040 | dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); | |
1041 | ||
3cb5d966 | 1042 | DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", |
80c39712 | 1043 | plane, |
9b372c2d | 1044 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 | 1045 | lo_start, lo_end) * unit, |
9b372c2d | 1046 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 TV |
1047 | hi_start, hi_end) * unit, |
1048 | low * unit, high * unit); | |
80c39712 | 1049 | |
9b372c2d | 1050 | dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), |
a0acb557 AT |
1051 | FLD_VAL(high, hi_start, hi_end) | |
1052 | FLD_VAL(low, lo_start, lo_end)); | |
80c39712 TV |
1053 | } |
1054 | ||
1055 | void dispc_enable_fifomerge(bool enable) | |
1056 | { | |
e6b0f884 TV |
1057 | if (!dss_has_feature(FEAT_FIFO_MERGE)) { |
1058 | WARN_ON(enable); | |
1059 | return; | |
1060 | } | |
1061 | ||
80c39712 TV |
1062 | DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); |
1063 | REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); | |
80c39712 TV |
1064 | } |
1065 | ||
f0e5caab | 1066 | static void dispc_ovl_set_fir(enum omap_plane plane, |
0d66cbb5 AJ |
1067 | int hinc, int vinc, |
1068 | enum omap_color_component color_comp) | |
80c39712 TV |
1069 | { |
1070 | u32 val; | |
80c39712 | 1071 | |
0d66cbb5 AJ |
1072 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
1073 | u8 hinc_start, hinc_end, vinc_start, vinc_end; | |
a0acb557 | 1074 | |
0d66cbb5 AJ |
1075 | dss_feat_get_reg_field(FEAT_REG_FIRHINC, |
1076 | &hinc_start, &hinc_end); | |
1077 | dss_feat_get_reg_field(FEAT_REG_FIRVINC, | |
1078 | &vinc_start, &vinc_end); | |
1079 | val = FLD_VAL(vinc, vinc_start, vinc_end) | | |
1080 | FLD_VAL(hinc, hinc_start, hinc_end); | |
a0acb557 | 1081 | |
0d66cbb5 AJ |
1082 | dispc_write_reg(DISPC_OVL_FIR(plane), val); |
1083 | } else { | |
1084 | val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); | |
1085 | dispc_write_reg(DISPC_OVL_FIR2(plane), val); | |
1086 | } | |
80c39712 TV |
1087 | } |
1088 | ||
f0e5caab | 1089 | static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1090 | { |
1091 | u32 val; | |
87a7484b | 1092 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1093 | |
87a7484b AT |
1094 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1095 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1096 | ||
1097 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1098 | FLD_VAL(haccu, hor_start, hor_end); | |
1099 | ||
9b372c2d | 1100 | dispc_write_reg(DISPC_OVL_ACCU0(plane), val); |
80c39712 TV |
1101 | } |
1102 | ||
f0e5caab | 1103 | static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1104 | { |
1105 | u32 val; | |
87a7484b | 1106 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1107 | |
87a7484b AT |
1108 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1109 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1110 | ||
1111 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1112 | FLD_VAL(haccu, hor_start, hor_end); | |
1113 | ||
9b372c2d | 1114 | dispc_write_reg(DISPC_OVL_ACCU1(plane), val); |
80c39712 TV |
1115 | } |
1116 | ||
f0e5caab TV |
1117 | static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, |
1118 | int vaccu) | |
ab5ca071 AJ |
1119 | { |
1120 | u32 val; | |
1121 | ||
1122 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1123 | dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); | |
1124 | } | |
1125 | ||
f0e5caab TV |
1126 | static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, |
1127 | int vaccu) | |
ab5ca071 AJ |
1128 | { |
1129 | u32 val; | |
1130 | ||
1131 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1132 | dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); | |
1133 | } | |
80c39712 | 1134 | |
f0e5caab | 1135 | static void dispc_ovl_set_scale_param(enum omap_plane plane, |
80c39712 TV |
1136 | u16 orig_width, u16 orig_height, |
1137 | u16 out_width, u16 out_height, | |
0d66cbb5 AJ |
1138 | bool five_taps, u8 rotation, |
1139 | enum omap_color_component color_comp) | |
80c39712 | 1140 | { |
0d66cbb5 | 1141 | int fir_hinc, fir_vinc; |
80c39712 | 1142 | |
ed14a3ce AJ |
1143 | fir_hinc = 1024 * orig_width / out_width; |
1144 | fir_vinc = 1024 * orig_height / out_height; | |
80c39712 | 1145 | |
debd9074 CM |
1146 | dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, |
1147 | color_comp); | |
f0e5caab | 1148 | dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); |
0d66cbb5 AJ |
1149 | } |
1150 | ||
f0e5caab | 1151 | static void dispc_ovl_set_scaling_common(enum omap_plane plane, |
0d66cbb5 AJ |
1152 | u16 orig_width, u16 orig_height, |
1153 | u16 out_width, u16 out_height, | |
1154 | bool ilace, bool five_taps, | |
1155 | bool fieldmode, enum omap_color_mode color_mode, | |
1156 | u8 rotation) | |
1157 | { | |
1158 | int accu0 = 0; | |
1159 | int accu1 = 0; | |
1160 | u32 l; | |
80c39712 | 1161 | |
f0e5caab | 1162 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1163 | out_width, out_height, five_taps, |
1164 | rotation, DISPC_COLOR_COMPONENT_RGB_Y); | |
9b372c2d | 1165 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1166 | |
87a7484b AT |
1167 | /* RESIZEENABLE and VERTICALTAPS */ |
1168 | l &= ~((0x3 << 5) | (0x1 << 21)); | |
ed14a3ce AJ |
1169 | l |= (orig_width != out_width) ? (1 << 5) : 0; |
1170 | l |= (orig_height != out_height) ? (1 << 6) : 0; | |
87a7484b | 1171 | l |= five_taps ? (1 << 21) : 0; |
80c39712 | 1172 | |
87a7484b AT |
1173 | /* VRESIZECONF and HRESIZECONF */ |
1174 | if (dss_has_feature(FEAT_RESIZECONF)) { | |
1175 | l &= ~(0x3 << 7); | |
0d66cbb5 AJ |
1176 | l |= (orig_width <= out_width) ? 0 : (1 << 7); |
1177 | l |= (orig_height <= out_height) ? 0 : (1 << 8); | |
87a7484b | 1178 | } |
80c39712 | 1179 | |
87a7484b AT |
1180 | /* LINEBUFFERSPLIT */ |
1181 | if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { | |
1182 | l &= ~(0x1 << 22); | |
1183 | l |= five_taps ? (1 << 22) : 0; | |
1184 | } | |
80c39712 | 1185 | |
9b372c2d | 1186 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); |
80c39712 TV |
1187 | |
1188 | /* | |
1189 | * field 0 = even field = bottom field | |
1190 | * field 1 = odd field = top field | |
1191 | */ | |
1192 | if (ilace && !fieldmode) { | |
1193 | accu1 = 0; | |
0d66cbb5 | 1194 | accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; |
80c39712 TV |
1195 | if (accu0 >= 1024/2) { |
1196 | accu1 = 1024/2; | |
1197 | accu0 -= accu1; | |
1198 | } | |
1199 | } | |
1200 | ||
f0e5caab TV |
1201 | dispc_ovl_set_vid_accu0(plane, 0, accu0); |
1202 | dispc_ovl_set_vid_accu1(plane, 0, accu1); | |
80c39712 TV |
1203 | } |
1204 | ||
f0e5caab | 1205 | static void dispc_ovl_set_scaling_uv(enum omap_plane plane, |
0d66cbb5 AJ |
1206 | u16 orig_width, u16 orig_height, |
1207 | u16 out_width, u16 out_height, | |
1208 | bool ilace, bool five_taps, | |
1209 | bool fieldmode, enum omap_color_mode color_mode, | |
1210 | u8 rotation) | |
1211 | { | |
1212 | int scale_x = out_width != orig_width; | |
1213 | int scale_y = out_height != orig_height; | |
1214 | ||
1215 | if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) | |
1216 | return; | |
1217 | if ((color_mode != OMAP_DSS_COLOR_YUV2 && | |
1218 | color_mode != OMAP_DSS_COLOR_UYVY && | |
1219 | color_mode != OMAP_DSS_COLOR_NV12)) { | |
1220 | /* reset chroma resampling for RGB formats */ | |
1221 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); | |
1222 | return; | |
1223 | } | |
1224 | switch (color_mode) { | |
1225 | case OMAP_DSS_COLOR_NV12: | |
1226 | /* UV is subsampled by 2 vertically*/ | |
1227 | orig_height >>= 1; | |
1228 | /* UV is subsampled by 2 horz.*/ | |
1229 | orig_width >>= 1; | |
1230 | break; | |
1231 | case OMAP_DSS_COLOR_YUV2: | |
1232 | case OMAP_DSS_COLOR_UYVY: | |
1233 | /*For YUV422 with 90/270 rotation, | |
1234 | *we don't upsample chroma | |
1235 | */ | |
1236 | if (rotation == OMAP_DSS_ROT_0 || | |
1237 | rotation == OMAP_DSS_ROT_180) | |
1238 | /* UV is subsampled by 2 hrz*/ | |
1239 | orig_width >>= 1; | |
1240 | /* must use FIR for YUV422 if rotated */ | |
1241 | if (rotation != OMAP_DSS_ROT_0) | |
1242 | scale_x = scale_y = true; | |
1243 | break; | |
1244 | default: | |
1245 | BUG(); | |
1246 | } | |
1247 | ||
1248 | if (out_width != orig_width) | |
1249 | scale_x = true; | |
1250 | if (out_height != orig_height) | |
1251 | scale_y = true; | |
1252 | ||
f0e5caab | 1253 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1254 | out_width, out_height, five_taps, |
1255 | rotation, DISPC_COLOR_COMPONENT_UV); | |
1256 | ||
1257 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), | |
1258 | (scale_x || scale_y) ? 1 : 0, 8, 8); | |
1259 | /* set H scaling */ | |
1260 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); | |
1261 | /* set V scaling */ | |
1262 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); | |
1263 | ||
f0e5caab TV |
1264 | dispc_ovl_set_vid_accu2_0(plane, 0x80, 0); |
1265 | dispc_ovl_set_vid_accu2_1(plane, 0x80, 0); | |
0d66cbb5 AJ |
1266 | } |
1267 | ||
f0e5caab | 1268 | static void dispc_ovl_set_scaling(enum omap_plane plane, |
0d66cbb5 AJ |
1269 | u16 orig_width, u16 orig_height, |
1270 | u16 out_width, u16 out_height, | |
1271 | bool ilace, bool five_taps, | |
1272 | bool fieldmode, enum omap_color_mode color_mode, | |
1273 | u8 rotation) | |
1274 | { | |
1275 | BUG_ON(plane == OMAP_DSS_GFX); | |
1276 | ||
f0e5caab | 1277 | dispc_ovl_set_scaling_common(plane, |
0d66cbb5 AJ |
1278 | orig_width, orig_height, |
1279 | out_width, out_height, | |
1280 | ilace, five_taps, | |
1281 | fieldmode, color_mode, | |
1282 | rotation); | |
1283 | ||
f0e5caab | 1284 | dispc_ovl_set_scaling_uv(plane, |
0d66cbb5 AJ |
1285 | orig_width, orig_height, |
1286 | out_width, out_height, | |
1287 | ilace, five_taps, | |
1288 | fieldmode, color_mode, | |
1289 | rotation); | |
1290 | } | |
1291 | ||
f0e5caab | 1292 | static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, |
80c39712 TV |
1293 | bool mirroring, enum omap_color_mode color_mode) |
1294 | { | |
87a7484b AT |
1295 | bool row_repeat = false; |
1296 | int vidrot = 0; | |
1297 | ||
80c39712 TV |
1298 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1299 | color_mode == OMAP_DSS_COLOR_UYVY) { | |
80c39712 TV |
1300 | |
1301 | if (mirroring) { | |
1302 | switch (rotation) { | |
1303 | case OMAP_DSS_ROT_0: | |
1304 | vidrot = 2; | |
1305 | break; | |
1306 | case OMAP_DSS_ROT_90: | |
1307 | vidrot = 1; | |
1308 | break; | |
1309 | case OMAP_DSS_ROT_180: | |
1310 | vidrot = 0; | |
1311 | break; | |
1312 | case OMAP_DSS_ROT_270: | |
1313 | vidrot = 3; | |
1314 | break; | |
1315 | } | |
1316 | } else { | |
1317 | switch (rotation) { | |
1318 | case OMAP_DSS_ROT_0: | |
1319 | vidrot = 0; | |
1320 | break; | |
1321 | case OMAP_DSS_ROT_90: | |
1322 | vidrot = 1; | |
1323 | break; | |
1324 | case OMAP_DSS_ROT_180: | |
1325 | vidrot = 2; | |
1326 | break; | |
1327 | case OMAP_DSS_ROT_270: | |
1328 | vidrot = 3; | |
1329 | break; | |
1330 | } | |
1331 | } | |
1332 | ||
80c39712 | 1333 | if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) |
87a7484b | 1334 | row_repeat = true; |
80c39712 | 1335 | else |
87a7484b | 1336 | row_repeat = false; |
80c39712 | 1337 | } |
87a7484b | 1338 | |
9b372c2d | 1339 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); |
87a7484b | 1340 | if (dss_has_feature(FEAT_ROWREPEATENABLE)) |
9b372c2d AT |
1341 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), |
1342 | row_repeat ? 1 : 0, 18, 18); | |
80c39712 TV |
1343 | } |
1344 | ||
1345 | static int color_mode_to_bpp(enum omap_color_mode color_mode) | |
1346 | { | |
1347 | switch (color_mode) { | |
1348 | case OMAP_DSS_COLOR_CLUT1: | |
1349 | return 1; | |
1350 | case OMAP_DSS_COLOR_CLUT2: | |
1351 | return 2; | |
1352 | case OMAP_DSS_COLOR_CLUT4: | |
1353 | return 4; | |
1354 | case OMAP_DSS_COLOR_CLUT8: | |
f20e4220 | 1355 | case OMAP_DSS_COLOR_NV12: |
80c39712 TV |
1356 | return 8; |
1357 | case OMAP_DSS_COLOR_RGB12U: | |
1358 | case OMAP_DSS_COLOR_RGB16: | |
1359 | case OMAP_DSS_COLOR_ARGB16: | |
1360 | case OMAP_DSS_COLOR_YUV2: | |
1361 | case OMAP_DSS_COLOR_UYVY: | |
f20e4220 AJ |
1362 | case OMAP_DSS_COLOR_RGBA16: |
1363 | case OMAP_DSS_COLOR_RGBX16: | |
1364 | case OMAP_DSS_COLOR_ARGB16_1555: | |
1365 | case OMAP_DSS_COLOR_XRGB16_1555: | |
80c39712 TV |
1366 | return 16; |
1367 | case OMAP_DSS_COLOR_RGB24P: | |
1368 | return 24; | |
1369 | case OMAP_DSS_COLOR_RGB24U: | |
1370 | case OMAP_DSS_COLOR_ARGB32: | |
1371 | case OMAP_DSS_COLOR_RGBA32: | |
1372 | case OMAP_DSS_COLOR_RGBX32: | |
1373 | return 32; | |
1374 | default: | |
1375 | BUG(); | |
1376 | } | |
1377 | } | |
1378 | ||
1379 | static s32 pixinc(int pixels, u8 ps) | |
1380 | { | |
1381 | if (pixels == 1) | |
1382 | return 1; | |
1383 | else if (pixels > 1) | |
1384 | return 1 + (pixels - 1) * ps; | |
1385 | else if (pixels < 0) | |
1386 | return 1 - (-pixels + 1) * ps; | |
1387 | else | |
1388 | BUG(); | |
1389 | } | |
1390 | ||
1391 | static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, | |
1392 | u16 screen_width, | |
1393 | u16 width, u16 height, | |
1394 | enum omap_color_mode color_mode, bool fieldmode, | |
1395 | unsigned int field_offset, | |
1396 | unsigned *offset0, unsigned *offset1, | |
1397 | s32 *row_inc, s32 *pix_inc) | |
1398 | { | |
1399 | u8 ps; | |
1400 | ||
1401 | /* FIXME CLUT formats */ | |
1402 | switch (color_mode) { | |
1403 | case OMAP_DSS_COLOR_CLUT1: | |
1404 | case OMAP_DSS_COLOR_CLUT2: | |
1405 | case OMAP_DSS_COLOR_CLUT4: | |
1406 | case OMAP_DSS_COLOR_CLUT8: | |
1407 | BUG(); | |
1408 | return; | |
1409 | case OMAP_DSS_COLOR_YUV2: | |
1410 | case OMAP_DSS_COLOR_UYVY: | |
1411 | ps = 4; | |
1412 | break; | |
1413 | default: | |
1414 | ps = color_mode_to_bpp(color_mode) / 8; | |
1415 | break; | |
1416 | } | |
1417 | ||
1418 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1419 | width, height); | |
1420 | ||
1421 | /* | |
1422 | * field 0 = even field = bottom field | |
1423 | * field 1 = odd field = top field | |
1424 | */ | |
1425 | switch (rotation + mirror * 4) { | |
1426 | case OMAP_DSS_ROT_0: | |
1427 | case OMAP_DSS_ROT_180: | |
1428 | /* | |
1429 | * If the pixel format is YUV or UYVY divide the width | |
1430 | * of the image by 2 for 0 and 180 degree rotation. | |
1431 | */ | |
1432 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1433 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1434 | width = width >> 1; | |
1435 | case OMAP_DSS_ROT_90: | |
1436 | case OMAP_DSS_ROT_270: | |
1437 | *offset1 = 0; | |
1438 | if (field_offset) | |
1439 | *offset0 = field_offset * screen_width * ps; | |
1440 | else | |
1441 | *offset0 = 0; | |
1442 | ||
1443 | *row_inc = pixinc(1 + (screen_width - width) + | |
1444 | (fieldmode ? screen_width : 0), | |
1445 | ps); | |
1446 | *pix_inc = pixinc(1, ps); | |
1447 | break; | |
1448 | ||
1449 | case OMAP_DSS_ROT_0 + 4: | |
1450 | case OMAP_DSS_ROT_180 + 4: | |
1451 | /* If the pixel format is YUV or UYVY divide the width | |
1452 | * of the image by 2 for 0 degree and 180 degree | |
1453 | */ | |
1454 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1455 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1456 | width = width >> 1; | |
1457 | case OMAP_DSS_ROT_90 + 4: | |
1458 | case OMAP_DSS_ROT_270 + 4: | |
1459 | *offset1 = 0; | |
1460 | if (field_offset) | |
1461 | *offset0 = field_offset * screen_width * ps; | |
1462 | else | |
1463 | *offset0 = 0; | |
1464 | *row_inc = pixinc(1 - (screen_width + width) - | |
1465 | (fieldmode ? screen_width : 0), | |
1466 | ps); | |
1467 | *pix_inc = pixinc(1, ps); | |
1468 | break; | |
1469 | ||
1470 | default: | |
1471 | BUG(); | |
1472 | } | |
1473 | } | |
1474 | ||
1475 | static void calc_dma_rotation_offset(u8 rotation, bool mirror, | |
1476 | u16 screen_width, | |
1477 | u16 width, u16 height, | |
1478 | enum omap_color_mode color_mode, bool fieldmode, | |
1479 | unsigned int field_offset, | |
1480 | unsigned *offset0, unsigned *offset1, | |
1481 | s32 *row_inc, s32 *pix_inc) | |
1482 | { | |
1483 | u8 ps; | |
1484 | u16 fbw, fbh; | |
1485 | ||
1486 | /* FIXME CLUT formats */ | |
1487 | switch (color_mode) { | |
1488 | case OMAP_DSS_COLOR_CLUT1: | |
1489 | case OMAP_DSS_COLOR_CLUT2: | |
1490 | case OMAP_DSS_COLOR_CLUT4: | |
1491 | case OMAP_DSS_COLOR_CLUT8: | |
1492 | BUG(); | |
1493 | return; | |
1494 | default: | |
1495 | ps = color_mode_to_bpp(color_mode) / 8; | |
1496 | break; | |
1497 | } | |
1498 | ||
1499 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1500 | width, height); | |
1501 | ||
1502 | /* width & height are overlay sizes, convert to fb sizes */ | |
1503 | ||
1504 | if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { | |
1505 | fbw = width; | |
1506 | fbh = height; | |
1507 | } else { | |
1508 | fbw = height; | |
1509 | fbh = width; | |
1510 | } | |
1511 | ||
1512 | /* | |
1513 | * field 0 = even field = bottom field | |
1514 | * field 1 = odd field = top field | |
1515 | */ | |
1516 | switch (rotation + mirror * 4) { | |
1517 | case OMAP_DSS_ROT_0: | |
1518 | *offset1 = 0; | |
1519 | if (field_offset) | |
1520 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1521 | else | |
1522 | *offset0 = *offset1; | |
1523 | *row_inc = pixinc(1 + (screen_width - fbw) + | |
1524 | (fieldmode ? screen_width : 0), | |
1525 | ps); | |
1526 | *pix_inc = pixinc(1, ps); | |
1527 | break; | |
1528 | case OMAP_DSS_ROT_90: | |
1529 | *offset1 = screen_width * (fbh - 1) * ps; | |
1530 | if (field_offset) | |
1531 | *offset0 = *offset1 + field_offset * ps; | |
1532 | else | |
1533 | *offset0 = *offset1; | |
1534 | *row_inc = pixinc(screen_width * (fbh - 1) + 1 + | |
1535 | (fieldmode ? 1 : 0), ps); | |
1536 | *pix_inc = pixinc(-screen_width, ps); | |
1537 | break; | |
1538 | case OMAP_DSS_ROT_180: | |
1539 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
1540 | if (field_offset) | |
1541 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
1542 | else | |
1543 | *offset0 = *offset1; | |
1544 | *row_inc = pixinc(-1 - | |
1545 | (screen_width - fbw) - | |
1546 | (fieldmode ? screen_width : 0), | |
1547 | ps); | |
1548 | *pix_inc = pixinc(-1, ps); | |
1549 | break; | |
1550 | case OMAP_DSS_ROT_270: | |
1551 | *offset1 = (fbw - 1) * ps; | |
1552 | if (field_offset) | |
1553 | *offset0 = *offset1 - field_offset * ps; | |
1554 | else | |
1555 | *offset0 = *offset1; | |
1556 | *row_inc = pixinc(-screen_width * (fbh - 1) - 1 - | |
1557 | (fieldmode ? 1 : 0), ps); | |
1558 | *pix_inc = pixinc(screen_width, ps); | |
1559 | break; | |
1560 | ||
1561 | /* mirroring */ | |
1562 | case OMAP_DSS_ROT_0 + 4: | |
1563 | *offset1 = (fbw - 1) * ps; | |
1564 | if (field_offset) | |
1565 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1566 | else | |
1567 | *offset0 = *offset1; | |
1568 | *row_inc = pixinc(screen_width * 2 - 1 + | |
1569 | (fieldmode ? screen_width : 0), | |
1570 | ps); | |
1571 | *pix_inc = pixinc(-1, ps); | |
1572 | break; | |
1573 | ||
1574 | case OMAP_DSS_ROT_90 + 4: | |
1575 | *offset1 = 0; | |
1576 | if (field_offset) | |
1577 | *offset0 = *offset1 + field_offset * ps; | |
1578 | else | |
1579 | *offset0 = *offset1; | |
1580 | *row_inc = pixinc(-screen_width * (fbh - 1) + 1 + | |
1581 | (fieldmode ? 1 : 0), | |
1582 | ps); | |
1583 | *pix_inc = pixinc(screen_width, ps); | |
1584 | break; | |
1585 | ||
1586 | case OMAP_DSS_ROT_180 + 4: | |
1587 | *offset1 = screen_width * (fbh - 1) * ps; | |
1588 | if (field_offset) | |
1589 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
1590 | else | |
1591 | *offset0 = *offset1; | |
1592 | *row_inc = pixinc(1 - screen_width * 2 - | |
1593 | (fieldmode ? screen_width : 0), | |
1594 | ps); | |
1595 | *pix_inc = pixinc(1, ps); | |
1596 | break; | |
1597 | ||
1598 | case OMAP_DSS_ROT_270 + 4: | |
1599 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
1600 | if (field_offset) | |
1601 | *offset0 = *offset1 - field_offset * ps; | |
1602 | else | |
1603 | *offset0 = *offset1; | |
1604 | *row_inc = pixinc(screen_width * (fbh - 1) - 1 - | |
1605 | (fieldmode ? 1 : 0), | |
1606 | ps); | |
1607 | *pix_inc = pixinc(-screen_width, ps); | |
1608 | break; | |
1609 | ||
1610 | default: | |
1611 | BUG(); | |
1612 | } | |
1613 | } | |
1614 | ||
ff1b2cde SS |
1615 | static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width, |
1616 | u16 height, u16 out_width, u16 out_height, | |
1617 | enum omap_color_mode color_mode) | |
80c39712 TV |
1618 | { |
1619 | u32 fclk = 0; | |
26d9dd0d | 1620 | u64 tmp, pclk = dispc_mgr_pclk_rate(channel); |
80c39712 | 1621 | |
7282f1b7 CM |
1622 | if (height <= out_height && width <= out_width) |
1623 | return (unsigned long) pclk; | |
1624 | ||
80c39712 | 1625 | if (height > out_height) { |
ebdc5249 AT |
1626 | struct omap_dss_device *dssdev = dispc_mgr_get_device(channel); |
1627 | unsigned int ppl = dssdev->panel.timings.x_res; | |
80c39712 TV |
1628 | |
1629 | tmp = pclk * height * out_width; | |
1630 | do_div(tmp, 2 * out_height * ppl); | |
1631 | fclk = tmp; | |
1632 | ||
2d9c5597 VS |
1633 | if (height > 2 * out_height) { |
1634 | if (ppl == out_width) | |
1635 | return 0; | |
1636 | ||
80c39712 TV |
1637 | tmp = pclk * (height - 2 * out_height) * out_width; |
1638 | do_div(tmp, 2 * out_height * (ppl - out_width)); | |
1639 | fclk = max(fclk, (u32) tmp); | |
1640 | } | |
1641 | } | |
1642 | ||
1643 | if (width > out_width) { | |
1644 | tmp = pclk * width; | |
1645 | do_div(tmp, out_width); | |
1646 | fclk = max(fclk, (u32) tmp); | |
1647 | ||
1648 | if (color_mode == OMAP_DSS_COLOR_RGB24U) | |
1649 | fclk <<= 1; | |
1650 | } | |
1651 | ||
1652 | return fclk; | |
1653 | } | |
1654 | ||
ff1b2cde SS |
1655 | static unsigned long calc_fclk(enum omap_channel channel, u16 width, |
1656 | u16 height, u16 out_width, u16 out_height) | |
80c39712 TV |
1657 | { |
1658 | unsigned int hf, vf; | |
1659 | ||
1660 | /* | |
1661 | * FIXME how to determine the 'A' factor | |
1662 | * for the no downscaling case ? | |
1663 | */ | |
1664 | ||
1665 | if (width > 3 * out_width) | |
1666 | hf = 4; | |
1667 | else if (width > 2 * out_width) | |
1668 | hf = 3; | |
1669 | else if (width > out_width) | |
1670 | hf = 2; | |
1671 | else | |
1672 | hf = 1; | |
1673 | ||
1674 | if (height > out_height) | |
1675 | vf = 2; | |
1676 | else | |
1677 | vf = 1; | |
1678 | ||
7282f1b7 CM |
1679 | if (cpu_is_omap24xx()) { |
1680 | if (vf > 1 && hf > 1) | |
1681 | return dispc_mgr_pclk_rate(channel) * 4; | |
1682 | else | |
1683 | return dispc_mgr_pclk_rate(channel) * 2; | |
1684 | } else if (cpu_is_omap34xx()) { | |
1685 | return dispc_mgr_pclk_rate(channel) * vf * hf; | |
1686 | } else { | |
1687 | return dispc_mgr_pclk_rate(channel) * hf; | |
1688 | } | |
80c39712 TV |
1689 | } |
1690 | ||
79ad75f2 AT |
1691 | static int dispc_ovl_calc_scaling(enum omap_plane plane, |
1692 | enum omap_channel channel, u16 width, u16 height, | |
1693 | u16 out_width, u16 out_height, | |
1694 | enum omap_color_mode color_mode, bool *five_taps) | |
1695 | { | |
1696 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); | |
0373cac6 | 1697 | const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); |
7282f1b7 CM |
1698 | const int maxsinglelinewidth = |
1699 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
79ad75f2 AT |
1700 | unsigned long fclk = 0; |
1701 | ||
f95cb5eb TV |
1702 | if (width == out_width && height == out_height) |
1703 | return 0; | |
1704 | ||
1705 | if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) | |
1706 | return -EINVAL; | |
79ad75f2 AT |
1707 | |
1708 | if (out_width < width / maxdownscale || | |
1709 | out_width > width * 8) | |
1710 | return -EINVAL; | |
1711 | ||
1712 | if (out_height < height / maxdownscale || | |
1713 | out_height > height * 8) | |
1714 | return -EINVAL; | |
1715 | ||
7282f1b7 CM |
1716 | if (cpu_is_omap24xx()) { |
1717 | if (width > maxsinglelinewidth) | |
1718 | DSSERR("Cannot scale max input width exceeded"); | |
1719 | *five_taps = false; | |
1720 | fclk = calc_fclk(channel, width, height, out_width, | |
1721 | out_height); | |
1722 | } else if (cpu_is_omap34xx()) { | |
1723 | if (width > (maxsinglelinewidth * 2)) { | |
1724 | DSSERR("Cannot setup scaling"); | |
1725 | DSSERR("width exceeds maximum width possible"); | |
1726 | return -EINVAL; | |
1727 | } | |
1728 | fclk = calc_fclk_five_taps(channel, width, height, out_width, | |
1729 | out_height, color_mode); | |
1730 | if (width > maxsinglelinewidth) { | |
1731 | if (height > out_height && height < out_height * 2) | |
1732 | *five_taps = false; | |
1733 | else { | |
1734 | DSSERR("cannot setup scaling with five taps"); | |
1735 | return -EINVAL; | |
1736 | } | |
1737 | } | |
1738 | if (!*five_taps) | |
1739 | fclk = calc_fclk(channel, width, height, out_width, | |
1740 | out_height); | |
1741 | } else { | |
1742 | if (width > maxsinglelinewidth) { | |
1743 | DSSERR("Cannot scale width exceeds max line width"); | |
1744 | return -EINVAL; | |
1745 | } | |
79ad75f2 AT |
1746 | fclk = calc_fclk(channel, width, height, out_width, |
1747 | out_height); | |
79ad75f2 AT |
1748 | } |
1749 | ||
79ad75f2 AT |
1750 | DSSDBG("required fclk rate = %lu Hz\n", fclk); |
1751 | DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate()); | |
1752 | ||
1753 | if (!fclk || fclk > dispc_fclk_rate()) { | |
1754 | DSSERR("failed to set up scaling, " | |
1755 | "required fclk rate = %lu Hz, " | |
1756 | "current fclk rate = %lu Hz\n", | |
1757 | fclk, dispc_fclk_rate()); | |
1758 | return -EINVAL; | |
1759 | } | |
1760 | ||
1761 | return 0; | |
1762 | } | |
1763 | ||
a4273b7c | 1764 | int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi, |
2cc5d1af | 1765 | bool ilace, bool replication) |
80c39712 | 1766 | { |
79ad75f2 | 1767 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); |
7282f1b7 | 1768 | bool five_taps = true; |
80c39712 | 1769 | bool fieldmode = 0; |
79ad75f2 | 1770 | int r, cconv = 0; |
80c39712 TV |
1771 | unsigned offset0, offset1; |
1772 | s32 row_inc; | |
1773 | s32 pix_inc; | |
a4273b7c | 1774 | u16 frame_height = oi->height; |
80c39712 | 1775 | unsigned int field_offset = 0; |
cf073668 | 1776 | u16 outw, outh; |
2cc5d1af TV |
1777 | enum omap_channel channel; |
1778 | ||
1779 | channel = dispc_ovl_get_channel_out(plane); | |
80c39712 | 1780 | |
a4273b7c | 1781 | DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> " |
f38545da TV |
1782 | "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n", |
1783 | plane, oi->paddr, oi->p_uv_addr, | |
c3d92529 AT |
1784 | oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, |
1785 | oi->out_width, oi->out_height, oi->color_mode, oi->rotation, | |
f38545da | 1786 | oi->mirror, ilace, channel, replication); |
e6d80f95 | 1787 | |
a4273b7c | 1788 | if (oi->paddr == 0) |
80c39712 TV |
1789 | return -EINVAL; |
1790 | ||
cf073668 TV |
1791 | outw = oi->out_width == 0 ? oi->width : oi->out_width; |
1792 | outh = oi->out_height == 0 ? oi->height : oi->out_height; | |
1793 | ||
1794 | if (ilace && oi->height == outh) | |
80c39712 TV |
1795 | fieldmode = 1; |
1796 | ||
1797 | if (ilace) { | |
1798 | if (fieldmode) | |
a4273b7c AT |
1799 | oi->height /= 2; |
1800 | oi->pos_y /= 2; | |
cf073668 | 1801 | outh /= 2; |
80c39712 TV |
1802 | |
1803 | DSSDBG("adjusting for ilace: height %d, pos_y %d, " | |
1804 | "out_height %d\n", | |
cf073668 | 1805 | oi->height, oi->pos_y, outh); |
80c39712 TV |
1806 | } |
1807 | ||
a4273b7c | 1808 | if (!dss_feat_color_mode_supported(plane, oi->color_mode)) |
8dad2ab6 AT |
1809 | return -EINVAL; |
1810 | ||
79ad75f2 | 1811 | r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height, |
cf073668 | 1812 | outw, outh, oi->color_mode, |
79ad75f2 AT |
1813 | &five_taps); |
1814 | if (r) | |
1815 | return r; | |
80c39712 | 1816 | |
79ad75f2 AT |
1817 | if (oi->color_mode == OMAP_DSS_COLOR_YUV2 || |
1818 | oi->color_mode == OMAP_DSS_COLOR_UYVY || | |
1819 | oi->color_mode == OMAP_DSS_COLOR_NV12) | |
1820 | cconv = 1; | |
80c39712 TV |
1821 | |
1822 | if (ilace && !fieldmode) { | |
1823 | /* | |
1824 | * when downscaling the bottom field may have to start several | |
1825 | * source lines below the top field. Unfortunately ACCUI | |
1826 | * registers will only hold the fractional part of the offset | |
1827 | * so the integer part must be added to the base address of the | |
1828 | * bottom field. | |
1829 | */ | |
cf073668 | 1830 | if (!oi->height || oi->height == outh) |
80c39712 TV |
1831 | field_offset = 0; |
1832 | else | |
cf073668 | 1833 | field_offset = oi->height / outh / 2; |
80c39712 TV |
1834 | } |
1835 | ||
1836 | /* Fields are independent but interleaved in memory. */ | |
1837 | if (fieldmode) | |
1838 | field_offset = 1; | |
1839 | ||
a4273b7c AT |
1840 | if (oi->rotation_type == OMAP_DSS_ROT_DMA) |
1841 | calc_dma_rotation_offset(oi->rotation, oi->mirror, | |
1842 | oi->screen_width, oi->width, frame_height, | |
1843 | oi->color_mode, fieldmode, field_offset, | |
80c39712 TV |
1844 | &offset0, &offset1, &row_inc, &pix_inc); |
1845 | else | |
a4273b7c AT |
1846 | calc_vrfb_rotation_offset(oi->rotation, oi->mirror, |
1847 | oi->screen_width, oi->width, frame_height, | |
1848 | oi->color_mode, fieldmode, field_offset, | |
80c39712 TV |
1849 | &offset0, &offset1, &row_inc, &pix_inc); |
1850 | ||
1851 | DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", | |
1852 | offset0, offset1, row_inc, pix_inc); | |
1853 | ||
a4273b7c | 1854 | dispc_ovl_set_color_mode(plane, oi->color_mode); |
80c39712 | 1855 | |
a4273b7c AT |
1856 | dispc_ovl_set_ba0(plane, oi->paddr + offset0); |
1857 | dispc_ovl_set_ba1(plane, oi->paddr + offset1); | |
80c39712 | 1858 | |
a4273b7c AT |
1859 | if (OMAP_DSS_COLOR_NV12 == oi->color_mode) { |
1860 | dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0); | |
1861 | dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1); | |
0d66cbb5 AJ |
1862 | } |
1863 | ||
1864 | ||
f0e5caab TV |
1865 | dispc_ovl_set_row_inc(plane, row_inc); |
1866 | dispc_ovl_set_pix_inc(plane, pix_inc); | |
80c39712 | 1867 | |
a4273b7c | 1868 | DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width, |
cf073668 | 1869 | oi->height, outw, outh); |
80c39712 | 1870 | |
a4273b7c | 1871 | dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y); |
80c39712 | 1872 | |
a4273b7c | 1873 | dispc_ovl_set_pic_size(plane, oi->width, oi->height); |
80c39712 | 1874 | |
79ad75f2 | 1875 | if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) { |
a4273b7c | 1876 | dispc_ovl_set_scaling(plane, oi->width, oi->height, |
cf073668 | 1877 | outw, outh, |
0d66cbb5 | 1878 | ilace, five_taps, fieldmode, |
a4273b7c | 1879 | oi->color_mode, oi->rotation); |
cf073668 | 1880 | dispc_ovl_set_vid_size(plane, outw, outh); |
f0e5caab | 1881 | dispc_ovl_set_vid_color_conv(plane, cconv); |
80c39712 TV |
1882 | } |
1883 | ||
a4273b7c AT |
1884 | dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror, |
1885 | oi->color_mode); | |
80c39712 | 1886 | |
54128701 | 1887 | dispc_ovl_set_zorder(plane, oi->zorder); |
a4273b7c AT |
1888 | dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha); |
1889 | dispc_ovl_setup_global_alpha(plane, oi->global_alpha); | |
80c39712 | 1890 | |
c3d92529 | 1891 | dispc_ovl_enable_replication(plane, replication); |
c3d92529 | 1892 | |
80c39712 TV |
1893 | return 0; |
1894 | } | |
1895 | ||
f0e5caab | 1896 | int dispc_ovl_enable(enum omap_plane plane, bool enable) |
80c39712 | 1897 | { |
e6d80f95 TV |
1898 | DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); |
1899 | ||
9b372c2d | 1900 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); |
e6d80f95 TV |
1901 | |
1902 | return 0; | |
80c39712 TV |
1903 | } |
1904 | ||
1905 | static void dispc_disable_isr(void *data, u32 mask) | |
1906 | { | |
1907 | struct completion *compl = data; | |
1908 | complete(compl); | |
1909 | } | |
1910 | ||
2a205f34 | 1911 | static void _enable_lcd_out(enum omap_channel channel, bool enable) |
80c39712 | 1912 | { |
b6a44e77 | 1913 | if (channel == OMAP_DSS_CHANNEL_LCD2) { |
2a205f34 | 1914 | REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0); |
b6a44e77 TV |
1915 | /* flush posted write */ |
1916 | dispc_read_reg(DISPC_CONTROL2); | |
1917 | } else { | |
2a205f34 | 1918 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0); |
b6a44e77 TV |
1919 | dispc_read_reg(DISPC_CONTROL); |
1920 | } | |
80c39712 TV |
1921 | } |
1922 | ||
26d9dd0d | 1923 | static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable) |
80c39712 TV |
1924 | { |
1925 | struct completion frame_done_completion; | |
1926 | bool is_on; | |
1927 | int r; | |
2a205f34 | 1928 | u32 irq; |
80c39712 | 1929 | |
80c39712 TV |
1930 | /* When we disable LCD output, we need to wait until frame is done. |
1931 | * Otherwise the DSS is still working, and turning off the clocks | |
1932 | * prevents DSS from going to OFF mode */ | |
2a205f34 SS |
1933 | is_on = channel == OMAP_DSS_CHANNEL_LCD2 ? |
1934 | REG_GET(DISPC_CONTROL2, 0, 0) : | |
1935 | REG_GET(DISPC_CONTROL, 0, 0); | |
1936 | ||
1937 | irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 : | |
1938 | DISPC_IRQ_FRAMEDONE; | |
80c39712 TV |
1939 | |
1940 | if (!enable && is_on) { | |
1941 | init_completion(&frame_done_completion); | |
1942 | ||
1943 | r = omap_dispc_register_isr(dispc_disable_isr, | |
2a205f34 | 1944 | &frame_done_completion, irq); |
80c39712 TV |
1945 | |
1946 | if (r) | |
1947 | DSSERR("failed to register FRAMEDONE isr\n"); | |
1948 | } | |
1949 | ||
2a205f34 | 1950 | _enable_lcd_out(channel, enable); |
80c39712 TV |
1951 | |
1952 | if (!enable && is_on) { | |
1953 | if (!wait_for_completion_timeout(&frame_done_completion, | |
1954 | msecs_to_jiffies(100))) | |
1955 | DSSERR("timeout waiting for FRAME DONE\n"); | |
1956 | ||
1957 | r = omap_dispc_unregister_isr(dispc_disable_isr, | |
2a205f34 | 1958 | &frame_done_completion, irq); |
80c39712 TV |
1959 | |
1960 | if (r) | |
1961 | DSSERR("failed to unregister FRAMEDONE isr\n"); | |
1962 | } | |
80c39712 TV |
1963 | } |
1964 | ||
1965 | static void _enable_digit_out(bool enable) | |
1966 | { | |
1967 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1); | |
b6a44e77 TV |
1968 | /* flush posted write */ |
1969 | dispc_read_reg(DISPC_CONTROL); | |
80c39712 TV |
1970 | } |
1971 | ||
26d9dd0d | 1972 | static void dispc_mgr_enable_digit_out(bool enable) |
80c39712 TV |
1973 | { |
1974 | struct completion frame_done_completion; | |
e82b090b TV |
1975 | enum dss_hdmi_venc_clk_source_select src; |
1976 | int r, i; | |
1977 | u32 irq_mask; | |
1978 | int num_irqs; | |
80c39712 | 1979 | |
e6d80f95 | 1980 | if (REG_GET(DISPC_CONTROL, 1, 1) == enable) |
80c39712 | 1981 | return; |
80c39712 | 1982 | |
e82b090b TV |
1983 | src = dss_get_hdmi_venc_clk_source(); |
1984 | ||
80c39712 TV |
1985 | if (enable) { |
1986 | unsigned long flags; | |
1987 | /* When we enable digit output, we'll get an extra digit | |
1988 | * sync lost interrupt, that we need to ignore */ | |
1989 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
1990 | dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT; | |
1991 | _omap_dispc_set_irqs(); | |
1992 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
1993 | } | |
1994 | ||
1995 | /* When we disable digit output, we need to wait until fields are done. | |
1996 | * Otherwise the DSS is still working, and turning off the clocks | |
1997 | * prevents DSS from going to OFF mode. And when enabling, we need to | |
1998 | * wait for the extra sync losts */ | |
1999 | init_completion(&frame_done_completion); | |
2000 | ||
e82b090b TV |
2001 | if (src == DSS_HDMI_M_PCLK && enable == false) { |
2002 | irq_mask = DISPC_IRQ_FRAMEDONETV; | |
2003 | num_irqs = 1; | |
2004 | } else { | |
2005 | irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD; | |
2006 | /* XXX I understand from TRM that we should only wait for the | |
2007 | * current field to complete. But it seems we have to wait for | |
2008 | * both fields */ | |
2009 | num_irqs = 2; | |
2010 | } | |
2011 | ||
80c39712 | 2012 | r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion, |
e82b090b | 2013 | irq_mask); |
80c39712 | 2014 | if (r) |
e82b090b | 2015 | DSSERR("failed to register %x isr\n", irq_mask); |
80c39712 TV |
2016 | |
2017 | _enable_digit_out(enable); | |
2018 | ||
e82b090b TV |
2019 | for (i = 0; i < num_irqs; ++i) { |
2020 | if (!wait_for_completion_timeout(&frame_done_completion, | |
2021 | msecs_to_jiffies(100))) | |
2022 | DSSERR("timeout waiting for digit out to %s\n", | |
2023 | enable ? "start" : "stop"); | |
2024 | } | |
80c39712 | 2025 | |
e82b090b TV |
2026 | r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion, |
2027 | irq_mask); | |
80c39712 | 2028 | if (r) |
e82b090b | 2029 | DSSERR("failed to unregister %x isr\n", irq_mask); |
80c39712 TV |
2030 | |
2031 | if (enable) { | |
2032 | unsigned long flags; | |
2033 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
e82b090b | 2034 | dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT; |
80c39712 TV |
2035 | dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); |
2036 | _omap_dispc_set_irqs(); | |
2037 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
2038 | } | |
80c39712 TV |
2039 | } |
2040 | ||
26d9dd0d | 2041 | bool dispc_mgr_is_enabled(enum omap_channel channel) |
a2faee84 TV |
2042 | { |
2043 | if (channel == OMAP_DSS_CHANNEL_LCD) | |
2044 | return !!REG_GET(DISPC_CONTROL, 0, 0); | |
2045 | else if (channel == OMAP_DSS_CHANNEL_DIGIT) | |
2046 | return !!REG_GET(DISPC_CONTROL, 1, 1); | |
2a205f34 SS |
2047 | else if (channel == OMAP_DSS_CHANNEL_LCD2) |
2048 | return !!REG_GET(DISPC_CONTROL2, 0, 0); | |
a2faee84 TV |
2049 | else |
2050 | BUG(); | |
2051 | } | |
2052 | ||
26d9dd0d | 2053 | void dispc_mgr_enable(enum omap_channel channel, bool enable) |
a2faee84 | 2054 | { |
dac57a05 | 2055 | if (dispc_mgr_is_lcd(channel)) |
26d9dd0d | 2056 | dispc_mgr_enable_lcd_out(channel, enable); |
a2faee84 | 2057 | else if (channel == OMAP_DSS_CHANNEL_DIGIT) |
26d9dd0d | 2058 | dispc_mgr_enable_digit_out(enable); |
a2faee84 TV |
2059 | else |
2060 | BUG(); | |
2061 | } | |
2062 | ||
80c39712 TV |
2063 | void dispc_lcd_enable_signal_polarity(bool act_high) |
2064 | { | |
6ced40bf AT |
2065 | if (!dss_has_feature(FEAT_LCDENABLEPOL)) |
2066 | return; | |
2067 | ||
80c39712 | 2068 | REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); |
80c39712 TV |
2069 | } |
2070 | ||
2071 | void dispc_lcd_enable_signal(bool enable) | |
2072 | { | |
6ced40bf AT |
2073 | if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) |
2074 | return; | |
2075 | ||
80c39712 | 2076 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); |
80c39712 TV |
2077 | } |
2078 | ||
2079 | void dispc_pck_free_enable(bool enable) | |
2080 | { | |
6ced40bf AT |
2081 | if (!dss_has_feature(FEAT_PCKFREEENABLE)) |
2082 | return; | |
2083 | ||
80c39712 | 2084 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); |
80c39712 TV |
2085 | } |
2086 | ||
26d9dd0d | 2087 | void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) |
80c39712 | 2088 | { |
2a205f34 SS |
2089 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
2090 | REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16); | |
2091 | else | |
2092 | REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16); | |
80c39712 TV |
2093 | } |
2094 | ||
2095 | ||
26d9dd0d | 2096 | void dispc_mgr_set_lcd_display_type(enum omap_channel channel, |
64ba4f74 | 2097 | enum omap_lcd_display_type type) |
80c39712 TV |
2098 | { |
2099 | int mode; | |
2100 | ||
2101 | switch (type) { | |
2102 | case OMAP_DSS_LCD_DISPLAY_STN: | |
2103 | mode = 0; | |
2104 | break; | |
2105 | ||
2106 | case OMAP_DSS_LCD_DISPLAY_TFT: | |
2107 | mode = 1; | |
2108 | break; | |
2109 | ||
2110 | default: | |
2111 | BUG(); | |
2112 | return; | |
2113 | } | |
2114 | ||
2a205f34 SS |
2115 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
2116 | REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3); | |
2117 | else | |
2118 | REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3); | |
80c39712 TV |
2119 | } |
2120 | ||
2121 | void dispc_set_loadmode(enum omap_dss_load_mode mode) | |
2122 | { | |
80c39712 | 2123 | REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); |
80c39712 TV |
2124 | } |
2125 | ||
2126 | ||
c64dca40 | 2127 | static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) |
80c39712 | 2128 | { |
8613b000 | 2129 | dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); |
80c39712 TV |
2130 | } |
2131 | ||
c64dca40 | 2132 | static void dispc_mgr_set_trans_key(enum omap_channel ch, |
80c39712 TV |
2133 | enum omap_dss_trans_key_type type, |
2134 | u32 trans_key) | |
2135 | { | |
80c39712 TV |
2136 | if (ch == OMAP_DSS_CHANNEL_LCD) |
2137 | REG_FLD_MOD(DISPC_CONFIG, type, 11, 11); | |
2a205f34 | 2138 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
80c39712 | 2139 | REG_FLD_MOD(DISPC_CONFIG, type, 13, 13); |
2a205f34 SS |
2140 | else /* OMAP_DSS_CHANNEL_LCD2 */ |
2141 | REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11); | |
80c39712 | 2142 | |
8613b000 | 2143 | dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); |
80c39712 TV |
2144 | } |
2145 | ||
c64dca40 | 2146 | static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) |
80c39712 | 2147 | { |
80c39712 TV |
2148 | if (ch == OMAP_DSS_CHANNEL_LCD) |
2149 | REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10); | |
2a205f34 | 2150 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
80c39712 | 2151 | REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12); |
2a205f34 SS |
2152 | else /* OMAP_DSS_CHANNEL_LCD2 */ |
2153 | REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10); | |
80c39712 | 2154 | } |
11354dd5 | 2155 | |
c64dca40 TV |
2156 | static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, |
2157 | bool enable) | |
80c39712 | 2158 | { |
11354dd5 | 2159 | if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) |
80c39712 TV |
2160 | return; |
2161 | ||
80c39712 TV |
2162 | if (ch == OMAP_DSS_CHANNEL_LCD) |
2163 | REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); | |
2a205f34 | 2164 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
80c39712 | 2165 | REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); |
80c39712 | 2166 | } |
11354dd5 | 2167 | |
c64dca40 TV |
2168 | void dispc_mgr_setup(enum omap_channel channel, |
2169 | struct omap_overlay_manager_info *info) | |
2170 | { | |
2171 | dispc_mgr_set_default_color(channel, info->default_color); | |
2172 | dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); | |
2173 | dispc_mgr_enable_trans_key(channel, info->trans_enabled); | |
2174 | dispc_mgr_enable_alpha_fixed_zorder(channel, | |
2175 | info->partial_alpha_enabled); | |
2176 | if (dss_has_feature(FEAT_CPR)) { | |
2177 | dispc_mgr_enable_cpr(channel, info->cpr_enable); | |
2178 | dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); | |
2179 | } | |
2180 | } | |
80c39712 | 2181 | |
26d9dd0d | 2182 | void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) |
80c39712 TV |
2183 | { |
2184 | int code; | |
2185 | ||
2186 | switch (data_lines) { | |
2187 | case 12: | |
2188 | code = 0; | |
2189 | break; | |
2190 | case 16: | |
2191 | code = 1; | |
2192 | break; | |
2193 | case 18: | |
2194 | code = 2; | |
2195 | break; | |
2196 | case 24: | |
2197 | code = 3; | |
2198 | break; | |
2199 | default: | |
2200 | BUG(); | |
2201 | return; | |
2202 | } | |
2203 | ||
2a205f34 SS |
2204 | if (channel == OMAP_DSS_CHANNEL_LCD2) |
2205 | REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8); | |
2206 | else | |
2207 | REG_FLD_MOD(DISPC_CONTROL, code, 9, 8); | |
80c39712 TV |
2208 | } |
2209 | ||
569969d6 | 2210 | void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) |
80c39712 TV |
2211 | { |
2212 | u32 l; | |
569969d6 | 2213 | int gpout0, gpout1; |
80c39712 TV |
2214 | |
2215 | switch (mode) { | |
569969d6 AT |
2216 | case DSS_IO_PAD_MODE_RESET: |
2217 | gpout0 = 0; | |
2218 | gpout1 = 0; | |
80c39712 | 2219 | break; |
569969d6 AT |
2220 | case DSS_IO_PAD_MODE_RFBI: |
2221 | gpout0 = 1; | |
80c39712 TV |
2222 | gpout1 = 0; |
2223 | break; | |
569969d6 AT |
2224 | case DSS_IO_PAD_MODE_BYPASS: |
2225 | gpout0 = 1; | |
80c39712 TV |
2226 | gpout1 = 1; |
2227 | break; | |
80c39712 TV |
2228 | default: |
2229 | BUG(); | |
2230 | return; | |
2231 | } | |
2232 | ||
569969d6 AT |
2233 | l = dispc_read_reg(DISPC_CONTROL); |
2234 | l = FLD_MOD(l, gpout0, 15, 15); | |
2235 | l = FLD_MOD(l, gpout1, 16, 16); | |
2236 | dispc_write_reg(DISPC_CONTROL, l); | |
2237 | } | |
2238 | ||
2239 | void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) | |
2240 | { | |
2241 | if (channel == OMAP_DSS_CHANNEL_LCD2) | |
2242 | REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11); | |
2243 | else | |
2244 | REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11); | |
80c39712 TV |
2245 | } |
2246 | ||
2247 | static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, | |
2248 | int vsw, int vfp, int vbp) | |
2249 | { | |
2250 | if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { | |
2251 | if (hsw < 1 || hsw > 64 || | |
2252 | hfp < 1 || hfp > 256 || | |
2253 | hbp < 1 || hbp > 256 || | |
2254 | vsw < 1 || vsw > 64 || | |
2255 | vfp < 0 || vfp > 255 || | |
2256 | vbp < 0 || vbp > 255) | |
2257 | return false; | |
2258 | } else { | |
2259 | if (hsw < 1 || hsw > 256 || | |
2260 | hfp < 1 || hfp > 4096 || | |
2261 | hbp < 1 || hbp > 4096 || | |
2262 | vsw < 1 || vsw > 256 || | |
2263 | vfp < 0 || vfp > 4095 || | |
2264 | vbp < 0 || vbp > 4095) | |
2265 | return false; | |
2266 | } | |
2267 | ||
2268 | return true; | |
2269 | } | |
2270 | ||
2271 | bool dispc_lcd_timings_ok(struct omap_video_timings *timings) | |
2272 | { | |
2273 | return _dispc_lcd_timings_ok(timings->hsw, timings->hfp, | |
2274 | timings->hbp, timings->vsw, | |
2275 | timings->vfp, timings->vbp); | |
2276 | } | |
2277 | ||
26d9dd0d | 2278 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, |
64ba4f74 | 2279 | int hfp, int hbp, int vsw, int vfp, int vbp) |
80c39712 TV |
2280 | { |
2281 | u32 timing_h, timing_v; | |
2282 | ||
2283 | if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) { | |
2284 | timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) | | |
2285 | FLD_VAL(hbp-1, 27, 20); | |
2286 | ||
2287 | timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) | | |
2288 | FLD_VAL(vbp, 27, 20); | |
2289 | } else { | |
2290 | timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) | | |
2291 | FLD_VAL(hbp-1, 31, 20); | |
2292 | ||
2293 | timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) | | |
2294 | FLD_VAL(vbp, 31, 20); | |
2295 | } | |
2296 | ||
64ba4f74 SS |
2297 | dispc_write_reg(DISPC_TIMING_H(channel), timing_h); |
2298 | dispc_write_reg(DISPC_TIMING_V(channel), timing_v); | |
80c39712 TV |
2299 | } |
2300 | ||
2301 | /* change name to mode? */ | |
26d9dd0d | 2302 | void dispc_mgr_set_lcd_timings(enum omap_channel channel, |
64ba4f74 | 2303 | struct omap_video_timings *timings) |
80c39712 TV |
2304 | { |
2305 | unsigned xtot, ytot; | |
2306 | unsigned long ht, vt; | |
2307 | ||
2308 | if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp, | |
2309 | timings->hbp, timings->vsw, | |
2310 | timings->vfp, timings->vbp)) | |
2311 | BUG(); | |
2312 | ||
26d9dd0d | 2313 | _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp, |
64ba4f74 SS |
2314 | timings->hbp, timings->vsw, timings->vfp, |
2315 | timings->vbp); | |
80c39712 | 2316 | |
26d9dd0d | 2317 | dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res); |
80c39712 TV |
2318 | |
2319 | xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp; | |
2320 | ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp; | |
2321 | ||
2322 | ht = (timings->pixel_clock * 1000) / xtot; | |
2323 | vt = (timings->pixel_clock * 1000) / xtot / ytot; | |
2324 | ||
2a205f34 SS |
2325 | DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res, |
2326 | timings->y_res); | |
80c39712 TV |
2327 | DSSDBG("pck %u\n", timings->pixel_clock); |
2328 | DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", | |
2329 | timings->hsw, timings->hfp, timings->hbp, | |
2330 | timings->vsw, timings->vfp, timings->vbp); | |
2331 | ||
2332 | DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); | |
2333 | } | |
2334 | ||
26d9dd0d | 2335 | static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, |
ff1b2cde | 2336 | u16 pck_div) |
80c39712 TV |
2337 | { |
2338 | BUG_ON(lck_div < 1); | |
9eaaf207 | 2339 | BUG_ON(pck_div < 1); |
80c39712 | 2340 | |
ce7fa5eb | 2341 | dispc_write_reg(DISPC_DIVISORo(channel), |
80c39712 | 2342 | FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); |
80c39712 TV |
2343 | } |
2344 | ||
26d9dd0d | 2345 | static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, |
2a205f34 | 2346 | int *pck_div) |
80c39712 TV |
2347 | { |
2348 | u32 l; | |
ce7fa5eb | 2349 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 TV |
2350 | *lck_div = FLD_GET(l, 23, 16); |
2351 | *pck_div = FLD_GET(l, 7, 0); | |
2352 | } | |
2353 | ||
2354 | unsigned long dispc_fclk_rate(void) | |
2355 | { | |
a72b64b9 | 2356 | struct platform_device *dsidev; |
80c39712 TV |
2357 | unsigned long r = 0; |
2358 | ||
66534e8e | 2359 | switch (dss_get_dispc_clk_source()) { |
89a35e51 | 2360 | case OMAP_DSS_CLK_SRC_FCK: |
4fbafaf3 | 2361 | r = clk_get_rate(dispc.dss_clk); |
66534e8e | 2362 | break; |
89a35e51 | 2363 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
a72b64b9 AT |
2364 | dsidev = dsi_get_dsidev_from_id(0); |
2365 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
66534e8e | 2366 | break; |
5a8b572d AT |
2367 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
2368 | dsidev = dsi_get_dsidev_from_id(1); | |
2369 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
2370 | break; | |
66534e8e TA |
2371 | default: |
2372 | BUG(); | |
2373 | } | |
2374 | ||
80c39712 TV |
2375 | return r; |
2376 | } | |
2377 | ||
26d9dd0d | 2378 | unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) |
80c39712 | 2379 | { |
a72b64b9 | 2380 | struct platform_device *dsidev; |
80c39712 TV |
2381 | int lcd; |
2382 | unsigned long r; | |
2383 | u32 l; | |
2384 | ||
ce7fa5eb | 2385 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 TV |
2386 | |
2387 | lcd = FLD_GET(l, 23, 16); | |
2388 | ||
ea75159e | 2389 | switch (dss_get_lcd_clk_source(channel)) { |
89a35e51 | 2390 | case OMAP_DSS_CLK_SRC_FCK: |
4fbafaf3 | 2391 | r = clk_get_rate(dispc.dss_clk); |
ea75159e | 2392 | break; |
89a35e51 | 2393 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
a72b64b9 AT |
2394 | dsidev = dsi_get_dsidev_from_id(0); |
2395 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
ea75159e | 2396 | break; |
5a8b572d AT |
2397 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
2398 | dsidev = dsi_get_dsidev_from_id(1); | |
2399 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
2400 | break; | |
ea75159e TA |
2401 | default: |
2402 | BUG(); | |
2403 | } | |
80c39712 TV |
2404 | |
2405 | return r / lcd; | |
2406 | } | |
2407 | ||
26d9dd0d | 2408 | unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) |
80c39712 | 2409 | { |
80c39712 | 2410 | unsigned long r; |
80c39712 | 2411 | |
c3dc6a7a AT |
2412 | if (dispc_mgr_is_lcd(channel)) { |
2413 | int pcd; | |
2414 | u32 l; | |
80c39712 | 2415 | |
c3dc6a7a | 2416 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 | 2417 | |
c3dc6a7a | 2418 | pcd = FLD_GET(l, 7, 0); |
80c39712 | 2419 | |
c3dc6a7a AT |
2420 | r = dispc_mgr_lclk_rate(channel); |
2421 | ||
2422 | return r / pcd; | |
2423 | } else { | |
2424 | struct omap_dss_device *dssdev = | |
2425 | dispc_mgr_get_device(channel); | |
2426 | ||
2427 | switch (dssdev->type) { | |
2428 | case OMAP_DISPLAY_TYPE_VENC: | |
2429 | return venc_get_pixel_clock(); | |
2430 | case OMAP_DISPLAY_TYPE_HDMI: | |
2431 | return hdmi_get_pixel_clock(); | |
2432 | default: | |
2433 | BUG(); | |
2434 | } | |
2435 | } | |
80c39712 TV |
2436 | } |
2437 | ||
2438 | void dispc_dump_clocks(struct seq_file *s) | |
2439 | { | |
2440 | int lcd, pcd; | |
0cf35df3 | 2441 | u32 l; |
89a35e51 AT |
2442 | enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); |
2443 | enum omap_dss_clk_source lcd_clk_src; | |
80c39712 | 2444 | |
4fbafaf3 TV |
2445 | if (dispc_runtime_get()) |
2446 | return; | |
80c39712 | 2447 | |
80c39712 TV |
2448 | seq_printf(s, "- DISPC -\n"); |
2449 | ||
067a57e4 AT |
2450 | seq_printf(s, "dispc fclk source = %s (%s)\n", |
2451 | dss_get_generic_clk_source_name(dispc_clk_src), | |
2452 | dss_feat_get_clk_source_name(dispc_clk_src)); | |
80c39712 TV |
2453 | |
2454 | seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); | |
2a205f34 | 2455 | |
0cf35df3 MR |
2456 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { |
2457 | seq_printf(s, "- DISPC-CORE-CLK -\n"); | |
2458 | l = dispc_read_reg(DISPC_DIVISOR); | |
2459 | lcd = FLD_GET(l, 23, 16); | |
2460 | ||
2461 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
2462 | (dispc_fclk_rate()/lcd), lcd); | |
2463 | } | |
2a205f34 SS |
2464 | seq_printf(s, "- LCD1 -\n"); |
2465 | ||
ea75159e TA |
2466 | lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD); |
2467 | ||
2468 | seq_printf(s, "lcd1_clk source = %s (%s)\n", | |
2469 | dss_get_generic_clk_source_name(lcd_clk_src), | |
2470 | dss_feat_get_clk_source_name(lcd_clk_src)); | |
2471 | ||
26d9dd0d | 2472 | dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd); |
2a205f34 | 2473 | |
ff1b2cde | 2474 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", |
26d9dd0d | 2475 | dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd); |
ff1b2cde | 2476 | seq_printf(s, "pck\t\t%-16lupck div\t%u\n", |
26d9dd0d | 2477 | dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd); |
2a205f34 SS |
2478 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
2479 | seq_printf(s, "- LCD2 -\n"); | |
2480 | ||
ea75159e TA |
2481 | lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2); |
2482 | ||
2483 | seq_printf(s, "lcd2_clk source = %s (%s)\n", | |
2484 | dss_get_generic_clk_source_name(lcd_clk_src), | |
2485 | dss_feat_get_clk_source_name(lcd_clk_src)); | |
2486 | ||
26d9dd0d | 2487 | dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd); |
80c39712 | 2488 | |
2a205f34 | 2489 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", |
26d9dd0d | 2490 | dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd); |
2a205f34 | 2491 | seq_printf(s, "pck\t\t%-16lupck div\t%u\n", |
26d9dd0d | 2492 | dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd); |
2a205f34 | 2493 | } |
4fbafaf3 TV |
2494 | |
2495 | dispc_runtime_put(); | |
80c39712 TV |
2496 | } |
2497 | ||
dfc0fd8d TV |
2498 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
2499 | void dispc_dump_irqs(struct seq_file *s) | |
2500 | { | |
2501 | unsigned long flags; | |
2502 | struct dispc_irq_stats stats; | |
2503 | ||
2504 | spin_lock_irqsave(&dispc.irq_stats_lock, flags); | |
2505 | ||
2506 | stats = dispc.irq_stats; | |
2507 | memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats)); | |
2508 | dispc.irq_stats.last_reset = jiffies; | |
2509 | ||
2510 | spin_unlock_irqrestore(&dispc.irq_stats_lock, flags); | |
2511 | ||
2512 | seq_printf(s, "period %u ms\n", | |
2513 | jiffies_to_msecs(jiffies - stats.last_reset)); | |
2514 | ||
2515 | seq_printf(s, "irqs %d\n", stats.irq_count); | |
2516 | #define PIS(x) \ | |
2517 | seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]); | |
2518 | ||
2519 | PIS(FRAMEDONE); | |
2520 | PIS(VSYNC); | |
2521 | PIS(EVSYNC_EVEN); | |
2522 | PIS(EVSYNC_ODD); | |
2523 | PIS(ACBIAS_COUNT_STAT); | |
2524 | PIS(PROG_LINE_NUM); | |
2525 | PIS(GFX_FIFO_UNDERFLOW); | |
2526 | PIS(GFX_END_WIN); | |
2527 | PIS(PAL_GAMMA_MASK); | |
2528 | PIS(OCP_ERR); | |
2529 | PIS(VID1_FIFO_UNDERFLOW); | |
2530 | PIS(VID1_END_WIN); | |
2531 | PIS(VID2_FIFO_UNDERFLOW); | |
2532 | PIS(VID2_END_WIN); | |
b8c095b4 AT |
2533 | if (dss_feat_get_num_ovls() > 3) { |
2534 | PIS(VID3_FIFO_UNDERFLOW); | |
2535 | PIS(VID3_END_WIN); | |
2536 | } | |
dfc0fd8d TV |
2537 | PIS(SYNC_LOST); |
2538 | PIS(SYNC_LOST_DIGIT); | |
2539 | PIS(WAKEUP); | |
2a205f34 SS |
2540 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
2541 | PIS(FRAMEDONE2); | |
2542 | PIS(VSYNC2); | |
2543 | PIS(ACBIAS_COUNT_STAT2); | |
2544 | PIS(SYNC_LOST2); | |
2545 | } | |
dfc0fd8d TV |
2546 | #undef PIS |
2547 | } | |
dfc0fd8d TV |
2548 | #endif |
2549 | ||
80c39712 TV |
2550 | void dispc_dump_regs(struct seq_file *s) |
2551 | { | |
4dd2da15 AT |
2552 | int i, j; |
2553 | const char *mgr_names[] = { | |
2554 | [OMAP_DSS_CHANNEL_LCD] = "LCD", | |
2555 | [OMAP_DSS_CHANNEL_DIGIT] = "TV", | |
2556 | [OMAP_DSS_CHANNEL_LCD2] = "LCD2", | |
2557 | }; | |
2558 | const char *ovl_names[] = { | |
2559 | [OMAP_DSS_GFX] = "GFX", | |
2560 | [OMAP_DSS_VIDEO1] = "VID1", | |
2561 | [OMAP_DSS_VIDEO2] = "VID2", | |
b8c095b4 | 2562 | [OMAP_DSS_VIDEO3] = "VID3", |
4dd2da15 AT |
2563 | }; |
2564 | const char **p_names; | |
2565 | ||
9b372c2d | 2566 | #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) |
80c39712 | 2567 | |
4fbafaf3 TV |
2568 | if (dispc_runtime_get()) |
2569 | return; | |
80c39712 | 2570 | |
5010be80 | 2571 | /* DISPC common registers */ |
80c39712 TV |
2572 | DUMPREG(DISPC_REVISION); |
2573 | DUMPREG(DISPC_SYSCONFIG); | |
2574 | DUMPREG(DISPC_SYSSTATUS); | |
2575 | DUMPREG(DISPC_IRQSTATUS); | |
2576 | DUMPREG(DISPC_IRQENABLE); | |
2577 | DUMPREG(DISPC_CONTROL); | |
2578 | DUMPREG(DISPC_CONFIG); | |
2579 | DUMPREG(DISPC_CAPABLE); | |
80c39712 TV |
2580 | DUMPREG(DISPC_LINE_STATUS); |
2581 | DUMPREG(DISPC_LINE_NUMBER); | |
11354dd5 AT |
2582 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
2583 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 2584 | DUMPREG(DISPC_GLOBAL_ALPHA); |
2a205f34 SS |
2585 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
2586 | DUMPREG(DISPC_CONTROL2); | |
2587 | DUMPREG(DISPC_CONFIG2); | |
5010be80 AT |
2588 | } |
2589 | ||
2590 | #undef DUMPREG | |
2591 | ||
2592 | #define DISPC_REG(i, name) name(i) | |
4dd2da15 AT |
2593 | #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ |
2594 | 48 - strlen(#r) - strlen(p_names[i]), " ", \ | |
5010be80 AT |
2595 | dispc_read_reg(DISPC_REG(i, r))) |
2596 | ||
4dd2da15 | 2597 | p_names = mgr_names; |
5010be80 | 2598 | |
4dd2da15 AT |
2599 | /* DISPC channel specific registers */ |
2600 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { | |
2601 | DUMPREG(i, DISPC_DEFAULT_COLOR); | |
2602 | DUMPREG(i, DISPC_TRANS_COLOR); | |
2603 | DUMPREG(i, DISPC_SIZE_MGR); | |
80c39712 | 2604 | |
4dd2da15 AT |
2605 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
2606 | continue; | |
5010be80 | 2607 | |
4dd2da15 AT |
2608 | DUMPREG(i, DISPC_DEFAULT_COLOR); |
2609 | DUMPREG(i, DISPC_TRANS_COLOR); | |
2610 | DUMPREG(i, DISPC_TIMING_H); | |
2611 | DUMPREG(i, DISPC_TIMING_V); | |
2612 | DUMPREG(i, DISPC_POL_FREQ); | |
2613 | DUMPREG(i, DISPC_DIVISORo); | |
2614 | DUMPREG(i, DISPC_SIZE_MGR); | |
5010be80 | 2615 | |
4dd2da15 AT |
2616 | DUMPREG(i, DISPC_DATA_CYCLE1); |
2617 | DUMPREG(i, DISPC_DATA_CYCLE2); | |
2618 | DUMPREG(i, DISPC_DATA_CYCLE3); | |
2a205f34 | 2619 | |
332e9d70 | 2620 | if (dss_has_feature(FEAT_CPR)) { |
4dd2da15 AT |
2621 | DUMPREG(i, DISPC_CPR_COEF_R); |
2622 | DUMPREG(i, DISPC_CPR_COEF_G); | |
2623 | DUMPREG(i, DISPC_CPR_COEF_B); | |
332e9d70 | 2624 | } |
2a205f34 | 2625 | } |
80c39712 | 2626 | |
4dd2da15 AT |
2627 | p_names = ovl_names; |
2628 | ||
2629 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { | |
2630 | DUMPREG(i, DISPC_OVL_BA0); | |
2631 | DUMPREG(i, DISPC_OVL_BA1); | |
2632 | DUMPREG(i, DISPC_OVL_POSITION); | |
2633 | DUMPREG(i, DISPC_OVL_SIZE); | |
2634 | DUMPREG(i, DISPC_OVL_ATTRIBUTES); | |
2635 | DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); | |
2636 | DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); | |
2637 | DUMPREG(i, DISPC_OVL_ROW_INC); | |
2638 | DUMPREG(i, DISPC_OVL_PIXEL_INC); | |
2639 | if (dss_has_feature(FEAT_PRELOAD)) | |
2640 | DUMPREG(i, DISPC_OVL_PRELOAD); | |
2641 | ||
2642 | if (i == OMAP_DSS_GFX) { | |
2643 | DUMPREG(i, DISPC_OVL_WINDOW_SKIP); | |
2644 | DUMPREG(i, DISPC_OVL_TABLE_BA); | |
2645 | continue; | |
2646 | } | |
2647 | ||
2648 | DUMPREG(i, DISPC_OVL_FIR); | |
2649 | DUMPREG(i, DISPC_OVL_PICTURE_SIZE); | |
2650 | DUMPREG(i, DISPC_OVL_ACCU0); | |
2651 | DUMPREG(i, DISPC_OVL_ACCU1); | |
2652 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
2653 | DUMPREG(i, DISPC_OVL_BA0_UV); | |
2654 | DUMPREG(i, DISPC_OVL_BA1_UV); | |
2655 | DUMPREG(i, DISPC_OVL_FIR2); | |
2656 | DUMPREG(i, DISPC_OVL_ACCU2_0); | |
2657 | DUMPREG(i, DISPC_OVL_ACCU2_1); | |
2658 | } | |
2659 | if (dss_has_feature(FEAT_ATTR2)) | |
2660 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); | |
2661 | if (dss_has_feature(FEAT_PRELOAD)) | |
2662 | DUMPREG(i, DISPC_OVL_PRELOAD); | |
ab5ca071 | 2663 | } |
5010be80 AT |
2664 | |
2665 | #undef DISPC_REG | |
2666 | #undef DUMPREG | |
2667 | ||
2668 | #define DISPC_REG(plane, name, i) name(plane, i) | |
2669 | #define DUMPREG(plane, name, i) \ | |
4dd2da15 AT |
2670 | seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ |
2671 | 46 - strlen(#name) - strlen(p_names[plane]), " ", \ | |
5010be80 AT |
2672 | dispc_read_reg(DISPC_REG(plane, name, i))) |
2673 | ||
4dd2da15 | 2674 | /* Video pipeline coefficient registers */ |
332e9d70 | 2675 | |
4dd2da15 AT |
2676 | /* start from OMAP_DSS_VIDEO1 */ |
2677 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { | |
2678 | for (j = 0; j < 8; j++) | |
2679 | DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); | |
9b372c2d | 2680 | |
4dd2da15 AT |
2681 | for (j = 0; j < 8; j++) |
2682 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); | |
5010be80 | 2683 | |
4dd2da15 AT |
2684 | for (j = 0; j < 5; j++) |
2685 | DUMPREG(i, DISPC_OVL_CONV_COEF, j); | |
ab5ca071 | 2686 | |
4dd2da15 AT |
2687 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
2688 | for (j = 0; j < 8; j++) | |
2689 | DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); | |
2690 | } | |
2691 | ||
2692 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
2693 | for (j = 0; j < 8; j++) | |
2694 | DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); | |
2695 | ||
2696 | for (j = 0; j < 8; j++) | |
2697 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); | |
2698 | ||
2699 | for (j = 0; j < 8; j++) | |
2700 | DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); | |
2701 | } | |
332e9d70 | 2702 | } |
80c39712 | 2703 | |
4fbafaf3 | 2704 | dispc_runtime_put(); |
5010be80 AT |
2705 | |
2706 | #undef DISPC_REG | |
80c39712 TV |
2707 | #undef DUMPREG |
2708 | } | |
2709 | ||
26d9dd0d TV |
2710 | static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff, |
2711 | bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, | |
2712 | u8 acb) | |
80c39712 TV |
2713 | { |
2714 | u32 l = 0; | |
2715 | ||
2716 | DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n", | |
2717 | onoff, rf, ieo, ipc, ihs, ivs, acbi, acb); | |
2718 | ||
2719 | l |= FLD_VAL(onoff, 17, 17); | |
2720 | l |= FLD_VAL(rf, 16, 16); | |
2721 | l |= FLD_VAL(ieo, 15, 15); | |
2722 | l |= FLD_VAL(ipc, 14, 14); | |
2723 | l |= FLD_VAL(ihs, 13, 13); | |
2724 | l |= FLD_VAL(ivs, 12, 12); | |
2725 | l |= FLD_VAL(acbi, 11, 8); | |
2726 | l |= FLD_VAL(acb, 7, 0); | |
2727 | ||
ff1b2cde | 2728 | dispc_write_reg(DISPC_POL_FREQ(channel), l); |
80c39712 TV |
2729 | } |
2730 | ||
26d9dd0d | 2731 | void dispc_mgr_set_pol_freq(enum omap_channel channel, |
ff1b2cde | 2732 | enum omap_panel_config config, u8 acbi, u8 acb) |
80c39712 | 2733 | { |
26d9dd0d | 2734 | _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0, |
80c39712 TV |
2735 | (config & OMAP_DSS_LCD_RF) != 0, |
2736 | (config & OMAP_DSS_LCD_IEO) != 0, | |
2737 | (config & OMAP_DSS_LCD_IPC) != 0, | |
2738 | (config & OMAP_DSS_LCD_IHS) != 0, | |
2739 | (config & OMAP_DSS_LCD_IVS) != 0, | |
2740 | acbi, acb); | |
2741 | } | |
2742 | ||
2743 | /* with fck as input clock rate, find dispc dividers that produce req_pck */ | |
2744 | void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck, | |
2745 | struct dispc_clock_info *cinfo) | |
2746 | { | |
9eaaf207 | 2747 | u16 pcd_min, pcd_max; |
80c39712 TV |
2748 | unsigned long best_pck; |
2749 | u16 best_ld, cur_ld; | |
2750 | u16 best_pd, cur_pd; | |
2751 | ||
9eaaf207 TV |
2752 | pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); |
2753 | pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); | |
2754 | ||
2755 | if (!is_tft) | |
2756 | pcd_min = 3; | |
2757 | ||
80c39712 TV |
2758 | best_pck = 0; |
2759 | best_ld = 0; | |
2760 | best_pd = 0; | |
2761 | ||
2762 | for (cur_ld = 1; cur_ld <= 255; ++cur_ld) { | |
2763 | unsigned long lck = fck / cur_ld; | |
2764 | ||
9eaaf207 | 2765 | for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) { |
80c39712 TV |
2766 | unsigned long pck = lck / cur_pd; |
2767 | long old_delta = abs(best_pck - req_pck); | |
2768 | long new_delta = abs(pck - req_pck); | |
2769 | ||
2770 | if (best_pck == 0 || new_delta < old_delta) { | |
2771 | best_pck = pck; | |
2772 | best_ld = cur_ld; | |
2773 | best_pd = cur_pd; | |
2774 | ||
2775 | if (pck == req_pck) | |
2776 | goto found; | |
2777 | } | |
2778 | ||
2779 | if (pck < req_pck) | |
2780 | break; | |
2781 | } | |
2782 | ||
2783 | if (lck / pcd_min < req_pck) | |
2784 | break; | |
2785 | } | |
2786 | ||
2787 | found: | |
2788 | cinfo->lck_div = best_ld; | |
2789 | cinfo->pck_div = best_pd; | |
2790 | cinfo->lck = fck / cinfo->lck_div; | |
2791 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
2792 | } | |
2793 | ||
2794 | /* calculate clock rates using dividers in cinfo */ | |
2795 | int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, | |
2796 | struct dispc_clock_info *cinfo) | |
2797 | { | |
2798 | if (cinfo->lck_div > 255 || cinfo->lck_div == 0) | |
2799 | return -EINVAL; | |
9eaaf207 | 2800 | if (cinfo->pck_div < 1 || cinfo->pck_div > 255) |
80c39712 TV |
2801 | return -EINVAL; |
2802 | ||
2803 | cinfo->lck = dispc_fclk_rate / cinfo->lck_div; | |
2804 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
2805 | ||
2806 | return 0; | |
2807 | } | |
2808 | ||
26d9dd0d | 2809 | int dispc_mgr_set_clock_div(enum omap_channel channel, |
ff1b2cde | 2810 | struct dispc_clock_info *cinfo) |
80c39712 TV |
2811 | { |
2812 | DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); | |
2813 | DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); | |
2814 | ||
26d9dd0d | 2815 | dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); |
80c39712 TV |
2816 | |
2817 | return 0; | |
2818 | } | |
2819 | ||
26d9dd0d | 2820 | int dispc_mgr_get_clock_div(enum omap_channel channel, |
ff1b2cde | 2821 | struct dispc_clock_info *cinfo) |
80c39712 TV |
2822 | { |
2823 | unsigned long fck; | |
2824 | ||
2825 | fck = dispc_fclk_rate(); | |
2826 | ||
ce7fa5eb MR |
2827 | cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); |
2828 | cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); | |
80c39712 TV |
2829 | |
2830 | cinfo->lck = fck / cinfo->lck_div; | |
2831 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
2832 | ||
2833 | return 0; | |
2834 | } | |
2835 | ||
2836 | /* dispc.irq_lock has to be locked by the caller */ | |
2837 | static void _omap_dispc_set_irqs(void) | |
2838 | { | |
2839 | u32 mask; | |
2840 | u32 old_mask; | |
2841 | int i; | |
2842 | struct omap_dispc_isr_data *isr_data; | |
2843 | ||
2844 | mask = dispc.irq_error_mask; | |
2845 | ||
2846 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
2847 | isr_data = &dispc.registered_isr[i]; | |
2848 | ||
2849 | if (isr_data->isr == NULL) | |
2850 | continue; | |
2851 | ||
2852 | mask |= isr_data->mask; | |
2853 | } | |
2854 | ||
80c39712 TV |
2855 | old_mask = dispc_read_reg(DISPC_IRQENABLE); |
2856 | /* clear the irqstatus for newly enabled irqs */ | |
2857 | dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask); | |
2858 | ||
2859 | dispc_write_reg(DISPC_IRQENABLE, mask); | |
80c39712 TV |
2860 | } |
2861 | ||
2862 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) | |
2863 | { | |
2864 | int i; | |
2865 | int ret; | |
2866 | unsigned long flags; | |
2867 | struct omap_dispc_isr_data *isr_data; | |
2868 | ||
2869 | if (isr == NULL) | |
2870 | return -EINVAL; | |
2871 | ||
2872 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
2873 | ||
2874 | /* check for duplicate entry */ | |
2875 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
2876 | isr_data = &dispc.registered_isr[i]; | |
2877 | if (isr_data->isr == isr && isr_data->arg == arg && | |
2878 | isr_data->mask == mask) { | |
2879 | ret = -EINVAL; | |
2880 | goto err; | |
2881 | } | |
2882 | } | |
2883 | ||
2884 | isr_data = NULL; | |
2885 | ret = -EBUSY; | |
2886 | ||
2887 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
2888 | isr_data = &dispc.registered_isr[i]; | |
2889 | ||
2890 | if (isr_data->isr != NULL) | |
2891 | continue; | |
2892 | ||
2893 | isr_data->isr = isr; | |
2894 | isr_data->arg = arg; | |
2895 | isr_data->mask = mask; | |
2896 | ret = 0; | |
2897 | ||
2898 | break; | |
2899 | } | |
2900 | ||
b9cb0984 TV |
2901 | if (ret) |
2902 | goto err; | |
2903 | ||
80c39712 TV |
2904 | _omap_dispc_set_irqs(); |
2905 | ||
2906 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
2907 | ||
2908 | return 0; | |
2909 | err: | |
2910 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
2911 | ||
2912 | return ret; | |
2913 | } | |
2914 | EXPORT_SYMBOL(omap_dispc_register_isr); | |
2915 | ||
2916 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) | |
2917 | { | |
2918 | int i; | |
2919 | unsigned long flags; | |
2920 | int ret = -EINVAL; | |
2921 | struct omap_dispc_isr_data *isr_data; | |
2922 | ||
2923 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
2924 | ||
2925 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
2926 | isr_data = &dispc.registered_isr[i]; | |
2927 | if (isr_data->isr != isr || isr_data->arg != arg || | |
2928 | isr_data->mask != mask) | |
2929 | continue; | |
2930 | ||
2931 | /* found the correct isr */ | |
2932 | ||
2933 | isr_data->isr = NULL; | |
2934 | isr_data->arg = NULL; | |
2935 | isr_data->mask = 0; | |
2936 | ||
2937 | ret = 0; | |
2938 | break; | |
2939 | } | |
2940 | ||
2941 | if (ret == 0) | |
2942 | _omap_dispc_set_irqs(); | |
2943 | ||
2944 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
2945 | ||
2946 | return ret; | |
2947 | } | |
2948 | EXPORT_SYMBOL(omap_dispc_unregister_isr); | |
2949 | ||
2950 | #ifdef DEBUG | |
2951 | static void print_irq_status(u32 status) | |
2952 | { | |
2953 | if ((status & dispc.irq_error_mask) == 0) | |
2954 | return; | |
2955 | ||
2956 | printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status); | |
2957 | ||
2958 | #define PIS(x) \ | |
2959 | if (status & DISPC_IRQ_##x) \ | |
2960 | printk(#x " "); | |
2961 | PIS(GFX_FIFO_UNDERFLOW); | |
2962 | PIS(OCP_ERR); | |
2963 | PIS(VID1_FIFO_UNDERFLOW); | |
2964 | PIS(VID2_FIFO_UNDERFLOW); | |
b8c095b4 AT |
2965 | if (dss_feat_get_num_ovls() > 3) |
2966 | PIS(VID3_FIFO_UNDERFLOW); | |
80c39712 TV |
2967 | PIS(SYNC_LOST); |
2968 | PIS(SYNC_LOST_DIGIT); | |
2a205f34 SS |
2969 | if (dss_has_feature(FEAT_MGR_LCD2)) |
2970 | PIS(SYNC_LOST2); | |
80c39712 TV |
2971 | #undef PIS |
2972 | ||
2973 | printk("\n"); | |
2974 | } | |
2975 | #endif | |
2976 | ||
2977 | /* Called from dss.c. Note that we don't touch clocks here, | |
2978 | * but we presume they are on because we got an IRQ. However, | |
2979 | * an irq handler may turn the clocks off, so we may not have | |
2980 | * clock later in the function. */ | |
affe360d | 2981 | static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) |
80c39712 TV |
2982 | { |
2983 | int i; | |
affe360d | 2984 | u32 irqstatus, irqenable; |
80c39712 TV |
2985 | u32 handledirqs = 0; |
2986 | u32 unhandled_errors; | |
2987 | struct omap_dispc_isr_data *isr_data; | |
2988 | struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; | |
2989 | ||
2990 | spin_lock(&dispc.irq_lock); | |
2991 | ||
2992 | irqstatus = dispc_read_reg(DISPC_IRQSTATUS); | |
affe360d | 2993 | irqenable = dispc_read_reg(DISPC_IRQENABLE); |
2994 | ||
2995 | /* IRQ is not for us */ | |
2996 | if (!(irqstatus & irqenable)) { | |
2997 | spin_unlock(&dispc.irq_lock); | |
2998 | return IRQ_NONE; | |
2999 | } | |
80c39712 | 3000 | |
dfc0fd8d TV |
3001 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
3002 | spin_lock(&dispc.irq_stats_lock); | |
3003 | dispc.irq_stats.irq_count++; | |
3004 | dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs); | |
3005 | spin_unlock(&dispc.irq_stats_lock); | |
3006 | #endif | |
3007 | ||
80c39712 TV |
3008 | #ifdef DEBUG |
3009 | if (dss_debug) | |
3010 | print_irq_status(irqstatus); | |
3011 | #endif | |
3012 | /* Ack the interrupt. Do it here before clocks are possibly turned | |
3013 | * off */ | |
3014 | dispc_write_reg(DISPC_IRQSTATUS, irqstatus); | |
3015 | /* flush posted write */ | |
3016 | dispc_read_reg(DISPC_IRQSTATUS); | |
3017 | ||
3018 | /* make a copy and unlock, so that isrs can unregister | |
3019 | * themselves */ | |
3020 | memcpy(registered_isr, dispc.registered_isr, | |
3021 | sizeof(registered_isr)); | |
3022 | ||
3023 | spin_unlock(&dispc.irq_lock); | |
3024 | ||
3025 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
3026 | isr_data = ®istered_isr[i]; | |
3027 | ||
3028 | if (!isr_data->isr) | |
3029 | continue; | |
3030 | ||
3031 | if (isr_data->mask & irqstatus) { | |
3032 | isr_data->isr(isr_data->arg, irqstatus); | |
3033 | handledirqs |= isr_data->mask; | |
3034 | } | |
3035 | } | |
3036 | ||
3037 | spin_lock(&dispc.irq_lock); | |
3038 | ||
3039 | unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask; | |
3040 | ||
3041 | if (unhandled_errors) { | |
3042 | dispc.error_irqs |= unhandled_errors; | |
3043 | ||
3044 | dispc.irq_error_mask &= ~unhandled_errors; | |
3045 | _omap_dispc_set_irqs(); | |
3046 | ||
3047 | schedule_work(&dispc.error_work); | |
3048 | } | |
3049 | ||
3050 | spin_unlock(&dispc.irq_lock); | |
affe360d | 3051 | |
3052 | return IRQ_HANDLED; | |
80c39712 TV |
3053 | } |
3054 | ||
3055 | static void dispc_error_worker(struct work_struct *work) | |
3056 | { | |
3057 | int i; | |
3058 | u32 errors; | |
3059 | unsigned long flags; | |
fe3cc9d6 TV |
3060 | static const unsigned fifo_underflow_bits[] = { |
3061 | DISPC_IRQ_GFX_FIFO_UNDERFLOW, | |
3062 | DISPC_IRQ_VID1_FIFO_UNDERFLOW, | |
3063 | DISPC_IRQ_VID2_FIFO_UNDERFLOW, | |
b8c095b4 | 3064 | DISPC_IRQ_VID3_FIFO_UNDERFLOW, |
fe3cc9d6 TV |
3065 | }; |
3066 | ||
3067 | static const unsigned sync_lost_bits[] = { | |
3068 | DISPC_IRQ_SYNC_LOST, | |
3069 | DISPC_IRQ_SYNC_LOST_DIGIT, | |
3070 | DISPC_IRQ_SYNC_LOST2, | |
3071 | }; | |
80c39712 TV |
3072 | |
3073 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
3074 | errors = dispc.error_irqs; | |
3075 | dispc.error_irqs = 0; | |
3076 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
3077 | ||
13eae1f9 DZ |
3078 | dispc_runtime_get(); |
3079 | ||
fe3cc9d6 TV |
3080 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) { |
3081 | struct omap_overlay *ovl; | |
3082 | unsigned bit; | |
80c39712 | 3083 | |
fe3cc9d6 TV |
3084 | ovl = omap_dss_get_overlay(i); |
3085 | bit = fifo_underflow_bits[i]; | |
80c39712 | 3086 | |
fe3cc9d6 TV |
3087 | if (bit & errors) { |
3088 | DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n", | |
3089 | ovl->name); | |
f0e5caab | 3090 | dispc_ovl_enable(ovl->id, false); |
26d9dd0d | 3091 | dispc_mgr_go(ovl->manager->id); |
80c39712 | 3092 | mdelay(50); |
80c39712 TV |
3093 | } |
3094 | } | |
3095 | ||
fe3cc9d6 TV |
3096 | for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { |
3097 | struct omap_overlay_manager *mgr; | |
3098 | unsigned bit; | |
80c39712 | 3099 | |
fe3cc9d6 TV |
3100 | mgr = omap_dss_get_overlay_manager(i); |
3101 | bit = sync_lost_bits[i]; | |
80c39712 | 3102 | |
fe3cc9d6 TV |
3103 | if (bit & errors) { |
3104 | struct omap_dss_device *dssdev = mgr->device; | |
3105 | bool enable; | |
80c39712 | 3106 | |
fe3cc9d6 TV |
3107 | DSSERR("SYNC_LOST on channel %s, restarting the output " |
3108 | "with video overlays disabled\n", | |
3109 | mgr->name); | |
2a205f34 | 3110 | |
fe3cc9d6 TV |
3111 | enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; |
3112 | dssdev->driver->disable(dssdev); | |
2a205f34 | 3113 | |
2a205f34 SS |
3114 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) { |
3115 | struct omap_overlay *ovl; | |
3116 | ovl = omap_dss_get_overlay(i); | |
3117 | ||
fe3cc9d6 TV |
3118 | if (ovl->id != OMAP_DSS_GFX && |
3119 | ovl->manager == mgr) | |
f0e5caab | 3120 | dispc_ovl_enable(ovl->id, false); |
2a205f34 SS |
3121 | } |
3122 | ||
26d9dd0d | 3123 | dispc_mgr_go(mgr->id); |
2a205f34 | 3124 | mdelay(50); |
fe3cc9d6 | 3125 | |
2a205f34 SS |
3126 | if (enable) |
3127 | dssdev->driver->enable(dssdev); | |
3128 | } | |
3129 | } | |
3130 | ||
80c39712 TV |
3131 | if (errors & DISPC_IRQ_OCP_ERR) { |
3132 | DSSERR("OCP_ERR\n"); | |
3133 | for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { | |
3134 | struct omap_overlay_manager *mgr; | |
3135 | mgr = omap_dss_get_overlay_manager(i); | |
00f17e45 RC |
3136 | if (mgr->device && mgr->device->driver) |
3137 | mgr->device->driver->disable(mgr->device); | |
80c39712 TV |
3138 | } |
3139 | } | |
3140 | ||
3141 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
3142 | dispc.irq_error_mask |= errors; | |
3143 | _omap_dispc_set_irqs(); | |
3144 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
13eae1f9 DZ |
3145 | |
3146 | dispc_runtime_put(); | |
80c39712 TV |
3147 | } |
3148 | ||
3149 | int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout) | |
3150 | { | |
3151 | void dispc_irq_wait_handler(void *data, u32 mask) | |
3152 | { | |
3153 | complete((struct completion *)data); | |
3154 | } | |
3155 | ||
3156 | int r; | |
3157 | DECLARE_COMPLETION_ONSTACK(completion); | |
3158 | ||
3159 | r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, | |
3160 | irqmask); | |
3161 | ||
3162 | if (r) | |
3163 | return r; | |
3164 | ||
3165 | timeout = wait_for_completion_timeout(&completion, timeout); | |
3166 | ||
3167 | omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); | |
3168 | ||
3169 | if (timeout == 0) | |
3170 | return -ETIMEDOUT; | |
3171 | ||
3172 | if (timeout == -ERESTARTSYS) | |
3173 | return -ERESTARTSYS; | |
3174 | ||
3175 | return 0; | |
3176 | } | |
3177 | ||
3178 | int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, | |
3179 | unsigned long timeout) | |
3180 | { | |
3181 | void dispc_irq_wait_handler(void *data, u32 mask) | |
3182 | { | |
3183 | complete((struct completion *)data); | |
3184 | } | |
3185 | ||
3186 | int r; | |
3187 | DECLARE_COMPLETION_ONSTACK(completion); | |
3188 | ||
3189 | r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, | |
3190 | irqmask); | |
3191 | ||
3192 | if (r) | |
3193 | return r; | |
3194 | ||
3195 | timeout = wait_for_completion_interruptible_timeout(&completion, | |
3196 | timeout); | |
3197 | ||
3198 | omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); | |
3199 | ||
3200 | if (timeout == 0) | |
3201 | return -ETIMEDOUT; | |
3202 | ||
3203 | if (timeout == -ERESTARTSYS) | |
3204 | return -ERESTARTSYS; | |
3205 | ||
3206 | return 0; | |
3207 | } | |
3208 | ||
3209 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC | |
3210 | void dispc_fake_vsync_irq(void) | |
3211 | { | |
3212 | u32 irqstatus = DISPC_IRQ_VSYNC; | |
3213 | int i; | |
3214 | ||
ab83b14c | 3215 | WARN_ON(!in_interrupt()); |
80c39712 TV |
3216 | |
3217 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
3218 | struct omap_dispc_isr_data *isr_data; | |
3219 | isr_data = &dispc.registered_isr[i]; | |
3220 | ||
3221 | if (!isr_data->isr) | |
3222 | continue; | |
3223 | ||
3224 | if (isr_data->mask & irqstatus) | |
3225 | isr_data->isr(isr_data->arg, irqstatus); | |
3226 | } | |
80c39712 TV |
3227 | } |
3228 | #endif | |
3229 | ||
3230 | static void _omap_dispc_initialize_irq(void) | |
3231 | { | |
3232 | unsigned long flags; | |
3233 | ||
3234 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
3235 | ||
3236 | memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr)); | |
3237 | ||
3238 | dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR; | |
2a205f34 SS |
3239 | if (dss_has_feature(FEAT_MGR_LCD2)) |
3240 | dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2; | |
b8c095b4 AT |
3241 | if (dss_feat_get_num_ovls() > 3) |
3242 | dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW; | |
80c39712 TV |
3243 | |
3244 | /* there's SYNC_LOST_DIGIT waiting after enabling the DSS, | |
3245 | * so clear it */ | |
3246 | dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS)); | |
3247 | ||
3248 | _omap_dispc_set_irqs(); | |
3249 | ||
3250 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
3251 | } | |
3252 | ||
3253 | void dispc_enable_sidle(void) | |
3254 | { | |
3255 | REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ | |
3256 | } | |
3257 | ||
3258 | void dispc_disable_sidle(void) | |
3259 | { | |
3260 | REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ | |
3261 | } | |
3262 | ||
3263 | static void _omap_dispc_initial_config(void) | |
3264 | { | |
3265 | u32 l; | |
3266 | ||
0cf35df3 MR |
3267 | /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ |
3268 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { | |
3269 | l = dispc_read_reg(DISPC_DIVISOR); | |
3270 | /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ | |
3271 | l = FLD_MOD(l, 1, 0, 0); | |
3272 | l = FLD_MOD(l, 1, 23, 16); | |
3273 | dispc_write_reg(DISPC_DIVISOR, l); | |
3274 | } | |
3275 | ||
80c39712 | 3276 | /* FUNCGATED */ |
6ced40bf AT |
3277 | if (dss_has_feature(FEAT_FUNCGATED)) |
3278 | REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); | |
80c39712 TV |
3279 | |
3280 | /* L3 firewall setting: enable access to OCM RAM */ | |
3281 | /* XXX this should be somewhere in plat-omap */ | |
3282 | if (cpu_is_omap24xx()) | |
3283 | __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0)); | |
3284 | ||
3285 | _dispc_setup_color_conv_coef(); | |
3286 | ||
3287 | dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); | |
3288 | ||
3289 | dispc_read_plane_fifo_sizes(); | |
5ed8cf5b TV |
3290 | |
3291 | dispc_configure_burst_sizes(); | |
54128701 AT |
3292 | |
3293 | dispc_ovl_enable_zorder_planes(); | |
80c39712 TV |
3294 | } |
3295 | ||
060b6d9c SG |
3296 | /* DISPC HW IP initialisation */ |
3297 | static int omap_dispchw_probe(struct platform_device *pdev) | |
3298 | { | |
3299 | u32 rev; | |
affe360d | 3300 | int r = 0; |
ea9da36a | 3301 | struct resource *dispc_mem; |
4fbafaf3 | 3302 | struct clk *clk; |
ea9da36a | 3303 | |
060b6d9c SG |
3304 | dispc.pdev = pdev; |
3305 | ||
4fbafaf3 TV |
3306 | clk = clk_get(&pdev->dev, "fck"); |
3307 | if (IS_ERR(clk)) { | |
3308 | DSSERR("can't get fck\n"); | |
3309 | r = PTR_ERR(clk); | |
3310 | goto err_get_clk; | |
3311 | } | |
3312 | ||
3313 | dispc.dss_clk = clk; | |
3314 | ||
060b6d9c SG |
3315 | spin_lock_init(&dispc.irq_lock); |
3316 | ||
3317 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
3318 | spin_lock_init(&dispc.irq_stats_lock); | |
3319 | dispc.irq_stats.last_reset = jiffies; | |
3320 | #endif | |
3321 | ||
3322 | INIT_WORK(&dispc.error_work, dispc_error_worker); | |
3323 | ||
ea9da36a SG |
3324 | dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); |
3325 | if (!dispc_mem) { | |
3326 | DSSERR("can't get IORESOURCE_MEM DISPC\n"); | |
affe360d | 3327 | r = -EINVAL; |
4fbafaf3 | 3328 | goto err_ioremap; |
ea9da36a SG |
3329 | } |
3330 | dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem)); | |
060b6d9c SG |
3331 | if (!dispc.base) { |
3332 | DSSERR("can't ioremap DISPC\n"); | |
affe360d | 3333 | r = -ENOMEM; |
4fbafaf3 | 3334 | goto err_ioremap; |
affe360d | 3335 | } |
3336 | dispc.irq = platform_get_irq(dispc.pdev, 0); | |
3337 | if (dispc.irq < 0) { | |
3338 | DSSERR("platform_get_irq failed\n"); | |
3339 | r = -ENODEV; | |
4fbafaf3 | 3340 | goto err_irq; |
affe360d | 3341 | } |
3342 | ||
3343 | r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED, | |
3344 | "OMAP DISPC", dispc.pdev); | |
3345 | if (r < 0) { | |
3346 | DSSERR("request_irq failed\n"); | |
4fbafaf3 | 3347 | goto err_irq; |
060b6d9c SG |
3348 | } |
3349 | ||
4fbafaf3 TV |
3350 | pm_runtime_enable(&pdev->dev); |
3351 | ||
3352 | r = dispc_runtime_get(); | |
3353 | if (r) | |
3354 | goto err_runtime_get; | |
060b6d9c SG |
3355 | |
3356 | _omap_dispc_initial_config(); | |
3357 | ||
3358 | _omap_dispc_initialize_irq(); | |
3359 | ||
060b6d9c | 3360 | rev = dispc_read_reg(DISPC_REVISION); |
a06b62f8 | 3361 | dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", |
060b6d9c SG |
3362 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
3363 | ||
4fbafaf3 | 3364 | dispc_runtime_put(); |
060b6d9c SG |
3365 | |
3366 | return 0; | |
4fbafaf3 TV |
3367 | |
3368 | err_runtime_get: | |
3369 | pm_runtime_disable(&pdev->dev); | |
3370 | free_irq(dispc.irq, dispc.pdev); | |
3371 | err_irq: | |
affe360d | 3372 | iounmap(dispc.base); |
4fbafaf3 TV |
3373 | err_ioremap: |
3374 | clk_put(dispc.dss_clk); | |
3375 | err_get_clk: | |
affe360d | 3376 | return r; |
060b6d9c SG |
3377 | } |
3378 | ||
3379 | static int omap_dispchw_remove(struct platform_device *pdev) | |
3380 | { | |
4fbafaf3 TV |
3381 | pm_runtime_disable(&pdev->dev); |
3382 | ||
3383 | clk_put(dispc.dss_clk); | |
3384 | ||
affe360d | 3385 | free_irq(dispc.irq, dispc.pdev); |
060b6d9c SG |
3386 | iounmap(dispc.base); |
3387 | return 0; | |
3388 | } | |
3389 | ||
4fbafaf3 TV |
3390 | static int dispc_runtime_suspend(struct device *dev) |
3391 | { | |
3392 | dispc_save_context(); | |
4fbafaf3 TV |
3393 | dss_runtime_put(); |
3394 | ||
3395 | return 0; | |
3396 | } | |
3397 | ||
3398 | static int dispc_runtime_resume(struct device *dev) | |
3399 | { | |
3400 | int r; | |
3401 | ||
3402 | r = dss_runtime_get(); | |
3403 | if (r < 0) | |
3404 | return r; | |
3405 | ||
49ea86f3 | 3406 | dispc_restore_context(); |
4fbafaf3 TV |
3407 | |
3408 | return 0; | |
3409 | } | |
3410 | ||
3411 | static const struct dev_pm_ops dispc_pm_ops = { | |
3412 | .runtime_suspend = dispc_runtime_suspend, | |
3413 | .runtime_resume = dispc_runtime_resume, | |
3414 | }; | |
3415 | ||
060b6d9c SG |
3416 | static struct platform_driver omap_dispchw_driver = { |
3417 | .probe = omap_dispchw_probe, | |
3418 | .remove = omap_dispchw_remove, | |
3419 | .driver = { | |
3420 | .name = "omapdss_dispc", | |
3421 | .owner = THIS_MODULE, | |
4fbafaf3 | 3422 | .pm = &dispc_pm_ops, |
060b6d9c SG |
3423 | }, |
3424 | }; | |
3425 | ||
3426 | int dispc_init_platform_driver(void) | |
3427 | { | |
3428 | return platform_driver_register(&omap_dispchw_driver); | |
3429 | } | |
3430 | ||
3431 | void dispc_uninit_platform_driver(void) | |
3432 | { | |
3433 | return platform_driver_unregister(&omap_dispchw_driver); | |
3434 | } |