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OMAP: DSS2: DISPC: Prepare dispc_dump_regs() for shortening
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
80c39712
TV		 38
39#include <plat/sram.h>
40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
66be8f6c
GI		 66struct dispc_h_coef {
67 s8 hc4;
68 s8 hc3;
69 u8 hc2;
70 s8 hc1;
71 s8 hc0;
72};
73
74struct dispc_v_coef {
75 s8 vc22;
76 s8 vc2;
77 u8 vc1;
78 s8 vc0;
79 s8 vc00;
80};
81
5ed8cf5b
TV		 82enum omap_burst_size {
83 BURST_SIZE_X2 = 0,
84 BURST_SIZE_X4 = 1,
85 BURST_SIZE_X8 = 2,
86};
87
80c39712
TV		 88#define REG_GET(idx, start, end) \
89 FLD_GET(dispc_read_reg(idx), start, end)
90
91#define REG_FLD_MOD(idx, val, start, end) \
92 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
93
dfc0fd8d
TV		 94struct dispc_irq_stats {
95 unsigned long last_reset;
96 unsigned irq_count;
97 unsigned irqs[32];
98};
99
80c39712 100static struct {
060b6d9c 101 struct platform_device *pdev;
80c39712 102 void __iomem *base;
4fbafaf3
TV		 103
104 int ctx_loss_cnt;
105
affe360d 106 int irq;
4fbafaf3 107 struct clk *dss_clk;
80c39712
TV		 108
109 u32 fifo_size[3];
110
111 spinlock_t irq_lock;
112 u32 irq_error_mask;
113 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
114 u32 error_irqs;
115 struct work_struct error_work;
116
49ea86f3 117 bool ctx_valid;
80c39712 118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 119
120#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
121 spinlock_t irq_stats_lock;
122 struct dispc_irq_stats irq_stats;
123#endif
80c39712
TV		 124} dispc;
125
0d66cbb5
AJ		 126enum omap_color_component {
127 /* used for all color formats for OMAP3 and earlier
128 * and for RGB and Y color component on OMAP4
129 */
130 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
131 /* used for UV component for
132 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
133 * color formats on OMAP4
134 */
135 DISPC_COLOR_COMPONENT_UV = 1 << 1,
136};
137
80c39712
TV		 138static void _omap_dispc_set_irqs(void);
139
55978cc2 140static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 141{
55978cc2 142 __raw_writel(val, dispc.base + idx);
80c39712
TV		 143}
144
55978cc2 145static inline u32 dispc_read_reg(const u16 idx)
80c39712 146{
55978cc2 147 return __raw_readl(dispc.base + idx);
80c39712
TV		 148}
149
49ea86f3
TV		 150static int dispc_get_ctx_loss_count(void)
151{
152 struct device *dev = &dispc.pdev->dev;
153 struct omap_display_platform_data *pdata = dev->platform_data;
154 struct omap_dss_board_info *board_data = pdata->board_data;
155 int cnt;
156
157 if (!board_data->get_context_loss_count)
158 return -ENOENT;
159
160 cnt = board_data->get_context_loss_count(dev);
161
162 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
163
164 return cnt;
165}
166
80c39712 167#define SR(reg) \
55978cc2 168 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 169#define RR(reg) \
55978cc2 170 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 171
4fbafaf3 172static void dispc_save_context(void)
80c39712 173{
5719d35c 174 int i;
80c39712 175
4fbafaf3
TV		 176 DSSDBG("dispc_save_context\n");
177
80c39712
TV		 178 SR(IRQENABLE);
179 SR(CONTROL);
180 SR(CONFIG);
702d1448
AT		 181 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
182 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
183 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
184 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712 185 SR(LINE_NUMBER);
702d1448
AT		 186 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
187 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
188 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
189 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
332e9d70
TV		 190 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
191 SR(GLOBAL_ALPHA);
702d1448
AT		 192 SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
193 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34
SS		 194 if (dss_has_feature(FEAT_MGR_LCD2)) {
195 SR(CONTROL2);
702d1448
AT		 196 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
197 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
198 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
199 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
200 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
201 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
202 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2a205f34
SS		 203 SR(CONFIG2);
204 }
80c39712 205
9b372c2d
AT		 206 SR(OVL_BA0(OMAP_DSS_GFX));
207 SR(OVL_BA1(OMAP_DSS_GFX));
208 SR(OVL_POSITION(OMAP_DSS_GFX));
209 SR(OVL_SIZE(OMAP_DSS_GFX));
210 SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
211 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
212 SR(OVL_ROW_INC(OMAP_DSS_GFX));
213 SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
214 SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
215 SR(OVL_TABLE_BA(OMAP_DSS_GFX));
80c39712 216
702d1448
AT		 217 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
218 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
219 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 220
332e9d70
TV		 221 if (dss_has_feature(FEAT_CPR)) {
222 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
223 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
224 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
225 }
2a205f34 226 if (dss_has_feature(FEAT_MGR_LCD2)) {
332e9d70
TV		 227 if (dss_has_feature(FEAT_CPR)) {
228 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
229 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
230 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
231 }
2a205f34 232
702d1448
AT		 233 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
234 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
235 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 236 }
80c39712 237
332e9d70
TV		 238 if (dss_has_feature(FEAT_PRELOAD))
239 SR(OVL_PRELOAD(OMAP_DSS_GFX));
80c39712
TV		 240
241 /* VID1 */
9b372c2d
AT		 242 SR(OVL_BA0(OMAP_DSS_VIDEO1));
243 SR(OVL_BA1(OMAP_DSS_VIDEO1));
244 SR(OVL_POSITION(OMAP_DSS_VIDEO1));
245 SR(OVL_SIZE(OMAP_DSS_VIDEO1));
246 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
247 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
248 SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
249 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
250 SR(OVL_FIR(OMAP_DSS_VIDEO1));
251 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
252 SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
253 SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
254
5719d35c
AJ		 255 for (i = 0; i < 8; i++)
256 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
257
258 for (i = 0; i < 8; i++)
259 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
260
261 for (i = 0; i < 5; i++)
262 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
263
332e9d70
TV		 264 if (dss_has_feature(FEAT_FIR_COEF_V)) {
265 for (i = 0; i < 8; i++)
266 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
267 }
9b372c2d 268
ab5ca071
AJ		 269 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
270 SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
271 SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
272 SR(OVL_FIR2(OMAP_DSS_VIDEO1));
273 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
274 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
275
276 for (i = 0; i < 8; i++)
277 SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
278
279 for (i = 0; i < 8; i++)
280 SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
281
282 for (i = 0; i < 8; i++)
283 SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
284 }
285 if (dss_has_feature(FEAT_ATTR2))
286 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
287
332e9d70
TV		 288 if (dss_has_feature(FEAT_PRELOAD))
289 SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
80c39712
TV		 290
291 /* VID2 */
9b372c2d
AT		 292 SR(OVL_BA0(OMAP_DSS_VIDEO2));
293 SR(OVL_BA1(OMAP_DSS_VIDEO2));
294 SR(OVL_POSITION(OMAP_DSS_VIDEO2));
295 SR(OVL_SIZE(OMAP_DSS_VIDEO2));
296 SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
297 SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
298 SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
299 SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
300 SR(OVL_FIR(OMAP_DSS_VIDEO2));
301 SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
302 SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
303 SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
304
5719d35c
AJ		 305 for (i = 0; i < 8; i++)
306 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
307
308 for (i = 0; i < 8; i++)
309 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
310
311 for (i = 0; i < 5; i++)
312 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
313
332e9d70
TV		 314 if (dss_has_feature(FEAT_FIR_COEF_V)) {
315 for (i = 0; i < 8; i++)
316 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
317 }
9b372c2d 318
ab5ca071
AJ		 319 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
320 SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
321 SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
322 SR(OVL_FIR2(OMAP_DSS_VIDEO2));
323 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
324 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
325
326 for (i = 0; i < 8; i++)
327 SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
328
329 for (i = 0; i < 8; i++)
330 SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
331
332 for (i = 0; i < 8; i++)
333 SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
334 }
335 if (dss_has_feature(FEAT_ATTR2))
336 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
337
332e9d70
TV		 338 if (dss_has_feature(FEAT_PRELOAD))
339 SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
0cf35df3
MR		 340
341 if (dss_has_feature(FEAT_CORE_CLK_DIV))
342 SR(DIVISOR);
49ea86f3
TV		 343
344 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
345 dispc.ctx_valid = true;
346
347 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 348}
349
4fbafaf3 350static void dispc_restore_context(void)
80c39712 351{
49ea86f3 352 int i, ctx;
4fbafaf3
TV		 353
354 DSSDBG("dispc_restore_context\n");
355
49ea86f3
TV		 356 if (!dispc.ctx_valid)
357 return;
358
359 ctx = dispc_get_ctx_loss_count();
360
361 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
362 return;
363
364 DSSDBG("ctx_loss_count: saved %d, current %d\n",
365 dispc.ctx_loss_cnt, ctx);
366
75c7d59d 367 /*RR(IRQENABLE);*/
80c39712
TV		 368 /*RR(CONTROL);*/
369 RR(CONFIG);
702d1448
AT		 370 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
371 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
372 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
373 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
80c39712 374 RR(LINE_NUMBER);
702d1448
AT		 375 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
376 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
377 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
378 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
332e9d70
TV		 379 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
380 RR(GLOBAL_ALPHA);
702d1448
AT		 381 RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
382 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2a205f34 383 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 384 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
385 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
386 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
387 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
388 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
389 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
390 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2a205f34
SS		 391 RR(CONFIG2);
392 }
80c39712 393
9b372c2d
AT		 394 RR(OVL_BA0(OMAP_DSS_GFX));
395 RR(OVL_BA1(OMAP_DSS_GFX));
396 RR(OVL_POSITION(OMAP_DSS_GFX));
397 RR(OVL_SIZE(OMAP_DSS_GFX));
398 RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
399 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
400 RR(OVL_ROW_INC(OMAP_DSS_GFX));
401 RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
402 RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
403 RR(OVL_TABLE_BA(OMAP_DSS_GFX));
404
80c39712 405
702d1448
AT		 406 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
407 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
408 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
80c39712 409
332e9d70
TV		 410 if (dss_has_feature(FEAT_CPR)) {
411 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
412 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
413 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
414 }
2a205f34 415 if (dss_has_feature(FEAT_MGR_LCD2)) {
702d1448
AT		 416 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
417 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
418 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2a205f34 419
332e9d70
TV		 420 if (dss_has_feature(FEAT_CPR)) {
421 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
422 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
423 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
424 }
2a205f34 425 }
80c39712 426
332e9d70
TV		 427 if (dss_has_feature(FEAT_PRELOAD))
428 RR(OVL_PRELOAD(OMAP_DSS_GFX));
80c39712
TV		 429
430 /* VID1 */
9b372c2d
AT		 431 RR(OVL_BA0(OMAP_DSS_VIDEO1));
432 RR(OVL_BA1(OMAP_DSS_VIDEO1));
433 RR(OVL_POSITION(OMAP_DSS_VIDEO1));
434 RR(OVL_SIZE(OMAP_DSS_VIDEO1));
435 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
436 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
437 RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
438 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
439 RR(OVL_FIR(OMAP_DSS_VIDEO1));
440 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
441 RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
442 RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
443
5719d35c
AJ		 444 for (i = 0; i < 8; i++)
445 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
446
447 for (i = 0; i < 8; i++)
448 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
449
450 for (i = 0; i < 5; i++)
451 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
452
332e9d70
TV		 453 if (dss_has_feature(FEAT_FIR_COEF_V)) {
454 for (i = 0; i < 8; i++)
455 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
456 }
9b372c2d 457
ab5ca071
AJ		 458 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
459 RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
460 RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
461 RR(OVL_FIR2(OMAP_DSS_VIDEO1));
462 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
463 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
464
465 for (i = 0; i < 8; i++)
466 RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
467
468 for (i = 0; i < 8; i++)
469 RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
470
471 for (i = 0; i < 8; i++)
472 RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
473 }
474 if (dss_has_feature(FEAT_ATTR2))
475 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
476
332e9d70
TV		 477 if (dss_has_feature(FEAT_PRELOAD))
478 RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
80c39712
TV		 479
480 /* VID2 */
9b372c2d
AT		 481 RR(OVL_BA0(OMAP_DSS_VIDEO2));
482 RR(OVL_BA1(OMAP_DSS_VIDEO2));
483 RR(OVL_POSITION(OMAP_DSS_VIDEO2));
484 RR(OVL_SIZE(OMAP_DSS_VIDEO2));
485 RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
486 RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
487 RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
488 RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
489 RR(OVL_FIR(OMAP_DSS_VIDEO2));
490 RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
491 RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
492 RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
493
5719d35c
AJ		 494 for (i = 0; i < 8; i++)
495 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
496
497 for (i = 0; i < 8; i++)
498 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
499
500 for (i = 0; i < 5; i++)
501 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
502
332e9d70
TV		 503 if (dss_has_feature(FEAT_FIR_COEF_V)) {
504 for (i = 0; i < 8; i++)
505 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
506 }
9b372c2d 507
ab5ca071
AJ		 508 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
509 RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
510 RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
511 RR(OVL_FIR2(OMAP_DSS_VIDEO2));
512 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
513 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
514
515 for (i = 0; i < 8; i++)
516 RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
517
518 for (i = 0; i < 8; i++)
519 RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
520
521 for (i = 0; i < 8; i++)
522 RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
523 }
524 if (dss_has_feature(FEAT_ATTR2))
525 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
526
332e9d70
TV		 527 if (dss_has_feature(FEAT_PRELOAD))
528 RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
80c39712 529
0cf35df3
MR		 530 if (dss_has_feature(FEAT_CORE_CLK_DIV))
531 RR(DIVISOR);
532
80c39712
TV		 533 /* enable last, because LCD & DIGIT enable are here */
534 RR(CONTROL);
2a205f34
SS		 535 if (dss_has_feature(FEAT_MGR_LCD2))
536 RR(CONTROL2);
75c7d59d
VS		 537 /* clear spurious SYNC_LOST_DIGIT interrupts */
538 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
539
540 /*
541 * enable last so IRQs won't trigger before
542 * the context is fully restored
543 */
544 RR(IRQENABLE);
49ea86f3
TV		 545
546 DSSDBG("context restored\n");
80c39712
TV		 547}
548
549#undef SR
550#undef RR
551
4fbafaf3
TV		 552int dispc_runtime_get(void)
553{
554 int r;
555
556 DSSDBG("dispc_runtime_get\n");
557
558 r = pm_runtime_get_sync(&dispc.pdev->dev);
559 WARN_ON(r < 0);
560 return r < 0 ? r : 0;
561}
562
563void dispc_runtime_put(void)
564{
565 int r;
566
567 DSSDBG("dispc_runtime_put\n");
568
569 r = pm_runtime_put(&dispc.pdev->dev);
570 WARN_ON(r < 0);
80c39712
TV		 571}
572
4fbafaf3 573
80c39712
TV		 574bool dispc_go_busy(enum omap_channel channel)
575{
576 int bit;
577
2a205f34
SS		 578 if (channel == OMAP_DSS_CHANNEL_LCD ||
579 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 580 bit = 5; /* GOLCD */
581 else
582 bit = 6; /* GODIGIT */
583
2a205f34
SS		 584 if (channel == OMAP_DSS_CHANNEL_LCD2)
585 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
586 else
587 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 588}
589
590void dispc_go(enum omap_channel channel)
591{
592 int bit;
2a205f34 593 bool enable_bit, go_bit;
80c39712 594
2a205f34
SS		 595 if (channel == OMAP_DSS_CHANNEL_LCD ||
596 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 597 bit = 0; /* LCDENABLE */
598 else
599 bit = 1; /* DIGITALENABLE */
600
601 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 602 if (channel == OMAP_DSS_CHANNEL_LCD2)
603 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
604 else
605 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
606
607 if (!enable_bit)
e6d80f95 608 return;
80c39712 609
2a205f34
SS		 610 if (channel == OMAP_DSS_CHANNEL_LCD ||
611 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 612 bit = 5; /* GOLCD */
613 else
614 bit = 6; /* GODIGIT */
615
2a205f34
SS		 616 if (channel == OMAP_DSS_CHANNEL_LCD2)
617 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
618 else
619 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
620
621 if (go_bit) {
80c39712 622 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 623 return;
80c39712
TV		 624 }
625
2a205f34
SS		 626 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
627 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 628
2a205f34
SS		 629 if (channel == OMAP_DSS_CHANNEL_LCD2)
630 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
631 else
632 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 633}
634
635static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
636{
9b372c2d 637 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 638}
639
640static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
641{
9b372c2d 642 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 643}
644
645static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
646{
9b372c2d 647 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 648}
649
ab5ca071
AJ		 650static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
651{
652 BUG_ON(plane == OMAP_DSS_GFX);
653
654 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
655}
656
657static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
658{
659 BUG_ON(plane == OMAP_DSS_GFX);
660
661 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
662}
663
664static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
665{
666 BUG_ON(plane == OMAP_DSS_GFX);
667
668 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
669}
670
80c39712 671static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
0d66cbb5
AJ		 672 int vscaleup, int five_taps,
673 enum omap_color_component color_comp)
80c39712
TV		 674{
675 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 676 static const struct dispc_h_coef coef_hup[8] = {
677 { 0, 0, 128, 0, 0 },
678 { -1, 13, 124, -8, 0 },
679 { -2, 30, 112, -11, -1 },
680 { -5, 51, 95, -11, -2 },
681 { 0, -9, 73, 73, -9 },
682 { -2, -11, 95, 51, -5 },
683 { -1, -11, 112, 30, -2 },
684 { 0, -8, 124, 13, -1 },
80c39712
TV		 685 };
686
66be8f6c
GI		 687 /* Coefficients for vertical up-sampling */
688 static const struct dispc_v_coef coef_vup_3tap[8] = {
689 { 0, 0, 128, 0, 0 },
690 { 0, 3, 123, 2, 0 },
691 { 0, 12, 111, 5, 0 },
692 { 0, 32, 89, 7, 0 },
693 { 0, 0, 64, 64, 0 },
694 { 0, 7, 89, 32, 0 },
695 { 0, 5, 111, 12, 0 },
696 { 0, 2, 123, 3, 0 },
80c39712
TV		 697 };
698
66be8f6c
GI		 699 static const struct dispc_v_coef coef_vup_5tap[8] = {
700 { 0, 0, 128, 0, 0 },
701 { -1, 13, 124, -8, 0 },
702 { -2, 30, 112, -11, -1 },
703 { -5, 51, 95, -11, -2 },
704 { 0, -9, 73, 73, -9 },
705 { -2, -11, 95, 51, -5 },
706 { -1, -11, 112, 30, -2 },
707 { 0, -8, 124, 13, -1 },
80c39712
TV		 708 };
709
66be8f6c
GI		 710 /* Coefficients for horizontal down-sampling */
711 static const struct dispc_h_coef coef_hdown[8] = {
712 { 0, 36, 56, 36, 0 },
713 { 4, 40, 55, 31, -2 },
714 { 8, 44, 54, 27, -5 },
715 { 12, 48, 53, 22, -7 },
716 { -9, 17, 52, 51, 17 },
717 { -7, 22, 53, 48, 12 },
718 { -5, 27, 54, 44, 8 },
719 { -2, 31, 55, 40, 4 },
80c39712
TV		 720 };
721
66be8f6c
GI		 722 /* Coefficients for vertical down-sampling */
723 static const struct dispc_v_coef coef_vdown_3tap[8] = {
724 { 0, 36, 56, 36, 0 },
725 { 0, 40, 57, 31, 0 },
726 { 0, 45, 56, 27, 0 },
727 { 0, 50, 55, 23, 0 },
728 { 0, 18, 55, 55, 0 },
729 { 0, 23, 55, 50, 0 },
730 { 0, 27, 56, 45, 0 },
731 { 0, 31, 57, 40, 0 },
80c39712
TV		 732 };
733
66be8f6c
GI		 734 static const struct dispc_v_coef coef_vdown_5tap[8] = {
735 { 0, 36, 56, 36, 0 },
736 { 4, 40, 55, 31, -2 },
737 { 8, 44, 54, 27, -5 },
738 { 12, 48, 53, 22, -7 },
739 { -9, 17, 52, 51, 17 },
740 { -7, 22, 53, 48, 12 },
741 { -5, 27, 54, 44, 8 },
742 { -2, 31, 55, 40, 4 },
80c39712
TV		 743 };
744
66be8f6c
GI		 745 const struct dispc_h_coef *h_coef;
746 const struct dispc_v_coef *v_coef;
80c39712
TV		 747 int i;
748
749 if (hscaleup)
750 h_coef = coef_hup;
751 else
752 h_coef = coef_hdown;
753
66be8f6c
GI		 754 if (vscaleup)
755 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
756 else
757 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 758
759 for (i = 0; i < 8; i++) {
760 u32 h, hv;
761
66be8f6c
GI		 762 h = FLD_VAL(h_coef[i].hc0, 7, 0)
763 | FLD_VAL(h_coef[i].hc1, 15, 8)
764 | FLD_VAL(h_coef[i].hc2, 23, 16)
765 | FLD_VAL(h_coef[i].hc3, 31, 24);
766 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
767 | FLD_VAL(v_coef[i].vc0, 15, 8)
768 | FLD_VAL(v_coef[i].vc1, 23, 16)
769 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712 770
0d66cbb5
AJ		 771 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
772 _dispc_write_firh_reg(plane, i, h);
773 _dispc_write_firhv_reg(plane, i, hv);
774 } else {
775 _dispc_write_firh2_reg(plane, i, h);
776 _dispc_write_firhv2_reg(plane, i, hv);
777 }
778
80c39712
TV		 779 }
780
66be8f6c
GI		 781 if (five_taps) {
782 for (i = 0; i < 8; i++) {
783 u32 v;
784 v = FLD_VAL(v_coef[i].vc00, 7, 0)
785 | FLD_VAL(v_coef[i].vc22, 15, 8);
0d66cbb5
AJ		 786 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
787 _dispc_write_firv_reg(plane, i, v);
788 else
789 _dispc_write_firv2_reg(plane, i, v);
66be8f6c 790 }
80c39712
TV		 791 }
792}
793
794static void _dispc_setup_color_conv_coef(void)
795{
796 const struct color_conv_coef {
797 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
798 int full_range;
799 } ctbl_bt601_5 = {
800 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
801 };
802
803 const struct color_conv_coef *ct;
804
805#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
806
807 ct = &ctbl_bt601_5;
808
9b372c2d
AT		 809 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
810 CVAL(ct->rcr, ct->ry));
811 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
812 CVAL(ct->gy, ct->rcb));
813 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
814 CVAL(ct->gcb, ct->gcr));
815 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
816 CVAL(ct->bcr, ct->by));
817 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
818 CVAL(0, ct->bcb));
819
820 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
821 CVAL(ct->rcr, ct->ry));
822 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
823 CVAL(ct->gy, ct->rcb));
824 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
825 CVAL(ct->gcb, ct->gcr));
826 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
827 CVAL(ct->bcr, ct->by));
828 dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
829 CVAL(0, ct->bcb));
80c39712
TV		 830
831#undef CVAL
832
9b372c2d
AT		 833 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
834 ct->full_range, 11, 11);
835 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
836 ct->full_range, 11, 11);
80c39712
TV		 837}
838
839
840static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
841{
9b372c2d 842 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 843}
844
845static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
846{
9b372c2d 847 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 848}
849
ab5ca071
AJ		 850static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
851{
852 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
853}
854
855static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
856{
857 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
858}
859
80c39712
TV		 860static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
861{
80c39712 862 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 863
864 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 865}
866
867static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
868{
80c39712 869 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 870
871 if (plane == OMAP_DSS_GFX)
872 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
873 else
874 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 875}
876
877static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
878{
879 u32 val;
80c39712
TV		 880
881 BUG_ON(plane == OMAP_DSS_GFX);
882
883 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 884
885 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 886}
887
fd28a390
R		 888static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
889{
890 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
891 return;
892
893 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
894 plane == OMAP_DSS_VIDEO1)
895 return;
896
9b372c2d 897 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 898}
899
80c39712
TV		 900static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
901{
a0acb557 902 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 903 return;
904
fd28a390
R		 905 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
906 plane == OMAP_DSS_VIDEO1)
907 return;
a0acb557 908
80c39712
TV		 909 if (plane == OMAP_DSS_GFX)
910 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
911 else if (plane == OMAP_DSS_VIDEO2)
912 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
913}
914
915static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
916{
9b372c2d 917 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 918}
919
920static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
921{
9b372c2d 922 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 923}
924
925static void _dispc_set_color_mode(enum omap_plane plane,
926 enum omap_color_mode color_mode)
927{
928 u32 m = 0;
f20e4220
AJ		 929 if (plane != OMAP_DSS_GFX) {
930 switch (color_mode) {
931 case OMAP_DSS_COLOR_NV12:
932 m = 0x0; break;
933 case OMAP_DSS_COLOR_RGB12U:
934 m = 0x1; break;
935 case OMAP_DSS_COLOR_RGBA16:
936 m = 0x2; break;
937 case OMAP_DSS_COLOR_RGBX16:
938 m = 0x4; break;
939 case OMAP_DSS_COLOR_ARGB16:
940 m = 0x5; break;
941 case OMAP_DSS_COLOR_RGB16:
942 m = 0x6; break;
943 case OMAP_DSS_COLOR_ARGB16_1555:
944 m = 0x7; break;
945 case OMAP_DSS_COLOR_RGB24U:
946 m = 0x8; break;
947 case OMAP_DSS_COLOR_RGB24P:
948 m = 0x9; break;
949 case OMAP_DSS_COLOR_YUV2:
950 m = 0xa; break;
951 case OMAP_DSS_COLOR_UYVY:
952 m = 0xb; break;
953 case OMAP_DSS_COLOR_ARGB32:
954 m = 0xc; break;
955 case OMAP_DSS_COLOR_RGBA32:
956 m = 0xd; break;
957 case OMAP_DSS_COLOR_RGBX32:
958 m = 0xe; break;
959 case OMAP_DSS_COLOR_XRGB16_1555:
960 m = 0xf; break;
961 default:
962 BUG(); break;
963 }
964 } else {
965 switch (color_mode) {
966 case OMAP_DSS_COLOR_CLUT1:
967 m = 0x0; break;
968 case OMAP_DSS_COLOR_CLUT2:
969 m = 0x1; break;
970 case OMAP_DSS_COLOR_CLUT4:
971 m = 0x2; break;
972 case OMAP_DSS_COLOR_CLUT8:
973 m = 0x3; break;
974 case OMAP_DSS_COLOR_RGB12U:
975 m = 0x4; break;
976 case OMAP_DSS_COLOR_ARGB16:
977 m = 0x5; break;
978 case OMAP_DSS_COLOR_RGB16:
979 m = 0x6; break;
980 case OMAP_DSS_COLOR_ARGB16_1555:
981 m = 0x7; break;
982 case OMAP_DSS_COLOR_RGB24U:
983 m = 0x8; break;
984 case OMAP_DSS_COLOR_RGB24P:
985 m = 0x9; break;
986 case OMAP_DSS_COLOR_YUV2:
987 m = 0xa; break;
988 case OMAP_DSS_COLOR_UYVY:
989 m = 0xb; break;
990 case OMAP_DSS_COLOR_ARGB32:
991 m = 0xc; break;
992 case OMAP_DSS_COLOR_RGBA32:
993 m = 0xd; break;
994 case OMAP_DSS_COLOR_RGBX32:
995 m = 0xe; break;
996 case OMAP_DSS_COLOR_XRGB16_1555:
997 m = 0xf; break;
998 default:
999 BUG(); break;
1000 }
80c39712
TV		 1001 }
1002
9b372c2d 1003 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 1004}
1005
e6d80f95 1006void dispc_set_channel_out(enum omap_plane plane,
80c39712
TV		 1007 enum omap_channel channel)
1008{
1009 int shift;
1010 u32 val;
2a205f34 1011 int chan = 0, chan2 = 0;
80c39712
TV		 1012
1013 switch (plane) {
1014 case OMAP_DSS_GFX:
1015 shift = 8;
1016 break;
1017 case OMAP_DSS_VIDEO1:
1018 case OMAP_DSS_VIDEO2:
1019 shift = 16;
1020 break;
1021 default:
1022 BUG();
1023 return;
1024 }
1025
9b372c2d 1026 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 1027 if (dss_has_feature(FEAT_MGR_LCD2)) {
1028 switch (channel) {
1029 case OMAP_DSS_CHANNEL_LCD:
1030 chan = 0;
1031 chan2 = 0;
1032 break;
1033 case OMAP_DSS_CHANNEL_DIGIT:
1034 chan = 1;
1035 chan2 = 0;
1036 break;
1037 case OMAP_DSS_CHANNEL_LCD2:
1038 chan = 0;
1039 chan2 = 1;
1040 break;
1041 default:
1042 BUG();
1043 }
1044
1045 val = FLD_MOD(val, chan, shift, shift);
1046 val = FLD_MOD(val, chan2, 31, 30);
1047 } else {
1048 val = FLD_MOD(val, channel, shift, shift);
1049 }
9b372c2d 1050 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1051}
1052
5ed8cf5b 1053static void dispc_set_burst_size(enum omap_plane plane,
80c39712
TV		 1054 enum omap_burst_size burst_size)
1055{
1056 int shift;
80c39712 1057
80c39712
TV		 1058 switch (plane) {
1059 case OMAP_DSS_GFX:
1060 shift = 6;
1061 break;
1062 case OMAP_DSS_VIDEO1:
1063 case OMAP_DSS_VIDEO2:
1064 shift = 14;
1065 break;
1066 default:
1067 BUG();
1068 return;
1069 }
1070
5ed8cf5b 1071 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1072}
1073
5ed8cf5b
TV		 1074static void dispc_configure_burst_sizes(void)
1075{
1076 int i;
1077 const int burst_size = BURST_SIZE_X8;
1078
1079 /* Configure burst size always to maximum size */
1080 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1081 dispc_set_burst_size(i, burst_size);
1082}
1083
1084u32 dispc_get_burst_size(enum omap_plane plane)
1085{
1086 unsigned unit = dss_feat_get_burst_size_unit();
1087 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1088 return unit * 8;
1089}
1090
d3862610
M		 1091void dispc_enable_gamma_table(bool enable)
1092{
1093 /*
1094 * This is partially implemented to support only disabling of
1095 * the gamma table.
1096 */
1097 if (enable) {
1098 DSSWARN("Gamma table enabling for TV not yet supported");
1099 return;
1100 }
1101
1102 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1103}
1104
3c07cae2
TV		 1105void dispc_enable_cpr(enum omap_channel channel, bool enable)
1106{
1107 u16 reg;
1108
1109 if (channel == OMAP_DSS_CHANNEL_LCD)
1110 reg = DISPC_CONFIG;
1111 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1112 reg = DISPC_CONFIG2;
1113 else
1114 return;
1115
1116 REG_FLD_MOD(reg, enable, 15, 15);
1117}
1118
1119void dispc_set_cpr_coef(enum omap_channel channel,
1120 struct omap_dss_cpr_coefs *coefs)
1121{
1122 u32 coef_r, coef_g, coef_b;
1123
1124 if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2)
1125 return;
1126
1127 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1128 FLD_VAL(coefs->rb, 9, 0);
1129 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1130 FLD_VAL(coefs->gb, 9, 0);
1131 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1132 FLD_VAL(coefs->bb, 9, 0);
1133
1134 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1135 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1136 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1137}
1138
80c39712
TV		 1139static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1140{
1141 u32 val;
1142
1143 BUG_ON(plane == OMAP_DSS_GFX);
1144
9b372c2d 1145 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1146 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1147 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1148}
1149
1150void dispc_enable_replication(enum omap_plane plane, bool enable)
1151{
1152 int bit;
1153
1154 if (plane == OMAP_DSS_GFX)
1155 bit = 5;
1156 else
1157 bit = 10;
1158
9b372c2d 1159 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
80c39712
TV		 1160}
1161
64ba4f74 1162void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1163{
1164 u32 val;
1165 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1166 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1167 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1168}
1169
1170void dispc_set_digit_size(u16 width, u16 height)
1171{
1172 u32 val;
1173 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1174 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1175 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1176}
1177
1178static void dispc_read_plane_fifo_sizes(void)
1179{
80c39712
TV		 1180 u32 size;
1181 int plane;
a0acb557 1182 u8 start, end;
5ed8cf5b
TV		 1183 u32 unit;
1184
1185 unit = dss_feat_get_buffer_size_unit();
80c39712 1186
a0acb557 1187 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1188
a0acb557 1189 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
5ed8cf5b
TV		 1190 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1191 size *= unit;
80c39712
TV		 1192 dispc.fifo_size[plane] = size;
1193 }
80c39712
TV		 1194}
1195
1196u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1197{
1198 return dispc.fifo_size[plane];
1199}
1200
5ed8cf5b 1201void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1202{
a0acb557 1203 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1204 u32 unit;
1205
1206 unit = dss_feat_get_buffer_size_unit();
1207
1208 WARN_ON(low % unit != 0);
1209 WARN_ON(high % unit != 0);
1210
1211 low /= unit;
1212 high /= unit;
a0acb557 1213
9b372c2d
AT		 1214 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1215 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1216
80c39712
TV		 1217 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1218 plane,
9b372c2d
AT		 1219 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1220 lo_start, lo_end),
1221 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1222 hi_start, hi_end),
80c39712
TV		 1223 low, high);
1224
9b372c2d 1225 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1226 FLD_VAL(high, hi_start, hi_end) |
1227 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1228}
1229
1230void dispc_enable_fifomerge(bool enable)
1231{
80c39712
TV		 1232 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1233 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1234}
1235
0d66cbb5
AJ		 1236static void _dispc_set_fir(enum omap_plane plane,
1237 int hinc, int vinc,
1238 enum omap_color_component color_comp)
80c39712
TV		 1239{
1240 u32 val;
80c39712 1241
0d66cbb5
AJ		 1242 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1243 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1244
0d66cbb5
AJ		 1245 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1246 &hinc_start, &hinc_end);
1247 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1248 &vinc_start, &vinc_end);
1249 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1250 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1251
0d66cbb5
AJ		 1252 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1253 } else {
1254 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1255 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1256 }
80c39712
TV		 1257}
1258
1259static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1260{
1261 u32 val;
87a7484b 1262 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1263
87a7484b
AT		 1264 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1265 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1266
1267 val = FLD_VAL(vaccu, vert_start, vert_end) |
1268 FLD_VAL(haccu, hor_start, hor_end);
1269
9b372c2d 1270 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1271}
1272
1273static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1274{
1275 u32 val;
87a7484b 1276 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1277
87a7484b
AT		 1278 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1279 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1280
1281 val = FLD_VAL(vaccu, vert_start, vert_end) |
1282 FLD_VAL(haccu, hor_start, hor_end);
1283
9b372c2d 1284 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1285}
1286
ab5ca071
AJ		 1287static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
1288{
1289 u32 val;
1290
1291 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1292 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1293}
1294
1295static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
1296{
1297 u32 val;
1298
1299 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1300 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1301}
80c39712 1302
0d66cbb5 1303static void _dispc_set_scale_param(enum omap_plane plane,
80c39712
TV		 1304 u16 orig_width, u16 orig_height,
1305 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1306 bool five_taps, u8 rotation,
1307 enum omap_color_component color_comp)
80c39712 1308{
0d66cbb5 1309 int fir_hinc, fir_vinc;
80c39712 1310 int hscaleup, vscaleup;
80c39712
TV		 1311
1312 hscaleup = orig_width <= out_width;
1313 vscaleup = orig_height <= out_height;
1314
0d66cbb5 1315 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
80c39712 1316
ed14a3ce
AJ		 1317 fir_hinc = 1024 * orig_width / out_width;
1318 fir_vinc = 1024 * orig_height / out_height;
80c39712 1319
0d66cbb5
AJ		 1320 _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1321}
1322
1323static void _dispc_set_scaling_common(enum omap_plane plane,
1324 u16 orig_width, u16 orig_height,
1325 u16 out_width, u16 out_height,
1326 bool ilace, bool five_taps,
1327 bool fieldmode, enum omap_color_mode color_mode,
1328 u8 rotation)
1329{
1330 int accu0 = 0;
1331 int accu1 = 0;
1332 u32 l;
80c39712 1333
0d66cbb5
AJ		 1334 _dispc_set_scale_param(plane, orig_width, orig_height,
1335 out_width, out_height, five_taps,
1336 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1337 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1338
87a7484b
AT		 1339 /* RESIZEENABLE and VERTICALTAPS */
1340 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1341 l |= (orig_width != out_width) ? (1 << 5) : 0;
1342 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1343 l |= five_taps ? (1 << 21) : 0;
80c39712 1344
87a7484b
AT		 1345 /* VRESIZECONF and HRESIZECONF */
1346 if (dss_has_feature(FEAT_RESIZECONF)) {
1347 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1348 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1349 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1350 }
80c39712 1351
87a7484b
AT		 1352 /* LINEBUFFERSPLIT */
1353 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1354 l &= ~(0x1 << 22);
1355 l |= five_taps ? (1 << 22) : 0;
1356 }
80c39712 1357
9b372c2d 1358 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1359
1360 /*
1361 * field 0 = even field = bottom field
1362 * field 1 = odd field = top field
1363 */
1364 if (ilace && !fieldmode) {
1365 accu1 = 0;
0d66cbb5 1366 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1367 if (accu0 >= 1024/2) {
1368 accu1 = 1024/2;
1369 accu0 -= accu1;
1370 }
1371 }
1372
1373 _dispc_set_vid_accu0(plane, 0, accu0);
1374 _dispc_set_vid_accu1(plane, 0, accu1);
1375}
1376
0d66cbb5
AJ		 1377static void _dispc_set_scaling_uv(enum omap_plane plane,
1378 u16 orig_width, u16 orig_height,
1379 u16 out_width, u16 out_height,
1380 bool ilace, bool five_taps,
1381 bool fieldmode, enum omap_color_mode color_mode,
1382 u8 rotation)
1383{
1384 int scale_x = out_width != orig_width;
1385 int scale_y = out_height != orig_height;
1386
1387 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1388 return;
1389 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1390 color_mode != OMAP_DSS_COLOR_UYVY &&
1391 color_mode != OMAP_DSS_COLOR_NV12)) {
1392 /* reset chroma resampling for RGB formats */
1393 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1394 return;
1395 }
1396 switch (color_mode) {
1397 case OMAP_DSS_COLOR_NV12:
1398 /* UV is subsampled by 2 vertically*/
1399 orig_height >>= 1;
1400 /* UV is subsampled by 2 horz.*/
1401 orig_width >>= 1;
1402 break;
1403 case OMAP_DSS_COLOR_YUV2:
1404 case OMAP_DSS_COLOR_UYVY:
1405 /*For YUV422 with 90/270 rotation,
1406 *we don't upsample chroma
1407 */
1408 if (rotation == OMAP_DSS_ROT_0 ||
1409 rotation == OMAP_DSS_ROT_180)
1410 /* UV is subsampled by 2 hrz*/
1411 orig_width >>= 1;
1412 /* must use FIR for YUV422 if rotated */
1413 if (rotation != OMAP_DSS_ROT_0)
1414 scale_x = scale_y = true;
1415 break;
1416 default:
1417 BUG();
1418 }
1419
1420 if (out_width != orig_width)
1421 scale_x = true;
1422 if (out_height != orig_height)
1423 scale_y = true;
1424
1425 _dispc_set_scale_param(plane, orig_width, orig_height,
1426 out_width, out_height, five_taps,
1427 rotation, DISPC_COLOR_COMPONENT_UV);
1428
1429 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1430 (scale_x || scale_y) ? 1 : 0, 8, 8);
1431 /* set H scaling */
1432 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1433 /* set V scaling */
1434 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1435
1436 _dispc_set_vid_accu2_0(plane, 0x80, 0);
1437 _dispc_set_vid_accu2_1(plane, 0x80, 0);
1438}
1439
1440static void _dispc_set_scaling(enum omap_plane plane,
1441 u16 orig_width, u16 orig_height,
1442 u16 out_width, u16 out_height,
1443 bool ilace, bool five_taps,
1444 bool fieldmode, enum omap_color_mode color_mode,
1445 u8 rotation)
1446{
1447 BUG_ON(plane == OMAP_DSS_GFX);
1448
1449 _dispc_set_scaling_common(plane,
1450 orig_width, orig_height,
1451 out_width, out_height,
1452 ilace, five_taps,
1453 fieldmode, color_mode,
1454 rotation);
1455
1456 _dispc_set_scaling_uv(plane,
1457 orig_width, orig_height,
1458 out_width, out_height,
1459 ilace, five_taps,
1460 fieldmode, color_mode,
1461 rotation);
1462}
1463
80c39712
TV		 1464static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1465 bool mirroring, enum omap_color_mode color_mode)
1466{
87a7484b
AT		 1467 bool row_repeat = false;
1468 int vidrot = 0;
1469
80c39712
TV		 1470 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1471 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1472
1473 if (mirroring) {
1474 switch (rotation) {
1475 case OMAP_DSS_ROT_0:
1476 vidrot = 2;
1477 break;
1478 case OMAP_DSS_ROT_90:
1479 vidrot = 1;
1480 break;
1481 case OMAP_DSS_ROT_180:
1482 vidrot = 0;
1483 break;
1484 case OMAP_DSS_ROT_270:
1485 vidrot = 3;
1486 break;
1487 }
1488 } else {
1489 switch (rotation) {
1490 case OMAP_DSS_ROT_0:
1491 vidrot = 0;
1492 break;
1493 case OMAP_DSS_ROT_90:
1494 vidrot = 1;
1495 break;
1496 case OMAP_DSS_ROT_180:
1497 vidrot = 2;
1498 break;
1499 case OMAP_DSS_ROT_270:
1500 vidrot = 3;
1501 break;
1502 }
1503 }
1504
80c39712 1505 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1506 row_repeat = true;
80c39712 1507 else
87a7484b 1508 row_repeat = false;
80c39712 1509 }
87a7484b 1510
9b372c2d 1511 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1512 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1513 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1514 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1515}
1516
1517static int color_mode_to_bpp(enum omap_color_mode color_mode)
1518{
1519 switch (color_mode) {
1520 case OMAP_DSS_COLOR_CLUT1:
1521 return 1;
1522 case OMAP_DSS_COLOR_CLUT2:
1523 return 2;
1524 case OMAP_DSS_COLOR_CLUT4:
1525 return 4;
1526 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1527 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1528 return 8;
1529 case OMAP_DSS_COLOR_RGB12U:
1530 case OMAP_DSS_COLOR_RGB16:
1531 case OMAP_DSS_COLOR_ARGB16:
1532 case OMAP_DSS_COLOR_YUV2:
1533 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1534 case OMAP_DSS_COLOR_RGBA16:
1535 case OMAP_DSS_COLOR_RGBX16:
1536 case OMAP_DSS_COLOR_ARGB16_1555:
1537 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1538 return 16;
1539 case OMAP_DSS_COLOR_RGB24P:
1540 return 24;
1541 case OMAP_DSS_COLOR_RGB24U:
1542 case OMAP_DSS_COLOR_ARGB32:
1543 case OMAP_DSS_COLOR_RGBA32:
1544 case OMAP_DSS_COLOR_RGBX32:
1545 return 32;
1546 default:
1547 BUG();
1548 }
1549}
1550
1551static s32 pixinc(int pixels, u8 ps)
1552{
1553 if (pixels == 1)
1554 return 1;
1555 else if (pixels > 1)
1556 return 1 + (pixels - 1) * ps;
1557 else if (pixels < 0)
1558 return 1 - (-pixels + 1) * ps;
1559 else
1560 BUG();
1561}
1562
1563static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1564 u16 screen_width,
1565 u16 width, u16 height,
1566 enum omap_color_mode color_mode, bool fieldmode,
1567 unsigned int field_offset,
1568 unsigned *offset0, unsigned *offset1,
1569 s32 *row_inc, s32 *pix_inc)
1570{
1571 u8 ps;
1572
1573 /* FIXME CLUT formats */
1574 switch (color_mode) {
1575 case OMAP_DSS_COLOR_CLUT1:
1576 case OMAP_DSS_COLOR_CLUT2:
1577 case OMAP_DSS_COLOR_CLUT4:
1578 case OMAP_DSS_COLOR_CLUT8:
1579 BUG();
1580 return;
1581 case OMAP_DSS_COLOR_YUV2:
1582 case OMAP_DSS_COLOR_UYVY:
1583 ps = 4;
1584 break;
1585 default:
1586 ps = color_mode_to_bpp(color_mode) / 8;
1587 break;
1588 }
1589
1590 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1591 width, height);
1592
1593 /*
1594 * field 0 = even field = bottom field
1595 * field 1 = odd field = top field
1596 */
1597 switch (rotation + mirror * 4) {
1598 case OMAP_DSS_ROT_0:
1599 case OMAP_DSS_ROT_180:
1600 /*
1601 * If the pixel format is YUV or UYVY divide the width
1602 * of the image by 2 for 0 and 180 degree rotation.
1603 */
1604 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1605 color_mode == OMAP_DSS_COLOR_UYVY)
1606 width = width >> 1;
1607 case OMAP_DSS_ROT_90:
1608 case OMAP_DSS_ROT_270:
1609 *offset1 = 0;
1610 if (field_offset)
1611 *offset0 = field_offset * screen_width * ps;
1612 else
1613 *offset0 = 0;
1614
1615 *row_inc = pixinc(1 + (screen_width - width) +
1616 (fieldmode ? screen_width : 0),
1617 ps);
1618 *pix_inc = pixinc(1, ps);
1619 break;
1620
1621 case OMAP_DSS_ROT_0 + 4:
1622 case OMAP_DSS_ROT_180 + 4:
1623 /* If the pixel format is YUV or UYVY divide the width
1624 * of the image by 2 for 0 degree and 180 degree
1625 */
1626 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1627 color_mode == OMAP_DSS_COLOR_UYVY)
1628 width = width >> 1;
1629 case OMAP_DSS_ROT_90 + 4:
1630 case OMAP_DSS_ROT_270 + 4:
1631 *offset1 = 0;
1632 if (field_offset)
1633 *offset0 = field_offset * screen_width * ps;
1634 else
1635 *offset0 = 0;
1636 *row_inc = pixinc(1 - (screen_width + width) -
1637 (fieldmode ? screen_width : 0),
1638 ps);
1639 *pix_inc = pixinc(1, ps);
1640 break;
1641
1642 default:
1643 BUG();
1644 }
1645}
1646
1647static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1648 u16 screen_width,
1649 u16 width, u16 height,
1650 enum omap_color_mode color_mode, bool fieldmode,
1651 unsigned int field_offset,
1652 unsigned *offset0, unsigned *offset1,
1653 s32 *row_inc, s32 *pix_inc)
1654{
1655 u8 ps;
1656 u16 fbw, fbh;
1657
1658 /* FIXME CLUT formats */
1659 switch (color_mode) {
1660 case OMAP_DSS_COLOR_CLUT1:
1661 case OMAP_DSS_COLOR_CLUT2:
1662 case OMAP_DSS_COLOR_CLUT4:
1663 case OMAP_DSS_COLOR_CLUT8:
1664 BUG();
1665 return;
1666 default:
1667 ps = color_mode_to_bpp(color_mode) / 8;
1668 break;
1669 }
1670
1671 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1672 width, height);
1673
1674 /* width & height are overlay sizes, convert to fb sizes */
1675
1676 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1677 fbw = width;
1678 fbh = height;
1679 } else {
1680 fbw = height;
1681 fbh = width;
1682 }
1683
1684 /*
1685 * field 0 = even field = bottom field
1686 * field 1 = odd field = top field
1687 */
1688 switch (rotation + mirror * 4) {
1689 case OMAP_DSS_ROT_0:
1690 *offset1 = 0;
1691 if (field_offset)
1692 *offset0 = *offset1 + field_offset * screen_width * ps;
1693 else
1694 *offset0 = *offset1;
1695 *row_inc = pixinc(1 + (screen_width - fbw) +
1696 (fieldmode ? screen_width : 0),
1697 ps);
1698 *pix_inc = pixinc(1, ps);
1699 break;
1700 case OMAP_DSS_ROT_90:
1701 *offset1 = screen_width * (fbh - 1) * ps;
1702 if (field_offset)
1703 *offset0 = *offset1 + field_offset * ps;
1704 else
1705 *offset0 = *offset1;
1706 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1707 (fieldmode ? 1 : 0), ps);
1708 *pix_inc = pixinc(-screen_width, ps);
1709 break;
1710 case OMAP_DSS_ROT_180:
1711 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1712 if (field_offset)
1713 *offset0 = *offset1 - field_offset * screen_width * ps;
1714 else
1715 *offset0 = *offset1;
1716 *row_inc = pixinc(-1 -
1717 (screen_width - fbw) -
1718 (fieldmode ? screen_width : 0),
1719 ps);
1720 *pix_inc = pixinc(-1, ps);
1721 break;
1722 case OMAP_DSS_ROT_270:
1723 *offset1 = (fbw - 1) * ps;
1724 if (field_offset)
1725 *offset0 = *offset1 - field_offset * ps;
1726 else
1727 *offset0 = *offset1;
1728 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1729 (fieldmode ? 1 : 0), ps);
1730 *pix_inc = pixinc(screen_width, ps);
1731 break;
1732
1733 /* mirroring */
1734 case OMAP_DSS_ROT_0 + 4:
1735 *offset1 = (fbw - 1) * ps;
1736 if (field_offset)
1737 *offset0 = *offset1 + field_offset * screen_width * ps;
1738 else
1739 *offset0 = *offset1;
1740 *row_inc = pixinc(screen_width * 2 - 1 +
1741 (fieldmode ? screen_width : 0),
1742 ps);
1743 *pix_inc = pixinc(-1, ps);
1744 break;
1745
1746 case OMAP_DSS_ROT_90 + 4:
1747 *offset1 = 0;
1748 if (field_offset)
1749 *offset0 = *offset1 + field_offset * ps;
1750 else
1751 *offset0 = *offset1;
1752 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1753 (fieldmode ? 1 : 0),
1754 ps);
1755 *pix_inc = pixinc(screen_width, ps);
1756 break;
1757
1758 case OMAP_DSS_ROT_180 + 4:
1759 *offset1 = screen_width * (fbh - 1) * ps;
1760 if (field_offset)
1761 *offset0 = *offset1 - field_offset * screen_width * ps;
1762 else
1763 *offset0 = *offset1;
1764 *row_inc = pixinc(1 - screen_width * 2 -
1765 (fieldmode ? screen_width : 0),
1766 ps);
1767 *pix_inc = pixinc(1, ps);
1768 break;
1769
1770 case OMAP_DSS_ROT_270 + 4:
1771 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1772 if (field_offset)
1773 *offset0 = *offset1 - field_offset * ps;
1774 else
1775 *offset0 = *offset1;
1776 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1777 (fieldmode ? 1 : 0),
1778 ps);
1779 *pix_inc = pixinc(-screen_width, ps);
1780 break;
1781
1782 default:
1783 BUG();
1784 }
1785}
1786
ff1b2cde
SS		 1787static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1788 u16 height, u16 out_width, u16 out_height,
1789 enum omap_color_mode color_mode)
80c39712
TV		 1790{
1791 u32 fclk = 0;
1792 /* FIXME venc pclk? */
ff1b2cde 1793 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1794
1795 if (height > out_height) {
1796 /* FIXME get real display PPL */
1797 unsigned int ppl = 800;
1798
1799 tmp = pclk * height * out_width;
1800 do_div(tmp, 2 * out_height * ppl);
1801 fclk = tmp;
1802
2d9c5597
VS		 1803 if (height > 2 * out_height) {
1804 if (ppl == out_width)
1805 return 0;
1806
80c39712
TV		 1807 tmp = pclk * (height - 2 * out_height) * out_width;
1808 do_div(tmp, 2 * out_height * (ppl - out_width));
1809 fclk = max(fclk, (u32) tmp);
1810 }
1811 }
1812
1813 if (width > out_width) {
1814 tmp = pclk * width;
1815 do_div(tmp, out_width);
1816 fclk = max(fclk, (u32) tmp);
1817
1818 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1819 fclk <<= 1;
1820 }
1821
1822 return fclk;
1823}
1824
ff1b2cde
SS		 1825static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1826 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1827{
1828 unsigned int hf, vf;
1829
1830 /*
1831 * FIXME how to determine the 'A' factor
1832 * for the no downscaling case ?
1833 */
1834
1835 if (width > 3 * out_width)
1836 hf = 4;
1837 else if (width > 2 * out_width)
1838 hf = 3;
1839 else if (width > out_width)
1840 hf = 2;
1841 else
1842 hf = 1;
1843
1844 if (height > out_height)
1845 vf = 2;
1846 else
1847 vf = 1;
1848
1849 /* FIXME venc pclk? */
ff1b2cde 1850 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1851}
1852
e6d80f95 1853int dispc_setup_plane(enum omap_plane plane,
80c39712
TV		 1854 u32 paddr, u16 screen_width,
1855 u16 pos_x, u16 pos_y,
1856 u16 width, u16 height,
1857 u16 out_width, u16 out_height,
1858 enum omap_color_mode color_mode,
1859 bool ilace,
1860 enum omap_dss_rotation_type rotation_type,
e6d80f95 1861 u8 rotation, bool mirror,
18faa1b6 1862 u8 global_alpha, u8 pre_mult_alpha,
0d66cbb5 1863 enum omap_channel channel, u32 puv_addr)
80c39712
TV		 1864{
1865 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1866 bool five_taps = 0;
1867 bool fieldmode = 0;
1868 int cconv = 0;
1869 unsigned offset0, offset1;
1870 s32 row_inc;
1871 s32 pix_inc;
1872 u16 frame_height = height;
1873 unsigned int field_offset = 0;
1874
e6d80f95
TV		 1875 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
1876 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
1877 plane, paddr, screen_width, pos_x, pos_y,
1878 width, height,
1879 out_width, out_height,
1880 ilace, color_mode,
1881 rotation, mirror, channel);
1882
80c39712
TV		 1883 if (paddr == 0)
1884 return -EINVAL;
1885
1886 if (ilace && height == out_height)
1887 fieldmode = 1;
1888
1889 if (ilace) {
1890 if (fieldmode)
1891 height /= 2;
1892 pos_y /= 2;
1893 out_height /= 2;
1894
1895 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1896 "out_height %d\n",
1897 height, pos_y, out_height);
1898 }
1899
8dad2ab6
AT		 1900 if (!dss_feat_color_mode_supported(plane, color_mode))
1901 return -EINVAL;
1902
80c39712
TV		 1903 if (plane == OMAP_DSS_GFX) {
1904 if (width != out_width || height != out_height)
1905 return -EINVAL;
80c39712
TV		 1906 } else {
1907 /* video plane */
1908
1909 unsigned long fclk = 0;
1910
1911 if (out_width < width / maxdownscale ||
1912 out_width > width * 8)
1913 return -EINVAL;
1914
1915 if (out_height < height / maxdownscale ||
1916 out_height > height * 8)
1917 return -EINVAL;
1918
8dad2ab6 1919 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
0d66cbb5
AJ		 1920 color_mode == OMAP_DSS_COLOR_UYVY ||
1921 color_mode == OMAP_DSS_COLOR_NV12)
80c39712 1922 cconv = 1;
80c39712
TV		 1923
1924 /* Must use 5-tap filter? */
1925 five_taps = height > out_height * 2;
1926
1927 if (!five_taps) {
18faa1b6
SS		 1928 fclk = calc_fclk(channel, width, height, out_width,
1929 out_height);
80c39712
TV		 1930
1931 /* Try 5-tap filter if 3-tap fclk is too high */
1932 if (cpu_is_omap34xx() && height > out_height &&
1933 fclk > dispc_fclk_rate())
1934 five_taps = true;
1935 }
1936
1937 if (width > (2048 >> five_taps)) {
1938 DSSERR("failed to set up scaling, fclk too low\n");
1939 return -EINVAL;
1940 }
1941
1942 if (five_taps)
18faa1b6
SS		 1943 fclk = calc_fclk_five_taps(channel, width, height,
1944 out_width, out_height, color_mode);
80c39712
TV		 1945
1946 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1947 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1948
2d9c5597 1949 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1950 DSSERR("failed to set up scaling, "
1951 "required fclk rate = %lu Hz, "
1952 "current fclk rate = %lu Hz\n",
1953 fclk, dispc_fclk_rate());
1954 return -EINVAL;
1955 }
1956 }
1957
1958 if (ilace && !fieldmode) {
1959 /*
1960 * when downscaling the bottom field may have to start several
1961 * source lines below the top field. Unfortunately ACCUI
1962 * registers will only hold the fractional part of the offset
1963 * so the integer part must be added to the base address of the
1964 * bottom field.
1965 */
1966 if (!height || height == out_height)
1967 field_offset = 0;
1968 else
1969 field_offset = height / out_height / 2;
1970 }
1971
1972 /* Fields are independent but interleaved in memory. */
1973 if (fieldmode)
1974 field_offset = 1;
1975
1976 if (rotation_type == OMAP_DSS_ROT_DMA)
1977 calc_dma_rotation_offset(rotation, mirror,
1978 screen_width, width, frame_height, color_mode,
1979 fieldmode, field_offset,
1980 &offset0, &offset1, &row_inc, &pix_inc);
1981 else
1982 calc_vrfb_rotation_offset(rotation, mirror,
1983 screen_width, width, frame_height, color_mode,
1984 fieldmode, field_offset,
1985 &offset0, &offset1, &row_inc, &pix_inc);
1986
1987 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1988 offset0, offset1, row_inc, pix_inc);
1989
1990 _dispc_set_color_mode(plane, color_mode);
1991
1992 _dispc_set_plane_ba0(plane, paddr + offset0);
1993 _dispc_set_plane_ba1(plane, paddr + offset1);
1994
0d66cbb5
AJ		 1995 if (OMAP_DSS_COLOR_NV12 == color_mode) {
1996 _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
1997 _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
1998 }
1999
2000
80c39712
TV		 2001 _dispc_set_row_inc(plane, row_inc);
2002 _dispc_set_pix_inc(plane, pix_inc);
2003
2004 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
2005 out_width, out_height);
2006
2007 _dispc_set_plane_pos(plane, pos_x, pos_y);
2008
2009 _dispc_set_pic_size(plane, width, height);
2010
2011 if (plane != OMAP_DSS_GFX) {
2012 _dispc_set_scaling(plane, width, height,
2013 out_width, out_height,
0d66cbb5
AJ		 2014 ilace, five_taps, fieldmode,
2015 color_mode, rotation);
80c39712
TV		 2016 _dispc_set_vid_size(plane, out_width, out_height);
2017 _dispc_set_vid_color_conv(plane, cconv);
2018 }
2019
2020 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
2021
fd28a390
R		 2022 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
2023 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 2024
2025 return 0;
2026}
2027
e6d80f95 2028int dispc_enable_plane(enum omap_plane plane, bool enable)
80c39712 2029{
e6d80f95
TV		 2030 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2031
9b372c2d 2032 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2033
2034 return 0;
80c39712
TV		 2035}
2036
2037static void dispc_disable_isr(void *data, u32 mask)
2038{
2039 struct completion *compl = data;
2040 complete(compl);
2041}
2042
2a205f34 2043static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2044{
2a205f34
SS		 2045 if (channel == OMAP_DSS_CHANNEL_LCD2)
2046 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
2047 else
2048 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 2049}
2050
2a205f34 2051static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2052{
2053 struct completion frame_done_completion;
2054 bool is_on;
2055 int r;
2a205f34 2056 u32 irq;
80c39712 2057
80c39712
TV		 2058 /* When we disable LCD output, we need to wait until frame is done.
2059 * Otherwise the DSS is still working, and turning off the clocks
2060 * prevents DSS from going to OFF mode */
2a205f34
SS		 2061 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2062 REG_GET(DISPC_CONTROL2, 0, 0) :
2063 REG_GET(DISPC_CONTROL, 0, 0);
2064
2065 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2066 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2067
2068 if (!enable && is_on) {
2069 init_completion(&frame_done_completion);
2070
2071 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2072 &frame_done_completion, irq);
80c39712
TV		 2073
2074 if (r)
2075 DSSERR("failed to register FRAMEDONE isr\n");
2076 }
2077
2a205f34 2078 _enable_lcd_out(channel, enable);
80c39712
TV		 2079
2080 if (!enable && is_on) {
2081 if (!wait_for_completion_timeout(&frame_done_completion,
2082 msecs_to_jiffies(100)))
2083 DSSERR("timeout waiting for FRAME DONE\n");
2084
2085 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2086 &frame_done_completion, irq);
80c39712
TV		 2087
2088 if (r)
2089 DSSERR("failed to unregister FRAMEDONE isr\n");
2090 }
80c39712
TV		 2091}
2092
2093static void _enable_digit_out(bool enable)
2094{
2095 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2096}
2097
a2faee84 2098static void dispc_enable_digit_out(bool enable)
80c39712
TV		 2099{
2100 struct completion frame_done_completion;
2101 int r;
2102
e6d80f95 2103 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2104 return;
80c39712
TV		 2105
2106 if (enable) {
2107 unsigned long flags;
2108 /* When we enable digit output, we'll get an extra digit
2109 * sync lost interrupt, that we need to ignore */
2110 spin_lock_irqsave(&dispc.irq_lock, flags);
2111 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2112 _omap_dispc_set_irqs();
2113 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2114 }
2115
2116 /* When we disable digit output, we need to wait until fields are done.
2117 * Otherwise the DSS is still working, and turning off the clocks
2118 * prevents DSS from going to OFF mode. And when enabling, we need to
2119 * wait for the extra sync losts */
2120 init_completion(&frame_done_completion);
2121
2122 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2123 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
2124 if (r)
2125 DSSERR("failed to register EVSYNC isr\n");
2126
2127 _enable_digit_out(enable);
2128
2129 /* XXX I understand from TRM that we should only wait for the
2130 * current field to complete. But it seems we have to wait
2131 * for both fields */
2132 if (!wait_for_completion_timeout(&frame_done_completion,
2133 msecs_to_jiffies(100)))
2134 DSSERR("timeout waiting for EVSYNC\n");
2135
2136 if (!wait_for_completion_timeout(&frame_done_completion,
2137 msecs_to_jiffies(100)))
2138 DSSERR("timeout waiting for EVSYNC\n");
2139
2140 r = omap_dispc_unregister_isr(dispc_disable_isr,
2141 &frame_done_completion,
2142 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
2143 if (r)
2144 DSSERR("failed to unregister EVSYNC isr\n");
2145
2146 if (enable) {
2147 unsigned long flags;
2148 spin_lock_irqsave(&dispc.irq_lock, flags);
2149 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 2150 if (dss_has_feature(FEAT_MGR_LCD2))
2151 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 2152 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2153 _omap_dispc_set_irqs();
2154 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2155 }
80c39712
TV		 2156}
2157
a2faee84
TV		 2158bool dispc_is_channel_enabled(enum omap_channel channel)
2159{
2160 if (channel == OMAP_DSS_CHANNEL_LCD)
2161 return !!REG_GET(DISPC_CONTROL, 0, 0);
2162 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2163 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2164 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2165 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2166 else
2167 BUG();
2168}
2169
2170void dispc_enable_channel(enum omap_channel channel, bool enable)
2171{
2a205f34
SS		 2172 if (channel == OMAP_DSS_CHANNEL_LCD ||
2173 channel == OMAP_DSS_CHANNEL_LCD2)
2174 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 2175 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2176 dispc_enable_digit_out(enable);
2177 else
2178 BUG();
2179}
2180
80c39712
TV		 2181void dispc_lcd_enable_signal_polarity(bool act_high)
2182{
6ced40bf
AT		 2183 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2184 return;
2185
80c39712 2186 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2187}
2188
2189void dispc_lcd_enable_signal(bool enable)
2190{
6ced40bf
AT		 2191 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2192 return;
2193
80c39712 2194 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2195}
2196
2197void dispc_pck_free_enable(bool enable)
2198{
6ced40bf
AT		 2199 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2200 return;
2201
80c39712 2202 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2203}
2204
64ba4f74 2205void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2206{
2a205f34
SS		 2207 if (channel == OMAP_DSS_CHANNEL_LCD2)
2208 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2209 else
2210 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2211}
2212
2213
64ba4f74
SS		 2214void dispc_set_lcd_display_type(enum omap_channel channel,
2215 enum omap_lcd_display_type type)
80c39712
TV		 2216{
2217 int mode;
2218
2219 switch (type) {
2220 case OMAP_DSS_LCD_DISPLAY_STN:
2221 mode = 0;
2222 break;
2223
2224 case OMAP_DSS_LCD_DISPLAY_TFT:
2225 mode = 1;
2226 break;
2227
2228 default:
2229 BUG();
2230 return;
2231 }
2232
2a205f34
SS		 2233 if (channel == OMAP_DSS_CHANNEL_LCD2)
2234 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2235 else
2236 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2237}
2238
2239void dispc_set_loadmode(enum omap_dss_load_mode mode)
2240{
80c39712 2241 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2242}
2243
2244
2245void dispc_set_default_color(enum omap_channel channel, u32 color)
2246{
8613b000 2247 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2248}
2249
2250u32 dispc_get_default_color(enum omap_channel channel)
2251{
80c39712
TV		 2252 u32 l;
2253
2254 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2255 channel != OMAP_DSS_CHANNEL_LCD &&
2256 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712 2257
8613b000 2258 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2259
2260 return l;
2261}
2262
2263void dispc_set_trans_key(enum omap_channel ch,
2264 enum omap_dss_trans_key_type type,
2265 u32 trans_key)
2266{
80c39712
TV		 2267 if (ch == OMAP_DSS_CHANNEL_LCD)
2268 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2269 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2270 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2271 else /* OMAP_DSS_CHANNEL_LCD2 */
2272 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2273
8613b000 2274 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2275}
2276
2277void dispc_get_trans_key(enum omap_channel ch,
2278 enum omap_dss_trans_key_type *type,
2279 u32 *trans_key)
2280{
80c39712
TV		 2281 if (type) {
2282 if (ch == OMAP_DSS_CHANNEL_LCD)
2283 *type = REG_GET(DISPC_CONFIG, 11, 11);
2284 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2285 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2286 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2287 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2288 else
2289 BUG();
2290 }
2291
2292 if (trans_key)
8613b000 2293 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2294}
2295
2296void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2297{
80c39712
TV		 2298 if (ch == OMAP_DSS_CHANNEL_LCD)
2299 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2300 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2301 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2302 else /* OMAP_DSS_CHANNEL_LCD2 */
2303 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2304}
2305void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2306{
a0acb557 2307 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2308 return;
2309
80c39712
TV		 2310 if (ch == OMAP_DSS_CHANNEL_LCD)
2311 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2312 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2313 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2314 else /* OMAP_DSS_CHANNEL_LCD2 */
2315 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2316}
2317bool dispc_alpha_blending_enabled(enum omap_channel ch)
2318{
2319 bool enabled;
2320
a0acb557 2321 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2322 return false;
2323
80c39712
TV		 2324 if (ch == OMAP_DSS_CHANNEL_LCD)
2325 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2326 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2327 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2328 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2329 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2330 else
2331 BUG();
80c39712
TV		 2332
2333 return enabled;
80c39712
TV		 2334}
2335
2336
2337bool dispc_trans_key_enabled(enum omap_channel ch)
2338{
2339 bool enabled;
2340
80c39712
TV		 2341 if (ch == OMAP_DSS_CHANNEL_LCD)
2342 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2343 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2344 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2345 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2346 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2347 else
2348 BUG();
80c39712
TV		 2349
2350 return enabled;
2351}
2352
2353
64ba4f74 2354void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2355{
2356 int code;
2357
2358 switch (data_lines) {
2359 case 12:
2360 code = 0;
2361 break;
2362 case 16:
2363 code = 1;
2364 break;
2365 case 18:
2366 code = 2;
2367 break;
2368 case 24:
2369 code = 3;
2370 break;
2371 default:
2372 BUG();
2373 return;
2374 }
2375
2a205f34
SS		 2376 if (channel == OMAP_DSS_CHANNEL_LCD2)
2377 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2378 else
2379 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2380}
2381
64ba4f74
SS		 2382void dispc_set_parallel_interface_mode(enum omap_channel channel,
2383 enum omap_parallel_interface_mode mode)
80c39712
TV		 2384{
2385 u32 l;
2386 int stallmode;
2387 int gpout0 = 1;
2388 int gpout1;
2389
2390 switch (mode) {
2391 case OMAP_DSS_PARALLELMODE_BYPASS:
2392 stallmode = 0;
2393 gpout1 = 1;
2394 break;
2395
2396 case OMAP_DSS_PARALLELMODE_RFBI:
2397 stallmode = 1;
2398 gpout1 = 0;
2399 break;
2400
2401 case OMAP_DSS_PARALLELMODE_DSI:
2402 stallmode = 1;
2403 gpout1 = 1;
2404 break;
2405
2406 default:
2407 BUG();
2408 return;
2409 }
2410
2a205f34
SS		 2411 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2412 l = dispc_read_reg(DISPC_CONTROL2);
2413 l = FLD_MOD(l, stallmode, 11, 11);
2414 dispc_write_reg(DISPC_CONTROL2, l);
2415 } else {
2416 l = dispc_read_reg(DISPC_CONTROL);
2417 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2418 l = FLD_MOD(l, gpout0, 15, 15);
2419 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2420 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2421 }
80c39712
TV		 2422}
2423
2424static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2425 int vsw, int vfp, int vbp)
2426{
2427 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2428 if (hsw < 1 || hsw > 64 ||
2429 hfp < 1 || hfp > 256 ||
2430 hbp < 1 || hbp > 256 ||
2431 vsw < 1 || vsw > 64 ||
2432 vfp < 0 || vfp > 255 ||
2433 vbp < 0 || vbp > 255)
2434 return false;
2435 } else {
2436 if (hsw < 1 || hsw > 256 ||
2437 hfp < 1 || hfp > 4096 ||
2438 hbp < 1 || hbp > 4096 ||
2439 vsw < 1 || vsw > 256 ||
2440 vfp < 0 || vfp > 4095 ||
2441 vbp < 0 || vbp > 4095)
2442 return false;
2443 }
2444
2445 return true;
2446}
2447
2448bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2449{
2450 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2451 timings->hbp, timings->vsw,
2452 timings->vfp, timings->vbp);
2453}
2454
64ba4f74
SS		 2455static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2456 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2457{
2458 u32 timing_h, timing_v;
2459
2460 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2461 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2462 FLD_VAL(hbp-1, 27, 20);
2463
2464 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2465 FLD_VAL(vbp, 27, 20);
2466 } else {
2467 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2468 FLD_VAL(hbp-1, 31, 20);
2469
2470 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2471 FLD_VAL(vbp, 31, 20);
2472 }
2473
64ba4f74
SS		 2474 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2475 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2476}
2477
2478/* change name to mode? */
64ba4f74
SS		 2479void dispc_set_lcd_timings(enum omap_channel channel,
2480 struct omap_video_timings *timings)
80c39712
TV		 2481{
2482 unsigned xtot, ytot;
2483 unsigned long ht, vt;
2484
2485 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2486 timings->hbp, timings->vsw,
2487 timings->vfp, timings->vbp))
2488 BUG();
2489
64ba4f74
SS		 2490 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2491 timings->hbp, timings->vsw, timings->vfp,
2492 timings->vbp);
80c39712 2493
64ba4f74 2494 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2495
2496 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2497 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2498
2499 ht = (timings->pixel_clock * 1000) / xtot;
2500 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2501
2a205f34
SS		 2502 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2503 timings->y_res);
80c39712
TV		 2504 DSSDBG("pck %u\n", timings->pixel_clock);
2505 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2506 timings->hsw, timings->hfp, timings->hbp,
2507 timings->vsw, timings->vfp, timings->vbp);
2508
2509 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2510}
2511
ff1b2cde
SS		 2512static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2513 u16 pck_div)
80c39712
TV		 2514{
2515 BUG_ON(lck_div < 1);
2516 BUG_ON(pck_div < 2);
2517
ce7fa5eb 2518 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2519 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2520}
2521
2a205f34
SS		 2522static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2523 int *pck_div)
80c39712
TV		 2524{
2525 u32 l;
ce7fa5eb 2526 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2527 *lck_div = FLD_GET(l, 23, 16);
2528 *pck_div = FLD_GET(l, 7, 0);
2529}
2530
2531unsigned long dispc_fclk_rate(void)
2532{
a72b64b9 2533 struct platform_device *dsidev;
80c39712
TV		 2534 unsigned long r = 0;
2535
66534e8e 2536 switch (dss_get_dispc_clk_source()) {
89a35e51 2537 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2538 r = clk_get_rate(dispc.dss_clk);
66534e8e 2539 break;
89a35e51 2540 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2541 dsidev = dsi_get_dsidev_from_id(0);
2542 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2543 break;
5a8b572d
AT		 2544 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2545 dsidev = dsi_get_dsidev_from_id(1);
2546 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2547 break;
66534e8e
TA		 2548 default:
2549 BUG();
2550 }
2551
80c39712
TV		 2552 return r;
2553}
2554
ff1b2cde 2555unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712 2556{
a72b64b9 2557 struct platform_device *dsidev;
80c39712
TV		 2558 int lcd;
2559 unsigned long r;
2560 u32 l;
2561
ce7fa5eb 2562 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2563
2564 lcd = FLD_GET(l, 23, 16);
2565
ea75159e 2566 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2567 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2568 r = clk_get_rate(dispc.dss_clk);
ea75159e 2569 break;
89a35e51 2570 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2571 dsidev = dsi_get_dsidev_from_id(0);
2572 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2573 break;
5a8b572d
AT		 2574 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2575 dsidev = dsi_get_dsidev_from_id(1);
2576 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2577 break;
ea75159e
TA		 2578 default:
2579 BUG();
2580 }
80c39712
TV		 2581
2582 return r / lcd;
2583}
2584
ff1b2cde 2585unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712 2586{
ea75159e 2587 int pcd;
80c39712
TV		 2588 unsigned long r;
2589 u32 l;
2590
ce7fa5eb 2591 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2592
80c39712
TV		 2593 pcd = FLD_GET(l, 7, 0);
2594
ea75159e 2595 r = dispc_lclk_rate(channel);
80c39712 2596
ea75159e 2597 return r / pcd;
80c39712
TV		 2598}
2599
2600void dispc_dump_clocks(struct seq_file *s)
2601{
2602 int lcd, pcd;
0cf35df3 2603 u32 l;
89a35e51
AT		 2604 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2605 enum omap_dss_clk_source lcd_clk_src;
80c39712 2606
4fbafaf3
TV		 2607 if (dispc_runtime_get())
2608 return;
80c39712 2609
80c39712
TV		 2610 seq_printf(s, "- DISPC -\n");
2611
067a57e4
AT		 2612 seq_printf(s, "dispc fclk source = %s (%s)\n",
2613 dss_get_generic_clk_source_name(dispc_clk_src),
2614 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2615
2616 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2617
0cf35df3
MR		 2618 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2619 seq_printf(s, "- DISPC-CORE-CLK -\n");
2620 l = dispc_read_reg(DISPC_DIVISOR);
2621 lcd = FLD_GET(l, 23, 16);
2622
2623 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2624 (dispc_fclk_rate()/lcd), lcd);
2625 }
2a205f34
SS		 2626 seq_printf(s, "- LCD1 -\n");
2627
ea75159e
TA		 2628 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2629
2630 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2631 dss_get_generic_clk_source_name(lcd_clk_src),
2632 dss_feat_get_clk_source_name(lcd_clk_src));
2633
2a205f34
SS		 2634 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2635
ff1b2cde
SS		 2636 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2637 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2638 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2639 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2640 if (dss_has_feature(FEAT_MGR_LCD2)) {
2641 seq_printf(s, "- LCD2 -\n");
2642
ea75159e
TA		 2643 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2644
2645 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2646 dss_get_generic_clk_source_name(lcd_clk_src),
2647 dss_feat_get_clk_source_name(lcd_clk_src));
2648
2a205f34 2649 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2650
2a205f34
SS		 2651 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2652 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2653 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2654 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2655 }
4fbafaf3
TV		 2656
2657 dispc_runtime_put();
80c39712
TV		 2658}
2659
dfc0fd8d
TV		 2660#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2661void dispc_dump_irqs(struct seq_file *s)
2662{
2663 unsigned long flags;
2664 struct dispc_irq_stats stats;
2665
2666 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2667
2668 stats = dispc.irq_stats;
2669 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2670 dispc.irq_stats.last_reset = jiffies;
2671
2672 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2673
2674 seq_printf(s, "period %u ms\n",
2675 jiffies_to_msecs(jiffies - stats.last_reset));
2676
2677 seq_printf(s, "irqs %d\n", stats.irq_count);
2678#define PIS(x) \
2679 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2680
2681 PIS(FRAMEDONE);
2682 PIS(VSYNC);
2683 PIS(EVSYNC_EVEN);
2684 PIS(EVSYNC_ODD);
2685 PIS(ACBIAS_COUNT_STAT);
2686 PIS(PROG_LINE_NUM);
2687 PIS(GFX_FIFO_UNDERFLOW);
2688 PIS(GFX_END_WIN);
2689 PIS(PAL_GAMMA_MASK);
2690 PIS(OCP_ERR);
2691 PIS(VID1_FIFO_UNDERFLOW);
2692 PIS(VID1_END_WIN);
2693 PIS(VID2_FIFO_UNDERFLOW);
2694 PIS(VID2_END_WIN);
2695 PIS(SYNC_LOST);
2696 PIS(SYNC_LOST_DIGIT);
2697 PIS(WAKEUP);
2a205f34
SS		 2698 if (dss_has_feature(FEAT_MGR_LCD2)) {
2699 PIS(FRAMEDONE2);
2700 PIS(VSYNC2);
2701 PIS(ACBIAS_COUNT_STAT2);
2702 PIS(SYNC_LOST2);
2703 }
dfc0fd8d
TV		 2704#undef PIS
2705}
dfc0fd8d
TV		 2706#endif
2707
80c39712
TV		 2708void dispc_dump_regs(struct seq_file *s)
2709{
9b372c2d 2710#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2711
4fbafaf3
TV		 2712 if (dispc_runtime_get())
2713 return;
80c39712 2714
5010be80 2715 /* DISPC common registers */
80c39712
TV		 2716 DUMPREG(DISPC_REVISION);
2717 DUMPREG(DISPC_SYSCONFIG);
2718 DUMPREG(DISPC_SYSSTATUS);
2719 DUMPREG(DISPC_IRQSTATUS);
2720 DUMPREG(DISPC_IRQENABLE);
2721 DUMPREG(DISPC_CONTROL);
2722 DUMPREG(DISPC_CONFIG);
2723 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2724 DUMPREG(DISPC_LINE_STATUS);
2725 DUMPREG(DISPC_LINE_NUMBER);
332e9d70
TV		 2726 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2727 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2728 if (dss_has_feature(FEAT_MGR_LCD2)) {
2729 DUMPREG(DISPC_CONTROL2);
2730 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2731 }
2732
2733#undef DUMPREG
2734
2735#define DISPC_REG(i, name) name(i)
2736#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, #i, \
2737 48 - strlen(#r) - strlen(#i), " ", \
2738 dispc_read_reg(DISPC_REG(i, r)))
2739
2740 /* LCD registers */
2741 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DEFAULT_COLOR);
2742 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TRANS_COLOR);
2743 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TIMING_H);
2744 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_TIMING_V);
2745 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_POL_FREQ);
2746 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DIVISORo);
2747 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_SIZE_MGR);
2748
2749 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE1);
2750 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE2);
2751 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_DATA_CYCLE3);
80c39712 2752
332e9d70 2753 if (dss_has_feature(FEAT_CPR)) {
5010be80
AT		 2754 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_R);
2755 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_G);
2756 DUMPREG(OMAP_DSS_CHANNEL_LCD, DISPC_CPR_COEF_B);
332e9d70 2757 }
5010be80
AT		 2758
2759 /* DIGIT registers */
2760 DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_DEFAULT_COLOR);
2761 DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_TRANS_COLOR);
2762 DUMPREG(OMAP_DSS_CHANNEL_DIGIT, DISPC_SIZE_MGR);
2763
2764 /* LCD2 registers */
2a205f34 2765 if (dss_has_feature(FEAT_MGR_LCD2)) {
5010be80
AT		 2766 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DEFAULT_COLOR);
2767 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TRANS_COLOR);
2768 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TIMING_H);
2769 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_TIMING_V);
2770 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_POL_FREQ);
2771 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DIVISORo);
2772 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_SIZE_MGR);
2773
2774 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE1);
2775 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE2);
2776 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_DATA_CYCLE3);
2a205f34 2777
332e9d70 2778 if (dss_has_feature(FEAT_CPR)) {
5010be80
AT		 2779 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_R);
2780 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_G);
2781 DUMPREG(OMAP_DSS_CHANNEL_LCD2, DISPC_CPR_COEF_B);
332e9d70 2782 }
2a205f34 2783 }
80c39712 2784
5010be80
AT		 2785 /* GFX registers */
2786 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_BA0);
2787 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_BA1);
2788 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_POSITION);
2789 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_SIZE);
2790 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_ATTRIBUTES);
2791 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_FIFO_THRESHOLD);
2792 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_FIFO_SIZE_STATUS);
2793 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_ROW_INC);
2794 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_PIXEL_INC);
2795 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_WINDOW_SKIP);
2796 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_TABLE_BA);
332e9d70 2797 if (dss_has_feature(FEAT_PRELOAD))
5010be80
AT		 2798 DUMPREG(OMAP_DSS_GFX, DISPC_OVL_PRELOAD);
2799
2800 /* VIDEO1 registers */
2801 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA0);
2802 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA1);
2803 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_POSITION);
2804 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_SIZE);
2805 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ATTRIBUTES);
2806 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIFO_THRESHOLD);
2807 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIFO_SIZE_STATUS);
2808 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ROW_INC);
2809 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PIXEL_INC);
2810 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR);
2811 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PICTURE_SIZE);
2812 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU0);
2813 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU1);
2814 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2815 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA0_UV);
2816 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_BA1_UV);
2817 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR2);
2818 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU2_0);
2819 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ACCU2_1);
332e9d70 2820 }
5010be80
AT		 2821 if (dss_has_feature(FEAT_ATTR2))
2822 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_ATTRIBUTES2);
2823 if (dss_has_feature(FEAT_PRELOAD))
2824 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_PRELOAD);
2825
2826 /* VIDEO2 registers */
2827 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA0);
2828 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA1);
2829 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_POSITION);
2830 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_SIZE);
2831 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ATTRIBUTES);
2832 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIFO_THRESHOLD);
2833 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIFO_SIZE_STATUS);
2834 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ROW_INC);
2835 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PIXEL_INC);
2836 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR);
2837 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PICTURE_SIZE);
2838 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU0);
2839 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU1);
ab5ca071 2840 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
5010be80
AT		 2841 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA0_UV);
2842 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_BA1_UV);
2843 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR2);
2844 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU2_0);
2845 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ACCU2_1);
ab5ca071
AJ		 2846 }
2847 if (dss_has_feature(FEAT_ATTR2))
5010be80
AT		 2848 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_ATTRIBUTES2);
2849 if (dss_has_feature(FEAT_PRELOAD))
2850 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_PRELOAD);
2851
2852#undef DISPC_REG
2853#undef DUMPREG
2854
2855#define DISPC_REG(plane, name, i) name(plane, i)
2856#define DUMPREG(plane, name, i) \
2857 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, #plane, \
2858 46 - strlen(#name) - strlen(#plane), " ", \
2859 dispc_read_reg(DISPC_REG(plane, name, i)))
2860
2861 /* VIDEO1 coefficient registers */
2862 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 0);
2863 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 1);
2864 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 2);
2865 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 3);
2866 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 4);
2867 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 5);
2868 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 6);
2869 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H, 7);
2870
2871 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 0);
2872 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 1);
2873 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 2);
2874 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 3);
2875 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 4);
2876 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 5);
2877 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 6);
2878 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV, 7);
2879
2880 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 0);
2881 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 1);
2882 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 2);
2883 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 3);
2884 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_CONV_COEF, 4);
332e9d70
TV		 2885
2886 if (dss_has_feature(FEAT_FIR_COEF_V)) {
5010be80
AT		 2887 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 0);
2888 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 1);
2889 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 2);
2890 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 3);
2891 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 4);
2892 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 5);
2893 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 6);
2894 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V, 7);
332e9d70 2895 }
9b372c2d 2896
ab5ca071 2897 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
5010be80
AT		 2898 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 0);
2899 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 1);
2900 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 2);
2901 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 3);
2902 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 4);
2903 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 5);
2904 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 6);
2905 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_H2, 7);
2906
2907 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 0);
2908 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 1);
2909 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 2);
2910 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 3);
2911 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 4);
2912 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 5);
2913 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 6);
2914 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_HV2, 7);
2915
2916 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 0);
2917 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 1);
2918 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 2);
2919 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 3);
2920 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 4);
2921 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 5);
2922 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 6);
2923 DUMPREG(OMAP_DSS_VIDEO1, DISPC_OVL_FIR_COEF_V2, 7);
2924 }
2925
2926 /* VIDEO2 coefficient registers */
2927 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 0);
2928 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 1);
2929 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 2);
2930 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 3);
2931 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 4);
2932 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 5);
2933 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 6);
2934 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H, 7);
2935
2936 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 0);
2937 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 1);
2938 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 2);
2939 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 3);
2940 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 4);
2941 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 5);
2942 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 6);
2943 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV, 7);
2944
2945 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 0);
2946 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 1);
2947 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 2);
2948 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 3);
2949 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_CONV_COEF, 4);
2950 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2951 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 0);
2952 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 1);
2953 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 2);
2954 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 3);
2955 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 4);
2956 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 5);
2957 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 6);
2958 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V, 7);
ab5ca071 2959 }
ab5ca071 2960
5010be80
AT		 2961 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2962 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 0);
2963 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 1);
2964 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 2);
2965 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 3);
2966 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 4);
2967 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 5);
2968 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 6);
2969 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_H2, 7);
2970
2971 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 0);
2972 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 1);
2973 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 2);
2974 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 3);
2975 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 4);
2976 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 5);
2977 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 6);
2978 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_HV2, 7);
2979
2980 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 0);
2981 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 1);
2982 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 2);
2983 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 3);
2984 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 4);
2985 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 5);
2986 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 6);
2987 DUMPREG(OMAP_DSS_VIDEO2, DISPC_OVL_FIR_COEF_V2, 7);
332e9d70 2988 }
80c39712 2989
4fbafaf3 2990 dispc_runtime_put();
5010be80
AT		 2991
2992#undef DISPC_REG
80c39712
TV		 2993#undef DUMPREG
2994}
2995
ff1b2cde
SS		 2996static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2997 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2998{
2999 u32 l = 0;
3000
3001 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
3002 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
3003
3004 l |= FLD_VAL(onoff, 17, 17);
3005 l |= FLD_VAL(rf, 16, 16);
3006 l |= FLD_VAL(ieo, 15, 15);
3007 l |= FLD_VAL(ipc, 14, 14);
3008 l |= FLD_VAL(ihs, 13, 13);
3009 l |= FLD_VAL(ivs, 12, 12);
3010 l |= FLD_VAL(acbi, 11, 8);
3011 l |= FLD_VAL(acb, 7, 0);
3012
ff1b2cde 3013 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3014}
3015
ff1b2cde
SS		 3016void dispc_set_pol_freq(enum omap_channel channel,
3017 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 3018{
ff1b2cde 3019 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 3020 (config & OMAP_DSS_LCD_RF) != 0,
3021 (config & OMAP_DSS_LCD_IEO) != 0,
3022 (config & OMAP_DSS_LCD_IPC) != 0,
3023 (config & OMAP_DSS_LCD_IHS) != 0,
3024 (config & OMAP_DSS_LCD_IVS) != 0,
3025 acbi, acb);
3026}
3027
3028/* with fck as input clock rate, find dispc dividers that produce req_pck */
3029void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3030 struct dispc_clock_info *cinfo)
3031{
3032 u16 pcd_min = is_tft ? 2 : 3;
3033 unsigned long best_pck;
3034 u16 best_ld, cur_ld;
3035 u16 best_pd, cur_pd;
3036
3037 best_pck = 0;
3038 best_ld = 0;
3039 best_pd = 0;
3040
3041 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3042 unsigned long lck = fck / cur_ld;
3043
3044 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
3045 unsigned long pck = lck / cur_pd;
3046 long old_delta = abs(best_pck - req_pck);
3047 long new_delta = abs(pck - req_pck);
3048
3049 if (best_pck == 0 || new_delta < old_delta) {
3050 best_pck = pck;
3051 best_ld = cur_ld;
3052 best_pd = cur_pd;
3053
3054 if (pck == req_pck)
3055 goto found;
3056 }
3057
3058 if (pck < req_pck)
3059 break;
3060 }
3061
3062 if (lck / pcd_min < req_pck)
3063 break;
3064 }
3065
3066found:
3067 cinfo->lck_div = best_ld;
3068 cinfo->pck_div = best_pd;
3069 cinfo->lck = fck / cinfo->lck_div;
3070 cinfo->pck = cinfo->lck / cinfo->pck_div;
3071}
3072
3073/* calculate clock rates using dividers in cinfo */
3074int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3075 struct dispc_clock_info *cinfo)
3076{
3077 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3078 return -EINVAL;
3079 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
3080 return -EINVAL;
3081
3082 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3083 cinfo->pck = cinfo->lck / cinfo->pck_div;
3084
3085 return 0;
3086}
3087
ff1b2cde
SS		 3088int dispc_set_clock_div(enum omap_channel channel,
3089 struct dispc_clock_info *cinfo)
80c39712
TV		 3090{
3091 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3092 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3093
ff1b2cde 3094 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3095
3096 return 0;
3097}
3098
ff1b2cde
SS		 3099int dispc_get_clock_div(enum omap_channel channel,
3100 struct dispc_clock_info *cinfo)
80c39712
TV		 3101{
3102 unsigned long fck;
3103
3104 fck = dispc_fclk_rate();
3105
ce7fa5eb
MR		 3106 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3107 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3108
3109 cinfo->lck = fck / cinfo->lck_div;
3110 cinfo->pck = cinfo->lck / cinfo->pck_div;
3111
3112 return 0;
3113}
3114
3115/* dispc.irq_lock has to be locked by the caller */
3116static void _omap_dispc_set_irqs(void)
3117{
3118 u32 mask;
3119 u32 old_mask;
3120 int i;
3121 struct omap_dispc_isr_data *isr_data;
3122
3123 mask = dispc.irq_error_mask;
3124
3125 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3126 isr_data = &dispc.registered_isr[i];
3127
3128 if (isr_data->isr == NULL)
3129 continue;
3130
3131 mask |= isr_data->mask;
3132 }
3133
80c39712
TV		 3134 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3135 /* clear the irqstatus for newly enabled irqs */
3136 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3137
3138 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3139}
3140
3141int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3142{
3143 int i;
3144 int ret;
3145 unsigned long flags;
3146 struct omap_dispc_isr_data *isr_data;
3147
3148 if (isr == NULL)
3149 return -EINVAL;
3150
3151 spin_lock_irqsave(&dispc.irq_lock, flags);
3152
3153 /* check for duplicate entry */
3154 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3155 isr_data = &dispc.registered_isr[i];
3156 if (isr_data->isr == isr && isr_data->arg == arg &&
3157 isr_data->mask == mask) {
3158 ret = -EINVAL;
3159 goto err;
3160 }
3161 }
3162
3163 isr_data = NULL;
3164 ret = -EBUSY;
3165
3166 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3167 isr_data = &dispc.registered_isr[i];
3168
3169 if (isr_data->isr != NULL)
3170 continue;
3171
3172 isr_data->isr = isr;
3173 isr_data->arg = arg;
3174 isr_data->mask = mask;
3175 ret = 0;
3176
3177 break;
3178 }
3179
b9cb0984
TV		 3180 if (ret)
3181 goto err;
3182
80c39712
TV		 3183 _omap_dispc_set_irqs();
3184
3185 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3186
3187 return 0;
3188err:
3189 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3190
3191 return ret;
3192}
3193EXPORT_SYMBOL(omap_dispc_register_isr);
3194
3195int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3196{
3197 int i;
3198 unsigned long flags;
3199 int ret = -EINVAL;
3200 struct omap_dispc_isr_data *isr_data;
3201
3202 spin_lock_irqsave(&dispc.irq_lock, flags);
3203
3204 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3205 isr_data = &dispc.registered_isr[i];
3206 if (isr_data->isr != isr || isr_data->arg != arg ||
3207 isr_data->mask != mask)
3208 continue;
3209
3210 /* found the correct isr */
3211
3212 isr_data->isr = NULL;
3213 isr_data->arg = NULL;
3214 isr_data->mask = 0;
3215
3216 ret = 0;
3217 break;
3218 }
3219
3220 if (ret == 0)
3221 _omap_dispc_set_irqs();
3222
3223 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3224
3225 return ret;
3226}
3227EXPORT_SYMBOL(omap_dispc_unregister_isr);
3228
3229#ifdef DEBUG
3230static void print_irq_status(u32 status)
3231{
3232 if ((status & dispc.irq_error_mask) == 0)
3233 return;
3234
3235 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3236
3237#define PIS(x) \
3238 if (status & DISPC_IRQ_##x) \
3239 printk(#x " ");
3240 PIS(GFX_FIFO_UNDERFLOW);
3241 PIS(OCP_ERR);
3242 PIS(VID1_FIFO_UNDERFLOW);
3243 PIS(VID2_FIFO_UNDERFLOW);
3244 PIS(SYNC_LOST);
3245 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3246 if (dss_has_feature(FEAT_MGR_LCD2))
3247 PIS(SYNC_LOST2);
80c39712
TV		 3248#undef PIS
3249
3250 printk("\n");
3251}
3252#endif
3253
3254/* Called from dss.c. Note that we don't touch clocks here,
3255 * but we presume they are on because we got an IRQ. However,
3256 * an irq handler may turn the clocks off, so we may not have
3257 * clock later in the function. */
affe360d 3258static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3259{
3260 int i;
affe360d 3261 u32 irqstatus, irqenable;
80c39712
TV		 3262 u32 handledirqs = 0;
3263 u32 unhandled_errors;
3264 struct omap_dispc_isr_data *isr_data;
3265 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3266
3267 spin_lock(&dispc.irq_lock);
3268
3269 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3270 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3271
3272 /* IRQ is not for us */
3273 if (!(irqstatus & irqenable)) {
3274 spin_unlock(&dispc.irq_lock);
3275 return IRQ_NONE;
3276 }
80c39712 3277
dfc0fd8d
TV		 3278#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3279 spin_lock(&dispc.irq_stats_lock);
3280 dispc.irq_stats.irq_count++;
3281 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3282 spin_unlock(&dispc.irq_stats_lock);
3283#endif
3284
80c39712
TV		 3285#ifdef DEBUG
3286 if (dss_debug)
3287 print_irq_status(irqstatus);
3288#endif
3289 /* Ack the interrupt. Do it here before clocks are possibly turned
3290 * off */
3291 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3292 /* flush posted write */
3293 dispc_read_reg(DISPC_IRQSTATUS);
3294
3295 /* make a copy and unlock, so that isrs can unregister
3296 * themselves */
3297 memcpy(registered_isr, dispc.registered_isr,
3298 sizeof(registered_isr));
3299
3300 spin_unlock(&dispc.irq_lock);
3301
3302 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3303 isr_data = &registered_isr[i];
3304
3305 if (!isr_data->isr)
3306 continue;
3307
3308 if (isr_data->mask & irqstatus) {
3309 isr_data->isr(isr_data->arg, irqstatus);
3310 handledirqs |= isr_data->mask;
3311 }
3312 }
3313
3314 spin_lock(&dispc.irq_lock);
3315
3316 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3317
3318 if (unhandled_errors) {
3319 dispc.error_irqs |= unhandled_errors;
3320
3321 dispc.irq_error_mask &= ~unhandled_errors;
3322 _omap_dispc_set_irqs();
3323
3324 schedule_work(&dispc.error_work);
3325 }
3326
3327 spin_unlock(&dispc.irq_lock);
affe360d 3328
3329 return IRQ_HANDLED;
80c39712
TV		 3330}
3331
3332static void dispc_error_worker(struct work_struct *work)
3333{
3334 int i;
3335 u32 errors;
3336 unsigned long flags;
3337
3338 spin_lock_irqsave(&dispc.irq_lock, flags);
3339 errors = dispc.error_irqs;
3340 dispc.error_irqs = 0;
3341 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3342
13eae1f9
DZ		 3343 dispc_runtime_get();
3344
80c39712
TV		 3345 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
3346 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
3347 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3348 struct omap_overlay *ovl;
3349 ovl = omap_dss_get_overlay(i);
3350
3351 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3352 continue;
3353
3354 if (ovl->id == 0) {
3355 dispc_enable_plane(ovl->id, 0);
3356 dispc_go(ovl->manager->id);
3357 mdelay(50);
3358 break;
3359 }
3360 }
3361 }
3362
3363 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3364 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3365 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3366 struct omap_overlay *ovl;
3367 ovl = omap_dss_get_overlay(i);
3368
3369 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3370 continue;
3371
3372 if (ovl->id == 1) {
3373 dispc_enable_plane(ovl->id, 0);
3374 dispc_go(ovl->manager->id);
3375 mdelay(50);
3376 break;
3377 }
3378 }
3379 }
3380
3381 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3382 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3383 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3384 struct omap_overlay *ovl;
3385 ovl = omap_dss_get_overlay(i);
3386
3387 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3388 continue;
3389
3390 if (ovl->id == 2) {
3391 dispc_enable_plane(ovl->id, 0);
3392 dispc_go(ovl->manager->id);
3393 mdelay(50);
3394 break;
3395 }
3396 }
3397 }
3398
3399 if (errors & DISPC_IRQ_SYNC_LOST) {
3400 struct omap_overlay_manager *manager = NULL;
3401 bool enable = false;
3402
3403 DSSERR("SYNC_LOST, disabling LCD\n");
3404
3405 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3406 struct omap_overlay_manager *mgr;
3407 mgr = omap_dss_get_overlay_manager(i);
3408
3409 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3410 manager = mgr;
3411 enable = mgr->device->state ==
3412 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3413 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3414 break;
3415 }
3416 }
3417
3418 if (manager) {
37ac60e4 3419 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3420 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3421 struct omap_overlay *ovl;
3422 ovl = omap_dss_get_overlay(i);
3423
3424 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3425 continue;
3426
3427 if (ovl->id != 0 && ovl->manager == manager)
3428 dispc_enable_plane(ovl->id, 0);
3429 }
3430
3431 dispc_go(manager->id);
3432 mdelay(50);
3433 if (enable)
37ac60e4 3434 dssdev->driver->enable(dssdev);
80c39712
TV		 3435 }
3436 }
3437
3438 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3439 struct omap_overlay_manager *manager = NULL;
3440 bool enable = false;
3441
3442 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3443
3444 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3445 struct omap_overlay_manager *mgr;
3446 mgr = omap_dss_get_overlay_manager(i);
3447
3448 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3449 manager = mgr;
3450 enable = mgr->device->state ==
3451 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3452 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3453 break;
3454 }
3455 }
3456
3457 if (manager) {
37ac60e4 3458 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3459 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3460 struct omap_overlay *ovl;
3461 ovl = omap_dss_get_overlay(i);
3462
3463 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3464 continue;
3465
3466 if (ovl->id != 0 && ovl->manager == manager)
3467 dispc_enable_plane(ovl->id, 0);
3468 }
3469
3470 dispc_go(manager->id);
3471 mdelay(50);
3472 if (enable)
37ac60e4 3473 dssdev->driver->enable(dssdev);
80c39712
TV		 3474 }
3475 }
3476
2a205f34
SS		 3477 if (errors & DISPC_IRQ_SYNC_LOST2) {
3478 struct omap_overlay_manager *manager = NULL;
3479 bool enable = false;
3480
3481 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3482
3483 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3484 struct omap_overlay_manager *mgr;
3485 mgr = omap_dss_get_overlay_manager(i);
3486
3487 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3488 manager = mgr;
3489 enable = mgr->device->state ==
3490 OMAP_DSS_DISPLAY_ACTIVE;
3491 mgr->device->driver->disable(mgr->device);
3492 break;
3493 }
3494 }
3495
3496 if (manager) {
3497 struct omap_dss_device *dssdev = manager->device;
3498 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3499 struct omap_overlay *ovl;
3500 ovl = omap_dss_get_overlay(i);
3501
3502 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3503 continue;
3504
3505 if (ovl->id != 0 && ovl->manager == manager)
3506 dispc_enable_plane(ovl->id, 0);
3507 }
3508
3509 dispc_go(manager->id);
3510 mdelay(50);
3511 if (enable)
3512 dssdev->driver->enable(dssdev);
3513 }
3514 }
3515
80c39712
TV		 3516 if (errors & DISPC_IRQ_OCP_ERR) {
3517 DSSERR("OCP_ERR\n");
3518 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3519 struct omap_overlay_manager *mgr;
3520 mgr = omap_dss_get_overlay_manager(i);
3521
3522 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3523 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3524 }
3525 }
3526
3527 spin_lock_irqsave(&dispc.irq_lock, flags);
3528 dispc.irq_error_mask |= errors;
3529 _omap_dispc_set_irqs();
3530 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3531
3532 dispc_runtime_put();
80c39712
TV		 3533}
3534
3535int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3536{
3537 void dispc_irq_wait_handler(void *data, u32 mask)
3538 {
3539 complete((struct completion *)data);
3540 }
3541
3542 int r;
3543 DECLARE_COMPLETION_ONSTACK(completion);
3544
3545 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3546 irqmask);
3547
3548 if (r)
3549 return r;
3550
3551 timeout = wait_for_completion_timeout(&completion, timeout);
3552
3553 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3554
3555 if (timeout == 0)
3556 return -ETIMEDOUT;
3557
3558 if (timeout == -ERESTARTSYS)
3559 return -ERESTARTSYS;
3560
3561 return 0;
3562}
3563
3564int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3565 unsigned long timeout)
3566{
3567 void dispc_irq_wait_handler(void *data, u32 mask)
3568 {
3569 complete((struct completion *)data);
3570 }
3571
3572 int r;
3573 DECLARE_COMPLETION_ONSTACK(completion);
3574
3575 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3576 irqmask);
3577
3578 if (r)
3579 return r;
3580
3581 timeout = wait_for_completion_interruptible_timeout(&completion,
3582 timeout);
3583
3584 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3585
3586 if (timeout == 0)
3587 return -ETIMEDOUT;
3588
3589 if (timeout == -ERESTARTSYS)
3590 return -ERESTARTSYS;
3591
3592 return 0;
3593}
3594
3595#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3596void dispc_fake_vsync_irq(void)
3597{
3598 u32 irqstatus = DISPC_IRQ_VSYNC;
3599 int i;
3600
ab83b14c 3601 WARN_ON(!in_interrupt());
80c39712
TV		 3602
3603 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3604 struct omap_dispc_isr_data *isr_data;
3605 isr_data = &dispc.registered_isr[i];
3606
3607 if (!isr_data->isr)
3608 continue;
3609
3610 if (isr_data->mask & irqstatus)
3611 isr_data->isr(isr_data->arg, irqstatus);
3612 }
80c39712
TV		 3613}
3614#endif
3615
3616static void _omap_dispc_initialize_irq(void)
3617{
3618 unsigned long flags;
3619
3620 spin_lock_irqsave(&dispc.irq_lock, flags);
3621
3622 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3623
3624 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3625 if (dss_has_feature(FEAT_MGR_LCD2))
3626 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3627
3628 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3629 * so clear it */
3630 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3631
3632 _omap_dispc_set_irqs();
3633
3634 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3635}
3636
3637void dispc_enable_sidle(void)
3638{
3639 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3640}
3641
3642void dispc_disable_sidle(void)
3643{
3644 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3645}
3646
3647static void _omap_dispc_initial_config(void)
3648{
3649 u32 l;
3650
0cf35df3
MR		 3651 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3652 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3653 l = dispc_read_reg(DISPC_DIVISOR);
3654 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3655 l = FLD_MOD(l, 1, 0, 0);
3656 l = FLD_MOD(l, 1, 23, 16);
3657 dispc_write_reg(DISPC_DIVISOR, l);
3658 }
3659
80c39712 3660 /* FUNCGATED */
6ced40bf
AT		 3661 if (dss_has_feature(FEAT_FUNCGATED))
3662 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3663
3664 /* L3 firewall setting: enable access to OCM RAM */
3665 /* XXX this should be somewhere in plat-omap */
3666 if (cpu_is_omap24xx())
3667 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3668
3669 _dispc_setup_color_conv_coef();
3670
3671 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3672
3673 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3674
3675 dispc_configure_burst_sizes();
80c39712
TV		 3676}
3677
060b6d9c
SG		 3678/* DISPC HW IP initialisation */
3679static int omap_dispchw_probe(struct platform_device *pdev)
3680{
3681 u32 rev;
affe360d 3682 int r = 0;
ea9da36a 3683 struct resource *dispc_mem;
4fbafaf3 3684 struct clk *clk;
ea9da36a 3685
060b6d9c
SG		 3686 dispc.pdev = pdev;
3687
4fbafaf3
TV		 3688 clk = clk_get(&pdev->dev, "fck");
3689 if (IS_ERR(clk)) {
3690 DSSERR("can't get fck\n");
3691 r = PTR_ERR(clk);
3692 goto err_get_clk;
3693 }
3694
3695 dispc.dss_clk = clk;
3696
060b6d9c
SG		 3697 spin_lock_init(&dispc.irq_lock);
3698
3699#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3700 spin_lock_init(&dispc.irq_stats_lock);
3701 dispc.irq_stats.last_reset = jiffies;
3702#endif
3703
3704 INIT_WORK(&dispc.error_work, dispc_error_worker);
3705
ea9da36a
SG		 3706 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3707 if (!dispc_mem) {
3708 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3709 r = -EINVAL;
4fbafaf3 3710 goto err_ioremap;
ea9da36a
SG		 3711 }
3712 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3713 if (!dispc.base) {
3714 DSSERR("can't ioremap DISPC\n");
affe360d 3715 r = -ENOMEM;
4fbafaf3 3716 goto err_ioremap;
affe360d 3717 }
3718 dispc.irq = platform_get_irq(dispc.pdev, 0);
3719 if (dispc.irq < 0) {
3720 DSSERR("platform_get_irq failed\n");
3721 r = -ENODEV;
4fbafaf3 3722 goto err_irq;
affe360d 3723 }
3724
3725 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3726 "OMAP DISPC", dispc.pdev);
3727 if (r < 0) {
3728 DSSERR("request_irq failed\n");
4fbafaf3 3729 goto err_irq;
060b6d9c
SG		 3730 }
3731
4fbafaf3
TV		 3732 pm_runtime_enable(&pdev->dev);
3733
3734 r = dispc_runtime_get();
3735 if (r)
3736 goto err_runtime_get;
060b6d9c
SG		 3737
3738 _omap_dispc_initial_config();
3739
3740 _omap_dispc_initialize_irq();
3741
060b6d9c 3742 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3743 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3744 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3745
4fbafaf3 3746 dispc_runtime_put();
060b6d9c
SG		 3747
3748 return 0;
4fbafaf3
TV		 3749
3750err_runtime_get:
3751 pm_runtime_disable(&pdev->dev);
3752 free_irq(dispc.irq, dispc.pdev);
3753err_irq:
affe360d 3754 iounmap(dispc.base);
4fbafaf3
TV		 3755err_ioremap:
3756 clk_put(dispc.dss_clk);
3757err_get_clk:
affe360d 3758 return r;
060b6d9c
SG		 3759}
3760
3761static int omap_dispchw_remove(struct platform_device *pdev)
3762{
4fbafaf3
TV		 3763 pm_runtime_disable(&pdev->dev);
3764
3765 clk_put(dispc.dss_clk);
3766
affe360d 3767 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3768 iounmap(dispc.base);
3769 return 0;
3770}
3771
4fbafaf3
TV		 3772static int dispc_runtime_suspend(struct device *dev)
3773{
3774 dispc_save_context();
3775 clk_disable(dispc.dss_clk);
3776 dss_runtime_put();
3777
3778 return 0;
3779}
3780
3781static int dispc_runtime_resume(struct device *dev)
3782{
3783 int r;
3784
3785 r = dss_runtime_get();
3786 if (r < 0)
3787 return r;
3788
3789 clk_enable(dispc.dss_clk);
49ea86f3 3790 dispc_restore_context();
4fbafaf3
TV		 3791
3792 return 0;
3793}
3794
3795static const struct dev_pm_ops dispc_pm_ops = {
3796 .runtime_suspend = dispc_runtime_suspend,
3797 .runtime_resume = dispc_runtime_resume,
3798};
3799
060b6d9c
SG		 3800static struct platform_driver omap_dispchw_driver = {
3801 .probe = omap_dispchw_probe,
3802 .remove = omap_dispchw_remove,
3803 .driver = {
3804 .name = "omapdss_dispc",
3805 .owner = THIS_MODULE,
4fbafaf3 3806 .pm = &dispc_pm_ops,
060b6d9c
SG		 3807 },
3808};
3809
3810int dispc_init_platform_driver(void)
3811{
3812 return platform_driver_register(&omap_dispchw_driver);
3813}
3814
3815void dispc_uninit_platform_driver(void)
3816{
3817 return platform_driver_unregister(&omap_dispchw_driver);
3818}
Linux kernel - Deliverables
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