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OMAPDSS: DISPC: Configure overlay-like parameters in dispc_wb_setup
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
a0b38cc4 40#include <video/omapdss.h>
80c39712
TV		 41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
9b372c2d 44#include "dispc.h"
80c39712
TV		 45
46/* DISPC */
8613b000 47#define DISPC_SZ_REGS SZ_4K
80c39712 48
80c39712
TV		 49#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
50 DISPC_IRQ_OCP_ERR | \
51 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
52 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
53 DISPC_IRQ_SYNC_LOST | \
54 DISPC_IRQ_SYNC_LOST_DIGIT)
55
56#define DISPC_MAX_NR_ISRS 8
57
58struct omap_dispc_isr_data {
59 omap_dispc_isr_t isr;
60 void *arg;
61 u32 mask;
62};
63
5ed8cf5b
TV		 64enum omap_burst_size {
65 BURST_SIZE_X2 = 0,
66 BURST_SIZE_X4 = 1,
67 BURST_SIZE_X8 = 2,
68};
69
80c39712
TV		 70#define REG_GET(idx, start, end) \
71 FLD_GET(dispc_read_reg(idx), start, end)
72
73#define REG_FLD_MOD(idx, val, start, end) \
74 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
75
dfc0fd8d
TV		 76struct dispc_irq_stats {
77 unsigned long last_reset;
78 unsigned irq_count;
79 unsigned irqs[32];
80};
81
dcbe765b
CM		 82struct dispc_features {
83 u8 sw_start;
84 u8 fp_start;
85 u8 bp_start;
86 u16 sw_max;
87 u16 vp_max;
88 u16 hp_max;
3e8a6ff2 89 int (*calc_scaling) (enum omap_plane plane,
dcbe765b
CM		 90 const struct omap_video_timings *mgr_timings,
91 u16 width, u16 height, u16 out_width, u16 out_height,
92 enum omap_color_mode color_mode, bool *five_taps,
93 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 94 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
3e8a6ff2 95 unsigned long (*calc_core_clk) (enum omap_plane plane,
8ba85306
AT		 96 u16 width, u16 height, u16 out_width, u16 out_height,
97 bool mem_to_mem);
42a6961c 98 u8 num_fifos;
66a0f9e4
TV		 99
100 /* swap GFX & WB fifos */
101 bool gfx_fifo_workaround:1;
dcbe765b
CM		 102};
103
42a6961c
TV		 104#define DISPC_MAX_NR_FIFOS 5
105
80c39712 106static struct {
060b6d9c 107 struct platform_device *pdev;
80c39712 108 void __iomem *base;
4fbafaf3
TV		 109
110 int ctx_loss_cnt;
111
affe360d 112 int irq;
4fbafaf3 113 struct clk *dss_clk;
80c39712 114
42a6961c
TV		 115 u32 fifo_size[DISPC_MAX_NR_FIFOS];
116 /* maps which plane is using a fifo. fifo-id -> plane-id */
117 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712
TV		 118
119 spinlock_t irq_lock;
120 u32 irq_error_mask;
121 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
122 u32 error_irqs;
123 struct work_struct error_work;
124
49ea86f3 125 bool ctx_valid;
80c39712 126 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 127
dcbe765b
CM		 128 const struct dispc_features *feat;
129
dfc0fd8d
TV		 130#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
131 spinlock_t irq_stats_lock;
132 struct dispc_irq_stats irq_stats;
133#endif
80c39712
TV		 134} dispc;
135
0d66cbb5
AJ		 136enum omap_color_component {
137 /* used for all color formats for OMAP3 and earlier
138 * and for RGB and Y color component on OMAP4
139 */
140 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
141 /* used for UV component for
142 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
143 * color formats on OMAP4
144 */
145 DISPC_COLOR_COMPONENT_UV = 1 << 1,
146};
147
efa70b3b
CM		 148enum mgr_reg_fields {
149 DISPC_MGR_FLD_ENABLE,
150 DISPC_MGR_FLD_STNTFT,
151 DISPC_MGR_FLD_GO,
152 DISPC_MGR_FLD_TFTDATALINES,
153 DISPC_MGR_FLD_STALLMODE,
154 DISPC_MGR_FLD_TCKENABLE,
155 DISPC_MGR_FLD_TCKSELECTION,
156 DISPC_MGR_FLD_CPR,
157 DISPC_MGR_FLD_FIFOHANDCHECK,
158 /* used to maintain a count of the above fields */
159 DISPC_MGR_FLD_NUM,
160};
161
162static const struct {
163 const char *name;
164 u32 vsync_irq;
165 u32 framedone_irq;
166 u32 sync_lost_irq;
167 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
168} mgr_desc[] = {
169 [OMAP_DSS_CHANNEL_LCD] = {
170 .name = "LCD",
171 .vsync_irq = DISPC_IRQ_VSYNC,
172 .framedone_irq = DISPC_IRQ_FRAMEDONE,
173 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
174 .reg_desc = {
175 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
176 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
177 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
178 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
179 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
180 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
181 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
182 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
183 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
184 },
185 },
186 [OMAP_DSS_CHANNEL_DIGIT] = {
187 .name = "DIGIT",
188 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
189 .framedone_irq = 0,
190 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
191 .reg_desc = {
192 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
193 [DISPC_MGR_FLD_STNTFT] = { },
194 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
195 [DISPC_MGR_FLD_TFTDATALINES] = { },
196 [DISPC_MGR_FLD_STALLMODE] = { },
197 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
198 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
199 [DISPC_MGR_FLD_CPR] = { },
200 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
201 },
202 },
203 [OMAP_DSS_CHANNEL_LCD2] = {
204 .name = "LCD2",
205 .vsync_irq = DISPC_IRQ_VSYNC2,
206 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
207 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
208 .reg_desc = {
209 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
210 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
211 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
212 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
213 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
214 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
215 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
216 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
217 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
218 },
219 },
e86d456a
CM		 220 [OMAP_DSS_CHANNEL_LCD3] = {
221 .name = "LCD3",
222 .vsync_irq = DISPC_IRQ_VSYNC3,
223 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
224 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
225 .reg_desc = {
226 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
227 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
228 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
229 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
230 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
231 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
232 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
233 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
234 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
235 },
236 },
efa70b3b
CM		 237};
238
80c39712 239static void _omap_dispc_set_irqs(void);
3e8a6ff2
AT		 240static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
241static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 242
55978cc2 243static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 244{
55978cc2 245 __raw_writel(val, dispc.base + idx);
80c39712
TV		 246}
247
55978cc2 248static inline u32 dispc_read_reg(const u16 idx)
80c39712 249{
55978cc2 250 return __raw_readl(dispc.base + idx);
80c39712
TV		 251}
252
efa70b3b
CM		 253static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
254{
255 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
256 return REG_GET(rfld.reg, rfld.high, rfld.low);
257}
258
259static void mgr_fld_write(enum omap_channel channel,
260 enum mgr_reg_fields regfld, int val) {
261 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
262 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
263}
264
80c39712 265#define SR(reg) \
55978cc2 266 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 267#define RR(reg) \
55978cc2 268 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 269
4fbafaf3 270static void dispc_save_context(void)
80c39712 271{
c6104b8e 272 int i, j;
80c39712 273
4fbafaf3
TV		 274 DSSDBG("dispc_save_context\n");
275
80c39712
TV		 276 SR(IRQENABLE);
277 SR(CONTROL);
278 SR(CONFIG);
80c39712 279 SR(LINE_NUMBER);
11354dd5
AT		 280 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
281 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 282 SR(GLOBAL_ALPHA);
2a205f34
SS		 283 if (dss_has_feature(FEAT_MGR_LCD2)) {
284 SR(CONTROL2);
2a205f34
SS		 285 SR(CONFIG2);
286 }
e86d456a
CM		 287 if (dss_has_feature(FEAT_MGR_LCD3)) {
288 SR(CONTROL3);
289 SR(CONFIG3);
290 }
80c39712 291
c6104b8e
AT		 292 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
293 SR(DEFAULT_COLOR(i));
294 SR(TRANS_COLOR(i));
295 SR(SIZE_MGR(i));
296 if (i == OMAP_DSS_CHANNEL_DIGIT)
297 continue;
298 SR(TIMING_H(i));
299 SR(TIMING_V(i));
300 SR(POL_FREQ(i));
301 SR(DIVISORo(i));
302
303 SR(DATA_CYCLE1(i));
304 SR(DATA_CYCLE2(i));
305 SR(DATA_CYCLE3(i));
306
332e9d70 307 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 308 SR(CPR_COEF_R(i));
309 SR(CPR_COEF_G(i));
310 SR(CPR_COEF_B(i));
332e9d70 311 }
2a205f34 312 }
80c39712 313
c6104b8e
AT		 314 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
315 SR(OVL_BA0(i));
316 SR(OVL_BA1(i));
317 SR(OVL_POSITION(i));
318 SR(OVL_SIZE(i));
319 SR(OVL_ATTRIBUTES(i));
320 SR(OVL_FIFO_THRESHOLD(i));
321 SR(OVL_ROW_INC(i));
322 SR(OVL_PIXEL_INC(i));
323 if (dss_has_feature(FEAT_PRELOAD))
324 SR(OVL_PRELOAD(i));
325 if (i == OMAP_DSS_GFX) {
326 SR(OVL_WINDOW_SKIP(i));
327 SR(OVL_TABLE_BA(i));
328 continue;
329 }
330 SR(OVL_FIR(i));
331 SR(OVL_PICTURE_SIZE(i));
332 SR(OVL_ACCU0(i));
333 SR(OVL_ACCU1(i));
9b372c2d 334
c6104b8e
AT		 335 for (j = 0; j < 8; j++)
336 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 337
c6104b8e
AT		 338 for (j = 0; j < 8; j++)
339 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 340
c6104b8e
AT		 341 for (j = 0; j < 5; j++)
342 SR(OVL_CONV_COEF(i, j));
ab5ca071 343
c6104b8e
AT		 344 if (dss_has_feature(FEAT_FIR_COEF_V)) {
345 for (j = 0; j < 8; j++)
346 SR(OVL_FIR_COEF_V(i, j));
347 }
9b372c2d 348
c6104b8e
AT		 349 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
350 SR(OVL_BA0_UV(i));
351 SR(OVL_BA1_UV(i));
352 SR(OVL_FIR2(i));
353 SR(OVL_ACCU2_0(i));
354 SR(OVL_ACCU2_1(i));
ab5ca071 355
c6104b8e
AT		 356 for (j = 0; j < 8; j++)
357 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 358
c6104b8e
AT		 359 for (j = 0; j < 8; j++)
360 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 361
c6104b8e
AT		 362 for (j = 0; j < 8; j++)
363 SR(OVL_FIR_COEF_V2(i, j));
364 }
365 if (dss_has_feature(FEAT_ATTR2))
366 SR(OVL_ATTRIBUTES2(i));
ab5ca071 367 }
0cf35df3
MR		 368
369 if (dss_has_feature(FEAT_CORE_CLK_DIV))
370 SR(DIVISOR);
49ea86f3 371
00928eaf 372 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 373 dispc.ctx_valid = true;
374
375 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 376}
377
4fbafaf3 378static void dispc_restore_context(void)
80c39712 379{
c6104b8e 380 int i, j, ctx;
4fbafaf3
TV		 381
382 DSSDBG("dispc_restore_context\n");
383
49ea86f3
TV		 384 if (!dispc.ctx_valid)
385 return;
386
00928eaf 387 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 388
389 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
390 return;
391
392 DSSDBG("ctx_loss_count: saved %d, current %d\n",
393 dispc.ctx_loss_cnt, ctx);
394
75c7d59d 395 /*RR(IRQENABLE);*/
80c39712
TV		 396 /*RR(CONTROL);*/
397 RR(CONFIG);
80c39712 398 RR(LINE_NUMBER);
11354dd5
AT		 399 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
400 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 401 RR(GLOBAL_ALPHA);
c6104b8e 402 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 403 RR(CONFIG2);
e86d456a
CM		 404 if (dss_has_feature(FEAT_MGR_LCD3))
405 RR(CONFIG3);
80c39712 406
c6104b8e
AT		 407 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
408 RR(DEFAULT_COLOR(i));
409 RR(TRANS_COLOR(i));
410 RR(SIZE_MGR(i));
411 if (i == OMAP_DSS_CHANNEL_DIGIT)
412 continue;
413 RR(TIMING_H(i));
414 RR(TIMING_V(i));
415 RR(POL_FREQ(i));
416 RR(DIVISORo(i));
417
418 RR(DATA_CYCLE1(i));
419 RR(DATA_CYCLE2(i));
420 RR(DATA_CYCLE3(i));
2a205f34 421
332e9d70 422 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 423 RR(CPR_COEF_R(i));
424 RR(CPR_COEF_G(i));
425 RR(CPR_COEF_B(i));
332e9d70 426 }
2a205f34 427 }
80c39712 428
c6104b8e
AT		 429 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
430 RR(OVL_BA0(i));
431 RR(OVL_BA1(i));
432 RR(OVL_POSITION(i));
433 RR(OVL_SIZE(i));
434 RR(OVL_ATTRIBUTES(i));
435 RR(OVL_FIFO_THRESHOLD(i));
436 RR(OVL_ROW_INC(i));
437 RR(OVL_PIXEL_INC(i));
438 if (dss_has_feature(FEAT_PRELOAD))
439 RR(OVL_PRELOAD(i));
440 if (i == OMAP_DSS_GFX) {
441 RR(OVL_WINDOW_SKIP(i));
442 RR(OVL_TABLE_BA(i));
443 continue;
444 }
445 RR(OVL_FIR(i));
446 RR(OVL_PICTURE_SIZE(i));
447 RR(OVL_ACCU0(i));
448 RR(OVL_ACCU1(i));
9b372c2d 449
c6104b8e
AT		 450 for (j = 0; j < 8; j++)
451 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 452
c6104b8e
AT		 453 for (j = 0; j < 8; j++)
454 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 455
c6104b8e
AT		 456 for (j = 0; j < 5; j++)
457 RR(OVL_CONV_COEF(i, j));
ab5ca071 458
c6104b8e
AT		 459 if (dss_has_feature(FEAT_FIR_COEF_V)) {
460 for (j = 0; j < 8; j++)
461 RR(OVL_FIR_COEF_V(i, j));
462 }
9b372c2d 463
c6104b8e
AT		 464 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
465 RR(OVL_BA0_UV(i));
466 RR(OVL_BA1_UV(i));
467 RR(OVL_FIR2(i));
468 RR(OVL_ACCU2_0(i));
469 RR(OVL_ACCU2_1(i));
ab5ca071 470
c6104b8e
AT		 471 for (j = 0; j < 8; j++)
472 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 473
c6104b8e
AT		 474 for (j = 0; j < 8; j++)
475 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 476
c6104b8e
AT		 477 for (j = 0; j < 8; j++)
478 RR(OVL_FIR_COEF_V2(i, j));
479 }
480 if (dss_has_feature(FEAT_ATTR2))
481 RR(OVL_ATTRIBUTES2(i));
ab5ca071 482 }
80c39712 483
0cf35df3
MR		 484 if (dss_has_feature(FEAT_CORE_CLK_DIV))
485 RR(DIVISOR);
486
80c39712
TV		 487 /* enable last, because LCD & DIGIT enable are here */
488 RR(CONTROL);
2a205f34
SS		 489 if (dss_has_feature(FEAT_MGR_LCD2))
490 RR(CONTROL2);
e86d456a
CM		 491 if (dss_has_feature(FEAT_MGR_LCD3))
492 RR(CONTROL3);
75c7d59d
VS		 493 /* clear spurious SYNC_LOST_DIGIT interrupts */
494 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
495
496 /*
497 * enable last so IRQs won't trigger before
498 * the context is fully restored
499 */
500 RR(IRQENABLE);
49ea86f3
TV		 501
502 DSSDBG("context restored\n");
80c39712
TV		 503}
504
505#undef SR
506#undef RR
507
4fbafaf3
TV		 508int dispc_runtime_get(void)
509{
510 int r;
511
512 DSSDBG("dispc_runtime_get\n");
513
514 r = pm_runtime_get_sync(&dispc.pdev->dev);
515 WARN_ON(r < 0);
516 return r < 0 ? r : 0;
517}
518
519void dispc_runtime_put(void)
520{
521 int r;
522
523 DSSDBG("dispc_runtime_put\n");
524
0eaf9f52 525 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 526 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 527}
528
3dcec4d6
TV		 529u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
530{
efa70b3b 531 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 532}
533
7d1365c9
TV		 534u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
535{
efa70b3b 536 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 537}
538
26d9dd0d 539bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 540{
efa70b3b 541 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 542}
543
26d9dd0d 544void dispc_mgr_go(enum omap_channel channel)
80c39712 545{
2a205f34 546 bool enable_bit, go_bit;
80c39712 547
80c39712 548 /* if the channel is not enabled, we don't need GO */
efa70b3b 549 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
2a205f34
SS		 550
551 if (!enable_bit)
e6d80f95 552 return;
80c39712 553
efa70b3b 554 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
2a205f34
SS		 555
556 if (go_bit) {
80c39712 557 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 558 return;
80c39712
TV		 559 }
560
efa70b3b 561 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 562
efa70b3b 563 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 564}
565
f0e5caab 566static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 567{
9b372c2d 568 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 569}
570
f0e5caab 571static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 572{
9b372c2d 573 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 574}
575
f0e5caab 576static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 577{
9b372c2d 578 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 579}
580
f0e5caab 581static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 582{
583 BUG_ON(plane == OMAP_DSS_GFX);
584
585 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
586}
587
f0e5caab
TV		 588static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
589 u32 value)
ab5ca071
AJ		 590{
591 BUG_ON(plane == OMAP_DSS_GFX);
592
593 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
594}
595
f0e5caab 596static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 597{
598 BUG_ON(plane == OMAP_DSS_GFX);
599
600 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
601}
602
debd9074
CM		 603static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
604 int fir_vinc, int five_taps,
605 enum omap_color_component color_comp)
80c39712 606{
debd9074 607 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 608 int i;
609
debd9074
CM		 610 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
611 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 612
613 for (i = 0; i < 8; i++) {
614 u32 h, hv;
615
debd9074
CM		 616 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
617 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
618 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
619 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
620 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
621 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
622 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
623 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 624
0d66cbb5 625 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 626 dispc_ovl_write_firh_reg(plane, i, h);
627 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 628 } else {
f0e5caab
TV		 629 dispc_ovl_write_firh2_reg(plane, i, h);
630 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 631 }
632
80c39712
TV		 633 }
634
66be8f6c
GI		 635 if (five_taps) {
636 for (i = 0; i < 8; i++) {
637 u32 v;
debd9074
CM		 638 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
639 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 640 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 641 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 642 else
f0e5caab 643 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 644 }
80c39712
TV		 645 }
646}
647
648static void _dispc_setup_color_conv_coef(void)
649{
ac01c29e 650 int i;
80c39712
TV		 651 const struct color_conv_coef {
652 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
653 int full_range;
654 } ctbl_bt601_5 = {
655 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
656 };
657
658 const struct color_conv_coef *ct;
659
660#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
661
662 ct = &ctbl_bt601_5;
663
ac01c29e
AT		 664 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
665 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
666 CVAL(ct->rcr, ct->ry));
667 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
668 CVAL(ct->gy, ct->rcb));
669 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
670 CVAL(ct->gcb, ct->gcr));
671 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
672 CVAL(ct->bcr, ct->by));
673 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
674 CVAL(0, ct->bcb));
675
676 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
677 11, 11);
678 }
80c39712
TV		 679
680#undef CVAL
80c39712
TV		 681}
682
683
f0e5caab 684static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 685{
9b372c2d 686 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 687}
688
f0e5caab 689static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 690{
9b372c2d 691 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 692}
693
f0e5caab 694static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 695{
696 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
697}
698
f0e5caab 699static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 700{
701 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
702}
703
d79db853
AT		 704static void dispc_ovl_set_pos(enum omap_plane plane,
705 enum omap_overlay_caps caps, int x, int y)
80c39712 706{
d79db853
AT		 707 u32 val;
708
709 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
710 return;
711
712 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 713
714 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 715}
716
78b687fc
AT		 717static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
718 int height)
80c39712 719{
80c39712 720 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 721
36d87d95 722 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 723 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
724 else
725 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 726}
727
78b687fc
AT		 728static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
729 int height)
80c39712
TV		 730{
731 u32 val;
80c39712
TV		 732
733 BUG_ON(plane == OMAP_DSS_GFX);
734
735 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 736
36d87d95
AT		 737 if (plane == OMAP_DSS_WB)
738 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
739 else
740 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 741}
742
5b54ed3e
AT		 743static void dispc_ovl_set_zorder(enum omap_plane plane,
744 enum omap_overlay_caps caps, u8 zorder)
54128701 745{
5b54ed3e 746 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 747 return;
748
749 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
750}
751
752static void dispc_ovl_enable_zorder_planes(void)
753{
754 int i;
755
756 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
757 return;
758
759 for (i = 0; i < dss_feat_get_num_ovls(); i++)
760 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
761}
762
5b54ed3e
AT		 763static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
764 enum omap_overlay_caps caps, bool enable)
fd28a390 765{
5b54ed3e 766 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 767 return;
768
9b372c2d 769 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 770}
771
5b54ed3e
AT		 772static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
773 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 774{
b8c095b4 775 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 776 int shift;
777
5b54ed3e 778 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 779 return;
a0acb557 780
fe3cc9d6
TV		 781 shift = shifts[plane];
782 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 783}
784
f0e5caab 785static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 786{
9b372c2d 787 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 788}
789
f0e5caab 790static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 791{
9b372c2d 792 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 793}
794
f0e5caab 795static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 796 enum omap_color_mode color_mode)
797{
798 u32 m = 0;
f20e4220
AJ		 799 if (plane != OMAP_DSS_GFX) {
800 switch (color_mode) {
801 case OMAP_DSS_COLOR_NV12:
802 m = 0x0; break;
08f3267e 803 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 804 m = 0x1; break;
805 case OMAP_DSS_COLOR_RGBA16:
806 m = 0x2; break;
08f3267e 807 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 808 m = 0x4; break;
809 case OMAP_DSS_COLOR_ARGB16:
810 m = 0x5; break;
811 case OMAP_DSS_COLOR_RGB16:
812 m = 0x6; break;
813 case OMAP_DSS_COLOR_ARGB16_1555:
814 m = 0x7; break;
815 case OMAP_DSS_COLOR_RGB24U:
816 m = 0x8; break;
817 case OMAP_DSS_COLOR_RGB24P:
818 m = 0x9; break;
819 case OMAP_DSS_COLOR_YUV2:
820 m = 0xa; break;
821 case OMAP_DSS_COLOR_UYVY:
822 m = 0xb; break;
823 case OMAP_DSS_COLOR_ARGB32:
824 m = 0xc; break;
825 case OMAP_DSS_COLOR_RGBA32:
826 m = 0xd; break;
827 case OMAP_DSS_COLOR_RGBX32:
828 m = 0xe; break;
829 case OMAP_DSS_COLOR_XRGB16_1555:
830 m = 0xf; break;
831 default:
c6eee968 832 BUG(); return;
f20e4220
AJ		 833 }
834 } else {
835 switch (color_mode) {
836 case OMAP_DSS_COLOR_CLUT1:
837 m = 0x0; break;
838 case OMAP_DSS_COLOR_CLUT2:
839 m = 0x1; break;
840 case OMAP_DSS_COLOR_CLUT4:
841 m = 0x2; break;
842 case OMAP_DSS_COLOR_CLUT8:
843 m = 0x3; break;
844 case OMAP_DSS_COLOR_RGB12U:
845 m = 0x4; break;
846 case OMAP_DSS_COLOR_ARGB16:
847 m = 0x5; break;
848 case OMAP_DSS_COLOR_RGB16:
849 m = 0x6; break;
850 case OMAP_DSS_COLOR_ARGB16_1555:
851 m = 0x7; break;
852 case OMAP_DSS_COLOR_RGB24U:
853 m = 0x8; break;
854 case OMAP_DSS_COLOR_RGB24P:
855 m = 0x9; break;
08f3267e 856 case OMAP_DSS_COLOR_RGBX16:
f20e4220 857 m = 0xa; break;
08f3267e 858 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 859 m = 0xb; break;
860 case OMAP_DSS_COLOR_ARGB32:
861 m = 0xc; break;
862 case OMAP_DSS_COLOR_RGBA32:
863 m = 0xd; break;
864 case OMAP_DSS_COLOR_RGBX32:
865 m = 0xe; break;
866 case OMAP_DSS_COLOR_XRGB16_1555:
867 m = 0xf; break;
868 default:
c6eee968 869 BUG(); return;
f20e4220 870 }
80c39712
TV		 871 }
872
9b372c2d 873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 874}
875
65e006ff
CM		 876static void dispc_ovl_configure_burst_type(enum omap_plane plane,
877 enum omap_dss_rotation_type rotation_type)
878{
879 if (dss_has_feature(FEAT_BURST_2D) == 0)
880 return;
881
882 if (rotation_type == OMAP_DSS_ROT_TILER)
883 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
884 else
885 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
886}
887
f427984e 888void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 889{
890 int shift;
891 u32 val;
2a205f34 892 int chan = 0, chan2 = 0;
80c39712
TV		 893
894 switch (plane) {
895 case OMAP_DSS_GFX:
896 shift = 8;
897 break;
898 case OMAP_DSS_VIDEO1:
899 case OMAP_DSS_VIDEO2:
b8c095b4 900 case OMAP_DSS_VIDEO3:
80c39712
TV		 901 shift = 16;
902 break;
903 default:
904 BUG();
905 return;
906 }
907
9b372c2d 908 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 909 if (dss_has_feature(FEAT_MGR_LCD2)) {
910 switch (channel) {
911 case OMAP_DSS_CHANNEL_LCD:
912 chan = 0;
913 chan2 = 0;
914 break;
915 case OMAP_DSS_CHANNEL_DIGIT:
916 chan = 1;
917 chan2 = 0;
918 break;
919 case OMAP_DSS_CHANNEL_LCD2:
920 chan = 0;
921 chan2 = 1;
922 break;
e86d456a
CM		 923 case OMAP_DSS_CHANNEL_LCD3:
924 if (dss_has_feature(FEAT_MGR_LCD3)) {
925 chan = 0;
926 chan2 = 2;
927 } else {
928 BUG();
929 return;
930 }
931 break;
2a205f34
SS		 932 default:
933 BUG();
c6eee968 934 return;
2a205f34
SS		 935 }
936
937 val = FLD_MOD(val, chan, shift, shift);
938 val = FLD_MOD(val, chan2, 31, 30);
939 } else {
940 val = FLD_MOD(val, channel, shift, shift);
941 }
9b372c2d 942 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 943}
944
2cc5d1af
TV		 945static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
946{
947 int shift;
948 u32 val;
949 enum omap_channel channel;
950
951 switch (plane) {
952 case OMAP_DSS_GFX:
953 shift = 8;
954 break;
955 case OMAP_DSS_VIDEO1:
956 case OMAP_DSS_VIDEO2:
957 case OMAP_DSS_VIDEO3:
958 shift = 16;
959 break;
960 default:
961 BUG();
c6eee968 962 return 0;
2cc5d1af
TV		 963 }
964
965 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
966
e86d456a
CM		 967 if (dss_has_feature(FEAT_MGR_LCD3)) {
968 if (FLD_GET(val, 31, 30) == 0)
969 channel = FLD_GET(val, shift, shift);
970 else if (FLD_GET(val, 31, 30) == 1)
971 channel = OMAP_DSS_CHANNEL_LCD2;
972 else
973 channel = OMAP_DSS_CHANNEL_LCD3;
974 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 975 if (FLD_GET(val, 31, 30) == 0)
976 channel = FLD_GET(val, shift, shift);
977 else
978 channel = OMAP_DSS_CHANNEL_LCD2;
979 } else {
980 channel = FLD_GET(val, shift, shift);
981 }
982
983 return channel;
984}
985
d9ac773c
AT		 986void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
987{
988 enum omap_plane plane = OMAP_DSS_WB;
989
990 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
991}
992
f0e5caab 993static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 994 enum omap_burst_size burst_size)
995{
b8c095b4 996 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 997 int shift;
80c39712 998
fe3cc9d6 999 shift = shifts[plane];
5ed8cf5b 1000 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1001}
1002
5ed8cf5b
TV		 1003static void dispc_configure_burst_sizes(void)
1004{
1005 int i;
1006 const int burst_size = BURST_SIZE_X8;
1007
1008 /* Configure burst size always to maximum size */
1009 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 1010 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1011}
1012
83fa2f2e 1013static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1014{
1015 unsigned unit = dss_feat_get_burst_size_unit();
1016 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1017 return unit * 8;
1018}
1019
d3862610
M		 1020void dispc_enable_gamma_table(bool enable)
1021{
1022 /*
1023 * This is partially implemented to support only disabling of
1024 * the gamma table.
1025 */
1026 if (enable) {
1027 DSSWARN("Gamma table enabling for TV not yet supported");
1028 return;
1029 }
1030
1031 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1032}
1033
c64dca40 1034static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1035{
efa70b3b 1036 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1037 return;
1038
efa70b3b 1039 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1040}
1041
c64dca40 1042static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 1043 struct omap_dss_cpr_coefs *coefs)
1044{
1045 u32 coef_r, coef_g, coef_b;
1046
dd88b7a6 1047 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1048 return;
1049
1050 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1051 FLD_VAL(coefs->rb, 9, 0);
1052 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1053 FLD_VAL(coefs->gb, 9, 0);
1054 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1055 FLD_VAL(coefs->bb, 9, 0);
1056
1057 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1058 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1059 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1060}
1061
f0e5caab 1062static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1063{
1064 u32 val;
1065
1066 BUG_ON(plane == OMAP_DSS_GFX);
1067
9b372c2d 1068 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1069 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1070 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1071}
1072
d79db853
AT		 1073static void dispc_ovl_enable_replication(enum omap_plane plane,
1074 enum omap_overlay_caps caps, bool enable)
80c39712 1075{
b8c095b4 1076 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1077 int shift;
80c39712 1078
d79db853
AT		 1079 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1080 return;
1081
fe3cc9d6
TV		 1082 shift = shifts[plane];
1083 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1084}
1085
8f366162 1086static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1087 u16 height)
80c39712
TV		 1088{
1089 u32 val;
80c39712 1090
80c39712 1091 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 1092 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1093}
1094
42a6961c 1095static void dispc_init_fifos(void)
80c39712 1096{
80c39712 1097 u32 size;
42a6961c 1098 int fifo;
a0acb557 1099 u8 start, end;
5ed8cf5b
TV		 1100 u32 unit;
1101
1102 unit = dss_feat_get_buffer_size_unit();
80c39712 1103
a0acb557 1104 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1105
42a6961c
TV		 1106 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1107 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1108 size *= unit;
42a6961c
TV		 1109 dispc.fifo_size[fifo] = size;
1110
1111 /*
1112 * By default fifos are mapped directly to overlays, fifo 0 to
1113 * ovl 0, fifo 1 to ovl 1, etc.
1114 */
1115 dispc.fifo_assignment[fifo] = fifo;
80c39712 1116 }
66a0f9e4
TV		 1117
1118 /*
1119 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1120 * causes problems with certain use cases, like using the tiler in 2D
1121 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1122 * giving GFX plane a larger fifo. WB but should work fine with a
1123 * smaller fifo.
1124 */
1125 if (dispc.feat->gfx_fifo_workaround) {
1126 u32 v;
1127
1128 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1129
1130 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1131 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1132 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1133 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1134
1135 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1136
1137 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1138 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1139 }
80c39712
TV		 1140}
1141
83fa2f2e 1142static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1143{
42a6961c
TV		 1144 int fifo;
1145 u32 size = 0;
1146
1147 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1148 if (dispc.fifo_assignment[fifo] == plane)
1149 size += dispc.fifo_size[fifo];
1150 }
1151
1152 return size;
80c39712
TV		 1153}
1154
6f04e1bf 1155void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1156{
a0acb557 1157 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1158 u32 unit;
1159
1160 unit = dss_feat_get_buffer_size_unit();
1161
1162 WARN_ON(low % unit != 0);
1163 WARN_ON(high % unit != 0);
1164
1165 low /= unit;
1166 high /= unit;
a0acb557 1167
9b372c2d
AT		 1168 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1169 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1170
3cb5d966 1171 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1172 plane,
9b372c2d 1173 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1174 lo_start, lo_end) * unit,
9b372c2d 1175 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1176 hi_start, hi_end) * unit,
1177 low * unit, high * unit);
80c39712 1178
9b372c2d 1179 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1180 FLD_VAL(high, hi_start, hi_end) |
1181 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1182}
1183
1184void dispc_enable_fifomerge(bool enable)
1185{
e6b0f884
TV		 1186 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1187 WARN_ON(enable);
1188 return;
1189 }
1190
80c39712
TV		 1191 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1192 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1193}
1194
83fa2f2e 1195void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1196 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1197 bool manual_update)
83fa2f2e
TV		 1198{
1199 /*
1200 * All sizes are in bytes. Both the buffer and burst are made of
1201 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1202 */
1203
1204 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1205 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1206 int i;
83fa2f2e
TV		 1207
1208 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1209 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1210
e0e405b9
TV		 1211 if (use_fifomerge) {
1212 total_fifo_size = 0;
1213 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1214 total_fifo_size += dispc_ovl_get_fifo_size(i);
1215 } else {
1216 total_fifo_size = ovl_fifo_size;
1217 }
1218
1219 /*
1220 * We use the same low threshold for both fifomerge and non-fifomerge
1221 * cases, but for fifomerge we calculate the high threshold using the
1222 * combined fifo size
1223 */
1224
3568f2a4 1225 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1226 *fifo_low = ovl_fifo_size - burst_size * 2;
1227 *fifo_high = total_fifo_size - burst_size;
1228 } else {
1229 *fifo_low = ovl_fifo_size - burst_size;
1230 *fifo_high = total_fifo_size - buf_unit;
1231 }
83fa2f2e
TV		 1232}
1233
f0e5caab 1234static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1235 int hinc, int vinc,
1236 enum omap_color_component color_comp)
80c39712
TV		 1237{
1238 u32 val;
80c39712 1239
0d66cbb5
AJ		 1240 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1241 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1242
0d66cbb5
AJ		 1243 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1244 &hinc_start, &hinc_end);
1245 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1246 &vinc_start, &vinc_end);
1247 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1248 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1249
0d66cbb5
AJ		 1250 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1251 } else {
1252 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1253 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1254 }
80c39712
TV		 1255}
1256
f0e5caab 1257static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1258{
1259 u32 val;
87a7484b 1260 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1261
87a7484b
AT		 1262 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1263 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1264
1265 val = FLD_VAL(vaccu, vert_start, vert_end) |
1266 FLD_VAL(haccu, hor_start, hor_end);
1267
9b372c2d 1268 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1269}
1270
f0e5caab 1271static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1272{
1273 u32 val;
87a7484b 1274 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1275
87a7484b
AT		 1276 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1277 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1278
1279 val = FLD_VAL(vaccu, vert_start, vert_end) |
1280 FLD_VAL(haccu, hor_start, hor_end);
1281
9b372c2d 1282 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1283}
1284
f0e5caab
TV		 1285static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1286 int vaccu)
ab5ca071
AJ		 1287{
1288 u32 val;
1289
1290 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1291 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1292}
1293
f0e5caab
TV		 1294static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1295 int vaccu)
ab5ca071
AJ		 1296{
1297 u32 val;
1298
1299 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1300 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1301}
80c39712 1302
f0e5caab 1303static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1304 u16 orig_width, u16 orig_height,
1305 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1306 bool five_taps, u8 rotation,
1307 enum omap_color_component color_comp)
80c39712 1308{
0d66cbb5 1309 int fir_hinc, fir_vinc;
80c39712 1310
ed14a3ce
AJ		 1311 fir_hinc = 1024 * orig_width / out_width;
1312 fir_vinc = 1024 * orig_height / out_height;
80c39712 1313
debd9074
CM		 1314 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1315 color_comp);
f0e5caab 1316 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1317}
1318
05dd0f53
CM		 1319static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1320 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1321 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1322{
1323 int h_accu2_0, h_accu2_1;
1324 int v_accu2_0, v_accu2_1;
1325 int chroma_hinc, chroma_vinc;
1326 int idx;
1327
1328 struct accu {
1329 s8 h0_m, h0_n;
1330 s8 h1_m, h1_n;
1331 s8 v0_m, v0_n;
1332 s8 v1_m, v1_n;
1333 };
1334
1335 const struct accu *accu_table;
1336 const struct accu *accu_val;
1337
1338 static const struct accu accu_nv12[4] = {
1339 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1340 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1341 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1342 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1343 };
1344
1345 static const struct accu accu_nv12_ilace[4] = {
1346 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1347 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1348 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1349 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1350 };
1351
1352 static const struct accu accu_yuv[4] = {
1353 { 0, 1, 0, 1, 0, 1, 0, 1 },
1354 { 0, 1, 0, 1, 0, 1, 0, 1 },
1355 { -1, 1, 0, 1, 0, 1, 0, 1 },
1356 { 0, 1, 0, 1, -1, 1, 0, 1 },
1357 };
1358
1359 switch (rotation) {
1360 case OMAP_DSS_ROT_0:
1361 idx = 0;
1362 break;
1363 case OMAP_DSS_ROT_90:
1364 idx = 1;
1365 break;
1366 case OMAP_DSS_ROT_180:
1367 idx = 2;
1368 break;
1369 case OMAP_DSS_ROT_270:
1370 idx = 3;
1371 break;
1372 default:
1373 BUG();
c6eee968 1374 return;
05dd0f53
CM		 1375 }
1376
1377 switch (color_mode) {
1378 case OMAP_DSS_COLOR_NV12:
1379 if (ilace)
1380 accu_table = accu_nv12_ilace;
1381 else
1382 accu_table = accu_nv12;
1383 break;
1384 case OMAP_DSS_COLOR_YUV2:
1385 case OMAP_DSS_COLOR_UYVY:
1386 accu_table = accu_yuv;
1387 break;
1388 default:
1389 BUG();
c6eee968 1390 return;
05dd0f53
CM		 1391 }
1392
1393 accu_val = &accu_table[idx];
1394
1395 chroma_hinc = 1024 * orig_width / out_width;
1396 chroma_vinc = 1024 * orig_height / out_height;
1397
1398 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1399 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1400 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1401 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1402
1403 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1404 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1405}
1406
f0e5caab 1407static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1408 u16 orig_width, u16 orig_height,
1409 u16 out_width, u16 out_height,
1410 bool ilace, bool five_taps,
1411 bool fieldmode, enum omap_color_mode color_mode,
1412 u8 rotation)
1413{
1414 int accu0 = 0;
1415 int accu1 = 0;
1416 u32 l;
80c39712 1417
f0e5caab 1418 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1419 out_width, out_height, five_taps,
1420 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1421 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1422
87a7484b
AT		 1423 /* RESIZEENABLE and VERTICALTAPS */
1424 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1425 l |= (orig_width != out_width) ? (1 << 5) : 0;
1426 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1427 l |= five_taps ? (1 << 21) : 0;
80c39712 1428
87a7484b
AT		 1429 /* VRESIZECONF and HRESIZECONF */
1430 if (dss_has_feature(FEAT_RESIZECONF)) {
1431 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1432 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1433 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1434 }
80c39712 1435
87a7484b
AT		 1436 /* LINEBUFFERSPLIT */
1437 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1438 l &= ~(0x1 << 22);
1439 l |= five_taps ? (1 << 22) : 0;
1440 }
80c39712 1441
9b372c2d 1442 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1443
1444 /*
1445 * field 0 = even field = bottom field
1446 * field 1 = odd field = top field
1447 */
1448 if (ilace && !fieldmode) {
1449 accu1 = 0;
0d66cbb5 1450 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1451 if (accu0 >= 1024/2) {
1452 accu1 = 1024/2;
1453 accu0 -= accu1;
1454 }
1455 }
1456
f0e5caab
TV		 1457 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1458 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1459}
1460
f0e5caab 1461static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1462 u16 orig_width, u16 orig_height,
1463 u16 out_width, u16 out_height,
1464 bool ilace, bool five_taps,
1465 bool fieldmode, enum omap_color_mode color_mode,
1466 u8 rotation)
1467{
1468 int scale_x = out_width != orig_width;
1469 int scale_y = out_height != orig_height;
f92afae2 1470 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1471
1472 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1473 return;
1474 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1475 color_mode != OMAP_DSS_COLOR_UYVY &&
1476 color_mode != OMAP_DSS_COLOR_NV12)) {
1477 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1478 if (plane != OMAP_DSS_WB)
1479 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1480 return;
1481 }
36377357
TV		 1482
1483 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1484 out_height, ilace, color_mode, rotation);
1485
0d66cbb5
AJ		 1486 switch (color_mode) {
1487 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1488 if (chroma_upscale) {
1489 /* UV is subsampled by 2 horizontally and vertically */
1490 orig_height >>= 1;
1491 orig_width >>= 1;
1492 } else {
1493 /* UV is downsampled by 2 horizontally and vertically */
1494 orig_height <<= 1;
1495 orig_width <<= 1;
1496 }
1497
0d66cbb5
AJ		 1498 break;
1499 case OMAP_DSS_COLOR_YUV2:
1500 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1501 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1502 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1503 rotation == OMAP_DSS_ROT_180) {
1504 if (chroma_upscale)
1505 /* UV is subsampled by 2 horizontally */
1506 orig_width >>= 1;
1507 else
1508 /* UV is downsampled by 2 horizontally */
1509 orig_width <<= 1;
1510 }
1511
0d66cbb5
AJ		 1512 /* must use FIR for YUV422 if rotated */
1513 if (rotation != OMAP_DSS_ROT_0)
1514 scale_x = scale_y = true;
20fbb50b 1515
0d66cbb5
AJ		 1516 break;
1517 default:
1518 BUG();
c6eee968 1519 return;
0d66cbb5
AJ		 1520 }
1521
1522 if (out_width != orig_width)
1523 scale_x = true;
1524 if (out_height != orig_height)
1525 scale_y = true;
1526
f0e5caab 1527 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1528 out_width, out_height, five_taps,
1529 rotation, DISPC_COLOR_COMPONENT_UV);
1530
2a5561b1
AT		 1531 if (plane != OMAP_DSS_WB)
1532 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1533 (scale_x || scale_y) ? 1 : 0, 8, 8);
1534
0d66cbb5
AJ		 1535 /* set H scaling */
1536 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1537 /* set V scaling */
1538 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1539}
1540
f0e5caab 1541static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1542 u16 orig_width, u16 orig_height,
1543 u16 out_width, u16 out_height,
1544 bool ilace, bool five_taps,
1545 bool fieldmode, enum omap_color_mode color_mode,
1546 u8 rotation)
1547{
1548 BUG_ON(plane == OMAP_DSS_GFX);
1549
f0e5caab 1550 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1551 orig_width, orig_height,
1552 out_width, out_height,
1553 ilace, five_taps,
1554 fieldmode, color_mode,
1555 rotation);
1556
f0e5caab 1557 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1558 orig_width, orig_height,
1559 out_width, out_height,
1560 ilace, five_taps,
1561 fieldmode, color_mode,
1562 rotation);
1563}
1564
f0e5caab 1565static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1566 bool mirroring, enum omap_color_mode color_mode)
1567{
87a7484b
AT		 1568 bool row_repeat = false;
1569 int vidrot = 0;
1570
80c39712
TV		 1571 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1572 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1573
1574 if (mirroring) {
1575 switch (rotation) {
1576 case OMAP_DSS_ROT_0:
1577 vidrot = 2;
1578 break;
1579 case OMAP_DSS_ROT_90:
1580 vidrot = 1;
1581 break;
1582 case OMAP_DSS_ROT_180:
1583 vidrot = 0;
1584 break;
1585 case OMAP_DSS_ROT_270:
1586 vidrot = 3;
1587 break;
1588 }
1589 } else {
1590 switch (rotation) {
1591 case OMAP_DSS_ROT_0:
1592 vidrot = 0;
1593 break;
1594 case OMAP_DSS_ROT_90:
1595 vidrot = 1;
1596 break;
1597 case OMAP_DSS_ROT_180:
1598 vidrot = 2;
1599 break;
1600 case OMAP_DSS_ROT_270:
1601 vidrot = 3;
1602 break;
1603 }
1604 }
1605
80c39712 1606 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1607 row_repeat = true;
80c39712 1608 else
87a7484b 1609 row_repeat = false;
80c39712 1610 }
87a7484b 1611
9b372c2d 1612 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1613 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1614 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1615 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1616}
1617
1618static int color_mode_to_bpp(enum omap_color_mode color_mode)
1619{
1620 switch (color_mode) {
1621 case OMAP_DSS_COLOR_CLUT1:
1622 return 1;
1623 case OMAP_DSS_COLOR_CLUT2:
1624 return 2;
1625 case OMAP_DSS_COLOR_CLUT4:
1626 return 4;
1627 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1628 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1629 return 8;
1630 case OMAP_DSS_COLOR_RGB12U:
1631 case OMAP_DSS_COLOR_RGB16:
1632 case OMAP_DSS_COLOR_ARGB16:
1633 case OMAP_DSS_COLOR_YUV2:
1634 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1635 case OMAP_DSS_COLOR_RGBA16:
1636 case OMAP_DSS_COLOR_RGBX16:
1637 case OMAP_DSS_COLOR_ARGB16_1555:
1638 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1639 return 16;
1640 case OMAP_DSS_COLOR_RGB24P:
1641 return 24;
1642 case OMAP_DSS_COLOR_RGB24U:
1643 case OMAP_DSS_COLOR_ARGB32:
1644 case OMAP_DSS_COLOR_RGBA32:
1645 case OMAP_DSS_COLOR_RGBX32:
1646 return 32;
1647 default:
1648 BUG();
c6eee968 1649 return 0;
80c39712
TV		 1650 }
1651}
1652
1653static s32 pixinc(int pixels, u8 ps)
1654{
1655 if (pixels == 1)
1656 return 1;
1657 else if (pixels > 1)
1658 return 1 + (pixels - 1) * ps;
1659 else if (pixels < 0)
1660 return 1 - (-pixels + 1) * ps;
1661 else
1662 BUG();
c6eee968 1663 return 0;
80c39712
TV		 1664}
1665
1666static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1667 u16 screen_width,
1668 u16 width, u16 height,
1669 enum omap_color_mode color_mode, bool fieldmode,
1670 unsigned int field_offset,
1671 unsigned *offset0, unsigned *offset1,
aed74b55 1672 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1673{
1674 u8 ps;
1675
1676 /* FIXME CLUT formats */
1677 switch (color_mode) {
1678 case OMAP_DSS_COLOR_CLUT1:
1679 case OMAP_DSS_COLOR_CLUT2:
1680 case OMAP_DSS_COLOR_CLUT4:
1681 case OMAP_DSS_COLOR_CLUT8:
1682 BUG();
1683 return;
1684 case OMAP_DSS_COLOR_YUV2:
1685 case OMAP_DSS_COLOR_UYVY:
1686 ps = 4;
1687 break;
1688 default:
1689 ps = color_mode_to_bpp(color_mode) / 8;
1690 break;
1691 }
1692
1693 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1694 width, height);
1695
1696 /*
1697 * field 0 = even field = bottom field
1698 * field 1 = odd field = top field
1699 */
1700 switch (rotation + mirror * 4) {
1701 case OMAP_DSS_ROT_0:
1702 case OMAP_DSS_ROT_180:
1703 /*
1704 * If the pixel format is YUV or UYVY divide the width
1705 * of the image by 2 for 0 and 180 degree rotation.
1706 */
1707 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1708 color_mode == OMAP_DSS_COLOR_UYVY)
1709 width = width >> 1;
1710 case OMAP_DSS_ROT_90:
1711 case OMAP_DSS_ROT_270:
1712 *offset1 = 0;
1713 if (field_offset)
1714 *offset0 = field_offset * screen_width * ps;
1715 else
1716 *offset0 = 0;
1717
aed74b55
CM		 1718 *row_inc = pixinc(1 +
1719 (y_predecim * screen_width - x_predecim * width) +
1720 (fieldmode ? screen_width : 0), ps);
1721 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1722 break;
1723
1724 case OMAP_DSS_ROT_0 + 4:
1725 case OMAP_DSS_ROT_180 + 4:
1726 /* If the pixel format is YUV or UYVY divide the width
1727 * of the image by 2 for 0 degree and 180 degree
1728 */
1729 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1730 color_mode == OMAP_DSS_COLOR_UYVY)
1731 width = width >> 1;
1732 case OMAP_DSS_ROT_90 + 4:
1733 case OMAP_DSS_ROT_270 + 4:
1734 *offset1 = 0;
1735 if (field_offset)
1736 *offset0 = field_offset * screen_width * ps;
1737 else
1738 *offset0 = 0;
aed74b55
CM		 1739 *row_inc = pixinc(1 -
1740 (y_predecim * screen_width + x_predecim * width) -
1741 (fieldmode ? screen_width : 0), ps);
1742 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1743 break;
1744
1745 default:
1746 BUG();
c6eee968 1747 return;
80c39712
TV		 1748 }
1749}
1750
1751static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1752 u16 screen_width,
1753 u16 width, u16 height,
1754 enum omap_color_mode color_mode, bool fieldmode,
1755 unsigned int field_offset,
1756 unsigned *offset0, unsigned *offset1,
aed74b55 1757 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1758{
1759 u8 ps;
1760 u16 fbw, fbh;
1761
1762 /* FIXME CLUT formats */
1763 switch (color_mode) {
1764 case OMAP_DSS_COLOR_CLUT1:
1765 case OMAP_DSS_COLOR_CLUT2:
1766 case OMAP_DSS_COLOR_CLUT4:
1767 case OMAP_DSS_COLOR_CLUT8:
1768 BUG();
1769 return;
1770 default:
1771 ps = color_mode_to_bpp(color_mode) / 8;
1772 break;
1773 }
1774
1775 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1776 width, height);
1777
1778 /* width & height are overlay sizes, convert to fb sizes */
1779
1780 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1781 fbw = width;
1782 fbh = height;
1783 } else {
1784 fbw = height;
1785 fbh = width;
1786 }
1787
1788 /*
1789 * field 0 = even field = bottom field
1790 * field 1 = odd field = top field
1791 */
1792 switch (rotation + mirror * 4) {
1793 case OMAP_DSS_ROT_0:
1794 *offset1 = 0;
1795 if (field_offset)
1796 *offset0 = *offset1 + field_offset * screen_width * ps;
1797 else
1798 *offset0 = *offset1;
aed74b55
CM		 1799 *row_inc = pixinc(1 +
1800 (y_predecim * screen_width - fbw * x_predecim) +
1801 (fieldmode ? screen_width : 0), ps);
1802 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1803 color_mode == OMAP_DSS_COLOR_UYVY)
1804 *pix_inc = pixinc(x_predecim, 2 * ps);
1805 else
1806 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1807 break;
1808 case OMAP_DSS_ROT_90:
1809 *offset1 = screen_width * (fbh - 1) * ps;
1810 if (field_offset)
1811 *offset0 = *offset1 + field_offset * ps;
1812 else
1813 *offset0 = *offset1;
aed74b55
CM		 1814 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1815 y_predecim + (fieldmode ? 1 : 0), ps);
1816 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1817 break;
1818 case OMAP_DSS_ROT_180:
1819 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1820 if (field_offset)
1821 *offset0 = *offset1 - field_offset * screen_width * ps;
1822 else
1823 *offset0 = *offset1;
1824 *row_inc = pixinc(-1 -
aed74b55
CM		 1825 (y_predecim * screen_width - fbw * x_predecim) -
1826 (fieldmode ? screen_width : 0), ps);
1827 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1828 color_mode == OMAP_DSS_COLOR_UYVY)
1829 *pix_inc = pixinc(-x_predecim, 2 * ps);
1830 else
1831 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1832 break;
1833 case OMAP_DSS_ROT_270:
1834 *offset1 = (fbw - 1) * ps;
1835 if (field_offset)
1836 *offset0 = *offset1 - field_offset * ps;
1837 else
1838 *offset0 = *offset1;
aed74b55
CM		 1839 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1840 y_predecim - (fieldmode ? 1 : 0), ps);
1841 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1842 break;
1843
1844 /* mirroring */
1845 case OMAP_DSS_ROT_0 + 4:
1846 *offset1 = (fbw - 1) * ps;
1847 if (field_offset)
1848 *offset0 = *offset1 + field_offset * screen_width * ps;
1849 else
1850 *offset0 = *offset1;
aed74b55 1851 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1852 (fieldmode ? screen_width : 0),
1853 ps);
aed74b55
CM		 1854 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1855 color_mode == OMAP_DSS_COLOR_UYVY)
1856 *pix_inc = pixinc(-x_predecim, 2 * ps);
1857 else
1858 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1859 break;
1860
1861 case OMAP_DSS_ROT_90 + 4:
1862 *offset1 = 0;
1863 if (field_offset)
1864 *offset0 = *offset1 + field_offset * ps;
1865 else
1866 *offset0 = *offset1;
aed74b55
CM		 1867 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1868 y_predecim + (fieldmode ? 1 : 0),
80c39712 1869 ps);
aed74b55 1870 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1871 break;
1872
1873 case OMAP_DSS_ROT_180 + 4:
1874 *offset1 = screen_width * (fbh - 1) * ps;
1875 if (field_offset)
1876 *offset0 = *offset1 - field_offset * screen_width * ps;
1877 else
1878 *offset0 = *offset1;
aed74b55 1879 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1880 (fieldmode ? screen_width : 0),
1881 ps);
aed74b55
CM		 1882 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1883 color_mode == OMAP_DSS_COLOR_UYVY)
1884 *pix_inc = pixinc(x_predecim, 2 * ps);
1885 else
1886 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1887 break;
1888
1889 case OMAP_DSS_ROT_270 + 4:
1890 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1891 if (field_offset)
1892 *offset0 = *offset1 - field_offset * ps;
1893 else
1894 *offset0 = *offset1;
aed74b55
CM		 1895 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1896 y_predecim - (fieldmode ? 1 : 0),
80c39712 1897 ps);
aed74b55 1898 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1899 break;
1900
1901 default:
1902 BUG();
c6eee968 1903 return;
80c39712
TV		 1904 }
1905}
1906
65e006ff
CM		 1907static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1908 enum omap_color_mode color_mode, bool fieldmode,
1909 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1910 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1911{
1912 u8 ps;
1913
1914 switch (color_mode) {
1915 case OMAP_DSS_COLOR_CLUT1:
1916 case OMAP_DSS_COLOR_CLUT2:
1917 case OMAP_DSS_COLOR_CLUT4:
1918 case OMAP_DSS_COLOR_CLUT8:
1919 BUG();
1920 return;
1921 default:
1922 ps = color_mode_to_bpp(color_mode) / 8;
1923 break;
1924 }
1925
1926 DSSDBG("scrw %d, width %d\n", screen_width, width);
1927
1928 /*
1929 * field 0 = even field = bottom field
1930 * field 1 = odd field = top field
1931 */
1932 *offset1 = 0;
1933 if (field_offset)
1934 *offset0 = *offset1 + field_offset * screen_width * ps;
1935 else
1936 *offset0 = *offset1;
1937 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1938 (fieldmode ? screen_width : 0), ps);
1939 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1940 color_mode == OMAP_DSS_COLOR_UYVY)
1941 *pix_inc = pixinc(x_predecim, 2 * ps);
1942 else
1943 *pix_inc = pixinc(x_predecim, ps);
1944}
1945
7faa9233
CM		 1946/*
1947 * This function is used to avoid synclosts in OMAP3, because of some
1948 * undocumented horizontal position and timing related limitations.
1949 */
3e8a6ff2 1950static int check_horiz_timing_omap3(enum omap_plane plane,
81ab95b7 1951 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1952 u16 width, u16 height, u16 out_width, u16 out_height)
1953{
1954 int DS = DIV_ROUND_UP(height, out_height);
3e8a6ff2 1955 unsigned long nonactive;
7faa9233
CM		 1956 static const u8 limits[3] = { 8, 10, 20 };
1957 u64 val, blank;
3e8a6ff2
AT		 1958 unsigned long pclk = dispc_plane_pclk_rate(plane);
1959 unsigned long lclk = dispc_plane_lclk_rate(plane);
7faa9233
CM		 1960 int i;
1961
81ab95b7 1962 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 1963
1964 i = 0;
1965 if (out_height < height)
1966 i++;
1967 if (out_width < width)
1968 i++;
81ab95b7 1969 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1970 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1971 if (blank <= limits[i])
1972 return -EINVAL;
1973
1974 /*
1975 * Pixel data should be prepared before visible display point starts.
1976 * So, atleast DS-2 lines must have already been fetched by DISPC
1977 * during nonactive - pos_x period.
1978 */
1979 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1980 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1981 val, max(0, DS - 2) * width);
1982 if (val < max(0, DS - 2) * width)
1983 return -EINVAL;
1984
1985 /*
1986 * All lines need to be refilled during the nonactive period of which
1987 * only one line can be loaded during the active period. So, atleast
1988 * DS - 1 lines should be loaded during nonactive period.
1989 */
1990 val = div_u64((u64)nonactive * lclk, pclk);
1991 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1992 val, max(0, DS - 1) * width);
1993 if (val < max(0, DS - 1) * width)
1994 return -EINVAL;
1995
1996 return 0;
1997}
1998
3e8a6ff2 1999static unsigned long calc_core_clk_five_taps(enum omap_plane plane,
81ab95b7
AT		 2000 const struct omap_video_timings *mgr_timings, u16 width,
2001 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2002 enum omap_color_mode color_mode)
80c39712 2003{
8b53d991 2004 u32 core_clk = 0;
3e8a6ff2
AT		 2005 u64 tmp;
2006 unsigned long pclk = dispc_plane_pclk_rate(plane);
80c39712 2007
7282f1b7
CM		 2008 if (height <= out_height && width <= out_width)
2009 return (unsigned long) pclk;
2010
80c39712 2011 if (height > out_height) {
81ab95b7 2012 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2013
2014 tmp = pclk * height * out_width;
2015 do_div(tmp, 2 * out_height * ppl);
8b53d991 2016 core_clk = tmp;
80c39712 2017
2d9c5597
VS		 2018 if (height > 2 * out_height) {
2019 if (ppl == out_width)
2020 return 0;
2021
80c39712
TV		 2022 tmp = pclk * (height - 2 * out_height) * out_width;
2023 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2024 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2025 }
2026 }
2027
2028 if (width > out_width) {
2029 tmp = pclk * width;
2030 do_div(tmp, out_width);
8b53d991 2031 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2032
2033 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2034 core_clk <<= 1;
80c39712
TV		 2035 }
2036
8b53d991 2037 return core_clk;
80c39712
TV		 2038}
2039
3e8a6ff2 2040static unsigned long calc_core_clk_24xx(enum omap_plane plane, u16 width,
8ba85306 2041 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2042{
3e8a6ff2 2043 unsigned long pclk = dispc_plane_pclk_rate(plane);
dcbe765b
CM		 2044
2045 if (height > out_height && width > out_width)
2046 return pclk * 4;
2047 else
2048 return pclk * 2;
2049}
2050
3e8a6ff2 2051static unsigned long calc_core_clk_34xx(enum omap_plane plane, u16 width,
8ba85306 2052 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2053{
2054 unsigned int hf, vf;
3e8a6ff2 2055 unsigned long pclk = dispc_plane_pclk_rate(plane);
80c39712
TV		 2056
2057 /*
2058 * FIXME how to determine the 'A' factor
2059 * for the no downscaling case ?
2060 */
2061
2062 if (width > 3 * out_width)
2063 hf = 4;
2064 else if (width > 2 * out_width)
2065 hf = 3;
2066 else if (width > out_width)
2067 hf = 2;
2068 else
2069 hf = 1;
80c39712
TV		 2070 if (height > out_height)
2071 vf = 2;
2072 else
2073 vf = 1;
2074
dcbe765b
CM		 2075 return pclk * vf * hf;
2076}
2077
3e8a6ff2 2078static unsigned long calc_core_clk_44xx(enum omap_plane plane, u16 width,
8ba85306 2079 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2080{
8ba85306
AT		 2081 unsigned long pclk;
2082
2083 /*
2084 * If the overlay/writeback is in mem to mem mode, there are no
2085 * downscaling limitations with respect to pixel clock, return 1 as
2086 * required core clock to represent that we have sufficient enough
2087 * core clock to do maximum downscaling
2088 */
2089 if (mem_to_mem)
2090 return 1;
2091
2092 pclk = dispc_plane_pclk_rate(plane);
dcbe765b
CM		 2093
2094 if (width > out_width)
2095 return DIV_ROUND_UP(pclk, out_width) * width;
2096 else
2097 return pclk;
2098}
2099
3e8a6ff2 2100static int dispc_ovl_calc_scaling_24xx(enum omap_plane plane,
dcbe765b
CM		 2101 const struct omap_video_timings *mgr_timings,
2102 u16 width, u16 height, u16 out_width, u16 out_height,
2103 enum omap_color_mode color_mode, bool *five_taps,
2104 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2105 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2106{
2107 int error;
2108 u16 in_width, in_height;
2109 int min_factor = min(*decim_x, *decim_y);
2110 const int maxsinglelinewidth =
2111 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2112
dcbe765b
CM		 2113 *five_taps = false;
2114
2115 do {
2116 in_height = DIV_ROUND_UP(height, *decim_y);
2117 in_width = DIV_ROUND_UP(width, *decim_x);
3e8a6ff2 2118 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
8ba85306 2119 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2120 error = (in_width > maxsinglelinewidth || !*core_clk ||
2121 *core_clk > dispc_core_clk_rate());
2122 if (error) {
2123 if (*decim_x == *decim_y) {
2124 *decim_x = min_factor;
2125 ++*decim_y;
2126 } else {
2127 swap(*decim_x, *decim_y);
2128 if (*decim_x < *decim_y)
2129 ++*decim_x;
2130 }
2131 }
2132 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2133
2134 if (in_width > maxsinglelinewidth) {
2135 DSSERR("Cannot scale max input width exceeded");
2136 return -EINVAL;
2137 }
2138 return 0;
2139}
2140
3e8a6ff2 2141static int dispc_ovl_calc_scaling_34xx(enum omap_plane plane,
dcbe765b
CM		 2142 const struct omap_video_timings *mgr_timings,
2143 u16 width, u16 height, u16 out_width, u16 out_height,
2144 enum omap_color_mode color_mode, bool *five_taps,
2145 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2146 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2147{
2148 int error;
2149 u16 in_width, in_height;
2150 int min_factor = min(*decim_x, *decim_y);
2151 const int maxsinglelinewidth =
2152 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2153
2154 do {
2155 in_height = DIV_ROUND_UP(height, *decim_y);
2156 in_width = DIV_ROUND_UP(width, *decim_x);
3e8a6ff2 2157 *core_clk = calc_core_clk_five_taps(plane, mgr_timings,
dcbe765b
CM		 2158 in_width, in_height, out_width, out_height, color_mode);
2159
3e8a6ff2
AT		 2160 error = check_horiz_timing_omap3(plane, mgr_timings,
2161 pos_x, in_width, in_height, out_width,
2162 out_height);
dcbe765b
CM		 2163
2164 if (in_width > maxsinglelinewidth)
2165 if (in_height > out_height &&
2166 in_height < out_height * 2)
2167 *five_taps = false;
2168 if (!*five_taps)
3e8a6ff2 2169 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
8ba85306
AT		 2170 in_height, out_width, out_height,
2171 mem_to_mem);
dcbe765b
CM		 2172
2173 error = (error || in_width > maxsinglelinewidth * 2 ||
2174 (in_width > maxsinglelinewidth && *five_taps) ||
2175 !*core_clk || *core_clk > dispc_core_clk_rate());
2176 if (error) {
2177 if (*decim_x == *decim_y) {
2178 *decim_x = min_factor;
2179 ++*decim_y;
2180 } else {
2181 swap(*decim_x, *decim_y);
2182 if (*decim_x < *decim_y)
2183 ++*decim_x;
2184 }
2185 }
2186 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2187
3e8a6ff2 2188 if (check_horiz_timing_omap3(plane, mgr_timings, pos_x, width, height,
dcbe765b
CM		 2189 out_width, out_height)){
2190 DSSERR("horizontal timing too tight\n");
2191 return -EINVAL;
7282f1b7 2192 }
dcbe765b
CM		 2193
2194 if (in_width > (maxsinglelinewidth * 2)) {
2195 DSSERR("Cannot setup scaling");
2196 DSSERR("width exceeds maximum width possible");
2197 return -EINVAL;
2198 }
2199
2200 if (in_width > maxsinglelinewidth && *five_taps) {
2201 DSSERR("cannot setup scaling with five taps");
2202 return -EINVAL;
2203 }
2204 return 0;
2205}
2206
3e8a6ff2 2207static int dispc_ovl_calc_scaling_44xx(enum omap_plane plane,
dcbe765b
CM		 2208 const struct omap_video_timings *mgr_timings,
2209 u16 width, u16 height, u16 out_width, u16 out_height,
2210 enum omap_color_mode color_mode, bool *five_taps,
2211 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2212 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2213{
2214 u16 in_width, in_width_max;
2215 int decim_x_min = *decim_x;
2216 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2217 const int maxsinglelinewidth =
2218 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2219 unsigned long pclk = dispc_plane_pclk_rate(plane);
8ba85306 2220 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2221
8ba85306
AT		 2222 if (mem_to_mem)
2223 in_width_max = DIV_ROUND_UP(out_width, maxdownscale);
2224 else
2225 in_width_max = dispc_core_clk_rate() /
2226 DIV_ROUND_UP(pclk, out_width);
dcbe765b 2227
dcbe765b
CM		 2228 *decim_x = DIV_ROUND_UP(width, in_width_max);
2229
2230 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2231 if (*decim_x > *x_predecim)
2232 return -EINVAL;
2233
2234 do {
2235 in_width = DIV_ROUND_UP(width, *decim_x);
2236 } while (*decim_x <= *x_predecim &&
2237 in_width > maxsinglelinewidth && ++*decim_x);
2238
2239 if (in_width > maxsinglelinewidth) {
2240 DSSERR("Cannot scale width exceeds max line width");
2241 return -EINVAL;
2242 }
2243
3e8a6ff2 2244 *core_clk = dispc.feat->calc_core_clk(plane, in_width, in_height,
8ba85306 2245 out_width, out_height, mem_to_mem);
dcbe765b 2246 return 0;
80c39712
TV		 2247}
2248
79ad75f2 2249static int dispc_ovl_calc_scaling(enum omap_plane plane,
3e8a6ff2 2250 enum omap_overlay_caps caps,
81ab95b7
AT		 2251 const struct omap_video_timings *mgr_timings,
2252 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2253 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2254 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2255 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2256{
0373cac6 2257 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2258 const int max_decim_limit = 16;
8b53d991 2259 unsigned long core_clk = 0;
dcbe765b 2260 int decim_x, decim_y, ret;
79ad75f2 2261
f95cb5eb
TV		 2262 if (width == out_width && height == out_height)
2263 return 0;
2264
5b54ed3e 2265 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2266 return -EINVAL;
79ad75f2 2267
aed74b55 2268 *x_predecim = max_decim_limit;
d557a9cf
CM		 2269 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2270 dss_has_feature(FEAT_BURST_2D)) ? 2 : max_decim_limit;
aed74b55
CM		 2271
2272 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2273 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2274 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2275 color_mode == OMAP_DSS_COLOR_CLUT8) {
2276 *x_predecim = 1;
2277 *y_predecim = 1;
2278 *five_taps = false;
2279 return 0;
2280 }
2281
2282 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2283 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2284
aed74b55 2285 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2286 return -EINVAL;
2287
aed74b55 2288 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2289 return -EINVAL;
2290
3e8a6ff2
AT		 2291 ret = dispc.feat->calc_scaling(plane, mgr_timings, width, height,
2292 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2293 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2294 mem_to_mem);
dcbe765b
CM		 2295 if (ret)
2296 return ret;
79ad75f2 2297
8b53d991
CM		 2298 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2299 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2300
8b53d991 2301 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2302 DSSERR("failed to set up scaling, "
8b53d991
CM		 2303 "required core clk rate = %lu Hz, "
2304 "current core clk rate = %lu Hz\n",
2305 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2306 return -EINVAL;
2307 }
2308
aed74b55
CM		 2309 *x_predecim = decim_x;
2310 *y_predecim = decim_y;
79ad75f2
AT		 2311 return 0;
2312}
2313
84a880fd 2314static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2315 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2316 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2317 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2318 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2319 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2320 bool replication, const struct omap_video_timings *mgr_timings,
2321 bool mem_to_mem)
80c39712 2322{
7282f1b7 2323 bool five_taps = true;
80c39712 2324 bool fieldmode = 0;
79ad75f2 2325 int r, cconv = 0;
80c39712
TV		 2326 unsigned offset0, offset1;
2327 s32 row_inc;
2328 s32 pix_inc;
84a880fd 2329 u16 frame_height = height;
80c39712 2330 unsigned int field_offset = 0;
84a880fd
AT		 2331 u16 in_height = height;
2332 u16 in_width = width;
aed74b55 2333 int x_predecim = 1, y_predecim = 1;
8050cbe4 2334 bool ilace = mgr_timings->interlace;
e6d80f95 2335
84a880fd 2336 if (paddr == 0)
80c39712
TV		 2337 return -EINVAL;
2338
84a880fd
AT		 2339 out_width = out_width == 0 ? width : out_width;
2340 out_height = out_height == 0 ? height : out_height;
cf073668 2341
84a880fd 2342 if (ilace && height == out_height)
80c39712
TV		 2343 fieldmode = 1;
2344
2345 if (ilace) {
2346 if (fieldmode)
aed74b55 2347 in_height /= 2;
8eeb7019 2348 pos_y /= 2;
aed74b55 2349 out_height /= 2;
80c39712
TV		 2350
2351 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2352 "out_height %d\n", in_height, pos_y,
2353 out_height);
80c39712
TV		 2354 }
2355
84a880fd 2356 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2357 return -EINVAL;
2358
3e8a6ff2 2359 r = dispc_ovl_calc_scaling(plane, caps, mgr_timings, in_width,
84a880fd
AT		 2360 in_height, out_width, out_height, color_mode,
2361 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2362 rotation_type, mem_to_mem);
79ad75f2
AT		 2363 if (r)
2364 return r;
80c39712 2365
aed74b55
CM		 2366 in_width = DIV_ROUND_UP(in_width, x_predecim);
2367 in_height = DIV_ROUND_UP(in_height, y_predecim);
2368
84a880fd
AT		 2369 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2370 color_mode == OMAP_DSS_COLOR_UYVY ||
2371 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2372 cconv = 1;
80c39712
TV		 2373
2374 if (ilace && !fieldmode) {
2375 /*
2376 * when downscaling the bottom field may have to start several
2377 * source lines below the top field. Unfortunately ACCUI
2378 * registers will only hold the fractional part of the offset
2379 * so the integer part must be added to the base address of the
2380 * bottom field.
2381 */
aed74b55 2382 if (!in_height || in_height == out_height)
80c39712
TV		 2383 field_offset = 0;
2384 else
aed74b55 2385 field_offset = in_height / out_height / 2;
80c39712
TV		 2386 }
2387
2388 /* Fields are independent but interleaved in memory. */
2389 if (fieldmode)
2390 field_offset = 1;
2391
c6eee968
TV		 2392 offset0 = 0;
2393 offset1 = 0;
2394 row_inc = 0;
2395 pix_inc = 0;
2396
84a880fd
AT		 2397 if (rotation_type == OMAP_DSS_ROT_TILER)
2398 calc_tiler_rotation_offset(screen_width, in_width,
2399 color_mode, fieldmode, field_offset,
65e006ff
CM		 2400 &offset0, &offset1, &row_inc, &pix_inc,
2401 x_predecim, y_predecim);
84a880fd
AT		 2402 else if (rotation_type == OMAP_DSS_ROT_DMA)
2403 calc_dma_rotation_offset(rotation, mirror,
2404 screen_width, in_width, frame_height,
2405 color_mode, fieldmode, field_offset,
aed74b55
CM		 2406 &offset0, &offset1, &row_inc, &pix_inc,
2407 x_predecim, y_predecim);
80c39712 2408 else
84a880fd
AT		 2409 calc_vrfb_rotation_offset(rotation, mirror,
2410 screen_width, in_width, frame_height,
2411 color_mode, fieldmode, field_offset,
aed74b55
CM		 2412 &offset0, &offset1, &row_inc, &pix_inc,
2413 x_predecim, y_predecim);
80c39712
TV		 2414
2415 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2416 offset0, offset1, row_inc, pix_inc);
2417
84a880fd 2418 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2419
84a880fd 2420 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2421
84a880fd
AT		 2422 dispc_ovl_set_ba0(plane, paddr + offset0);
2423 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2424
84a880fd
AT		 2425 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2426 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2427 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2428 }
2429
f0e5caab
TV		 2430 dispc_ovl_set_row_inc(plane, row_inc);
2431 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2432
84a880fd 2433 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2434 in_height, out_width, out_height);
80c39712 2435
84a880fd 2436 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2437
78b687fc 2438 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2439
5b54ed3e 2440 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2441 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2442 out_height, ilace, five_taps, fieldmode,
84a880fd 2443 color_mode, rotation);
78b687fc 2444 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2445 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2446 }
2447
84a880fd 2448 dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
80c39712 2449
84a880fd
AT		 2450 dispc_ovl_set_zorder(plane, caps, zorder);
2451 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2452 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2453
d79db853 2454 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2455
80c39712
TV		 2456 return 0;
2457}
2458
84a880fd 2459int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2460 bool replication, const struct omap_video_timings *mgr_timings,
2461 bool mem_to_mem)
84a880fd
AT		 2462{
2463 int r;
2464 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
2465 enum omap_channel channel;
2466
2467 channel = dispc_ovl_get_channel_out(plane);
2468
2469 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2470 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2471 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2472 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2473 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2474
3e8a6ff2
AT		 2475 r = dispc_ovl_setup_common(plane, ovl->caps, oi->paddr, oi->p_uv_addr,
2476 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2477 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2478 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2479 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2480
2481 return r;
2482}
2483
749feffa
AT		 2484int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
2485 const struct omap_video_timings *mgr_timings)
2486{
2487 int r;
2488 enum omap_plane plane = OMAP_DSS_WB;
2489 const int pos_x = 0, pos_y = 0;
2490 const u8 zorder = 0, global_alpha = 0;
2491 const bool replication = false;
2492 int in_width = mgr_timings->x_res;
2493 int in_height = mgr_timings->y_res;
2494 enum omap_overlay_caps caps =
2495 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2496
2497 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2498 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2499 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2500 wi->mirror);
2501
2502 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2503 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2504 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2505 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
2506 replication, mgr_timings, false);
2507
2508 return r;
2509}
2510
f0e5caab 2511int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2512{
e6d80f95
TV		 2513 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2514
9b372c2d 2515 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2516
2517 return 0;
80c39712
TV		 2518}
2519
2520static void dispc_disable_isr(void *data, u32 mask)
2521{
2522 struct completion *compl = data;
2523 complete(compl);
2524}
2525
2a205f34 2526static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2527{
efa70b3b
CM		 2528 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2529 /* flush posted write */
2530 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2531}
2532
26d9dd0d 2533static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2534{
2535 struct completion frame_done_completion;
2536 bool is_on;
2537 int r;
2a205f34 2538 u32 irq;
80c39712 2539
80c39712
TV		 2540 /* When we disable LCD output, we need to wait until frame is done.
2541 * Otherwise the DSS is still working, and turning off the clocks
2542 * prevents DSS from going to OFF mode */
efa70b3b 2543 is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2a205f34 2544
efa70b3b 2545 irq = mgr_desc[channel].framedone_irq;
80c39712
TV		 2546
2547 if (!enable && is_on) {
2548 init_completion(&frame_done_completion);
2549
2550 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2551 &frame_done_completion, irq);
80c39712
TV		 2552
2553 if (r)
2554 DSSERR("failed to register FRAMEDONE isr\n");
2555 }
2556
2a205f34 2557 _enable_lcd_out(channel, enable);
80c39712
TV		 2558
2559 if (!enable && is_on) {
2560 if (!wait_for_completion_timeout(&frame_done_completion,
2561 msecs_to_jiffies(100)))
2562 DSSERR("timeout waiting for FRAME DONE\n");
2563
2564 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2565 &frame_done_completion, irq);
80c39712
TV		 2566
2567 if (r)
2568 DSSERR("failed to unregister FRAMEDONE isr\n");
2569 }
80c39712
TV		 2570}
2571
2572static void _enable_digit_out(bool enable)
2573{
2574 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2575 /* flush posted write */
2576 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2577}
2578
26d9dd0d 2579static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2580{
2581 struct completion frame_done_completion;
e82b090b
TV		 2582 enum dss_hdmi_venc_clk_source_select src;
2583 int r, i;
2584 u32 irq_mask;
2585 int num_irqs;
80c39712 2586
e6d80f95 2587 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2588 return;
80c39712 2589
e82b090b
TV		 2590 src = dss_get_hdmi_venc_clk_source();
2591
80c39712
TV		 2592 if (enable) {
2593 unsigned long flags;
2594 /* When we enable digit output, we'll get an extra digit
2595 * sync lost interrupt, that we need to ignore */
2596 spin_lock_irqsave(&dispc.irq_lock, flags);
2597 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2598 _omap_dispc_set_irqs();
2599 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2600 }
2601
2602 /* When we disable digit output, we need to wait until fields are done.
2603 * Otherwise the DSS is still working, and turning off the clocks
2604 * prevents DSS from going to OFF mode. And when enabling, we need to
2605 * wait for the extra sync losts */
2606 init_completion(&frame_done_completion);
2607
e82b090b
TV		 2608 if (src == DSS_HDMI_M_PCLK && enable == false) {
2609 irq_mask = DISPC_IRQ_FRAMEDONETV;
2610 num_irqs = 1;
2611 } else {
2612 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2613 /* XXX I understand from TRM that we should only wait for the
2614 * current field to complete. But it seems we have to wait for
2615 * both fields */
2616 num_irqs = 2;
2617 }
2618
80c39712 2619 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2620 irq_mask);
80c39712 2621 if (r)
e82b090b 2622 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2623
2624 _enable_digit_out(enable);
2625
e82b090b
TV		 2626 for (i = 0; i < num_irqs; ++i) {
2627 if (!wait_for_completion_timeout(&frame_done_completion,
2628 msecs_to_jiffies(100)))
2629 DSSERR("timeout waiting for digit out to %s\n",
2630 enable ? "start" : "stop");
2631 }
80c39712 2632
e82b090b
TV		 2633 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2634 irq_mask);
80c39712 2635 if (r)
e82b090b 2636 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2637
2638 if (enable) {
2639 unsigned long flags;
2640 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2641 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2642 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2643 _omap_dispc_set_irqs();
2644 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2645 }
80c39712
TV		 2646}
2647
26d9dd0d 2648bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84 2649{
efa70b3b 2650 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
a2faee84
TV		 2651}
2652
26d9dd0d 2653void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2654{
dd88b7a6 2655 if (dss_mgr_is_lcd(channel))
26d9dd0d 2656 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2657 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2658 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2659 else
2660 BUG();
2661}
2662
80c39712
TV		 2663void dispc_lcd_enable_signal_polarity(bool act_high)
2664{
6ced40bf
AT		 2665 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2666 return;
2667
80c39712 2668 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2669}
2670
2671void dispc_lcd_enable_signal(bool enable)
2672{
6ced40bf
AT		 2673 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2674 return;
2675
80c39712 2676 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2677}
2678
2679void dispc_pck_free_enable(bool enable)
2680{
6ced40bf
AT		 2681 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2682 return;
2683
80c39712 2684 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2685}
2686
26d9dd0d 2687void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2688{
efa70b3b 2689 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2690}
2691
2692
d21f43bc 2693void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2694{
d21f43bc 2695 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2696}
2697
2698void dispc_set_loadmode(enum omap_dss_load_mode mode)
2699{
80c39712 2700 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2701}
2702
2703
c64dca40 2704static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2705{
8613b000 2706 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2707}
2708
c64dca40 2709static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2710 enum omap_dss_trans_key_type type,
2711 u32 trans_key)
2712{
efa70b3b 2713 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2714
8613b000 2715 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2716}
2717
c64dca40 2718static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2719{
efa70b3b 2720 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2721}
11354dd5 2722
c64dca40
TV		 2723static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2724 bool enable)
80c39712 2725{
11354dd5 2726 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2727 return;
2728
80c39712
TV		 2729 if (ch == OMAP_DSS_CHANNEL_LCD)
2730 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2731 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2732 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2733}
11354dd5 2734
c64dca40
TV		 2735void dispc_mgr_setup(enum omap_channel channel,
2736 struct omap_overlay_manager_info *info)
2737{
2738 dispc_mgr_set_default_color(channel, info->default_color);
2739 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2740 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2741 dispc_mgr_enable_alpha_fixed_zorder(channel,
2742 info->partial_alpha_enabled);
2743 if (dss_has_feature(FEAT_CPR)) {
2744 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2745 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2746 }
2747}
80c39712 2748
26d9dd0d 2749void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2750{
2751 int code;
2752
2753 switch (data_lines) {
2754 case 12:
2755 code = 0;
2756 break;
2757 case 16:
2758 code = 1;
2759 break;
2760 case 18:
2761 code = 2;
2762 break;
2763 case 24:
2764 code = 3;
2765 break;
2766 default:
2767 BUG();
2768 return;
2769 }
2770
efa70b3b 2771 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2772}
2773
569969d6 2774void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2775{
2776 u32 l;
569969d6 2777 int gpout0, gpout1;
80c39712
TV		 2778
2779 switch (mode) {
569969d6
AT		 2780 case DSS_IO_PAD_MODE_RESET:
2781 gpout0 = 0;
2782 gpout1 = 0;
80c39712 2783 break;
569969d6
AT		 2784 case DSS_IO_PAD_MODE_RFBI:
2785 gpout0 = 1;
80c39712
TV		 2786 gpout1 = 0;
2787 break;
569969d6
AT		 2788 case DSS_IO_PAD_MODE_BYPASS:
2789 gpout0 = 1;
80c39712
TV		 2790 gpout1 = 1;
2791 break;
80c39712
TV		 2792 default:
2793 BUG();
2794 return;
2795 }
2796
569969d6
AT		 2797 l = dispc_read_reg(DISPC_CONTROL);
2798 l = FLD_MOD(l, gpout0, 15, 15);
2799 l = FLD_MOD(l, gpout1, 16, 16);
2800 dispc_write_reg(DISPC_CONTROL, l);
2801}
2802
2803void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2804{
efa70b3b 2805 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2806}
2807
8f366162
AT		 2808static bool _dispc_mgr_size_ok(u16 width, u16 height)
2809{
2810 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2811 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2812}
2813
80c39712
TV		 2814static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2815 int vsw, int vfp, int vbp)
2816{
dcbe765b
CM		 2817 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2818 hfp < 1 || hfp > dispc.feat->hp_max ||
2819 hbp < 1 || hbp > dispc.feat->hp_max ||
2820 vsw < 1 || vsw > dispc.feat->sw_max ||
2821 vfp < 0 || vfp > dispc.feat->vp_max ||
2822 vbp < 0 || vbp > dispc.feat->vp_max)
2823 return false;
80c39712
TV		 2824 return true;
2825}
2826
8f366162 2827bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2828 const struct omap_video_timings *timings)
80c39712 2829{
8f366162
AT		 2830 bool timings_ok;
2831
2832 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2833
dd88b7a6 2834 if (dss_mgr_is_lcd(channel))
8f366162
AT		 2835 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2836 timings->hfp, timings->hbp,
2837 timings->vsw, timings->vfp,
2838 timings->vbp);
2839
2840 return timings_ok;
80c39712
TV		 2841}
2842
26d9dd0d 2843static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2844 int hfp, int hbp, int vsw, int vfp, int vbp,
2845 enum omap_dss_signal_level vsync_level,
2846 enum omap_dss_signal_level hsync_level,
2847 enum omap_dss_signal_edge data_pclk_edge,
2848 enum omap_dss_signal_level de_level,
2849 enum omap_dss_signal_edge sync_pclk_edge)
2850
80c39712 2851{
655e2941
AT		 2852 u32 timing_h, timing_v, l;
2853 bool onoff, rf, ipc;
80c39712 2854
dcbe765b
CM		 2855 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2856 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2857 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2858 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2859 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2860 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 2861
64ba4f74
SS		 2862 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2863 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 2864
2865 switch (data_pclk_edge) {
2866 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2867 ipc = false;
2868 break;
2869 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2870 ipc = true;
2871 break;
2872 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2873 default:
2874 BUG();
2875 }
2876
2877 switch (sync_pclk_edge) {
2878 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2879 onoff = false;
2880 rf = false;
2881 break;
2882 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2883 onoff = true;
2884 rf = false;
2885 break;
2886 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2887 onoff = true;
2888 rf = true;
2889 break;
2890 default:
2891 BUG();
2892 };
2893
2894 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2895 l |= FLD_VAL(onoff, 17, 17);
2896 l |= FLD_VAL(rf, 16, 16);
2897 l |= FLD_VAL(de_level, 15, 15);
2898 l |= FLD_VAL(ipc, 14, 14);
2899 l |= FLD_VAL(hsync_level, 13, 13);
2900 l |= FLD_VAL(vsync_level, 12, 12);
2901 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2902}
2903
2904/* change name to mode? */
c51d921a 2905void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2906 struct omap_video_timings *timings)
80c39712
TV		 2907{
2908 unsigned xtot, ytot;
2909 unsigned long ht, vt;
2aefad49 2910 struct omap_video_timings t = *timings;
80c39712 2911
2aefad49 2912 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 2913
2aefad49 2914 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2915 BUG();
c6eee968
TV		 2916 return;
2917 }
80c39712 2918
dd88b7a6 2919 if (dss_mgr_is_lcd(channel)) {
2aefad49 2920 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 2921 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2922 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 2923
2aefad49
AT		 2924 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2925 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 2926
c51d921a
AT		 2927 ht = (timings->pixel_clock * 1000) / xtot;
2928 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2929
2930 DSSDBG("pck %u\n", timings->pixel_clock);
2931 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 2932 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 2933 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2934 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2935 t.de_level, t.sync_pclk_edge);
80c39712 2936
c51d921a 2937 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 2938 } else {
23c8f88e 2939 if (t.interlace == true)
2aefad49 2940 t.y_res /= 2;
c51d921a 2941 }
8f366162 2942
2aefad49 2943 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 2944}
2945
26d9dd0d 2946static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2947 u16 pck_div)
80c39712
TV		 2948{
2949 BUG_ON(lck_div < 1);
9eaaf207 2950 BUG_ON(pck_div < 1);
80c39712 2951
ce7fa5eb 2952 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2953 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2954}
2955
26d9dd0d 2956static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2957 int *pck_div)
80c39712
TV		 2958{
2959 u32 l;
ce7fa5eb 2960 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2961 *lck_div = FLD_GET(l, 23, 16);
2962 *pck_div = FLD_GET(l, 7, 0);
2963}
2964
2965unsigned long dispc_fclk_rate(void)
2966{
a72b64b9 2967 struct platform_device *dsidev;
80c39712
TV		 2968 unsigned long r = 0;
2969
66534e8e 2970 switch (dss_get_dispc_clk_source()) {
89a35e51 2971 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2972 r = clk_get_rate(dispc.dss_clk);
66534e8e 2973 break;
89a35e51 2974 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2975 dsidev = dsi_get_dsidev_from_id(0);
2976 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2977 break;
5a8b572d
AT		 2978 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2979 dsidev = dsi_get_dsidev_from_id(1);
2980 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2981 break;
66534e8e
TA		 2982 default:
2983 BUG();
c6eee968 2984 return 0;
66534e8e
TA		 2985 }
2986
80c39712
TV		 2987 return r;
2988}
2989
26d9dd0d 2990unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2991{
a72b64b9 2992 struct platform_device *dsidev;
80c39712
TV		 2993 int lcd;
2994 unsigned long r;
2995 u32 l;
2996
ce7fa5eb 2997 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2998
2999 lcd = FLD_GET(l, 23, 16);
3000
ea75159e 3001 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 3002 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 3003 r = clk_get_rate(dispc.dss_clk);
ea75159e 3004 break;
89a35e51 3005 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3006 dsidev = dsi_get_dsidev_from_id(0);
3007 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 3008 break;
5a8b572d
AT		 3009 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3010 dsidev = dsi_get_dsidev_from_id(1);
3011 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3012 break;
ea75159e
TA		 3013 default:
3014 BUG();
c6eee968 3015 return 0;
ea75159e 3016 }
80c39712
TV		 3017
3018 return r / lcd;
3019}
3020
26d9dd0d 3021unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3022{
80c39712 3023 unsigned long r;
80c39712 3024
dd88b7a6 3025 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3026 int pcd;
3027 u32 l;
80c39712 3028
c3dc6a7a 3029 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3030
c3dc6a7a 3031 pcd = FLD_GET(l, 7, 0);
80c39712 3032
c3dc6a7a
AT		 3033 r = dispc_mgr_lclk_rate(channel);
3034
3035 return r / pcd;
3036 } else {
3fa03ba8 3037 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 3038
3fa03ba8
AT		 3039 source = dss_get_hdmi_venc_clk_source();
3040
3041 switch (source) {
3042 case DSS_VENC_TV_CLK:
c3dc6a7a 3043 return venc_get_pixel_clock();
3fa03ba8 3044 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 3045 return hdmi_get_pixel_clock();
3046 default:
3047 BUG();
c6eee968 3048 return 0;
c3dc6a7a
AT		 3049 }
3050 }
80c39712
TV		 3051}
3052
8b53d991
CM		 3053unsigned long dispc_core_clk_rate(void)
3054{
3055 int lcd;
3056 unsigned long fclk = dispc_fclk_rate();
3057
3058 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3059 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3060 else
3061 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3062
3063 return fclk / lcd;
3064}
3065
3e8a6ff2
AT		 3066static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3067{
3068 enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3069
3070 return dispc_mgr_pclk_rate(channel);
3071}
3072
3073static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3074{
3075 enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3076
3077 if (dss_mgr_is_lcd(channel))
3078 return dispc_mgr_lclk_rate(channel);
3079 else
3080 return dispc_fclk_rate();
3081
3082}
6f1891fc 3083static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3084{
3085 int lcd, pcd;
6f1891fc
CM		 3086 enum omap_dss_clk_source lcd_clk_src;
3087
3088 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3089
3090 lcd_clk_src = dss_get_lcd_clk_source(channel);
3091
3092 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3093 dss_get_generic_clk_source_name(lcd_clk_src),
3094 dss_feat_get_clk_source_name(lcd_clk_src));
3095
3096 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3097
3098 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3099 dispc_mgr_lclk_rate(channel), lcd);
3100 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3101 dispc_mgr_pclk_rate(channel), pcd);
3102}
3103
3104void dispc_dump_clocks(struct seq_file *s)
3105{
3106 int lcd;
0cf35df3 3107 u32 l;
89a35e51 3108 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3109
4fbafaf3
TV		 3110 if (dispc_runtime_get())
3111 return;
80c39712 3112
80c39712
TV		 3113 seq_printf(s, "- DISPC -\n");
3114
067a57e4
AT		 3115 seq_printf(s, "dispc fclk source = %s (%s)\n",
3116 dss_get_generic_clk_source_name(dispc_clk_src),
3117 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3118
3119 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3120
0cf35df3
MR		 3121 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3122 seq_printf(s, "- DISPC-CORE-CLK -\n");
3123 l = dispc_read_reg(DISPC_DIVISOR);
3124 lcd = FLD_GET(l, 23, 16);
3125
3126 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3127 (dispc_fclk_rate()/lcd), lcd);
3128 }
2a205f34 3129
6f1891fc 3130 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3131
6f1891fc
CM		 3132 if (dss_has_feature(FEAT_MGR_LCD2))
3133 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3134 if (dss_has_feature(FEAT_MGR_LCD3))
3135 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3136
3137 dispc_runtime_put();
80c39712
TV		 3138}
3139
dfc0fd8d
TV		 3140#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3141void dispc_dump_irqs(struct seq_file *s)
3142{
3143 unsigned long flags;
3144 struct dispc_irq_stats stats;
3145
3146 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3147
3148 stats = dispc.irq_stats;
3149 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3150 dispc.irq_stats.last_reset = jiffies;
3151
3152 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3153
3154 seq_printf(s, "period %u ms\n",
3155 jiffies_to_msecs(jiffies - stats.last_reset));
3156
3157 seq_printf(s, "irqs %d\n", stats.irq_count);
3158#define PIS(x) \
3159 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3160
3161 PIS(FRAMEDONE);
3162 PIS(VSYNC);
3163 PIS(EVSYNC_EVEN);
3164 PIS(EVSYNC_ODD);
3165 PIS(ACBIAS_COUNT_STAT);
3166 PIS(PROG_LINE_NUM);
3167 PIS(GFX_FIFO_UNDERFLOW);
3168 PIS(GFX_END_WIN);
3169 PIS(PAL_GAMMA_MASK);
3170 PIS(OCP_ERR);
3171 PIS(VID1_FIFO_UNDERFLOW);
3172 PIS(VID1_END_WIN);
3173 PIS(VID2_FIFO_UNDERFLOW);
3174 PIS(VID2_END_WIN);
b8c095b4
AT		 3175 if (dss_feat_get_num_ovls() > 3) {
3176 PIS(VID3_FIFO_UNDERFLOW);
3177 PIS(VID3_END_WIN);
3178 }
dfc0fd8d
TV		 3179 PIS(SYNC_LOST);
3180 PIS(SYNC_LOST_DIGIT);
3181 PIS(WAKEUP);
2a205f34
SS		 3182 if (dss_has_feature(FEAT_MGR_LCD2)) {
3183 PIS(FRAMEDONE2);
3184 PIS(VSYNC2);
3185 PIS(ACBIAS_COUNT_STAT2);
3186 PIS(SYNC_LOST2);
3187 }
6f1891fc
CM		 3188 if (dss_has_feature(FEAT_MGR_LCD3)) {
3189 PIS(FRAMEDONE3);
3190 PIS(VSYNC3);
3191 PIS(ACBIAS_COUNT_STAT3);
3192 PIS(SYNC_LOST3);
3193 }
dfc0fd8d
TV		 3194#undef PIS
3195}
dfc0fd8d
TV		 3196#endif
3197
e40402cf 3198static void dispc_dump_regs(struct seq_file *s)
80c39712 3199{
4dd2da15
AT		 3200 int i, j;
3201 const char *mgr_names[] = {
3202 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3203 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3204 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3205 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3206 };
3207 const char *ovl_names[] = {
3208 [OMAP_DSS_GFX] = "GFX",
3209 [OMAP_DSS_VIDEO1] = "VID1",
3210 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3211 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3212 };
3213 const char **p_names;
3214
9b372c2d 3215#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3216
4fbafaf3
TV		 3217 if (dispc_runtime_get())
3218 return;
80c39712 3219
5010be80 3220 /* DISPC common registers */
80c39712
TV		 3221 DUMPREG(DISPC_REVISION);
3222 DUMPREG(DISPC_SYSCONFIG);
3223 DUMPREG(DISPC_SYSSTATUS);
3224 DUMPREG(DISPC_IRQSTATUS);
3225 DUMPREG(DISPC_IRQENABLE);
3226 DUMPREG(DISPC_CONTROL);
3227 DUMPREG(DISPC_CONFIG);
3228 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3229 DUMPREG(DISPC_LINE_STATUS);
3230 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3231 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3232 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3233 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3234 if (dss_has_feature(FEAT_MGR_LCD2)) {
3235 DUMPREG(DISPC_CONTROL2);
3236 DUMPREG(DISPC_CONFIG2);
5010be80 3237 }
6f1891fc
CM		 3238 if (dss_has_feature(FEAT_MGR_LCD3)) {
3239 DUMPREG(DISPC_CONTROL3);
3240 DUMPREG(DISPC_CONFIG3);
3241 }
5010be80
AT		 3242
3243#undef DUMPREG
3244
3245#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 3246#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3247 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 3248 dispc_read_reg(DISPC_REG(i, r)))
3249
4dd2da15 3250 p_names = mgr_names;
5010be80 3251
4dd2da15
AT		 3252 /* DISPC channel specific registers */
3253 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3254 DUMPREG(i, DISPC_DEFAULT_COLOR);
3255 DUMPREG(i, DISPC_TRANS_COLOR);
3256 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3257
4dd2da15
AT		 3258 if (i == OMAP_DSS_CHANNEL_DIGIT)
3259 continue;
5010be80 3260
4dd2da15
AT		 3261 DUMPREG(i, DISPC_DEFAULT_COLOR);
3262 DUMPREG(i, DISPC_TRANS_COLOR);
3263 DUMPREG(i, DISPC_TIMING_H);
3264 DUMPREG(i, DISPC_TIMING_V);
3265 DUMPREG(i, DISPC_POL_FREQ);
3266 DUMPREG(i, DISPC_DIVISORo);
3267 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3268
4dd2da15
AT		 3269 DUMPREG(i, DISPC_DATA_CYCLE1);
3270 DUMPREG(i, DISPC_DATA_CYCLE2);
3271 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3272
332e9d70 3273 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3274 DUMPREG(i, DISPC_CPR_COEF_R);
3275 DUMPREG(i, DISPC_CPR_COEF_G);
3276 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3277 }
2a205f34 3278 }
80c39712 3279
4dd2da15
AT		 3280 p_names = ovl_names;
3281
3282 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3283 DUMPREG(i, DISPC_OVL_BA0);
3284 DUMPREG(i, DISPC_OVL_BA1);
3285 DUMPREG(i, DISPC_OVL_POSITION);
3286 DUMPREG(i, DISPC_OVL_SIZE);
3287 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3288 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3289 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3290 DUMPREG(i, DISPC_OVL_ROW_INC);
3291 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3292 if (dss_has_feature(FEAT_PRELOAD))
3293 DUMPREG(i, DISPC_OVL_PRELOAD);
3294
3295 if (i == OMAP_DSS_GFX) {
3296 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3297 DUMPREG(i, DISPC_OVL_TABLE_BA);
3298 continue;
3299 }
3300
3301 DUMPREG(i, DISPC_OVL_FIR);
3302 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3303 DUMPREG(i, DISPC_OVL_ACCU0);
3304 DUMPREG(i, DISPC_OVL_ACCU1);
3305 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3306 DUMPREG(i, DISPC_OVL_BA0_UV);
3307 DUMPREG(i, DISPC_OVL_BA1_UV);
3308 DUMPREG(i, DISPC_OVL_FIR2);
3309 DUMPREG(i, DISPC_OVL_ACCU2_0);
3310 DUMPREG(i, DISPC_OVL_ACCU2_1);
3311 }
3312 if (dss_has_feature(FEAT_ATTR2))
3313 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3314 if (dss_has_feature(FEAT_PRELOAD))
3315 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3316 }
5010be80
AT		 3317
3318#undef DISPC_REG
3319#undef DUMPREG
3320
3321#define DISPC_REG(plane, name, i) name(plane, i)
3322#define DUMPREG(plane, name, i) \
4dd2da15
AT		 3323 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3324 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 3325 dispc_read_reg(DISPC_REG(plane, name, i)))
3326
4dd2da15 3327 /* Video pipeline coefficient registers */
332e9d70 3328
4dd2da15
AT		 3329 /* start from OMAP_DSS_VIDEO1 */
3330 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3331 for (j = 0; j < 8; j++)
3332 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3333
4dd2da15
AT		 3334 for (j = 0; j < 8; j++)
3335 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3336
4dd2da15
AT		 3337 for (j = 0; j < 5; j++)
3338 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3339
4dd2da15
AT		 3340 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3341 for (j = 0; j < 8; j++)
3342 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3343 }
3344
3345 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3346 for (j = 0; j < 8; j++)
3347 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3348
3349 for (j = 0; j < 8; j++)
3350 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3351
3352 for (j = 0; j < 8; j++)
3353 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3354 }
332e9d70 3355 }
80c39712 3356
4fbafaf3 3357 dispc_runtime_put();
5010be80
AT		 3358
3359#undef DISPC_REG
80c39712
TV		 3360#undef DUMPREG
3361}
3362
80c39712 3363/* with fck as input clock rate, find dispc dividers that produce req_pck */
6d523e7b 3364void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
80c39712
TV		 3365 struct dispc_clock_info *cinfo)
3366{
9eaaf207 3367 u16 pcd_min, pcd_max;
80c39712
TV		 3368 unsigned long best_pck;
3369 u16 best_ld, cur_ld;
3370 u16 best_pd, cur_pd;
3371
9eaaf207
TV		 3372 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3373 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3374
80c39712
TV		 3375 best_pck = 0;
3376 best_ld = 0;
3377 best_pd = 0;
3378
3379 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3380 unsigned long lck = fck / cur_ld;
3381
9eaaf207 3382 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3383 unsigned long pck = lck / cur_pd;
3384 long old_delta = abs(best_pck - req_pck);
3385 long new_delta = abs(pck - req_pck);
3386
3387 if (best_pck == 0 || new_delta < old_delta) {
3388 best_pck = pck;
3389 best_ld = cur_ld;
3390 best_pd = cur_pd;
3391
3392 if (pck == req_pck)
3393 goto found;
3394 }
3395
3396 if (pck < req_pck)
3397 break;
3398 }
3399
3400 if (lck / pcd_min < req_pck)
3401 break;
3402 }
3403
3404found:
3405 cinfo->lck_div = best_ld;
3406 cinfo->pck_div = best_pd;
3407 cinfo->lck = fck / cinfo->lck_div;
3408 cinfo->pck = cinfo->lck / cinfo->pck_div;
3409}
3410
3411/* calculate clock rates using dividers in cinfo */
3412int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3413 struct dispc_clock_info *cinfo)
3414{
3415 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3416 return -EINVAL;
9eaaf207 3417 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3418 return -EINVAL;
3419
3420 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3421 cinfo->pck = cinfo->lck / cinfo->pck_div;
3422
3423 return 0;
3424}
3425
f0d08f89 3426void dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3427 struct dispc_clock_info *cinfo)
80c39712
TV		 3428{
3429 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3430 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3431
26d9dd0d 3432 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3433}
3434
26d9dd0d 3435int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3436 struct dispc_clock_info *cinfo)
80c39712
TV		 3437{
3438 unsigned long fck;
3439
3440 fck = dispc_fclk_rate();
3441
ce7fa5eb
MR		 3442 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3443 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3444
3445 cinfo->lck = fck / cinfo->lck_div;
3446 cinfo->pck = cinfo->lck / cinfo->pck_div;
3447
3448 return 0;
3449}
3450
3451/* dispc.irq_lock has to be locked by the caller */
3452static void _omap_dispc_set_irqs(void)
3453{
3454 u32 mask;
3455 u32 old_mask;
3456 int i;
3457 struct omap_dispc_isr_data *isr_data;
3458
3459 mask = dispc.irq_error_mask;
3460
3461 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3462 isr_data = &dispc.registered_isr[i];
3463
3464 if (isr_data->isr == NULL)
3465 continue;
3466
3467 mask |= isr_data->mask;
3468 }
3469
80c39712
TV		 3470 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3471 /* clear the irqstatus for newly enabled irqs */
3472 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3473
3474 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3475}
3476
3477int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3478{
3479 int i;
3480 int ret;
3481 unsigned long flags;
3482 struct omap_dispc_isr_data *isr_data;
3483
3484 if (isr == NULL)
3485 return -EINVAL;
3486
3487 spin_lock_irqsave(&dispc.irq_lock, flags);
3488
3489 /* check for duplicate entry */
3490 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3491 isr_data = &dispc.registered_isr[i];
3492 if (isr_data->isr == isr && isr_data->arg == arg &&
3493 isr_data->mask == mask) {
3494 ret = -EINVAL;
3495 goto err;
3496 }
3497 }
3498
3499 isr_data = NULL;
3500 ret = -EBUSY;
3501
3502 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3503 isr_data = &dispc.registered_isr[i];
3504
3505 if (isr_data->isr != NULL)
3506 continue;
3507
3508 isr_data->isr = isr;
3509 isr_data->arg = arg;
3510 isr_data->mask = mask;
3511 ret = 0;
3512
3513 break;
3514 }
3515
b9cb0984
TV		 3516 if (ret)
3517 goto err;
3518
80c39712
TV		 3519 _omap_dispc_set_irqs();
3520
3521 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3522
3523 return 0;
3524err:
3525 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3526
3527 return ret;
3528}
3529EXPORT_SYMBOL(omap_dispc_register_isr);
3530
3531int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3532{
3533 int i;
3534 unsigned long flags;
3535 int ret = -EINVAL;
3536 struct omap_dispc_isr_data *isr_data;
3537
3538 spin_lock_irqsave(&dispc.irq_lock, flags);
3539
3540 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3541 isr_data = &dispc.registered_isr[i];
3542 if (isr_data->isr != isr || isr_data->arg != arg ||
3543 isr_data->mask != mask)
3544 continue;
3545
3546 /* found the correct isr */
3547
3548 isr_data->isr = NULL;
3549 isr_data->arg = NULL;
3550 isr_data->mask = 0;
3551
3552 ret = 0;
3553 break;
3554 }
3555
3556 if (ret == 0)
3557 _omap_dispc_set_irqs();
3558
3559 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3560
3561 return ret;
3562}
3563EXPORT_SYMBOL(omap_dispc_unregister_isr);
3564
3565#ifdef DEBUG
3566static void print_irq_status(u32 status)
3567{
3568 if ((status & dispc.irq_error_mask) == 0)
3569 return;
3570
3571 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3572
3573#define PIS(x) \
3574 if (status & DISPC_IRQ_##x) \
3575 printk(#x " ");
3576 PIS(GFX_FIFO_UNDERFLOW);
3577 PIS(OCP_ERR);
3578 PIS(VID1_FIFO_UNDERFLOW);
3579 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3580 if (dss_feat_get_num_ovls() > 3)
3581 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3582 PIS(SYNC_LOST);
3583 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3584 if (dss_has_feature(FEAT_MGR_LCD2))
3585 PIS(SYNC_LOST2);
6f1891fc
CM		 3586 if (dss_has_feature(FEAT_MGR_LCD3))
3587 PIS(SYNC_LOST3);
80c39712
TV		 3588#undef PIS
3589
3590 printk("\n");
3591}
3592#endif
3593
3594/* Called from dss.c. Note that we don't touch clocks here,
3595 * but we presume they are on because we got an IRQ. However,
3596 * an irq handler may turn the clocks off, so we may not have
3597 * clock later in the function. */
affe360d 3598static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3599{
3600 int i;
affe360d 3601 u32 irqstatus, irqenable;
80c39712
TV		 3602 u32 handledirqs = 0;
3603 u32 unhandled_errors;
3604 struct omap_dispc_isr_data *isr_data;
3605 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3606
3607 spin_lock(&dispc.irq_lock);
3608
3609 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3610 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3611
3612 /* IRQ is not for us */
3613 if (!(irqstatus & irqenable)) {
3614 spin_unlock(&dispc.irq_lock);
3615 return IRQ_NONE;
3616 }
80c39712 3617
dfc0fd8d
TV		 3618#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3619 spin_lock(&dispc.irq_stats_lock);
3620 dispc.irq_stats.irq_count++;
3621 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3622 spin_unlock(&dispc.irq_stats_lock);
3623#endif
3624
80c39712
TV		 3625#ifdef DEBUG
3626 if (dss_debug)
3627 print_irq_status(irqstatus);
3628#endif
3629 /* Ack the interrupt. Do it here before clocks are possibly turned
3630 * off */
3631 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3632 /* flush posted write */
3633 dispc_read_reg(DISPC_IRQSTATUS);
3634
3635 /* make a copy and unlock, so that isrs can unregister
3636 * themselves */
3637 memcpy(registered_isr, dispc.registered_isr,
3638 sizeof(registered_isr));
3639
3640 spin_unlock(&dispc.irq_lock);
3641
3642 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3643 isr_data = &registered_isr[i];
3644
3645 if (!isr_data->isr)
3646 continue;
3647
3648 if (isr_data->mask & irqstatus) {
3649 isr_data->isr(isr_data->arg, irqstatus);
3650 handledirqs |= isr_data->mask;
3651 }
3652 }
3653
3654 spin_lock(&dispc.irq_lock);
3655
3656 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3657
3658 if (unhandled_errors) {
3659 dispc.error_irqs |= unhandled_errors;
3660
3661 dispc.irq_error_mask &= ~unhandled_errors;
3662 _omap_dispc_set_irqs();
3663
3664 schedule_work(&dispc.error_work);
3665 }
3666
3667 spin_unlock(&dispc.irq_lock);
affe360d 3668
3669 return IRQ_HANDLED;
80c39712
TV		 3670}
3671
3672static void dispc_error_worker(struct work_struct *work)
3673{
3674 int i;
3675 u32 errors;
3676 unsigned long flags;
fe3cc9d6
TV		 3677 static const unsigned fifo_underflow_bits[] = {
3678 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3679 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3680 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3681 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3682 };
3683
80c39712
TV		 3684 spin_lock_irqsave(&dispc.irq_lock, flags);
3685 errors = dispc.error_irqs;
3686 dispc.error_irqs = 0;
3687 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3688
13eae1f9
DZ		 3689 dispc_runtime_get();
3690
fe3cc9d6
TV		 3691 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3692 struct omap_overlay *ovl;
3693 unsigned bit;
80c39712 3694
fe3cc9d6
TV		 3695 ovl = omap_dss_get_overlay(i);
3696 bit = fifo_underflow_bits[i];
80c39712 3697
fe3cc9d6
TV		 3698 if (bit & errors) {
3699 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3700 ovl->name);
f0e5caab 3701 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3702 dispc_mgr_go(ovl->manager->id);
d7ad718d 3703 msleep(50);
80c39712
TV		 3704 }
3705 }
3706
fe3cc9d6
TV		 3707 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3708 struct omap_overlay_manager *mgr;
3709 unsigned bit;
80c39712 3710
fe3cc9d6 3711 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3712 bit = mgr_desc[i].sync_lost_irq;
80c39712 3713
fe3cc9d6 3714 if (bit & errors) {
794bc4ee 3715 struct omap_dss_device *dssdev = mgr->get_device(mgr);
fe3cc9d6 3716 bool enable;
80c39712 3717
fe3cc9d6
TV		 3718 DSSERR("SYNC_LOST on channel %s, restarting the output "
3719 "with video overlays disabled\n",
3720 mgr->name);
2a205f34 3721
fe3cc9d6
TV		 3722 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3723 dssdev->driver->disable(dssdev);
2a205f34 3724
2a205f34
SS		 3725 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3726 struct omap_overlay *ovl;
3727 ovl = omap_dss_get_overlay(i);
3728
fe3cc9d6
TV		 3729 if (ovl->id != OMAP_DSS_GFX &&
3730 ovl->manager == mgr)
f0e5caab 3731 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3732 }
3733
26d9dd0d 3734 dispc_mgr_go(mgr->id);
d7ad718d 3735 msleep(50);
fe3cc9d6 3736
2a205f34
SS		 3737 if (enable)
3738 dssdev->driver->enable(dssdev);
3739 }
3740 }
3741
80c39712
TV		 3742 if (errors & DISPC_IRQ_OCP_ERR) {
3743 DSSERR("OCP_ERR\n");
3744 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3745 struct omap_overlay_manager *mgr;
794bc4ee
AT		 3746 struct omap_dss_device *dssdev;
3747
80c39712 3748 mgr = omap_dss_get_overlay_manager(i);
794bc4ee
AT		 3749 dssdev = mgr->get_device(mgr);
3750
3751 if (dssdev && dssdev->driver)
3752 dssdev->driver->disable(dssdev);
80c39712
TV		 3753 }
3754 }
3755
3756 spin_lock_irqsave(&dispc.irq_lock, flags);
3757 dispc.irq_error_mask |= errors;
3758 _omap_dispc_set_irqs();
3759 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3760
3761 dispc_runtime_put();
80c39712
TV		 3762}
3763
3764int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3765{
3766 void dispc_irq_wait_handler(void *data, u32 mask)
3767 {
3768 complete((struct completion *)data);
3769 }
3770
3771 int r;
3772 DECLARE_COMPLETION_ONSTACK(completion);
3773
3774 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3775 irqmask);
3776
3777 if (r)
3778 return r;
3779
3780 timeout = wait_for_completion_timeout(&completion, timeout);
3781
3782 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3783
3784 if (timeout == 0)
3785 return -ETIMEDOUT;
3786
3787 if (timeout == -ERESTARTSYS)
3788 return -ERESTARTSYS;
3789
3790 return 0;
3791}
3792
3793int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3794 unsigned long timeout)
3795{
3796 void dispc_irq_wait_handler(void *data, u32 mask)
3797 {
3798 complete((struct completion *)data);
3799 }
3800
3801 int r;
3802 DECLARE_COMPLETION_ONSTACK(completion);
3803
3804 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3805 irqmask);
3806
3807 if (r)
3808 return r;
3809
3810 timeout = wait_for_completion_interruptible_timeout(&completion,
3811 timeout);
3812
3813 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3814
3815 if (timeout == 0)
3816 return -ETIMEDOUT;
3817
3818 if (timeout == -ERESTARTSYS)
3819 return -ERESTARTSYS;
3820
3821 return 0;
3822}
3823
80c39712
TV		 3824static void _omap_dispc_initialize_irq(void)
3825{
3826 unsigned long flags;
3827
3828 spin_lock_irqsave(&dispc.irq_lock, flags);
3829
3830 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3831
3832 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3833 if (dss_has_feature(FEAT_MGR_LCD2))
3834 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
e86d456a
CM		 3835 if (dss_has_feature(FEAT_MGR_LCD3))
3836 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
b8c095b4
AT		 3837 if (dss_feat_get_num_ovls() > 3)
3838 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3839
3840 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3841 * so clear it */
3842 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3843
3844 _omap_dispc_set_irqs();
3845
3846 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3847}
3848
3849void dispc_enable_sidle(void)
3850{
3851 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3852}
3853
3854void dispc_disable_sidle(void)
3855{
3856 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3857}
3858
3859static void _omap_dispc_initial_config(void)
3860{
3861 u32 l;
3862
0cf35df3
MR		 3863 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3864 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3865 l = dispc_read_reg(DISPC_DIVISOR);
3866 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3867 l = FLD_MOD(l, 1, 0, 0);
3868 l = FLD_MOD(l, 1, 23, 16);
3869 dispc_write_reg(DISPC_DIVISOR, l);
3870 }
3871
80c39712 3872 /* FUNCGATED */
6ced40bf
AT		 3873 if (dss_has_feature(FEAT_FUNCGATED))
3874 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3875
80c39712
TV		 3876 _dispc_setup_color_conv_coef();
3877
3878 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3879
42a6961c 3880 dispc_init_fifos();
5ed8cf5b
TV		 3881
3882 dispc_configure_burst_sizes();
54128701
AT		 3883
3884 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3885}
3886
dcbe765b
CM		 3887static const struct dispc_features omap24xx_dispc_feats __initconst = {
3888 .sw_start = 5,
3889 .fp_start = 15,
3890 .bp_start = 27,
3891 .sw_max = 64,
3892 .vp_max = 255,
3893 .hp_max = 256,
3894 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3895 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3896 .num_fifos = 3,
dcbe765b
CM		 3897};
3898
3899static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3900 .sw_start = 5,
3901 .fp_start = 15,
3902 .bp_start = 27,
3903 .sw_max = 64,
3904 .vp_max = 255,
3905 .hp_max = 256,
3906 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3907 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3908 .num_fifos = 3,
dcbe765b
CM		 3909};
3910
3911static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3912 .sw_start = 7,
3913 .fp_start = 19,
3914 .bp_start = 31,
3915 .sw_max = 256,
3916 .vp_max = 4095,
3917 .hp_max = 4096,
3918 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3919 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3920 .num_fifos = 3,
dcbe765b
CM		 3921};
3922
3923static const struct dispc_features omap44xx_dispc_feats __initconst = {
3924 .sw_start = 7,
3925 .fp_start = 19,
3926 .bp_start = 31,
3927 .sw_max = 256,
3928 .vp_max = 4095,
3929 .hp_max = 4096,
3930 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3931 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3932 .num_fifos = 5,
66a0f9e4 3933 .gfx_fifo_workaround = true,
dcbe765b
CM		 3934};
3935
3936static int __init dispc_init_features(struct device *dev)
3937{
3938 const struct dispc_features *src;
3939 struct dispc_features *dst;
3940
3941 dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
3942 if (!dst) {
3943 dev_err(dev, "Failed to allocate DISPC Features\n");
3944 return -ENOMEM;
3945 }
3946
3947 if (cpu_is_omap24xx()) {
3948 src = &omap24xx_dispc_feats;
3949 } else if (cpu_is_omap34xx()) {
3950 if (omap_rev() < OMAP3430_REV_ES3_0)
3951 src = &omap34xx_rev1_0_dispc_feats;
3952 else
3953 src = &omap34xx_rev3_0_dispc_feats;
3954 } else if (cpu_is_omap44xx()) {
3955 src = &omap44xx_dispc_feats;
23362832
AT		 3956 } else if (soc_is_omap54xx()) {
3957 src = &omap44xx_dispc_feats;
dcbe765b
CM		 3958 } else {
3959 return -ENODEV;
3960 }
3961
3962 memcpy(dst, src, sizeof(*dst));
3963 dispc.feat = dst;
3964
3965 return 0;
3966}
3967
060b6d9c 3968/* DISPC HW IP initialisation */
6e7e8f06 3969static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3970{
3971 u32 rev;
affe360d 3972 int r = 0;
ea9da36a 3973 struct resource *dispc_mem;
4fbafaf3 3974 struct clk *clk;
ea9da36a 3975
060b6d9c
SG		 3976 dispc.pdev = pdev;
3977
dcbe765b
CM		 3978 r = dispc_init_features(&dispc.pdev->dev);
3979 if (r)
3980 return r;
3981
060b6d9c
SG		 3982 spin_lock_init(&dispc.irq_lock);
3983
3984#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3985 spin_lock_init(&dispc.irq_stats_lock);
3986 dispc.irq_stats.last_reset = jiffies;
3987#endif
3988
3989 INIT_WORK(&dispc.error_work, dispc_error_worker);
3990
ea9da36a
SG		 3991 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3992 if (!dispc_mem) {
3993 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3994 return -EINVAL;
ea9da36a 3995 }
cd3b3449 3996
6e2a14d2
JL		 3997 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3998 resource_size(dispc_mem));
060b6d9c
SG		 3999 if (!dispc.base) {
4000 DSSERR("can't ioremap DISPC\n");
cd3b3449 4001 return -ENOMEM;
affe360d 4002 }
cd3b3449 4003
affe360d 4004 dispc.irq = platform_get_irq(dispc.pdev, 0);
4005 if (dispc.irq < 0) {
4006 DSSERR("platform_get_irq failed\n");
cd3b3449 4007 return -ENODEV;
affe360d 4008 }
4009
6e2a14d2
JL		 4010 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
4011 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 4012 if (r < 0) {
4013 DSSERR("request_irq failed\n");
cd3b3449
TV		 4014 return r;
4015 }
4016
4017 clk = clk_get(&pdev->dev, "fck");
4018 if (IS_ERR(clk)) {
4019 DSSERR("can't get fck\n");
4020 r = PTR_ERR(clk);
4021 return r;
060b6d9c
SG		 4022 }
4023
cd3b3449
TV		 4024 dispc.dss_clk = clk;
4025
4fbafaf3
TV		 4026 pm_runtime_enable(&pdev->dev);
4027
4028 r = dispc_runtime_get();
4029 if (r)
4030 goto err_runtime_get;
060b6d9c
SG		 4031
4032 _omap_dispc_initial_config();
4033
4034 _omap_dispc_initialize_irq();
4035
060b6d9c 4036 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4037 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4038 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4039
4fbafaf3 4040 dispc_runtime_put();
060b6d9c 4041
e40402cf
TV		 4042 dss_debugfs_create_file("dispc", dispc_dump_regs);
4043
4044#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4045 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
4046#endif
060b6d9c 4047 return 0;
4fbafaf3
TV		 4048
4049err_runtime_get:
4050 pm_runtime_disable(&pdev->dev);
4fbafaf3 4051 clk_put(dispc.dss_clk);
affe360d 4052 return r;
060b6d9c
SG		 4053}
4054
6e7e8f06 4055static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 4056{
4fbafaf3
TV		 4057 pm_runtime_disable(&pdev->dev);
4058
4059 clk_put(dispc.dss_clk);
4060
060b6d9c
SG		 4061 return 0;
4062}
4063
4fbafaf3
TV		 4064static int dispc_runtime_suspend(struct device *dev)
4065{
4066 dispc_save_context();
4fbafaf3
TV		 4067
4068 return 0;
4069}
4070
4071static int dispc_runtime_resume(struct device *dev)
4072{
49ea86f3 4073 dispc_restore_context();
4fbafaf3
TV		 4074
4075 return 0;
4076}
4077
4078static const struct dev_pm_ops dispc_pm_ops = {
4079 .runtime_suspend = dispc_runtime_suspend,
4080 .runtime_resume = dispc_runtime_resume,
4081};
4082
060b6d9c 4083static struct platform_driver omap_dispchw_driver = {
6e7e8f06 4084 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 4085 .driver = {
4086 .name = "omapdss_dispc",
4087 .owner = THIS_MODULE,
4fbafaf3 4088 .pm = &dispc_pm_ops,
060b6d9c
SG		 4089 },
4090};
4091
6e7e8f06 4092int __init dispc_init_platform_driver(void)
060b6d9c 4093{
11436e1d 4094 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 4095}
4096
6e7e8f06 4097void __exit dispc_uninit_platform_driver(void)
060b6d9c 4098{
04c742c3 4099 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4100}
Linux kernel - Deliverables
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