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OMAPDSS: APPLY: rewrite register writing
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712
TV		 39
40#include <plat/sram.h>
41#include <plat/clock.h>
42
a0b38cc4 43#include <video/omapdss.h>
80c39712
TV		 44
45#include "dss.h"
a0acb557 46#include "dss_features.h"
9b372c2d 47#include "dispc.h"
80c39712
TV		 48
49/* DISPC */
8613b000 50#define DISPC_SZ_REGS SZ_4K
80c39712 51
80c39712
TV		 52#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
53 DISPC_IRQ_OCP_ERR | \
54 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
55 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
56 DISPC_IRQ_SYNC_LOST | \
57 DISPC_IRQ_SYNC_LOST_DIGIT)
58
59#define DISPC_MAX_NR_ISRS 8
60
61struct omap_dispc_isr_data {
62 omap_dispc_isr_t isr;
63 void *arg;
64 u32 mask;
65};
66
66be8f6c
GI		 67struct dispc_h_coef {
68 s8 hc4;
69 s8 hc3;
70 u8 hc2;
71 s8 hc1;
72 s8 hc0;
73};
74
75struct dispc_v_coef {
76 s8 vc22;
77 s8 vc2;
78 u8 vc1;
79 s8 vc0;
80 s8 vc00;
81};
82
5ed8cf5b
TV		 83enum omap_burst_size {
84 BURST_SIZE_X2 = 0,
85 BURST_SIZE_X4 = 1,
86 BURST_SIZE_X8 = 2,
87};
88
80c39712
TV		 89#define REG_GET(idx, start, end) \
90 FLD_GET(dispc_read_reg(idx), start, end)
91
92#define REG_FLD_MOD(idx, val, start, end) \
93 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
94
dfc0fd8d
TV		 95struct dispc_irq_stats {
96 unsigned long last_reset;
97 unsigned irq_count;
98 unsigned irqs[32];
99};
100
80c39712 101static struct {
060b6d9c 102 struct platform_device *pdev;
80c39712 103 void __iomem *base;
4fbafaf3
TV		 104
105 int ctx_loss_cnt;
106
affe360d 107 int irq;
4fbafaf3 108 struct clk *dss_clk;
80c39712 109
e13a138b 110 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 111
112 spinlock_t irq_lock;
113 u32 irq_error_mask;
114 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
115 u32 error_irqs;
116 struct work_struct error_work;
117
49ea86f3 118 bool ctx_valid;
80c39712 119 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 120
121#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
122 spinlock_t irq_stats_lock;
123 struct dispc_irq_stats irq_stats;
124#endif
80c39712
TV		 125} dispc;
126
0d66cbb5
AJ		 127enum omap_color_component {
128 /* used for all color formats for OMAP3 and earlier
129 * and for RGB and Y color component on OMAP4
130 */
131 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
132 /* used for UV component for
133 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
134 * color formats on OMAP4
135 */
136 DISPC_COLOR_COMPONENT_UV = 1 << 1,
137};
138
80c39712
TV		 139static void _omap_dispc_set_irqs(void);
140
55978cc2 141static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 142{
55978cc2 143 __raw_writel(val, dispc.base + idx);
80c39712
TV		 144}
145
55978cc2 146static inline u32 dispc_read_reg(const u16 idx)
80c39712 147{
55978cc2 148 return __raw_readl(dispc.base + idx);
80c39712
TV		 149}
150
49ea86f3
TV		 151static int dispc_get_ctx_loss_count(void)
152{
153 struct device *dev = &dispc.pdev->dev;
154 struct omap_display_platform_data *pdata = dev->platform_data;
155 struct omap_dss_board_info *board_data = pdata->board_data;
156 int cnt;
157
158 if (!board_data->get_context_loss_count)
159 return -ENOENT;
160
161 cnt = board_data->get_context_loss_count(dev);
162
163 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
164
165 return cnt;
166}
167
80c39712 168#define SR(reg) \
55978cc2 169 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 170#define RR(reg) \
55978cc2 171 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 172
4fbafaf3 173static void dispc_save_context(void)
80c39712 174{
c6104b8e 175 int i, j;
80c39712 176
4fbafaf3
TV		 177 DSSDBG("dispc_save_context\n");
178
80c39712
TV		 179 SR(IRQENABLE);
180 SR(CONTROL);
181 SR(CONFIG);
80c39712 182 SR(LINE_NUMBER);
11354dd5
AT		 183 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
184 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 185 SR(GLOBAL_ALPHA);
2a205f34
SS		 186 if (dss_has_feature(FEAT_MGR_LCD2)) {
187 SR(CONTROL2);
2a205f34
SS		 188 SR(CONFIG2);
189 }
80c39712 190
c6104b8e
AT		 191 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
192 SR(DEFAULT_COLOR(i));
193 SR(TRANS_COLOR(i));
194 SR(SIZE_MGR(i));
195 if (i == OMAP_DSS_CHANNEL_DIGIT)
196 continue;
197 SR(TIMING_H(i));
198 SR(TIMING_V(i));
199 SR(POL_FREQ(i));
200 SR(DIVISORo(i));
201
202 SR(DATA_CYCLE1(i));
203 SR(DATA_CYCLE2(i));
204 SR(DATA_CYCLE3(i));
205
332e9d70 206 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 207 SR(CPR_COEF_R(i));
208 SR(CPR_COEF_G(i));
209 SR(CPR_COEF_B(i));
332e9d70 210 }
2a205f34 211 }
80c39712 212
c6104b8e
AT		 213 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
214 SR(OVL_BA0(i));
215 SR(OVL_BA1(i));
216 SR(OVL_POSITION(i));
217 SR(OVL_SIZE(i));
218 SR(OVL_ATTRIBUTES(i));
219 SR(OVL_FIFO_THRESHOLD(i));
220 SR(OVL_ROW_INC(i));
221 SR(OVL_PIXEL_INC(i));
222 if (dss_has_feature(FEAT_PRELOAD))
223 SR(OVL_PRELOAD(i));
224 if (i == OMAP_DSS_GFX) {
225 SR(OVL_WINDOW_SKIP(i));
226 SR(OVL_TABLE_BA(i));
227 continue;
228 }
229 SR(OVL_FIR(i));
230 SR(OVL_PICTURE_SIZE(i));
231 SR(OVL_ACCU0(i));
232 SR(OVL_ACCU1(i));
9b372c2d 233
c6104b8e
AT		 234 for (j = 0; j < 8; j++)
235 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 236
c6104b8e
AT		 237 for (j = 0; j < 8; j++)
238 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 239
c6104b8e
AT		 240 for (j = 0; j < 5; j++)
241 SR(OVL_CONV_COEF(i, j));
ab5ca071 242
c6104b8e
AT		 243 if (dss_has_feature(FEAT_FIR_COEF_V)) {
244 for (j = 0; j < 8; j++)
245 SR(OVL_FIR_COEF_V(i, j));
246 }
9b372c2d 247
c6104b8e
AT		 248 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
249 SR(OVL_BA0_UV(i));
250 SR(OVL_BA1_UV(i));
251 SR(OVL_FIR2(i));
252 SR(OVL_ACCU2_0(i));
253 SR(OVL_ACCU2_1(i));
ab5ca071 254
c6104b8e
AT		 255 for (j = 0; j < 8; j++)
256 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 257
c6104b8e
AT		 258 for (j = 0; j < 8; j++)
259 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 260
c6104b8e
AT		 261 for (j = 0; j < 8; j++)
262 SR(OVL_FIR_COEF_V2(i, j));
263 }
264 if (dss_has_feature(FEAT_ATTR2))
265 SR(OVL_ATTRIBUTES2(i));
ab5ca071 266 }
0cf35df3
MR		 267
268 if (dss_has_feature(FEAT_CORE_CLK_DIV))
269 SR(DIVISOR);
49ea86f3
TV		 270
271 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
272 dispc.ctx_valid = true;
273
274 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 275}
276
4fbafaf3 277static void dispc_restore_context(void)
80c39712 278{
c6104b8e 279 int i, j, ctx;
4fbafaf3
TV		 280
281 DSSDBG("dispc_restore_context\n");
282
49ea86f3
TV		 283 if (!dispc.ctx_valid)
284 return;
285
286 ctx = dispc_get_ctx_loss_count();
287
288 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
289 return;
290
291 DSSDBG("ctx_loss_count: saved %d, current %d\n",
292 dispc.ctx_loss_cnt, ctx);
293
75c7d59d 294 /*RR(IRQENABLE);*/
80c39712
TV		 295 /*RR(CONTROL);*/
296 RR(CONFIG);
80c39712 297 RR(LINE_NUMBER);
11354dd5
AT		 298 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
299 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 300 RR(GLOBAL_ALPHA);
c6104b8e 301 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 302 RR(CONFIG2);
80c39712 303
c6104b8e
AT		 304 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
305 RR(DEFAULT_COLOR(i));
306 RR(TRANS_COLOR(i));
307 RR(SIZE_MGR(i));
308 if (i == OMAP_DSS_CHANNEL_DIGIT)
309 continue;
310 RR(TIMING_H(i));
311 RR(TIMING_V(i));
312 RR(POL_FREQ(i));
313 RR(DIVISORo(i));
314
315 RR(DATA_CYCLE1(i));
316 RR(DATA_CYCLE2(i));
317 RR(DATA_CYCLE3(i));
2a205f34 318
332e9d70 319 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 320 RR(CPR_COEF_R(i));
321 RR(CPR_COEF_G(i));
322 RR(CPR_COEF_B(i));
332e9d70 323 }
2a205f34 324 }
80c39712 325
c6104b8e
AT		 326 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
327 RR(OVL_BA0(i));
328 RR(OVL_BA1(i));
329 RR(OVL_POSITION(i));
330 RR(OVL_SIZE(i));
331 RR(OVL_ATTRIBUTES(i));
332 RR(OVL_FIFO_THRESHOLD(i));
333 RR(OVL_ROW_INC(i));
334 RR(OVL_PIXEL_INC(i));
335 if (dss_has_feature(FEAT_PRELOAD))
336 RR(OVL_PRELOAD(i));
337 if (i == OMAP_DSS_GFX) {
338 RR(OVL_WINDOW_SKIP(i));
339 RR(OVL_TABLE_BA(i));
340 continue;
341 }
342 RR(OVL_FIR(i));
343 RR(OVL_PICTURE_SIZE(i));
344 RR(OVL_ACCU0(i));
345 RR(OVL_ACCU1(i));
9b372c2d 346
c6104b8e
AT		 347 for (j = 0; j < 8; j++)
348 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 349
c6104b8e
AT		 350 for (j = 0; j < 8; j++)
351 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 352
c6104b8e
AT		 353 for (j = 0; j < 5; j++)
354 RR(OVL_CONV_COEF(i, j));
ab5ca071 355
c6104b8e
AT		 356 if (dss_has_feature(FEAT_FIR_COEF_V)) {
357 for (j = 0; j < 8; j++)
358 RR(OVL_FIR_COEF_V(i, j));
359 }
9b372c2d 360
c6104b8e
AT		 361 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
362 RR(OVL_BA0_UV(i));
363 RR(OVL_BA1_UV(i));
364 RR(OVL_FIR2(i));
365 RR(OVL_ACCU2_0(i));
366 RR(OVL_ACCU2_1(i));
ab5ca071 367
c6104b8e
AT		 368 for (j = 0; j < 8; j++)
369 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 370
c6104b8e
AT		 371 for (j = 0; j < 8; j++)
372 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 373
c6104b8e
AT		 374 for (j = 0; j < 8; j++)
375 RR(OVL_FIR_COEF_V2(i, j));
376 }
377 if (dss_has_feature(FEAT_ATTR2))
378 RR(OVL_ATTRIBUTES2(i));
ab5ca071 379 }
80c39712 380
0cf35df3
MR		 381 if (dss_has_feature(FEAT_CORE_CLK_DIV))
382 RR(DIVISOR);
383
80c39712
TV		 384 /* enable last, because LCD & DIGIT enable are here */
385 RR(CONTROL);
2a205f34
SS		 386 if (dss_has_feature(FEAT_MGR_LCD2))
387 RR(CONTROL2);
75c7d59d
VS		 388 /* clear spurious SYNC_LOST_DIGIT interrupts */
389 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
390
391 /*
392 * enable last so IRQs won't trigger before
393 * the context is fully restored
394 */
395 RR(IRQENABLE);
49ea86f3
TV		 396
397 DSSDBG("context restored\n");
80c39712
TV		 398}
399
400#undef SR
401#undef RR
402
4fbafaf3
TV		 403int dispc_runtime_get(void)
404{
405 int r;
406
407 DSSDBG("dispc_runtime_get\n");
408
409 r = pm_runtime_get_sync(&dispc.pdev->dev);
410 WARN_ON(r < 0);
411 return r < 0 ? r : 0;
412}
413
414void dispc_runtime_put(void)
415{
416 int r;
417
418 DSSDBG("dispc_runtime_put\n");
419
420 r = pm_runtime_put(&dispc.pdev->dev);
421 WARN_ON(r < 0);
80c39712
TV		 422}
423
dac57a05
AT		 424static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
425{
426 if (channel == OMAP_DSS_CHANNEL_LCD ||
427 channel == OMAP_DSS_CHANNEL_LCD2)
428 return true;
429 else
430 return false;
431}
4fbafaf3 432
c3dc6a7a
AT		 433static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
434{
435 struct omap_overlay_manager *mgr =
436 omap_dss_get_overlay_manager(channel);
437
438 return mgr ? mgr->device : NULL;
439}
440
3dcec4d6
TV		 441u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
442{
443 switch (channel) {
444 case OMAP_DSS_CHANNEL_LCD:
445 return DISPC_IRQ_VSYNC;
446 case OMAP_DSS_CHANNEL_LCD2:
447 return DISPC_IRQ_VSYNC2;
448 case OMAP_DSS_CHANNEL_DIGIT:
449 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
450 default:
451 BUG();
452 }
453}
454
26d9dd0d 455bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 456{
457 int bit;
458
dac57a05 459 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 460 bit = 5; /* GOLCD */
461 else
462 bit = 6; /* GODIGIT */
463
2a205f34
SS		 464 if (channel == OMAP_DSS_CHANNEL_LCD2)
465 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
466 else
467 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 468}
469
26d9dd0d 470void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 471{
472 int bit;
2a205f34 473 bool enable_bit, go_bit;
80c39712 474
dac57a05 475 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 476 bit = 0; /* LCDENABLE */
477 else
478 bit = 1; /* DIGITALENABLE */
479
480 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 481 if (channel == OMAP_DSS_CHANNEL_LCD2)
482 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
483 else
484 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
485
486 if (!enable_bit)
e6d80f95 487 return;
80c39712 488
dac57a05 489 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 490 bit = 5; /* GOLCD */
491 else
492 bit = 6; /* GODIGIT */
493
2a205f34
SS		 494 if (channel == OMAP_DSS_CHANNEL_LCD2)
495 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
496 else
497 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
498
499 if (go_bit) {
80c39712 500 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 501 return;
80c39712
TV		 502 }
503
2a205f34
SS		 504 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
505 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 506
2a205f34
SS		 507 if (channel == OMAP_DSS_CHANNEL_LCD2)
508 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
509 else
510 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 511}
512
f0e5caab 513static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 514{
9b372c2d 515 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 516}
517
f0e5caab 518static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 519{
9b372c2d 520 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 521}
522
f0e5caab 523static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 524{
9b372c2d 525 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 526}
527
f0e5caab 528static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 529{
530 BUG_ON(plane == OMAP_DSS_GFX);
531
532 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
533}
534
f0e5caab
TV		 535static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
536 u32 value)
ab5ca071
AJ		 537{
538 BUG_ON(plane == OMAP_DSS_GFX);
539
540 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
541}
542
f0e5caab 543static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 544{
545 BUG_ON(plane == OMAP_DSS_GFX);
546
547 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
548}
549
f0e5caab 550static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
0d66cbb5
AJ		 551 int vscaleup, int five_taps,
552 enum omap_color_component color_comp)
80c39712
TV		 553{
554 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 555 static const struct dispc_h_coef coef_hup[8] = {
556 { 0, 0, 128, 0, 0 },
557 { -1, 13, 124, -8, 0 },
558 { -2, 30, 112, -11, -1 },
559 { -5, 51, 95, -11, -2 },
560 { 0, -9, 73, 73, -9 },
561 { -2, -11, 95, 51, -5 },
562 { -1, -11, 112, 30, -2 },
563 { 0, -8, 124, 13, -1 },
80c39712
TV		 564 };
565
66be8f6c
GI		 566 /* Coefficients for vertical up-sampling */
567 static const struct dispc_v_coef coef_vup_3tap[8] = {
568 { 0, 0, 128, 0, 0 },
569 { 0, 3, 123, 2, 0 },
570 { 0, 12, 111, 5, 0 },
571 { 0, 32, 89, 7, 0 },
572 { 0, 0, 64, 64, 0 },
573 { 0, 7, 89, 32, 0 },
574 { 0, 5, 111, 12, 0 },
575 { 0, 2, 123, 3, 0 },
80c39712
TV		 576 };
577
66be8f6c
GI		 578 static const struct dispc_v_coef coef_vup_5tap[8] = {
579 { 0, 0, 128, 0, 0 },
580 { -1, 13, 124, -8, 0 },
581 { -2, 30, 112, -11, -1 },
582 { -5, 51, 95, -11, -2 },
583 { 0, -9, 73, 73, -9 },
584 { -2, -11, 95, 51, -5 },
585 { -1, -11, 112, 30, -2 },
586 { 0, -8, 124, 13, -1 },
80c39712
TV		 587 };
588
66be8f6c
GI		 589 /* Coefficients for horizontal down-sampling */
590 static const struct dispc_h_coef coef_hdown[8] = {
591 { 0, 36, 56, 36, 0 },
592 { 4, 40, 55, 31, -2 },
593 { 8, 44, 54, 27, -5 },
594 { 12, 48, 53, 22, -7 },
595 { -9, 17, 52, 51, 17 },
596 { -7, 22, 53, 48, 12 },
597 { -5, 27, 54, 44, 8 },
598 { -2, 31, 55, 40, 4 },
80c39712
TV		 599 };
600
66be8f6c
GI		 601 /* Coefficients for vertical down-sampling */
602 static const struct dispc_v_coef coef_vdown_3tap[8] = {
603 { 0, 36, 56, 36, 0 },
604 { 0, 40, 57, 31, 0 },
605 { 0, 45, 56, 27, 0 },
606 { 0, 50, 55, 23, 0 },
607 { 0, 18, 55, 55, 0 },
608 { 0, 23, 55, 50, 0 },
609 { 0, 27, 56, 45, 0 },
610 { 0, 31, 57, 40, 0 },
80c39712
TV		 611 };
612
66be8f6c
GI		 613 static const struct dispc_v_coef coef_vdown_5tap[8] = {
614 { 0, 36, 56, 36, 0 },
615 { 4, 40, 55, 31, -2 },
616 { 8, 44, 54, 27, -5 },
617 { 12, 48, 53, 22, -7 },
618 { -9, 17, 52, 51, 17 },
619 { -7, 22, 53, 48, 12 },
620 { -5, 27, 54, 44, 8 },
621 { -2, 31, 55, 40, 4 },
80c39712
TV		 622 };
623
66be8f6c
GI		 624 const struct dispc_h_coef *h_coef;
625 const struct dispc_v_coef *v_coef;
80c39712
TV		 626 int i;
627
628 if (hscaleup)
629 h_coef = coef_hup;
630 else
631 h_coef = coef_hdown;
632
66be8f6c
GI		 633 if (vscaleup)
634 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
635 else
636 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 637
638 for (i = 0; i < 8; i++) {
639 u32 h, hv;
640
66be8f6c
GI		 641 h = FLD_VAL(h_coef[i].hc0, 7, 0)
642 | FLD_VAL(h_coef[i].hc1, 15, 8)
643 | FLD_VAL(h_coef[i].hc2, 23, 16)
644 | FLD_VAL(h_coef[i].hc3, 31, 24);
645 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
646 | FLD_VAL(v_coef[i].vc0, 15, 8)
647 | FLD_VAL(v_coef[i].vc1, 23, 16)
648 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712 649
0d66cbb5 650 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 651 dispc_ovl_write_firh_reg(plane, i, h);
652 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 653 } else {
f0e5caab
TV		 654 dispc_ovl_write_firh2_reg(plane, i, h);
655 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 656 }
657
80c39712
TV		 658 }
659
66be8f6c
GI		 660 if (five_taps) {
661 for (i = 0; i < 8; i++) {
662 u32 v;
663 v = FLD_VAL(v_coef[i].vc00, 7, 0)
664 | FLD_VAL(v_coef[i].vc22, 15, 8);
0d66cbb5 665 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 666 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 667 else
f0e5caab 668 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 669 }
80c39712
TV		 670 }
671}
672
673static void _dispc_setup_color_conv_coef(void)
674{
ac01c29e 675 int i;
80c39712
TV		 676 const struct color_conv_coef {
677 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
678 int full_range;
679 } ctbl_bt601_5 = {
680 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
681 };
682
683 const struct color_conv_coef *ct;
684
685#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
686
687 ct = &ctbl_bt601_5;
688
ac01c29e
AT		 689 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
690 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
691 CVAL(ct->rcr, ct->ry));
692 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
693 CVAL(ct->gy, ct->rcb));
694 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
695 CVAL(ct->gcb, ct->gcr));
696 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
697 CVAL(ct->bcr, ct->by));
698 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
699 CVAL(0, ct->bcb));
700
701 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
702 11, 11);
703 }
80c39712
TV		 704
705#undef CVAL
80c39712
TV		 706}
707
708
f0e5caab 709static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 710{
9b372c2d 711 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 712}
713
f0e5caab 714static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 715{
9b372c2d 716 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 717}
718
f0e5caab 719static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 720{
721 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
722}
723
f0e5caab 724static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 725{
726 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
727}
728
f0e5caab 729static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 730{
80c39712 731 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 732
733 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 734}
735
f0e5caab 736static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 737{
80c39712 738 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 739
740 if (plane == OMAP_DSS_GFX)
741 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
742 else
743 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 744}
745
f0e5caab 746static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 747{
748 u32 val;
80c39712
TV		 749
750 BUG_ON(plane == OMAP_DSS_GFX);
751
752 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 753
754 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 755}
756
54128701
AT		 757static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
758{
759 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
760
761 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
762 return;
763
764 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
765}
766
767static void dispc_ovl_enable_zorder_planes(void)
768{
769 int i;
770
771 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
772 return;
773
774 for (i = 0; i < dss_feat_get_num_ovls(); i++)
775 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
776}
777
f0e5caab 778static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 779{
f6dc8150 780 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 781
f6dc8150 782 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 783 return;
784
9b372c2d 785 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 786}
787
f0e5caab 788static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 789{
b8c095b4 790 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 791 int shift;
f6dc8150 792 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 793
f6dc8150 794 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 795 return;
a0acb557 796
fe3cc9d6
TV		 797 shift = shifts[plane];
798 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 799}
800
f0e5caab 801static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 802{
9b372c2d 803 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 804}
805
f0e5caab 806static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 807{
9b372c2d 808 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 809}
810
f0e5caab 811static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 812 enum omap_color_mode color_mode)
813{
814 u32 m = 0;
f20e4220
AJ		 815 if (plane != OMAP_DSS_GFX) {
816 switch (color_mode) {
817 case OMAP_DSS_COLOR_NV12:
818 m = 0x0; break;
819 case OMAP_DSS_COLOR_RGB12U:
820 m = 0x1; break;
821 case OMAP_DSS_COLOR_RGBA16:
822 m = 0x2; break;
823 case OMAP_DSS_COLOR_RGBX16:
824 m = 0x4; break;
825 case OMAP_DSS_COLOR_ARGB16:
826 m = 0x5; break;
827 case OMAP_DSS_COLOR_RGB16:
828 m = 0x6; break;
829 case OMAP_DSS_COLOR_ARGB16_1555:
830 m = 0x7; break;
831 case OMAP_DSS_COLOR_RGB24U:
832 m = 0x8; break;
833 case OMAP_DSS_COLOR_RGB24P:
834 m = 0x9; break;
835 case OMAP_DSS_COLOR_YUV2:
836 m = 0xa; break;
837 case OMAP_DSS_COLOR_UYVY:
838 m = 0xb; break;
839 case OMAP_DSS_COLOR_ARGB32:
840 m = 0xc; break;
841 case OMAP_DSS_COLOR_RGBA32:
842 m = 0xd; break;
843 case OMAP_DSS_COLOR_RGBX32:
844 m = 0xe; break;
845 case OMAP_DSS_COLOR_XRGB16_1555:
846 m = 0xf; break;
847 default:
848 BUG(); break;
849 }
850 } else {
851 switch (color_mode) {
852 case OMAP_DSS_COLOR_CLUT1:
853 m = 0x0; break;
854 case OMAP_DSS_COLOR_CLUT2:
855 m = 0x1; break;
856 case OMAP_DSS_COLOR_CLUT4:
857 m = 0x2; break;
858 case OMAP_DSS_COLOR_CLUT8:
859 m = 0x3; break;
860 case OMAP_DSS_COLOR_RGB12U:
861 m = 0x4; break;
862 case OMAP_DSS_COLOR_ARGB16:
863 m = 0x5; break;
864 case OMAP_DSS_COLOR_RGB16:
865 m = 0x6; break;
866 case OMAP_DSS_COLOR_ARGB16_1555:
867 m = 0x7; break;
868 case OMAP_DSS_COLOR_RGB24U:
869 m = 0x8; break;
870 case OMAP_DSS_COLOR_RGB24P:
871 m = 0x9; break;
872 case OMAP_DSS_COLOR_YUV2:
873 m = 0xa; break;
874 case OMAP_DSS_COLOR_UYVY:
875 m = 0xb; break;
876 case OMAP_DSS_COLOR_ARGB32:
877 m = 0xc; break;
878 case OMAP_DSS_COLOR_RGBA32:
879 m = 0xd; break;
880 case OMAP_DSS_COLOR_RGBX32:
881 m = 0xe; break;
882 case OMAP_DSS_COLOR_XRGB16_1555:
883 m = 0xf; break;
884 default:
885 BUG(); break;
886 }
80c39712
TV		 887 }
888
9b372c2d 889 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 890}
891
f427984e 892void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 893{
894 int shift;
895 u32 val;
2a205f34 896 int chan = 0, chan2 = 0;
80c39712
TV		 897
898 switch (plane) {
899 case OMAP_DSS_GFX:
900 shift = 8;
901 break;
902 case OMAP_DSS_VIDEO1:
903 case OMAP_DSS_VIDEO2:
b8c095b4 904 case OMAP_DSS_VIDEO3:
80c39712
TV		 905 shift = 16;
906 break;
907 default:
908 BUG();
909 return;
910 }
911
9b372c2d 912 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 913 if (dss_has_feature(FEAT_MGR_LCD2)) {
914 switch (channel) {
915 case OMAP_DSS_CHANNEL_LCD:
916 chan = 0;
917 chan2 = 0;
918 break;
919 case OMAP_DSS_CHANNEL_DIGIT:
920 chan = 1;
921 chan2 = 0;
922 break;
923 case OMAP_DSS_CHANNEL_LCD2:
924 chan = 0;
925 chan2 = 1;
926 break;
927 default:
928 BUG();
929 }
930
931 val = FLD_MOD(val, chan, shift, shift);
932 val = FLD_MOD(val, chan2, 31, 30);
933 } else {
934 val = FLD_MOD(val, channel, shift, shift);
935 }
9b372c2d 936 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 937}
938
2cc5d1af
TV		 939static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
940{
941 int shift;
942 u32 val;
943 enum omap_channel channel;
944
945 switch (plane) {
946 case OMAP_DSS_GFX:
947 shift = 8;
948 break;
949 case OMAP_DSS_VIDEO1:
950 case OMAP_DSS_VIDEO2:
951 case OMAP_DSS_VIDEO3:
952 shift = 16;
953 break;
954 default:
955 BUG();
956 }
957
958 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
959
960 if (dss_has_feature(FEAT_MGR_LCD2)) {
961 if (FLD_GET(val, 31, 30) == 0)
962 channel = FLD_GET(val, shift, shift);
963 else
964 channel = OMAP_DSS_CHANNEL_LCD2;
965 } else {
966 channel = FLD_GET(val, shift, shift);
967 }
968
969 return channel;
970}
971
f0e5caab 972static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 973 enum omap_burst_size burst_size)
974{
b8c095b4 975 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 976 int shift;
80c39712 977
fe3cc9d6 978 shift = shifts[plane];
5ed8cf5b 979 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 980}
981
5ed8cf5b
TV		 982static void dispc_configure_burst_sizes(void)
983{
984 int i;
985 const int burst_size = BURST_SIZE_X8;
986
987 /* Configure burst size always to maximum size */
988 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 989 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 990}
991
f0e5caab 992u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 993{
994 unsigned unit = dss_feat_get_burst_size_unit();
995 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
996 return unit * 8;
997}
998
d3862610
M		 999void dispc_enable_gamma_table(bool enable)
1000{
1001 /*
1002 * This is partially implemented to support only disabling of
1003 * the gamma table.
1004 */
1005 if (enable) {
1006 DSSWARN("Gamma table enabling for TV not yet supported");
1007 return;
1008 }
1009
1010 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1011}
1012
c64dca40 1013static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 1014{
1015 u16 reg;
1016
1017 if (channel == OMAP_DSS_CHANNEL_LCD)
1018 reg = DISPC_CONFIG;
1019 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1020 reg = DISPC_CONFIG2;
1021 else
1022 return;
1023
1024 REG_FLD_MOD(reg, enable, 15, 15);
1025}
1026
c64dca40 1027static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 1028 struct omap_dss_cpr_coefs *coefs)
1029{
1030 u32 coef_r, coef_g, coef_b;
1031
dac57a05 1032 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 1033 return;
1034
1035 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1036 FLD_VAL(coefs->rb, 9, 0);
1037 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1038 FLD_VAL(coefs->gb, 9, 0);
1039 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1040 FLD_VAL(coefs->bb, 9, 0);
1041
1042 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1043 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1044 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1045}
1046
f0e5caab 1047static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1048{
1049 u32 val;
1050
1051 BUG_ON(plane == OMAP_DSS_GFX);
1052
9b372c2d 1053 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1054 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1055 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1056}
1057
c3d92529 1058static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 1059{
b8c095b4 1060 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1061 int shift;
80c39712 1062
fe3cc9d6
TV		 1063 shift = shifts[plane];
1064 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1065}
1066
26d9dd0d 1067void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1068{
1069 u32 val;
1070 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1071 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1072 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1073}
1074
1075void dispc_set_digit_size(u16 width, u16 height)
1076{
1077 u32 val;
1078 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1079 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1080 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1081}
1082
1083static void dispc_read_plane_fifo_sizes(void)
1084{
80c39712
TV		 1085 u32 size;
1086 int plane;
a0acb557 1087 u8 start, end;
5ed8cf5b
TV		 1088 u32 unit;
1089
1090 unit = dss_feat_get_buffer_size_unit();
80c39712 1091
a0acb557 1092 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1093
e13a138b 1094 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1095 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1096 size *= unit;
80c39712
TV		 1097 dispc.fifo_size[plane] = size;
1098 }
80c39712
TV		 1099}
1100
f0e5caab 1101u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1102{
1103 return dispc.fifo_size[plane];
1104}
1105
6f04e1bf 1106void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1107{
a0acb557 1108 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1109 u32 unit;
1110
1111 unit = dss_feat_get_buffer_size_unit();
1112
1113 WARN_ON(low % unit != 0);
1114 WARN_ON(high % unit != 0);
1115
1116 low /= unit;
1117 high /= unit;
a0acb557 1118
9b372c2d
AT		 1119 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1120 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1121
80c39712
TV		 1122 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1123 plane,
9b372c2d
AT		 1124 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1125 lo_start, lo_end),
1126 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1127 hi_start, hi_end),
80c39712
TV		 1128 low, high);
1129
9b372c2d 1130 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1131 FLD_VAL(high, hi_start, hi_end) |
1132 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1133}
1134
1135void dispc_enable_fifomerge(bool enable)
1136{
80c39712
TV		 1137 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1138 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1139}
1140
f0e5caab 1141static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1142 int hinc, int vinc,
1143 enum omap_color_component color_comp)
80c39712
TV		 1144{
1145 u32 val;
80c39712 1146
0d66cbb5
AJ		 1147 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1148 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1149
0d66cbb5
AJ		 1150 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1151 &hinc_start, &hinc_end);
1152 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1153 &vinc_start, &vinc_end);
1154 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1155 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1156
0d66cbb5
AJ		 1157 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1158 } else {
1159 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1160 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1161 }
80c39712
TV		 1162}
1163
f0e5caab 1164static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1165{
1166 u32 val;
87a7484b 1167 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1168
87a7484b
AT		 1169 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1170 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1171
1172 val = FLD_VAL(vaccu, vert_start, vert_end) |
1173 FLD_VAL(haccu, hor_start, hor_end);
1174
9b372c2d 1175 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1176}
1177
f0e5caab 1178static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1179{
1180 u32 val;
87a7484b 1181 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1182
87a7484b
AT		 1183 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1184 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1185
1186 val = FLD_VAL(vaccu, vert_start, vert_end) |
1187 FLD_VAL(haccu, hor_start, hor_end);
1188
9b372c2d 1189 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1190}
1191
f0e5caab
TV		 1192static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1193 int vaccu)
ab5ca071
AJ		 1194{
1195 u32 val;
1196
1197 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1198 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1199}
1200
f0e5caab
TV		 1201static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1202 int vaccu)
ab5ca071
AJ		 1203{
1204 u32 val;
1205
1206 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1207 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1208}
80c39712 1209
f0e5caab 1210static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1211 u16 orig_width, u16 orig_height,
1212 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1213 bool five_taps, u8 rotation,
1214 enum omap_color_component color_comp)
80c39712 1215{
0d66cbb5 1216 int fir_hinc, fir_vinc;
80c39712 1217 int hscaleup, vscaleup;
80c39712
TV		 1218
1219 hscaleup = orig_width <= out_width;
1220 vscaleup = orig_height <= out_height;
1221
f0e5caab
TV		 1222 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1223 color_comp);
80c39712 1224
ed14a3ce
AJ		 1225 fir_hinc = 1024 * orig_width / out_width;
1226 fir_vinc = 1024 * orig_height / out_height;
80c39712 1227
f0e5caab 1228 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1229}
1230
f0e5caab 1231static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1232 u16 orig_width, u16 orig_height,
1233 u16 out_width, u16 out_height,
1234 bool ilace, bool five_taps,
1235 bool fieldmode, enum omap_color_mode color_mode,
1236 u8 rotation)
1237{
1238 int accu0 = 0;
1239 int accu1 = 0;
1240 u32 l;
80c39712 1241
f0e5caab 1242 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1243 out_width, out_height, five_taps,
1244 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1245 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1246
87a7484b
AT		 1247 /* RESIZEENABLE and VERTICALTAPS */
1248 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1249 l |= (orig_width != out_width) ? (1 << 5) : 0;
1250 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1251 l |= five_taps ? (1 << 21) : 0;
80c39712 1252
87a7484b
AT		 1253 /* VRESIZECONF and HRESIZECONF */
1254 if (dss_has_feature(FEAT_RESIZECONF)) {
1255 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1256 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1257 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1258 }
80c39712 1259
87a7484b
AT		 1260 /* LINEBUFFERSPLIT */
1261 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1262 l &= ~(0x1 << 22);
1263 l |= five_taps ? (1 << 22) : 0;
1264 }
80c39712 1265
9b372c2d 1266 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1267
1268 /*
1269 * field 0 = even field = bottom field
1270 * field 1 = odd field = top field
1271 */
1272 if (ilace && !fieldmode) {
1273 accu1 = 0;
0d66cbb5 1274 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1275 if (accu0 >= 1024/2) {
1276 accu1 = 1024/2;
1277 accu0 -= accu1;
1278 }
1279 }
1280
f0e5caab
TV		 1281 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1282 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1283}
1284
f0e5caab 1285static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1286 u16 orig_width, u16 orig_height,
1287 u16 out_width, u16 out_height,
1288 bool ilace, bool five_taps,
1289 bool fieldmode, enum omap_color_mode color_mode,
1290 u8 rotation)
1291{
1292 int scale_x = out_width != orig_width;
1293 int scale_y = out_height != orig_height;
1294
1295 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1296 return;
1297 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1298 color_mode != OMAP_DSS_COLOR_UYVY &&
1299 color_mode != OMAP_DSS_COLOR_NV12)) {
1300 /* reset chroma resampling for RGB formats */
1301 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1302 return;
1303 }
1304 switch (color_mode) {
1305 case OMAP_DSS_COLOR_NV12:
1306 /* UV is subsampled by 2 vertically*/
1307 orig_height >>= 1;
1308 /* UV is subsampled by 2 horz.*/
1309 orig_width >>= 1;
1310 break;
1311 case OMAP_DSS_COLOR_YUV2:
1312 case OMAP_DSS_COLOR_UYVY:
1313 /*For YUV422 with 90/270 rotation,
1314 *we don't upsample chroma
1315 */
1316 if (rotation == OMAP_DSS_ROT_0 ||
1317 rotation == OMAP_DSS_ROT_180)
1318 /* UV is subsampled by 2 hrz*/
1319 orig_width >>= 1;
1320 /* must use FIR for YUV422 if rotated */
1321 if (rotation != OMAP_DSS_ROT_0)
1322 scale_x = scale_y = true;
1323 break;
1324 default:
1325 BUG();
1326 }
1327
1328 if (out_width != orig_width)
1329 scale_x = true;
1330 if (out_height != orig_height)
1331 scale_y = true;
1332
f0e5caab 1333 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1334 out_width, out_height, five_taps,
1335 rotation, DISPC_COLOR_COMPONENT_UV);
1336
1337 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1338 (scale_x || scale_y) ? 1 : 0, 8, 8);
1339 /* set H scaling */
1340 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1341 /* set V scaling */
1342 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1343
f0e5caab
TV		 1344 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1345 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
0d66cbb5
AJ		 1346}
1347
f0e5caab 1348static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1349 u16 orig_width, u16 orig_height,
1350 u16 out_width, u16 out_height,
1351 bool ilace, bool five_taps,
1352 bool fieldmode, enum omap_color_mode color_mode,
1353 u8 rotation)
1354{
1355 BUG_ON(plane == OMAP_DSS_GFX);
1356
f0e5caab 1357 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1358 orig_width, orig_height,
1359 out_width, out_height,
1360 ilace, five_taps,
1361 fieldmode, color_mode,
1362 rotation);
1363
f0e5caab 1364 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1365 orig_width, orig_height,
1366 out_width, out_height,
1367 ilace, five_taps,
1368 fieldmode, color_mode,
1369 rotation);
1370}
1371
f0e5caab 1372static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1373 bool mirroring, enum omap_color_mode color_mode)
1374{
87a7484b
AT		 1375 bool row_repeat = false;
1376 int vidrot = 0;
1377
80c39712
TV		 1378 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1379 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1380
1381 if (mirroring) {
1382 switch (rotation) {
1383 case OMAP_DSS_ROT_0:
1384 vidrot = 2;
1385 break;
1386 case OMAP_DSS_ROT_90:
1387 vidrot = 1;
1388 break;
1389 case OMAP_DSS_ROT_180:
1390 vidrot = 0;
1391 break;
1392 case OMAP_DSS_ROT_270:
1393 vidrot = 3;
1394 break;
1395 }
1396 } else {
1397 switch (rotation) {
1398 case OMAP_DSS_ROT_0:
1399 vidrot = 0;
1400 break;
1401 case OMAP_DSS_ROT_90:
1402 vidrot = 1;
1403 break;
1404 case OMAP_DSS_ROT_180:
1405 vidrot = 2;
1406 break;
1407 case OMAP_DSS_ROT_270:
1408 vidrot = 3;
1409 break;
1410 }
1411 }
1412
80c39712 1413 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1414 row_repeat = true;
80c39712 1415 else
87a7484b 1416 row_repeat = false;
80c39712 1417 }
87a7484b 1418
9b372c2d 1419 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1420 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1421 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1422 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1423}
1424
1425static int color_mode_to_bpp(enum omap_color_mode color_mode)
1426{
1427 switch (color_mode) {
1428 case OMAP_DSS_COLOR_CLUT1:
1429 return 1;
1430 case OMAP_DSS_COLOR_CLUT2:
1431 return 2;
1432 case OMAP_DSS_COLOR_CLUT4:
1433 return 4;
1434 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1435 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1436 return 8;
1437 case OMAP_DSS_COLOR_RGB12U:
1438 case OMAP_DSS_COLOR_RGB16:
1439 case OMAP_DSS_COLOR_ARGB16:
1440 case OMAP_DSS_COLOR_YUV2:
1441 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1442 case OMAP_DSS_COLOR_RGBA16:
1443 case OMAP_DSS_COLOR_RGBX16:
1444 case OMAP_DSS_COLOR_ARGB16_1555:
1445 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1446 return 16;
1447 case OMAP_DSS_COLOR_RGB24P:
1448 return 24;
1449 case OMAP_DSS_COLOR_RGB24U:
1450 case OMAP_DSS_COLOR_ARGB32:
1451 case OMAP_DSS_COLOR_RGBA32:
1452 case OMAP_DSS_COLOR_RGBX32:
1453 return 32;
1454 default:
1455 BUG();
1456 }
1457}
1458
1459static s32 pixinc(int pixels, u8 ps)
1460{
1461 if (pixels == 1)
1462 return 1;
1463 else if (pixels > 1)
1464 return 1 + (pixels - 1) * ps;
1465 else if (pixels < 0)
1466 return 1 - (-pixels + 1) * ps;
1467 else
1468 BUG();
1469}
1470
1471static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1472 u16 screen_width,
1473 u16 width, u16 height,
1474 enum omap_color_mode color_mode, bool fieldmode,
1475 unsigned int field_offset,
1476 unsigned *offset0, unsigned *offset1,
1477 s32 *row_inc, s32 *pix_inc)
1478{
1479 u8 ps;
1480
1481 /* FIXME CLUT formats */
1482 switch (color_mode) {
1483 case OMAP_DSS_COLOR_CLUT1:
1484 case OMAP_DSS_COLOR_CLUT2:
1485 case OMAP_DSS_COLOR_CLUT4:
1486 case OMAP_DSS_COLOR_CLUT8:
1487 BUG();
1488 return;
1489 case OMAP_DSS_COLOR_YUV2:
1490 case OMAP_DSS_COLOR_UYVY:
1491 ps = 4;
1492 break;
1493 default:
1494 ps = color_mode_to_bpp(color_mode) / 8;
1495 break;
1496 }
1497
1498 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1499 width, height);
1500
1501 /*
1502 * field 0 = even field = bottom field
1503 * field 1 = odd field = top field
1504 */
1505 switch (rotation + mirror * 4) {
1506 case OMAP_DSS_ROT_0:
1507 case OMAP_DSS_ROT_180:
1508 /*
1509 * If the pixel format is YUV or UYVY divide the width
1510 * of the image by 2 for 0 and 180 degree rotation.
1511 */
1512 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1513 color_mode == OMAP_DSS_COLOR_UYVY)
1514 width = width >> 1;
1515 case OMAP_DSS_ROT_90:
1516 case OMAP_DSS_ROT_270:
1517 *offset1 = 0;
1518 if (field_offset)
1519 *offset0 = field_offset * screen_width * ps;
1520 else
1521 *offset0 = 0;
1522
1523 *row_inc = pixinc(1 + (screen_width - width) +
1524 (fieldmode ? screen_width : 0),
1525 ps);
1526 *pix_inc = pixinc(1, ps);
1527 break;
1528
1529 case OMAP_DSS_ROT_0 + 4:
1530 case OMAP_DSS_ROT_180 + 4:
1531 /* If the pixel format is YUV or UYVY divide the width
1532 * of the image by 2 for 0 degree and 180 degree
1533 */
1534 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1535 color_mode == OMAP_DSS_COLOR_UYVY)
1536 width = width >> 1;
1537 case OMAP_DSS_ROT_90 + 4:
1538 case OMAP_DSS_ROT_270 + 4:
1539 *offset1 = 0;
1540 if (field_offset)
1541 *offset0 = field_offset * screen_width * ps;
1542 else
1543 *offset0 = 0;
1544 *row_inc = pixinc(1 - (screen_width + width) -
1545 (fieldmode ? screen_width : 0),
1546 ps);
1547 *pix_inc = pixinc(1, ps);
1548 break;
1549
1550 default:
1551 BUG();
1552 }
1553}
1554
1555static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1556 u16 screen_width,
1557 u16 width, u16 height,
1558 enum omap_color_mode color_mode, bool fieldmode,
1559 unsigned int field_offset,
1560 unsigned *offset0, unsigned *offset1,
1561 s32 *row_inc, s32 *pix_inc)
1562{
1563 u8 ps;
1564 u16 fbw, fbh;
1565
1566 /* FIXME CLUT formats */
1567 switch (color_mode) {
1568 case OMAP_DSS_COLOR_CLUT1:
1569 case OMAP_DSS_COLOR_CLUT2:
1570 case OMAP_DSS_COLOR_CLUT4:
1571 case OMAP_DSS_COLOR_CLUT8:
1572 BUG();
1573 return;
1574 default:
1575 ps = color_mode_to_bpp(color_mode) / 8;
1576 break;
1577 }
1578
1579 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1580 width, height);
1581
1582 /* width & height are overlay sizes, convert to fb sizes */
1583
1584 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1585 fbw = width;
1586 fbh = height;
1587 } else {
1588 fbw = height;
1589 fbh = width;
1590 }
1591
1592 /*
1593 * field 0 = even field = bottom field
1594 * field 1 = odd field = top field
1595 */
1596 switch (rotation + mirror * 4) {
1597 case OMAP_DSS_ROT_0:
1598 *offset1 = 0;
1599 if (field_offset)
1600 *offset0 = *offset1 + field_offset * screen_width * ps;
1601 else
1602 *offset0 = *offset1;
1603 *row_inc = pixinc(1 + (screen_width - fbw) +
1604 (fieldmode ? screen_width : 0),
1605 ps);
1606 *pix_inc = pixinc(1, ps);
1607 break;
1608 case OMAP_DSS_ROT_90:
1609 *offset1 = screen_width * (fbh - 1) * ps;
1610 if (field_offset)
1611 *offset0 = *offset1 + field_offset * ps;
1612 else
1613 *offset0 = *offset1;
1614 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1615 (fieldmode ? 1 : 0), ps);
1616 *pix_inc = pixinc(-screen_width, ps);
1617 break;
1618 case OMAP_DSS_ROT_180:
1619 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1620 if (field_offset)
1621 *offset0 = *offset1 - field_offset * screen_width * ps;
1622 else
1623 *offset0 = *offset1;
1624 *row_inc = pixinc(-1 -
1625 (screen_width - fbw) -
1626 (fieldmode ? screen_width : 0),
1627 ps);
1628 *pix_inc = pixinc(-1, ps);
1629 break;
1630 case OMAP_DSS_ROT_270:
1631 *offset1 = (fbw - 1) * ps;
1632 if (field_offset)
1633 *offset0 = *offset1 - field_offset * ps;
1634 else
1635 *offset0 = *offset1;
1636 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1637 (fieldmode ? 1 : 0), ps);
1638 *pix_inc = pixinc(screen_width, ps);
1639 break;
1640
1641 /* mirroring */
1642 case OMAP_DSS_ROT_0 + 4:
1643 *offset1 = (fbw - 1) * ps;
1644 if (field_offset)
1645 *offset0 = *offset1 + field_offset * screen_width * ps;
1646 else
1647 *offset0 = *offset1;
1648 *row_inc = pixinc(screen_width * 2 - 1 +
1649 (fieldmode ? screen_width : 0),
1650 ps);
1651 *pix_inc = pixinc(-1, ps);
1652 break;
1653
1654 case OMAP_DSS_ROT_90 + 4:
1655 *offset1 = 0;
1656 if (field_offset)
1657 *offset0 = *offset1 + field_offset * ps;
1658 else
1659 *offset0 = *offset1;
1660 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1661 (fieldmode ? 1 : 0),
1662 ps);
1663 *pix_inc = pixinc(screen_width, ps);
1664 break;
1665
1666 case OMAP_DSS_ROT_180 + 4:
1667 *offset1 = screen_width * (fbh - 1) * ps;
1668 if (field_offset)
1669 *offset0 = *offset1 - field_offset * screen_width * ps;
1670 else
1671 *offset0 = *offset1;
1672 *row_inc = pixinc(1 - screen_width * 2 -
1673 (fieldmode ? screen_width : 0),
1674 ps);
1675 *pix_inc = pixinc(1, ps);
1676 break;
1677
1678 case OMAP_DSS_ROT_270 + 4:
1679 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1680 if (field_offset)
1681 *offset0 = *offset1 - field_offset * ps;
1682 else
1683 *offset0 = *offset1;
1684 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1685 (fieldmode ? 1 : 0),
1686 ps);
1687 *pix_inc = pixinc(-screen_width, ps);
1688 break;
1689
1690 default:
1691 BUG();
1692 }
1693}
1694
ff1b2cde
SS		 1695static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1696 u16 height, u16 out_width, u16 out_height,
1697 enum omap_color_mode color_mode)
80c39712
TV		 1698{
1699 u32 fclk = 0;
26d9dd0d 1700 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1701
1702 if (height > out_height) {
ebdc5249
AT		 1703 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1704 unsigned int ppl = dssdev->panel.timings.x_res;
80c39712
TV		 1705
1706 tmp = pclk * height * out_width;
1707 do_div(tmp, 2 * out_height * ppl);
1708 fclk = tmp;
1709
2d9c5597
VS		 1710 if (height > 2 * out_height) {
1711 if (ppl == out_width)
1712 return 0;
1713
80c39712
TV		 1714 tmp = pclk * (height - 2 * out_height) * out_width;
1715 do_div(tmp, 2 * out_height * (ppl - out_width));
1716 fclk = max(fclk, (u32) tmp);
1717 }
1718 }
1719
1720 if (width > out_width) {
1721 tmp = pclk * width;
1722 do_div(tmp, out_width);
1723 fclk = max(fclk, (u32) tmp);
1724
1725 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1726 fclk <<= 1;
1727 }
1728
1729 return fclk;
1730}
1731
ff1b2cde
SS		 1732static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1733 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1734{
1735 unsigned int hf, vf;
1736
1737 /*
1738 * FIXME how to determine the 'A' factor
1739 * for the no downscaling case ?
1740 */
1741
1742 if (width > 3 * out_width)
1743 hf = 4;
1744 else if (width > 2 * out_width)
1745 hf = 3;
1746 else if (width > out_width)
1747 hf = 2;
1748 else
1749 hf = 1;
1750
1751 if (height > out_height)
1752 vf = 2;
1753 else
1754 vf = 1;
1755
26d9dd0d 1756 return dispc_mgr_pclk_rate(channel) * vf * hf;
80c39712
TV		 1757}
1758
79ad75f2
AT		 1759static int dispc_ovl_calc_scaling(enum omap_plane plane,
1760 enum omap_channel channel, u16 width, u16 height,
1761 u16 out_width, u16 out_height,
1762 enum omap_color_mode color_mode, bool *five_taps)
1763{
1764 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1765 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
79ad75f2
AT		 1766 unsigned long fclk = 0;
1767
f95cb5eb
TV		 1768 if (width == out_width && height == out_height)
1769 return 0;
1770
1771 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1772 return -EINVAL;
79ad75f2
AT		 1773
1774 if (out_width < width / maxdownscale ||
1775 out_width > width * 8)
1776 return -EINVAL;
1777
1778 if (out_height < height / maxdownscale ||
1779 out_height > height * 8)
1780 return -EINVAL;
1781
1782 /* Must use 5-tap filter? */
1783 *five_taps = height > out_height * 2;
1784
1785 if (!*five_taps) {
1786 fclk = calc_fclk(channel, width, height, out_width,
1787 out_height);
1788
1789 /* Try 5-tap filter if 3-tap fclk is too high */
1790 if (cpu_is_omap34xx() && height > out_height &&
1791 fclk > dispc_fclk_rate())
1792 *five_taps = true;
1793 }
1794
1795 if (width > (2048 >> *five_taps)) {
1796 DSSERR("failed to set up scaling, fclk too low\n");
1797 return -EINVAL;
1798 }
1799
1800 if (*five_taps)
1801 fclk = calc_fclk_five_taps(channel, width, height,
1802 out_width, out_height, color_mode);
1803
1804 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1805 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1806
1807 if (!fclk || fclk > dispc_fclk_rate()) {
1808 DSSERR("failed to set up scaling, "
1809 "required fclk rate = %lu Hz, "
1810 "current fclk rate = %lu Hz\n",
1811 fclk, dispc_fclk_rate());
1812 return -EINVAL;
1813 }
1814
1815 return 0;
1816}
1817
a4273b7c 1818int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
2cc5d1af 1819 bool ilace, bool replication)
80c39712 1820{
79ad75f2
AT		 1821 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1822 bool five_taps = false;
80c39712 1823 bool fieldmode = 0;
79ad75f2 1824 int r, cconv = 0;
80c39712
TV		 1825 unsigned offset0, offset1;
1826 s32 row_inc;
1827 s32 pix_inc;
a4273b7c 1828 u16 frame_height = oi->height;
80c39712 1829 unsigned int field_offset = 0;
cf073668 1830 u16 outw, outh;
2cc5d1af
TV		 1831 enum omap_channel channel;
1832
1833 channel = dispc_ovl_get_channel_out(plane);
80c39712 1834
a4273b7c 1835 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 1836 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
1837 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 1838 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1839 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 1840 oi->mirror, ilace, channel, replication);
e6d80f95 1841
a4273b7c 1842 if (oi->paddr == 0)
80c39712
TV		 1843 return -EINVAL;
1844
cf073668
TV		 1845 outw = oi->out_width == 0 ? oi->width : oi->out_width;
1846 outh = oi->out_height == 0 ? oi->height : oi->out_height;
1847
1848 if (ilace && oi->height == outh)
80c39712
TV		 1849 fieldmode = 1;
1850
1851 if (ilace) {
1852 if (fieldmode)
a4273b7c
AT		 1853 oi->height /= 2;
1854 oi->pos_y /= 2;
cf073668 1855 outh /= 2;
80c39712
TV		 1856
1857 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1858 "out_height %d\n",
cf073668 1859 oi->height, oi->pos_y, outh);
80c39712
TV		 1860 }
1861
a4273b7c 1862 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 1863 return -EINVAL;
1864
79ad75f2 1865 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
cf073668 1866 outw, outh, oi->color_mode,
79ad75f2
AT		 1867 &five_taps);
1868 if (r)
1869 return r;
80c39712 1870
79ad75f2
AT		 1871 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1872 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1873 oi->color_mode == OMAP_DSS_COLOR_NV12)
1874 cconv = 1;
80c39712
TV		 1875
1876 if (ilace && !fieldmode) {
1877 /*
1878 * when downscaling the bottom field may have to start several
1879 * source lines below the top field. Unfortunately ACCUI
1880 * registers will only hold the fractional part of the offset
1881 * so the integer part must be added to the base address of the
1882 * bottom field.
1883 */
cf073668 1884 if (!oi->height || oi->height == outh)
80c39712
TV		 1885 field_offset = 0;
1886 else
cf073668 1887 field_offset = oi->height / outh / 2;
80c39712
TV		 1888 }
1889
1890 /* Fields are independent but interleaved in memory. */
1891 if (fieldmode)
1892 field_offset = 1;
1893
a4273b7c
AT		 1894 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1895 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1896 oi->screen_width, oi->width, frame_height,
1897 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1898 &offset0, &offset1, &row_inc, &pix_inc);
1899 else
a4273b7c
AT		 1900 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1901 oi->screen_width, oi->width, frame_height,
1902 oi->color_mode, fieldmode, field_offset,
80c39712
TV		 1903 &offset0, &offset1, &row_inc, &pix_inc);
1904
1905 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1906 offset0, offset1, row_inc, pix_inc);
1907
a4273b7c 1908 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 1909
a4273b7c
AT		 1910 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1911 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 1912
a4273b7c
AT		 1913 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1914 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1915 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 1916 }
1917
1918
f0e5caab
TV		 1919 dispc_ovl_set_row_inc(plane, row_inc);
1920 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 1921
a4273b7c 1922 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
cf073668 1923 oi->height, outw, outh);
80c39712 1924
a4273b7c 1925 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 1926
a4273b7c 1927 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
80c39712 1928
79ad75f2 1929 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
a4273b7c 1930 dispc_ovl_set_scaling(plane, oi->width, oi->height,
cf073668 1931 outw, outh,
0d66cbb5 1932 ilace, five_taps, fieldmode,
a4273b7c 1933 oi->color_mode, oi->rotation);
cf073668 1934 dispc_ovl_set_vid_size(plane, outw, outh);
f0e5caab 1935 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 1936 }
1937
a4273b7c
AT		 1938 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1939 oi->color_mode);
80c39712 1940
54128701 1941 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 1942 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1943 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 1944
c3d92529 1945 dispc_ovl_enable_replication(plane, replication);
c3d92529 1946
80c39712
TV		 1947 return 0;
1948}
1949
f0e5caab 1950int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 1951{
e6d80f95
TV		 1952 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1953
9b372c2d 1954 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 1955
1956 return 0;
80c39712
TV		 1957}
1958
1959static void dispc_disable_isr(void *data, u32 mask)
1960{
1961 struct completion *compl = data;
1962 complete(compl);
1963}
1964
2a205f34 1965static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1966{
b6a44e77 1967 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 1968 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 1969 /* flush posted write */
1970 dispc_read_reg(DISPC_CONTROL2);
1971 } else {
2a205f34 1972 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 1973 dispc_read_reg(DISPC_CONTROL);
1974 }
80c39712
TV		 1975}
1976
26d9dd0d 1977static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1978{
1979 struct completion frame_done_completion;
1980 bool is_on;
1981 int r;
2a205f34 1982 u32 irq;
80c39712 1983
80c39712
TV		 1984 /* When we disable LCD output, we need to wait until frame is done.
1985 * Otherwise the DSS is still working, and turning off the clocks
1986 * prevents DSS from going to OFF mode */
2a205f34
SS		 1987 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1988 REG_GET(DISPC_CONTROL2, 0, 0) :
1989 REG_GET(DISPC_CONTROL, 0, 0);
1990
1991 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1992 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1993
1994 if (!enable && is_on) {
1995 init_completion(&frame_done_completion);
1996
1997 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1998 &frame_done_completion, irq);
80c39712
TV		 1999
2000 if (r)
2001 DSSERR("failed to register FRAMEDONE isr\n");
2002 }
2003
2a205f34 2004 _enable_lcd_out(channel, enable);
80c39712
TV		 2005
2006 if (!enable && is_on) {
2007 if (!wait_for_completion_timeout(&frame_done_completion,
2008 msecs_to_jiffies(100)))
2009 DSSERR("timeout waiting for FRAME DONE\n");
2010
2011 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2012 &frame_done_completion, irq);
80c39712
TV		 2013
2014 if (r)
2015 DSSERR("failed to unregister FRAMEDONE isr\n");
2016 }
80c39712
TV		 2017}
2018
2019static void _enable_digit_out(bool enable)
2020{
2021 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2022 /* flush posted write */
2023 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2024}
2025
26d9dd0d 2026static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2027{
2028 struct completion frame_done_completion;
e82b090b
TV		 2029 enum dss_hdmi_venc_clk_source_select src;
2030 int r, i;
2031 u32 irq_mask;
2032 int num_irqs;
80c39712 2033
e6d80f95 2034 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2035 return;
80c39712 2036
e82b090b
TV		 2037 src = dss_get_hdmi_venc_clk_source();
2038
80c39712
TV		 2039 if (enable) {
2040 unsigned long flags;
2041 /* When we enable digit output, we'll get an extra digit
2042 * sync lost interrupt, that we need to ignore */
2043 spin_lock_irqsave(&dispc.irq_lock, flags);
2044 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2045 _omap_dispc_set_irqs();
2046 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2047 }
2048
2049 /* When we disable digit output, we need to wait until fields are done.
2050 * Otherwise the DSS is still working, and turning off the clocks
2051 * prevents DSS from going to OFF mode. And when enabling, we need to
2052 * wait for the extra sync losts */
2053 init_completion(&frame_done_completion);
2054
e82b090b
TV		 2055 if (src == DSS_HDMI_M_PCLK && enable == false) {
2056 irq_mask = DISPC_IRQ_FRAMEDONETV;
2057 num_irqs = 1;
2058 } else {
2059 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2060 /* XXX I understand from TRM that we should only wait for the
2061 * current field to complete. But it seems we have to wait for
2062 * both fields */
2063 num_irqs = 2;
2064 }
2065
80c39712 2066 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2067 irq_mask);
80c39712 2068 if (r)
e82b090b 2069 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2070
2071 _enable_digit_out(enable);
2072
e82b090b
TV		 2073 for (i = 0; i < num_irqs; ++i) {
2074 if (!wait_for_completion_timeout(&frame_done_completion,
2075 msecs_to_jiffies(100)))
2076 DSSERR("timeout waiting for digit out to %s\n",
2077 enable ? "start" : "stop");
2078 }
80c39712 2079
e82b090b
TV		 2080 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2081 irq_mask);
80c39712 2082 if (r)
e82b090b 2083 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2084
2085 if (enable) {
2086 unsigned long flags;
2087 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2088 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2089 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2090 _omap_dispc_set_irqs();
2091 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2092 }
80c39712
TV		 2093}
2094
26d9dd0d 2095bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2096{
2097 if (channel == OMAP_DSS_CHANNEL_LCD)
2098 return !!REG_GET(DISPC_CONTROL, 0, 0);
2099 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2100 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2101 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2102 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2103 else
2104 BUG();
2105}
2106
26d9dd0d 2107void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2108{
dac57a05 2109 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2110 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2111 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2112 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2113 else
2114 BUG();
2115}
2116
80c39712
TV		 2117void dispc_lcd_enable_signal_polarity(bool act_high)
2118{
6ced40bf
AT		 2119 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2120 return;
2121
80c39712 2122 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2123}
2124
2125void dispc_lcd_enable_signal(bool enable)
2126{
6ced40bf
AT		 2127 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2128 return;
2129
80c39712 2130 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2131}
2132
2133void dispc_pck_free_enable(bool enable)
2134{
6ced40bf
AT		 2135 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2136 return;
2137
80c39712 2138 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2139}
2140
26d9dd0d 2141void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2142{
2a205f34
SS		 2143 if (channel == OMAP_DSS_CHANNEL_LCD2)
2144 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2145 else
2146 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2147}
2148
2149
26d9dd0d 2150void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2151 enum omap_lcd_display_type type)
80c39712
TV		 2152{
2153 int mode;
2154
2155 switch (type) {
2156 case OMAP_DSS_LCD_DISPLAY_STN:
2157 mode = 0;
2158 break;
2159
2160 case OMAP_DSS_LCD_DISPLAY_TFT:
2161 mode = 1;
2162 break;
2163
2164 default:
2165 BUG();
2166 return;
2167 }
2168
2a205f34
SS		 2169 if (channel == OMAP_DSS_CHANNEL_LCD2)
2170 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2171 else
2172 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2173}
2174
2175void dispc_set_loadmode(enum omap_dss_load_mode mode)
2176{
80c39712 2177 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2178}
2179
2180
c64dca40 2181static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2182{
8613b000 2183 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2184}
2185
c64dca40 2186static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2187 enum omap_dss_trans_key_type type,
2188 u32 trans_key)
2189{
80c39712
TV		 2190 if (ch == OMAP_DSS_CHANNEL_LCD)
2191 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2192 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2193 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2194 else /* OMAP_DSS_CHANNEL_LCD2 */
2195 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2196
8613b000 2197 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2198}
2199
c64dca40 2200static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2201{
80c39712
TV		 2202 if (ch == OMAP_DSS_CHANNEL_LCD)
2203 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2204 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2205 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2206 else /* OMAP_DSS_CHANNEL_LCD2 */
2207 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2208}
11354dd5 2209
c64dca40
TV		 2210static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2211 bool enable)
80c39712 2212{
11354dd5 2213 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2214 return;
2215
80c39712
TV		 2216 if (ch == OMAP_DSS_CHANNEL_LCD)
2217 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2218 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2219 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2220}
11354dd5 2221
c64dca40
TV		 2222void dispc_mgr_setup(enum omap_channel channel,
2223 struct omap_overlay_manager_info *info)
2224{
2225 dispc_mgr_set_default_color(channel, info->default_color);
2226 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2227 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2228 dispc_mgr_enable_alpha_fixed_zorder(channel,
2229 info->partial_alpha_enabled);
2230 if (dss_has_feature(FEAT_CPR)) {
2231 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2232 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2233 }
2234}
80c39712 2235
26d9dd0d 2236void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2237{
2238 int code;
2239
2240 switch (data_lines) {
2241 case 12:
2242 code = 0;
2243 break;
2244 case 16:
2245 code = 1;
2246 break;
2247 case 18:
2248 code = 2;
2249 break;
2250 case 24:
2251 code = 3;
2252 break;
2253 default:
2254 BUG();
2255 return;
2256 }
2257
2a205f34
SS		 2258 if (channel == OMAP_DSS_CHANNEL_LCD2)
2259 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2260 else
2261 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2262}
2263
569969d6 2264void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2265{
2266 u32 l;
569969d6 2267 int gpout0, gpout1;
80c39712
TV		 2268
2269 switch (mode) {
569969d6
AT		 2270 case DSS_IO_PAD_MODE_RESET:
2271 gpout0 = 0;
2272 gpout1 = 0;
80c39712 2273 break;
569969d6
AT		 2274 case DSS_IO_PAD_MODE_RFBI:
2275 gpout0 = 1;
80c39712
TV		 2276 gpout1 = 0;
2277 break;
569969d6
AT		 2278 case DSS_IO_PAD_MODE_BYPASS:
2279 gpout0 = 1;
80c39712
TV		 2280 gpout1 = 1;
2281 break;
80c39712
TV		 2282 default:
2283 BUG();
2284 return;
2285 }
2286
569969d6
AT		 2287 l = dispc_read_reg(DISPC_CONTROL);
2288 l = FLD_MOD(l, gpout0, 15, 15);
2289 l = FLD_MOD(l, gpout1, 16, 16);
2290 dispc_write_reg(DISPC_CONTROL, l);
2291}
2292
2293void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2294{
2295 if (channel == OMAP_DSS_CHANNEL_LCD2)
2296 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2297 else
2298 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2299}
2300
2301static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2302 int vsw, int vfp, int vbp)
2303{
2304 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2305 if (hsw < 1 || hsw > 64 ||
2306 hfp < 1 || hfp > 256 ||
2307 hbp < 1 || hbp > 256 ||
2308 vsw < 1 || vsw > 64 ||
2309 vfp < 0 || vfp > 255 ||
2310 vbp < 0 || vbp > 255)
2311 return false;
2312 } else {
2313 if (hsw < 1 || hsw > 256 ||
2314 hfp < 1 || hfp > 4096 ||
2315 hbp < 1 || hbp > 4096 ||
2316 vsw < 1 || vsw > 256 ||
2317 vfp < 0 || vfp > 4095 ||
2318 vbp < 0 || vbp > 4095)
2319 return false;
2320 }
2321
2322 return true;
2323}
2324
2325bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2326{
2327 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2328 timings->hbp, timings->vsw,
2329 timings->vfp, timings->vbp);
2330}
2331
26d9dd0d 2332static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2333 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2334{
2335 u32 timing_h, timing_v;
2336
2337 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2338 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2339 FLD_VAL(hbp-1, 27, 20);
2340
2341 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2342 FLD_VAL(vbp, 27, 20);
2343 } else {
2344 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2345 FLD_VAL(hbp-1, 31, 20);
2346
2347 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2348 FLD_VAL(vbp, 31, 20);
2349 }
2350
64ba4f74
SS		 2351 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2352 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2353}
2354
2355/* change name to mode? */
26d9dd0d 2356void dispc_mgr_set_lcd_timings(enum omap_channel channel,
64ba4f74 2357 struct omap_video_timings *timings)
80c39712
TV		 2358{
2359 unsigned xtot, ytot;
2360 unsigned long ht, vt;
2361
2362 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2363 timings->hbp, timings->vsw,
2364 timings->vfp, timings->vbp))
2365 BUG();
2366
26d9dd0d 2367 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
64ba4f74
SS		 2368 timings->hbp, timings->vsw, timings->vfp,
2369 timings->vbp);
80c39712 2370
26d9dd0d 2371 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2372
2373 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2374 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2375
2376 ht = (timings->pixel_clock * 1000) / xtot;
2377 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2378
2a205f34
SS		 2379 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2380 timings->y_res);
80c39712
TV		 2381 DSSDBG("pck %u\n", timings->pixel_clock);
2382 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2383 timings->hsw, timings->hfp, timings->hbp,
2384 timings->vsw, timings->vfp, timings->vbp);
2385
2386 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2387}
2388
26d9dd0d 2389static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2390 u16 pck_div)
80c39712
TV		 2391{
2392 BUG_ON(lck_div < 1);
9eaaf207 2393 BUG_ON(pck_div < 1);
80c39712 2394
ce7fa5eb 2395 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2396 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2397}
2398
26d9dd0d 2399static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2400 int *pck_div)
80c39712
TV		 2401{
2402 u32 l;
ce7fa5eb 2403 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2404 *lck_div = FLD_GET(l, 23, 16);
2405 *pck_div = FLD_GET(l, 7, 0);
2406}
2407
2408unsigned long dispc_fclk_rate(void)
2409{
a72b64b9 2410 struct platform_device *dsidev;
80c39712
TV		 2411 unsigned long r = 0;
2412
66534e8e 2413 switch (dss_get_dispc_clk_source()) {
89a35e51 2414 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2415 r = clk_get_rate(dispc.dss_clk);
66534e8e 2416 break;
89a35e51 2417 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2418 dsidev = dsi_get_dsidev_from_id(0);
2419 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2420 break;
5a8b572d
AT		 2421 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2422 dsidev = dsi_get_dsidev_from_id(1);
2423 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2424 break;
66534e8e
TA		 2425 default:
2426 BUG();
2427 }
2428
80c39712
TV		 2429 return r;
2430}
2431
26d9dd0d 2432unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2433{
a72b64b9 2434 struct platform_device *dsidev;
80c39712
TV		 2435 int lcd;
2436 unsigned long r;
2437 u32 l;
2438
ce7fa5eb 2439 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2440
2441 lcd = FLD_GET(l, 23, 16);
2442
ea75159e 2443 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2444 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2445 r = clk_get_rate(dispc.dss_clk);
ea75159e 2446 break;
89a35e51 2447 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2448 dsidev = dsi_get_dsidev_from_id(0);
2449 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2450 break;
5a8b572d
AT		 2451 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2452 dsidev = dsi_get_dsidev_from_id(1);
2453 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2454 break;
ea75159e
TA		 2455 default:
2456 BUG();
2457 }
80c39712
TV		 2458
2459 return r / lcd;
2460}
2461
26d9dd0d 2462unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2463{
80c39712 2464 unsigned long r;
80c39712 2465
c3dc6a7a
AT		 2466 if (dispc_mgr_is_lcd(channel)) {
2467 int pcd;
2468 u32 l;
80c39712 2469
c3dc6a7a 2470 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2471
c3dc6a7a 2472 pcd = FLD_GET(l, 7, 0);
80c39712 2473
c3dc6a7a
AT		 2474 r = dispc_mgr_lclk_rate(channel);
2475
2476 return r / pcd;
2477 } else {
2478 struct omap_dss_device *dssdev =
2479 dispc_mgr_get_device(channel);
2480
2481 switch (dssdev->type) {
2482 case OMAP_DISPLAY_TYPE_VENC:
2483 return venc_get_pixel_clock();
2484 case OMAP_DISPLAY_TYPE_HDMI:
2485 return hdmi_get_pixel_clock();
2486 default:
2487 BUG();
2488 }
2489 }
80c39712
TV		 2490}
2491
2492void dispc_dump_clocks(struct seq_file *s)
2493{
2494 int lcd, pcd;
0cf35df3 2495 u32 l;
89a35e51
AT		 2496 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2497 enum omap_dss_clk_source lcd_clk_src;
80c39712 2498
4fbafaf3
TV		 2499 if (dispc_runtime_get())
2500 return;
80c39712 2501
80c39712
TV		 2502 seq_printf(s, "- DISPC -\n");
2503
067a57e4
AT		 2504 seq_printf(s, "dispc fclk source = %s (%s)\n",
2505 dss_get_generic_clk_source_name(dispc_clk_src),
2506 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2507
2508 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2509
0cf35df3
MR		 2510 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2511 seq_printf(s, "- DISPC-CORE-CLK -\n");
2512 l = dispc_read_reg(DISPC_DIVISOR);
2513 lcd = FLD_GET(l, 23, 16);
2514
2515 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2516 (dispc_fclk_rate()/lcd), lcd);
2517 }
2a205f34
SS		 2518 seq_printf(s, "- LCD1 -\n");
2519
ea75159e
TA		 2520 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2521
2522 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2523 dss_get_generic_clk_source_name(lcd_clk_src),
2524 dss_feat_get_clk_source_name(lcd_clk_src));
2525
26d9dd0d 2526 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2527
ff1b2cde 2528 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2529 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2530 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2531 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2532 if (dss_has_feature(FEAT_MGR_LCD2)) {
2533 seq_printf(s, "- LCD2 -\n");
2534
ea75159e
TA		 2535 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2536
2537 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2538 dss_get_generic_clk_source_name(lcd_clk_src),
2539 dss_feat_get_clk_source_name(lcd_clk_src));
2540
26d9dd0d 2541 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2542
2a205f34 2543 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2544 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2545 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2546 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2547 }
4fbafaf3
TV		 2548
2549 dispc_runtime_put();
80c39712
TV		 2550}
2551
dfc0fd8d
TV		 2552#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2553void dispc_dump_irqs(struct seq_file *s)
2554{
2555 unsigned long flags;
2556 struct dispc_irq_stats stats;
2557
2558 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2559
2560 stats = dispc.irq_stats;
2561 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2562 dispc.irq_stats.last_reset = jiffies;
2563
2564 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2565
2566 seq_printf(s, "period %u ms\n",
2567 jiffies_to_msecs(jiffies - stats.last_reset));
2568
2569 seq_printf(s, "irqs %d\n", stats.irq_count);
2570#define PIS(x) \
2571 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2572
2573 PIS(FRAMEDONE);
2574 PIS(VSYNC);
2575 PIS(EVSYNC_EVEN);
2576 PIS(EVSYNC_ODD);
2577 PIS(ACBIAS_COUNT_STAT);
2578 PIS(PROG_LINE_NUM);
2579 PIS(GFX_FIFO_UNDERFLOW);
2580 PIS(GFX_END_WIN);
2581 PIS(PAL_GAMMA_MASK);
2582 PIS(OCP_ERR);
2583 PIS(VID1_FIFO_UNDERFLOW);
2584 PIS(VID1_END_WIN);
2585 PIS(VID2_FIFO_UNDERFLOW);
2586 PIS(VID2_END_WIN);
b8c095b4
AT		 2587 if (dss_feat_get_num_ovls() > 3) {
2588 PIS(VID3_FIFO_UNDERFLOW);
2589 PIS(VID3_END_WIN);
2590 }
dfc0fd8d
TV		 2591 PIS(SYNC_LOST);
2592 PIS(SYNC_LOST_DIGIT);
2593 PIS(WAKEUP);
2a205f34
SS		 2594 if (dss_has_feature(FEAT_MGR_LCD2)) {
2595 PIS(FRAMEDONE2);
2596 PIS(VSYNC2);
2597 PIS(ACBIAS_COUNT_STAT2);
2598 PIS(SYNC_LOST2);
2599 }
dfc0fd8d
TV		 2600#undef PIS
2601}
dfc0fd8d
TV		 2602#endif
2603
80c39712
TV		 2604void dispc_dump_regs(struct seq_file *s)
2605{
4dd2da15
AT		 2606 int i, j;
2607 const char *mgr_names[] = {
2608 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2609 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2610 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2611 };
2612 const char *ovl_names[] = {
2613 [OMAP_DSS_GFX] = "GFX",
2614 [OMAP_DSS_VIDEO1] = "VID1",
2615 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2616 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2617 };
2618 const char **p_names;
2619
9b372c2d 2620#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2621
4fbafaf3
TV		 2622 if (dispc_runtime_get())
2623 return;
80c39712 2624
5010be80 2625 /* DISPC common registers */
80c39712
TV		 2626 DUMPREG(DISPC_REVISION);
2627 DUMPREG(DISPC_SYSCONFIG);
2628 DUMPREG(DISPC_SYSSTATUS);
2629 DUMPREG(DISPC_IRQSTATUS);
2630 DUMPREG(DISPC_IRQENABLE);
2631 DUMPREG(DISPC_CONTROL);
2632 DUMPREG(DISPC_CONFIG);
2633 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2634 DUMPREG(DISPC_LINE_STATUS);
2635 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2636 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2637 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2638 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2639 if (dss_has_feature(FEAT_MGR_LCD2)) {
2640 DUMPREG(DISPC_CONTROL2);
2641 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2642 }
2643
2644#undef DUMPREG
2645
2646#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2647#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2648 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2649 dispc_read_reg(DISPC_REG(i, r)))
2650
4dd2da15 2651 p_names = mgr_names;
5010be80 2652
4dd2da15
AT		 2653 /* DISPC channel specific registers */
2654 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2655 DUMPREG(i, DISPC_DEFAULT_COLOR);
2656 DUMPREG(i, DISPC_TRANS_COLOR);
2657 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2658
4dd2da15
AT		 2659 if (i == OMAP_DSS_CHANNEL_DIGIT)
2660 continue;
5010be80 2661
4dd2da15
AT		 2662 DUMPREG(i, DISPC_DEFAULT_COLOR);
2663 DUMPREG(i, DISPC_TRANS_COLOR);
2664 DUMPREG(i, DISPC_TIMING_H);
2665 DUMPREG(i, DISPC_TIMING_V);
2666 DUMPREG(i, DISPC_POL_FREQ);
2667 DUMPREG(i, DISPC_DIVISORo);
2668 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2669
4dd2da15
AT		 2670 DUMPREG(i, DISPC_DATA_CYCLE1);
2671 DUMPREG(i, DISPC_DATA_CYCLE2);
2672 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2673
332e9d70 2674 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2675 DUMPREG(i, DISPC_CPR_COEF_R);
2676 DUMPREG(i, DISPC_CPR_COEF_G);
2677 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2678 }
2a205f34 2679 }
80c39712 2680
4dd2da15
AT		 2681 p_names = ovl_names;
2682
2683 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2684 DUMPREG(i, DISPC_OVL_BA0);
2685 DUMPREG(i, DISPC_OVL_BA1);
2686 DUMPREG(i, DISPC_OVL_POSITION);
2687 DUMPREG(i, DISPC_OVL_SIZE);
2688 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2689 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2690 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2691 DUMPREG(i, DISPC_OVL_ROW_INC);
2692 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2693 if (dss_has_feature(FEAT_PRELOAD))
2694 DUMPREG(i, DISPC_OVL_PRELOAD);
2695
2696 if (i == OMAP_DSS_GFX) {
2697 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2698 DUMPREG(i, DISPC_OVL_TABLE_BA);
2699 continue;
2700 }
2701
2702 DUMPREG(i, DISPC_OVL_FIR);
2703 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2704 DUMPREG(i, DISPC_OVL_ACCU0);
2705 DUMPREG(i, DISPC_OVL_ACCU1);
2706 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2707 DUMPREG(i, DISPC_OVL_BA0_UV);
2708 DUMPREG(i, DISPC_OVL_BA1_UV);
2709 DUMPREG(i, DISPC_OVL_FIR2);
2710 DUMPREG(i, DISPC_OVL_ACCU2_0);
2711 DUMPREG(i, DISPC_OVL_ACCU2_1);
2712 }
2713 if (dss_has_feature(FEAT_ATTR2))
2714 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2715 if (dss_has_feature(FEAT_PRELOAD))
2716 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2717 }
5010be80
AT		 2718
2719#undef DISPC_REG
2720#undef DUMPREG
2721
2722#define DISPC_REG(plane, name, i) name(plane, i)
2723#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2724 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2725 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2726 dispc_read_reg(DISPC_REG(plane, name, i)))
2727
4dd2da15 2728 /* Video pipeline coefficient registers */
332e9d70 2729
4dd2da15
AT		 2730 /* start from OMAP_DSS_VIDEO1 */
2731 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2732 for (j = 0; j < 8; j++)
2733 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2734
4dd2da15
AT		 2735 for (j = 0; j < 8; j++)
2736 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2737
4dd2da15
AT		 2738 for (j = 0; j < 5; j++)
2739 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2740
4dd2da15
AT		 2741 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2742 for (j = 0; j < 8; j++)
2743 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2744 }
2745
2746 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2747 for (j = 0; j < 8; j++)
2748 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2749
2750 for (j = 0; j < 8; j++)
2751 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2752
2753 for (j = 0; j < 8; j++)
2754 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2755 }
332e9d70 2756 }
80c39712 2757
4fbafaf3 2758 dispc_runtime_put();
5010be80
AT		 2759
2760#undef DISPC_REG
80c39712
TV		 2761#undef DUMPREG
2762}
2763
26d9dd0d
TV		 2764static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2765 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2766 u8 acb)
80c39712
TV		 2767{
2768 u32 l = 0;
2769
2770 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2771 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2772
2773 l |= FLD_VAL(onoff, 17, 17);
2774 l |= FLD_VAL(rf, 16, 16);
2775 l |= FLD_VAL(ieo, 15, 15);
2776 l |= FLD_VAL(ipc, 14, 14);
2777 l |= FLD_VAL(ihs, 13, 13);
2778 l |= FLD_VAL(ivs, 12, 12);
2779 l |= FLD_VAL(acbi, 11, 8);
2780 l |= FLD_VAL(acb, 7, 0);
2781
ff1b2cde 2782 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2783}
2784
26d9dd0d 2785void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 2786 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2787{
26d9dd0d 2788 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2789 (config & OMAP_DSS_LCD_RF) != 0,
2790 (config & OMAP_DSS_LCD_IEO) != 0,
2791 (config & OMAP_DSS_LCD_IPC) != 0,
2792 (config & OMAP_DSS_LCD_IHS) != 0,
2793 (config & OMAP_DSS_LCD_IVS) != 0,
2794 acbi, acb);
2795}
2796
2797/* with fck as input clock rate, find dispc dividers that produce req_pck */
2798void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2799 struct dispc_clock_info *cinfo)
2800{
9eaaf207 2801 u16 pcd_min, pcd_max;
80c39712
TV		 2802 unsigned long best_pck;
2803 u16 best_ld, cur_ld;
2804 u16 best_pd, cur_pd;
2805
9eaaf207
TV		 2806 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2807 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2808
2809 if (!is_tft)
2810 pcd_min = 3;
2811
80c39712
TV		 2812 best_pck = 0;
2813 best_ld = 0;
2814 best_pd = 0;
2815
2816 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2817 unsigned long lck = fck / cur_ld;
2818
9eaaf207 2819 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 2820 unsigned long pck = lck / cur_pd;
2821 long old_delta = abs(best_pck - req_pck);
2822 long new_delta = abs(pck - req_pck);
2823
2824 if (best_pck == 0 || new_delta < old_delta) {
2825 best_pck = pck;
2826 best_ld = cur_ld;
2827 best_pd = cur_pd;
2828
2829 if (pck == req_pck)
2830 goto found;
2831 }
2832
2833 if (pck < req_pck)
2834 break;
2835 }
2836
2837 if (lck / pcd_min < req_pck)
2838 break;
2839 }
2840
2841found:
2842 cinfo->lck_div = best_ld;
2843 cinfo->pck_div = best_pd;
2844 cinfo->lck = fck / cinfo->lck_div;
2845 cinfo->pck = cinfo->lck / cinfo->pck_div;
2846}
2847
2848/* calculate clock rates using dividers in cinfo */
2849int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2850 struct dispc_clock_info *cinfo)
2851{
2852 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2853 return -EINVAL;
9eaaf207 2854 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 2855 return -EINVAL;
2856
2857 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2858 cinfo->pck = cinfo->lck / cinfo->pck_div;
2859
2860 return 0;
2861}
2862
26d9dd0d 2863int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 2864 struct dispc_clock_info *cinfo)
80c39712
TV		 2865{
2866 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2867 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2868
26d9dd0d 2869 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2870
2871 return 0;
2872}
2873
26d9dd0d 2874int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 2875 struct dispc_clock_info *cinfo)
80c39712
TV		 2876{
2877 unsigned long fck;
2878
2879 fck = dispc_fclk_rate();
2880
ce7fa5eb
MR		 2881 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2882 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2883
2884 cinfo->lck = fck / cinfo->lck_div;
2885 cinfo->pck = cinfo->lck / cinfo->pck_div;
2886
2887 return 0;
2888}
2889
2890/* dispc.irq_lock has to be locked by the caller */
2891static void _omap_dispc_set_irqs(void)
2892{
2893 u32 mask;
2894 u32 old_mask;
2895 int i;
2896 struct omap_dispc_isr_data *isr_data;
2897
2898 mask = dispc.irq_error_mask;
2899
2900 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2901 isr_data = &dispc.registered_isr[i];
2902
2903 if (isr_data->isr == NULL)
2904 continue;
2905
2906 mask |= isr_data->mask;
2907 }
2908
80c39712
TV		 2909 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2910 /* clear the irqstatus for newly enabled irqs */
2911 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2912
2913 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 2914}
2915
2916int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2917{
2918 int i;
2919 int ret;
2920 unsigned long flags;
2921 struct omap_dispc_isr_data *isr_data;
2922
2923 if (isr == NULL)
2924 return -EINVAL;
2925
2926 spin_lock_irqsave(&dispc.irq_lock, flags);
2927
2928 /* check for duplicate entry */
2929 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2930 isr_data = &dispc.registered_isr[i];
2931 if (isr_data->isr == isr && isr_data->arg == arg &&
2932 isr_data->mask == mask) {
2933 ret = -EINVAL;
2934 goto err;
2935 }
2936 }
2937
2938 isr_data = NULL;
2939 ret = -EBUSY;
2940
2941 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2942 isr_data = &dispc.registered_isr[i];
2943
2944 if (isr_data->isr != NULL)
2945 continue;
2946
2947 isr_data->isr = isr;
2948 isr_data->arg = arg;
2949 isr_data->mask = mask;
2950 ret = 0;
2951
2952 break;
2953 }
2954
b9cb0984
TV		 2955 if (ret)
2956 goto err;
2957
80c39712
TV		 2958 _omap_dispc_set_irqs();
2959
2960 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2961
2962 return 0;
2963err:
2964 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2965
2966 return ret;
2967}
2968EXPORT_SYMBOL(omap_dispc_register_isr);
2969
2970int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2971{
2972 int i;
2973 unsigned long flags;
2974 int ret = -EINVAL;
2975 struct omap_dispc_isr_data *isr_data;
2976
2977 spin_lock_irqsave(&dispc.irq_lock, flags);
2978
2979 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2980 isr_data = &dispc.registered_isr[i];
2981 if (isr_data->isr != isr || isr_data->arg != arg ||
2982 isr_data->mask != mask)
2983 continue;
2984
2985 /* found the correct isr */
2986
2987 isr_data->isr = NULL;
2988 isr_data->arg = NULL;
2989 isr_data->mask = 0;
2990
2991 ret = 0;
2992 break;
2993 }
2994
2995 if (ret == 0)
2996 _omap_dispc_set_irqs();
2997
2998 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2999
3000 return ret;
3001}
3002EXPORT_SYMBOL(omap_dispc_unregister_isr);
3003
3004#ifdef DEBUG
3005static void print_irq_status(u32 status)
3006{
3007 if ((status & dispc.irq_error_mask) == 0)
3008 return;
3009
3010 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3011
3012#define PIS(x) \
3013 if (status & DISPC_IRQ_##x) \
3014 printk(#x " ");
3015 PIS(GFX_FIFO_UNDERFLOW);
3016 PIS(OCP_ERR);
3017 PIS(VID1_FIFO_UNDERFLOW);
3018 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3019 if (dss_feat_get_num_ovls() > 3)
3020 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3021 PIS(SYNC_LOST);
3022 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3023 if (dss_has_feature(FEAT_MGR_LCD2))
3024 PIS(SYNC_LOST2);
80c39712
TV		 3025#undef PIS
3026
3027 printk("\n");
3028}
3029#endif
3030
3031/* Called from dss.c. Note that we don't touch clocks here,
3032 * but we presume they are on because we got an IRQ. However,
3033 * an irq handler may turn the clocks off, so we may not have
3034 * clock later in the function. */
affe360d 3035static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3036{
3037 int i;
affe360d 3038 u32 irqstatus, irqenable;
80c39712
TV		 3039 u32 handledirqs = 0;
3040 u32 unhandled_errors;
3041 struct omap_dispc_isr_data *isr_data;
3042 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3043
3044 spin_lock(&dispc.irq_lock);
3045
3046 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3047 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3048
3049 /* IRQ is not for us */
3050 if (!(irqstatus & irqenable)) {
3051 spin_unlock(&dispc.irq_lock);
3052 return IRQ_NONE;
3053 }
80c39712 3054
dfc0fd8d
TV		 3055#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3056 spin_lock(&dispc.irq_stats_lock);
3057 dispc.irq_stats.irq_count++;
3058 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3059 spin_unlock(&dispc.irq_stats_lock);
3060#endif
3061
80c39712
TV		 3062#ifdef DEBUG
3063 if (dss_debug)
3064 print_irq_status(irqstatus);
3065#endif
3066 /* Ack the interrupt. Do it here before clocks are possibly turned
3067 * off */
3068 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3069 /* flush posted write */
3070 dispc_read_reg(DISPC_IRQSTATUS);
3071
3072 /* make a copy and unlock, so that isrs can unregister
3073 * themselves */
3074 memcpy(registered_isr, dispc.registered_isr,
3075 sizeof(registered_isr));
3076
3077 spin_unlock(&dispc.irq_lock);
3078
3079 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3080 isr_data = &registered_isr[i];
3081
3082 if (!isr_data->isr)
3083 continue;
3084
3085 if (isr_data->mask & irqstatus) {
3086 isr_data->isr(isr_data->arg, irqstatus);
3087 handledirqs |= isr_data->mask;
3088 }
3089 }
3090
3091 spin_lock(&dispc.irq_lock);
3092
3093 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3094
3095 if (unhandled_errors) {
3096 dispc.error_irqs |= unhandled_errors;
3097
3098 dispc.irq_error_mask &= ~unhandled_errors;
3099 _omap_dispc_set_irqs();
3100
3101 schedule_work(&dispc.error_work);
3102 }
3103
3104 spin_unlock(&dispc.irq_lock);
affe360d 3105
3106 return IRQ_HANDLED;
80c39712
TV		 3107}
3108
3109static void dispc_error_worker(struct work_struct *work)
3110{
3111 int i;
3112 u32 errors;
3113 unsigned long flags;
fe3cc9d6
TV		 3114 static const unsigned fifo_underflow_bits[] = {
3115 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3116 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3117 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3118 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3119 };
3120
3121 static const unsigned sync_lost_bits[] = {
3122 DISPC_IRQ_SYNC_LOST,
3123 DISPC_IRQ_SYNC_LOST_DIGIT,
3124 DISPC_IRQ_SYNC_LOST2,
3125 };
80c39712
TV		 3126
3127 spin_lock_irqsave(&dispc.irq_lock, flags);
3128 errors = dispc.error_irqs;
3129 dispc.error_irqs = 0;
3130 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3131
13eae1f9
DZ		 3132 dispc_runtime_get();
3133
fe3cc9d6
TV		 3134 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3135 struct omap_overlay *ovl;
3136 unsigned bit;
80c39712 3137
fe3cc9d6
TV		 3138 ovl = omap_dss_get_overlay(i);
3139 bit = fifo_underflow_bits[i];
80c39712 3140
fe3cc9d6
TV		 3141 if (bit & errors) {
3142 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3143 ovl->name);
f0e5caab 3144 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3145 dispc_mgr_go(ovl->manager->id);
80c39712 3146 mdelay(50);
80c39712
TV		 3147 }
3148 }
3149
fe3cc9d6
TV		 3150 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3151 struct omap_overlay_manager *mgr;
3152 unsigned bit;
80c39712 3153
fe3cc9d6
TV		 3154 mgr = omap_dss_get_overlay_manager(i);
3155 bit = sync_lost_bits[i];
80c39712 3156
fe3cc9d6
TV		 3157 if (bit & errors) {
3158 struct omap_dss_device *dssdev = mgr->device;
3159 bool enable;
80c39712 3160
fe3cc9d6
TV		 3161 DSSERR("SYNC_LOST on channel %s, restarting the output "
3162 "with video overlays disabled\n",
3163 mgr->name);
2a205f34 3164
fe3cc9d6
TV		 3165 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3166 dssdev->driver->disable(dssdev);
2a205f34 3167
2a205f34
SS		 3168 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3169 struct omap_overlay *ovl;
3170 ovl = omap_dss_get_overlay(i);
3171
fe3cc9d6
TV		 3172 if (ovl->id != OMAP_DSS_GFX &&
3173 ovl->manager == mgr)
f0e5caab 3174 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3175 }
3176
26d9dd0d 3177 dispc_mgr_go(mgr->id);
2a205f34 3178 mdelay(50);
fe3cc9d6 3179
2a205f34
SS		 3180 if (enable)
3181 dssdev->driver->enable(dssdev);
3182 }
3183 }
3184
80c39712
TV		 3185 if (errors & DISPC_IRQ_OCP_ERR) {
3186 DSSERR("OCP_ERR\n");
3187 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3188 struct omap_overlay_manager *mgr;
3189 mgr = omap_dss_get_overlay_manager(i);
4a9e78ab 3190 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3191 }
3192 }
3193
3194 spin_lock_irqsave(&dispc.irq_lock, flags);
3195 dispc.irq_error_mask |= errors;
3196 _omap_dispc_set_irqs();
3197 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3198
3199 dispc_runtime_put();
80c39712
TV		 3200}
3201
3202int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3203{
3204 void dispc_irq_wait_handler(void *data, u32 mask)
3205 {
3206 complete((struct completion *)data);
3207 }
3208
3209 int r;
3210 DECLARE_COMPLETION_ONSTACK(completion);
3211
3212 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3213 irqmask);
3214
3215 if (r)
3216 return r;
3217
3218 timeout = wait_for_completion_timeout(&completion, timeout);
3219
3220 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3221
3222 if (timeout == 0)
3223 return -ETIMEDOUT;
3224
3225 if (timeout == -ERESTARTSYS)
3226 return -ERESTARTSYS;
3227
3228 return 0;
3229}
3230
3231int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3232 unsigned long timeout)
3233{
3234 void dispc_irq_wait_handler(void *data, u32 mask)
3235 {
3236 complete((struct completion *)data);
3237 }
3238
3239 int r;
3240 DECLARE_COMPLETION_ONSTACK(completion);
3241
3242 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3243 irqmask);
3244
3245 if (r)
3246 return r;
3247
3248 timeout = wait_for_completion_interruptible_timeout(&completion,
3249 timeout);
3250
3251 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3252
3253 if (timeout == 0)
3254 return -ETIMEDOUT;
3255
3256 if (timeout == -ERESTARTSYS)
3257 return -ERESTARTSYS;
3258
3259 return 0;
3260}
3261
3262#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3263void dispc_fake_vsync_irq(void)
3264{
3265 u32 irqstatus = DISPC_IRQ_VSYNC;
3266 int i;
3267
ab83b14c 3268 WARN_ON(!in_interrupt());
80c39712
TV		 3269
3270 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3271 struct omap_dispc_isr_data *isr_data;
3272 isr_data = &dispc.registered_isr[i];
3273
3274 if (!isr_data->isr)
3275 continue;
3276
3277 if (isr_data->mask & irqstatus)
3278 isr_data->isr(isr_data->arg, irqstatus);
3279 }
80c39712
TV		 3280}
3281#endif
3282
3283static void _omap_dispc_initialize_irq(void)
3284{
3285 unsigned long flags;
3286
3287 spin_lock_irqsave(&dispc.irq_lock, flags);
3288
3289 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3290
3291 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3292 if (dss_has_feature(FEAT_MGR_LCD2))
3293 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3294 if (dss_feat_get_num_ovls() > 3)
3295 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3296
3297 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3298 * so clear it */
3299 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3300
3301 _omap_dispc_set_irqs();
3302
3303 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3304}
3305
3306void dispc_enable_sidle(void)
3307{
3308 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3309}
3310
3311void dispc_disable_sidle(void)
3312{
3313 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3314}
3315
3316static void _omap_dispc_initial_config(void)
3317{
3318 u32 l;
3319
0cf35df3
MR		 3320 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3321 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3322 l = dispc_read_reg(DISPC_DIVISOR);
3323 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3324 l = FLD_MOD(l, 1, 0, 0);
3325 l = FLD_MOD(l, 1, 23, 16);
3326 dispc_write_reg(DISPC_DIVISOR, l);
3327 }
3328
80c39712 3329 /* FUNCGATED */
6ced40bf
AT		 3330 if (dss_has_feature(FEAT_FUNCGATED))
3331 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3332
3333 /* L3 firewall setting: enable access to OCM RAM */
3334 /* XXX this should be somewhere in plat-omap */
3335 if (cpu_is_omap24xx())
3336 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3337
3338 _dispc_setup_color_conv_coef();
3339
3340 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3341
3342 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3343
3344 dispc_configure_burst_sizes();
54128701
AT		 3345
3346 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3347}
3348
060b6d9c
SG		 3349/* DISPC HW IP initialisation */
3350static int omap_dispchw_probe(struct platform_device *pdev)
3351{
3352 u32 rev;
affe360d 3353 int r = 0;
ea9da36a 3354 struct resource *dispc_mem;
4fbafaf3 3355 struct clk *clk;
ea9da36a 3356
060b6d9c
SG		 3357 dispc.pdev = pdev;
3358
4fbafaf3
TV		 3359 clk = clk_get(&pdev->dev, "fck");
3360 if (IS_ERR(clk)) {
3361 DSSERR("can't get fck\n");
3362 r = PTR_ERR(clk);
3363 goto err_get_clk;
3364 }
3365
3366 dispc.dss_clk = clk;
3367
060b6d9c
SG		 3368 spin_lock_init(&dispc.irq_lock);
3369
3370#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3371 spin_lock_init(&dispc.irq_stats_lock);
3372 dispc.irq_stats.last_reset = jiffies;
3373#endif
3374
3375 INIT_WORK(&dispc.error_work, dispc_error_worker);
3376
ea9da36a
SG		 3377 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3378 if (!dispc_mem) {
3379 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3380 r = -EINVAL;
4fbafaf3 3381 goto err_ioremap;
ea9da36a
SG		 3382 }
3383 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3384 if (!dispc.base) {
3385 DSSERR("can't ioremap DISPC\n");
affe360d 3386 r = -ENOMEM;
4fbafaf3 3387 goto err_ioremap;
affe360d 3388 }
3389 dispc.irq = platform_get_irq(dispc.pdev, 0);
3390 if (dispc.irq < 0) {
3391 DSSERR("platform_get_irq failed\n");
3392 r = -ENODEV;
4fbafaf3 3393 goto err_irq;
affe360d 3394 }
3395
3396 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3397 "OMAP DISPC", dispc.pdev);
3398 if (r < 0) {
3399 DSSERR("request_irq failed\n");
4fbafaf3 3400 goto err_irq;
060b6d9c
SG		 3401 }
3402
4fbafaf3
TV		 3403 pm_runtime_enable(&pdev->dev);
3404
3405 r = dispc_runtime_get();
3406 if (r)
3407 goto err_runtime_get;
060b6d9c
SG		 3408
3409 _omap_dispc_initial_config();
3410
3411 _omap_dispc_initialize_irq();
3412
060b6d9c 3413 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3414 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3415 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3416
4fbafaf3 3417 dispc_runtime_put();
060b6d9c
SG		 3418
3419 return 0;
4fbafaf3
TV		 3420
3421err_runtime_get:
3422 pm_runtime_disable(&pdev->dev);
3423 free_irq(dispc.irq, dispc.pdev);
3424err_irq:
affe360d 3425 iounmap(dispc.base);
4fbafaf3
TV		 3426err_ioremap:
3427 clk_put(dispc.dss_clk);
3428err_get_clk:
affe360d 3429 return r;
060b6d9c
SG		 3430}
3431
3432static int omap_dispchw_remove(struct platform_device *pdev)
3433{
4fbafaf3
TV		 3434 pm_runtime_disable(&pdev->dev);
3435
3436 clk_put(dispc.dss_clk);
3437
affe360d 3438 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3439 iounmap(dispc.base);
3440 return 0;
3441}
3442
4fbafaf3
TV		 3443static int dispc_runtime_suspend(struct device *dev)
3444{
3445 dispc_save_context();
4fbafaf3
TV		 3446 dss_runtime_put();
3447
3448 return 0;
3449}
3450
3451static int dispc_runtime_resume(struct device *dev)
3452{
3453 int r;
3454
3455 r = dss_runtime_get();
3456 if (r < 0)
3457 return r;
3458
49ea86f3 3459 dispc_restore_context();
4fbafaf3
TV		 3460
3461 return 0;
3462}
3463
3464static const struct dev_pm_ops dispc_pm_ops = {
3465 .runtime_suspend = dispc_runtime_suspend,
3466 .runtime_resume = dispc_runtime_resume,
3467};
3468
060b6d9c
SG		 3469static struct platform_driver omap_dispchw_driver = {
3470 .probe = omap_dispchw_probe,
3471 .remove = omap_dispchw_remove,
3472 .driver = {
3473 .name = "omapdss_dispc",
3474 .owner = THIS_MODULE,
4fbafaf3 3475 .pm = &dispc_pm_ops,
060b6d9c
SG		 3476 },
3477};
3478
3479int dispc_init_platform_driver(void)
3480{
3481 return platform_driver_register(&omap_dispchw_driver);
3482}
3483
3484void dispc_uninit_platform_driver(void)
3485{
3486 return platform_driver_unregister(&omap_dispchw_driver);
3487}
Linux kernel - Deliverables
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