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80c39712 TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dispc.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * Some code and ideas taken from drivers/video/omap/ driver | |
8 | * by Imre Deak. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify it | |
11 | * under the terms of the GNU General Public License version 2 as published by | |
12 | * the Free Software Foundation. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
16 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
17 | * more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along with | |
20 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
23 | #define DSS_SUBSYS_NAME "DISPC" | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/vmalloc.h> | |
a8a35931 | 28 | #include <linux/export.h> |
80c39712 TV |
29 | #include <linux/clk.h> |
30 | #include <linux/io.h> | |
31 | #include <linux/jiffies.h> | |
32 | #include <linux/seq_file.h> | |
33 | #include <linux/delay.h> | |
34 | #include <linux/workqueue.h> | |
ab83b14c | 35 | #include <linux/hardirq.h> |
affe360d | 36 | #include <linux/interrupt.h> |
24e6289c | 37 | #include <linux/platform_device.h> |
4fbafaf3 | 38 | #include <linux/pm_runtime.h> |
80c39712 | 39 | |
a0b38cc4 | 40 | #include <video/omapdss.h> |
80c39712 TV |
41 | |
42 | #include "dss.h" | |
a0acb557 | 43 | #include "dss_features.h" |
9b372c2d | 44 | #include "dispc.h" |
80c39712 TV |
45 | |
46 | /* DISPC */ | |
8613b000 | 47 | #define DISPC_SZ_REGS SZ_4K |
80c39712 | 48 | |
80c39712 TV |
49 | #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \ |
50 | DISPC_IRQ_OCP_ERR | \ | |
51 | DISPC_IRQ_VID1_FIFO_UNDERFLOW | \ | |
52 | DISPC_IRQ_VID2_FIFO_UNDERFLOW | \ | |
53 | DISPC_IRQ_SYNC_LOST | \ | |
54 | DISPC_IRQ_SYNC_LOST_DIGIT) | |
55 | ||
56 | #define DISPC_MAX_NR_ISRS 8 | |
57 | ||
58 | struct omap_dispc_isr_data { | |
59 | omap_dispc_isr_t isr; | |
60 | void *arg; | |
61 | u32 mask; | |
62 | }; | |
63 | ||
5ed8cf5b TV |
64 | enum omap_burst_size { |
65 | BURST_SIZE_X2 = 0, | |
66 | BURST_SIZE_X4 = 1, | |
67 | BURST_SIZE_X8 = 2, | |
68 | }; | |
69 | ||
80c39712 TV |
70 | #define REG_GET(idx, start, end) \ |
71 | FLD_GET(dispc_read_reg(idx), start, end) | |
72 | ||
73 | #define REG_FLD_MOD(idx, val, start, end) \ | |
74 | dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end)) | |
75 | ||
dfc0fd8d TV |
76 | struct dispc_irq_stats { |
77 | unsigned long last_reset; | |
78 | unsigned irq_count; | |
79 | unsigned irqs[32]; | |
80 | }; | |
81 | ||
dcbe765b CM |
82 | struct dispc_features { |
83 | u8 sw_start; | |
84 | u8 fp_start; | |
85 | u8 bp_start; | |
86 | u16 sw_max; | |
87 | u16 vp_max; | |
88 | u16 hp_max; | |
89 | int (*calc_scaling) (enum omap_channel channel, | |
90 | const struct omap_video_timings *mgr_timings, | |
91 | u16 width, u16 height, u16 out_width, u16 out_height, | |
92 | enum omap_color_mode color_mode, bool *five_taps, | |
93 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
94 | u16 pos_x, unsigned long *core_clk); | |
95 | unsigned long (*calc_core_clk) (enum omap_channel channel, | |
96 | u16 width, u16 height, u16 out_width, u16 out_height); | |
42a6961c | 97 | u8 num_fifos; |
66a0f9e4 TV |
98 | |
99 | /* swap GFX & WB fifos */ | |
100 | bool gfx_fifo_workaround:1; | |
dcbe765b CM |
101 | }; |
102 | ||
42a6961c TV |
103 | #define DISPC_MAX_NR_FIFOS 5 |
104 | ||
80c39712 | 105 | static struct { |
060b6d9c | 106 | struct platform_device *pdev; |
80c39712 | 107 | void __iomem *base; |
4fbafaf3 TV |
108 | |
109 | int ctx_loss_cnt; | |
110 | ||
affe360d | 111 | int irq; |
4fbafaf3 | 112 | struct clk *dss_clk; |
80c39712 | 113 | |
42a6961c TV |
114 | u32 fifo_size[DISPC_MAX_NR_FIFOS]; |
115 | /* maps which plane is using a fifo. fifo-id -> plane-id */ | |
116 | int fifo_assignment[DISPC_MAX_NR_FIFOS]; | |
80c39712 TV |
117 | |
118 | spinlock_t irq_lock; | |
119 | u32 irq_error_mask; | |
120 | struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; | |
121 | u32 error_irqs; | |
122 | struct work_struct error_work; | |
123 | ||
49ea86f3 | 124 | bool ctx_valid; |
80c39712 | 125 | u32 ctx[DISPC_SZ_REGS / sizeof(u32)]; |
dfc0fd8d | 126 | |
dcbe765b CM |
127 | const struct dispc_features *feat; |
128 | ||
dfc0fd8d TV |
129 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
130 | spinlock_t irq_stats_lock; | |
131 | struct dispc_irq_stats irq_stats; | |
132 | #endif | |
80c39712 TV |
133 | } dispc; |
134 | ||
0d66cbb5 AJ |
135 | enum omap_color_component { |
136 | /* used for all color formats for OMAP3 and earlier | |
137 | * and for RGB and Y color component on OMAP4 | |
138 | */ | |
139 | DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0, | |
140 | /* used for UV component for | |
141 | * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12 | |
142 | * color formats on OMAP4 | |
143 | */ | |
144 | DISPC_COLOR_COMPONENT_UV = 1 << 1, | |
145 | }; | |
146 | ||
efa70b3b CM |
147 | enum mgr_reg_fields { |
148 | DISPC_MGR_FLD_ENABLE, | |
149 | DISPC_MGR_FLD_STNTFT, | |
150 | DISPC_MGR_FLD_GO, | |
151 | DISPC_MGR_FLD_TFTDATALINES, | |
152 | DISPC_MGR_FLD_STALLMODE, | |
153 | DISPC_MGR_FLD_TCKENABLE, | |
154 | DISPC_MGR_FLD_TCKSELECTION, | |
155 | DISPC_MGR_FLD_CPR, | |
156 | DISPC_MGR_FLD_FIFOHANDCHECK, | |
157 | /* used to maintain a count of the above fields */ | |
158 | DISPC_MGR_FLD_NUM, | |
159 | }; | |
160 | ||
161 | static const struct { | |
162 | const char *name; | |
163 | u32 vsync_irq; | |
164 | u32 framedone_irq; | |
165 | u32 sync_lost_irq; | |
166 | struct reg_field reg_desc[DISPC_MGR_FLD_NUM]; | |
167 | } mgr_desc[] = { | |
168 | [OMAP_DSS_CHANNEL_LCD] = { | |
169 | .name = "LCD", | |
170 | .vsync_irq = DISPC_IRQ_VSYNC, | |
171 | .framedone_irq = DISPC_IRQ_FRAMEDONE, | |
172 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST, | |
173 | .reg_desc = { | |
174 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 }, | |
175 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 }, | |
176 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 }, | |
177 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 }, | |
178 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 }, | |
179 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 }, | |
180 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 }, | |
181 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 }, | |
182 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, | |
183 | }, | |
184 | }, | |
185 | [OMAP_DSS_CHANNEL_DIGIT] = { | |
186 | .name = "DIGIT", | |
187 | .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN, | |
188 | .framedone_irq = 0, | |
189 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT, | |
190 | .reg_desc = { | |
191 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 }, | |
192 | [DISPC_MGR_FLD_STNTFT] = { }, | |
193 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 }, | |
194 | [DISPC_MGR_FLD_TFTDATALINES] = { }, | |
195 | [DISPC_MGR_FLD_STALLMODE] = { }, | |
196 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 }, | |
197 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 }, | |
198 | [DISPC_MGR_FLD_CPR] = { }, | |
199 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 }, | |
200 | }, | |
201 | }, | |
202 | [OMAP_DSS_CHANNEL_LCD2] = { | |
203 | .name = "LCD2", | |
204 | .vsync_irq = DISPC_IRQ_VSYNC2, | |
205 | .framedone_irq = DISPC_IRQ_FRAMEDONE2, | |
206 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST2, | |
207 | .reg_desc = { | |
208 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 }, | |
209 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 }, | |
210 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 }, | |
211 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 }, | |
212 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 }, | |
213 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 }, | |
214 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 }, | |
215 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 }, | |
216 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 }, | |
217 | }, | |
218 | }, | |
e86d456a CM |
219 | [OMAP_DSS_CHANNEL_LCD3] = { |
220 | .name = "LCD3", | |
221 | .vsync_irq = DISPC_IRQ_VSYNC3, | |
222 | .framedone_irq = DISPC_IRQ_FRAMEDONE3, | |
223 | .sync_lost_irq = DISPC_IRQ_SYNC_LOST3, | |
224 | .reg_desc = { | |
225 | [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 }, | |
226 | [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 }, | |
227 | [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 }, | |
228 | [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 }, | |
229 | [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 }, | |
230 | [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 }, | |
231 | [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 }, | |
232 | [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 }, | |
233 | [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 }, | |
234 | }, | |
235 | }, | |
efa70b3b CM |
236 | }; |
237 | ||
80c39712 TV |
238 | static void _omap_dispc_set_irqs(void); |
239 | ||
55978cc2 | 240 | static inline void dispc_write_reg(const u16 idx, u32 val) |
80c39712 | 241 | { |
55978cc2 | 242 | __raw_writel(val, dispc.base + idx); |
80c39712 TV |
243 | } |
244 | ||
55978cc2 | 245 | static inline u32 dispc_read_reg(const u16 idx) |
80c39712 | 246 | { |
55978cc2 | 247 | return __raw_readl(dispc.base + idx); |
80c39712 TV |
248 | } |
249 | ||
efa70b3b CM |
250 | static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld) |
251 | { | |
252 | const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld]; | |
253 | return REG_GET(rfld.reg, rfld.high, rfld.low); | |
254 | } | |
255 | ||
256 | static void mgr_fld_write(enum omap_channel channel, | |
257 | enum mgr_reg_fields regfld, int val) { | |
258 | const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld]; | |
259 | REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); | |
260 | } | |
261 | ||
80c39712 | 262 | #define SR(reg) \ |
55978cc2 | 263 | dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg) |
80c39712 | 264 | #define RR(reg) \ |
55978cc2 | 265 | dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)]) |
80c39712 | 266 | |
4fbafaf3 | 267 | static void dispc_save_context(void) |
80c39712 | 268 | { |
c6104b8e | 269 | int i, j; |
80c39712 | 270 | |
4fbafaf3 TV |
271 | DSSDBG("dispc_save_context\n"); |
272 | ||
80c39712 TV |
273 | SR(IRQENABLE); |
274 | SR(CONTROL); | |
275 | SR(CONFIG); | |
80c39712 | 276 | SR(LINE_NUMBER); |
11354dd5 AT |
277 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
278 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 279 | SR(GLOBAL_ALPHA); |
2a205f34 SS |
280 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
281 | SR(CONTROL2); | |
2a205f34 SS |
282 | SR(CONFIG2); |
283 | } | |
e86d456a CM |
284 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
285 | SR(CONTROL3); | |
286 | SR(CONFIG3); | |
287 | } | |
80c39712 | 288 | |
c6104b8e AT |
289 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
290 | SR(DEFAULT_COLOR(i)); | |
291 | SR(TRANS_COLOR(i)); | |
292 | SR(SIZE_MGR(i)); | |
293 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
294 | continue; | |
295 | SR(TIMING_H(i)); | |
296 | SR(TIMING_V(i)); | |
297 | SR(POL_FREQ(i)); | |
298 | SR(DIVISORo(i)); | |
299 | ||
300 | SR(DATA_CYCLE1(i)); | |
301 | SR(DATA_CYCLE2(i)); | |
302 | SR(DATA_CYCLE3(i)); | |
303 | ||
332e9d70 | 304 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
305 | SR(CPR_COEF_R(i)); |
306 | SR(CPR_COEF_G(i)); | |
307 | SR(CPR_COEF_B(i)); | |
332e9d70 | 308 | } |
2a205f34 | 309 | } |
80c39712 | 310 | |
c6104b8e AT |
311 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
312 | SR(OVL_BA0(i)); | |
313 | SR(OVL_BA1(i)); | |
314 | SR(OVL_POSITION(i)); | |
315 | SR(OVL_SIZE(i)); | |
316 | SR(OVL_ATTRIBUTES(i)); | |
317 | SR(OVL_FIFO_THRESHOLD(i)); | |
318 | SR(OVL_ROW_INC(i)); | |
319 | SR(OVL_PIXEL_INC(i)); | |
320 | if (dss_has_feature(FEAT_PRELOAD)) | |
321 | SR(OVL_PRELOAD(i)); | |
322 | if (i == OMAP_DSS_GFX) { | |
323 | SR(OVL_WINDOW_SKIP(i)); | |
324 | SR(OVL_TABLE_BA(i)); | |
325 | continue; | |
326 | } | |
327 | SR(OVL_FIR(i)); | |
328 | SR(OVL_PICTURE_SIZE(i)); | |
329 | SR(OVL_ACCU0(i)); | |
330 | SR(OVL_ACCU1(i)); | |
9b372c2d | 331 | |
c6104b8e AT |
332 | for (j = 0; j < 8; j++) |
333 | SR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 334 | |
c6104b8e AT |
335 | for (j = 0; j < 8; j++) |
336 | SR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 337 | |
c6104b8e AT |
338 | for (j = 0; j < 5; j++) |
339 | SR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 340 | |
c6104b8e AT |
341 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
342 | for (j = 0; j < 8; j++) | |
343 | SR(OVL_FIR_COEF_V(i, j)); | |
344 | } | |
9b372c2d | 345 | |
c6104b8e AT |
346 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
347 | SR(OVL_BA0_UV(i)); | |
348 | SR(OVL_BA1_UV(i)); | |
349 | SR(OVL_FIR2(i)); | |
350 | SR(OVL_ACCU2_0(i)); | |
351 | SR(OVL_ACCU2_1(i)); | |
ab5ca071 | 352 | |
c6104b8e AT |
353 | for (j = 0; j < 8; j++) |
354 | SR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 355 | |
c6104b8e AT |
356 | for (j = 0; j < 8; j++) |
357 | SR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 358 | |
c6104b8e AT |
359 | for (j = 0; j < 8; j++) |
360 | SR(OVL_FIR_COEF_V2(i, j)); | |
361 | } | |
362 | if (dss_has_feature(FEAT_ATTR2)) | |
363 | SR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 364 | } |
0cf35df3 MR |
365 | |
366 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
367 | SR(DIVISOR); | |
49ea86f3 | 368 | |
00928eaf | 369 | dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev); |
49ea86f3 TV |
370 | dispc.ctx_valid = true; |
371 | ||
372 | DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt); | |
80c39712 TV |
373 | } |
374 | ||
4fbafaf3 | 375 | static void dispc_restore_context(void) |
80c39712 | 376 | { |
c6104b8e | 377 | int i, j, ctx; |
4fbafaf3 TV |
378 | |
379 | DSSDBG("dispc_restore_context\n"); | |
380 | ||
49ea86f3 TV |
381 | if (!dispc.ctx_valid) |
382 | return; | |
383 | ||
00928eaf | 384 | ctx = dss_get_ctx_loss_count(&dispc.pdev->dev); |
49ea86f3 TV |
385 | |
386 | if (ctx >= 0 && ctx == dispc.ctx_loss_cnt) | |
387 | return; | |
388 | ||
389 | DSSDBG("ctx_loss_count: saved %d, current %d\n", | |
390 | dispc.ctx_loss_cnt, ctx); | |
391 | ||
75c7d59d | 392 | /*RR(IRQENABLE);*/ |
80c39712 TV |
393 | /*RR(CONTROL);*/ |
394 | RR(CONFIG); | |
80c39712 | 395 | RR(LINE_NUMBER); |
11354dd5 AT |
396 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
397 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 398 | RR(GLOBAL_ALPHA); |
c6104b8e | 399 | if (dss_has_feature(FEAT_MGR_LCD2)) |
2a205f34 | 400 | RR(CONFIG2); |
e86d456a CM |
401 | if (dss_has_feature(FEAT_MGR_LCD3)) |
402 | RR(CONFIG3); | |
80c39712 | 403 | |
c6104b8e AT |
404 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { |
405 | RR(DEFAULT_COLOR(i)); | |
406 | RR(TRANS_COLOR(i)); | |
407 | RR(SIZE_MGR(i)); | |
408 | if (i == OMAP_DSS_CHANNEL_DIGIT) | |
409 | continue; | |
410 | RR(TIMING_H(i)); | |
411 | RR(TIMING_V(i)); | |
412 | RR(POL_FREQ(i)); | |
413 | RR(DIVISORo(i)); | |
414 | ||
415 | RR(DATA_CYCLE1(i)); | |
416 | RR(DATA_CYCLE2(i)); | |
417 | RR(DATA_CYCLE3(i)); | |
2a205f34 | 418 | |
332e9d70 | 419 | if (dss_has_feature(FEAT_CPR)) { |
c6104b8e AT |
420 | RR(CPR_COEF_R(i)); |
421 | RR(CPR_COEF_G(i)); | |
422 | RR(CPR_COEF_B(i)); | |
332e9d70 | 423 | } |
2a205f34 | 424 | } |
80c39712 | 425 | |
c6104b8e AT |
426 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { |
427 | RR(OVL_BA0(i)); | |
428 | RR(OVL_BA1(i)); | |
429 | RR(OVL_POSITION(i)); | |
430 | RR(OVL_SIZE(i)); | |
431 | RR(OVL_ATTRIBUTES(i)); | |
432 | RR(OVL_FIFO_THRESHOLD(i)); | |
433 | RR(OVL_ROW_INC(i)); | |
434 | RR(OVL_PIXEL_INC(i)); | |
435 | if (dss_has_feature(FEAT_PRELOAD)) | |
436 | RR(OVL_PRELOAD(i)); | |
437 | if (i == OMAP_DSS_GFX) { | |
438 | RR(OVL_WINDOW_SKIP(i)); | |
439 | RR(OVL_TABLE_BA(i)); | |
440 | continue; | |
441 | } | |
442 | RR(OVL_FIR(i)); | |
443 | RR(OVL_PICTURE_SIZE(i)); | |
444 | RR(OVL_ACCU0(i)); | |
445 | RR(OVL_ACCU1(i)); | |
9b372c2d | 446 | |
c6104b8e AT |
447 | for (j = 0; j < 8; j++) |
448 | RR(OVL_FIR_COEF_H(i, j)); | |
ab5ca071 | 449 | |
c6104b8e AT |
450 | for (j = 0; j < 8; j++) |
451 | RR(OVL_FIR_COEF_HV(i, j)); | |
ab5ca071 | 452 | |
c6104b8e AT |
453 | for (j = 0; j < 5; j++) |
454 | RR(OVL_CONV_COEF(i, j)); | |
ab5ca071 | 455 | |
c6104b8e AT |
456 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
457 | for (j = 0; j < 8; j++) | |
458 | RR(OVL_FIR_COEF_V(i, j)); | |
459 | } | |
9b372c2d | 460 | |
c6104b8e AT |
461 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { |
462 | RR(OVL_BA0_UV(i)); | |
463 | RR(OVL_BA1_UV(i)); | |
464 | RR(OVL_FIR2(i)); | |
465 | RR(OVL_ACCU2_0(i)); | |
466 | RR(OVL_ACCU2_1(i)); | |
ab5ca071 | 467 | |
c6104b8e AT |
468 | for (j = 0; j < 8; j++) |
469 | RR(OVL_FIR_COEF_H2(i, j)); | |
ab5ca071 | 470 | |
c6104b8e AT |
471 | for (j = 0; j < 8; j++) |
472 | RR(OVL_FIR_COEF_HV2(i, j)); | |
ab5ca071 | 473 | |
c6104b8e AT |
474 | for (j = 0; j < 8; j++) |
475 | RR(OVL_FIR_COEF_V2(i, j)); | |
476 | } | |
477 | if (dss_has_feature(FEAT_ATTR2)) | |
478 | RR(OVL_ATTRIBUTES2(i)); | |
ab5ca071 | 479 | } |
80c39712 | 480 | |
0cf35df3 MR |
481 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) |
482 | RR(DIVISOR); | |
483 | ||
80c39712 TV |
484 | /* enable last, because LCD & DIGIT enable are here */ |
485 | RR(CONTROL); | |
2a205f34 SS |
486 | if (dss_has_feature(FEAT_MGR_LCD2)) |
487 | RR(CONTROL2); | |
e86d456a CM |
488 | if (dss_has_feature(FEAT_MGR_LCD3)) |
489 | RR(CONTROL3); | |
75c7d59d VS |
490 | /* clear spurious SYNC_LOST_DIGIT interrupts */ |
491 | dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); | |
492 | ||
493 | /* | |
494 | * enable last so IRQs won't trigger before | |
495 | * the context is fully restored | |
496 | */ | |
497 | RR(IRQENABLE); | |
49ea86f3 TV |
498 | |
499 | DSSDBG("context restored\n"); | |
80c39712 TV |
500 | } |
501 | ||
502 | #undef SR | |
503 | #undef RR | |
504 | ||
4fbafaf3 TV |
505 | int dispc_runtime_get(void) |
506 | { | |
507 | int r; | |
508 | ||
509 | DSSDBG("dispc_runtime_get\n"); | |
510 | ||
511 | r = pm_runtime_get_sync(&dispc.pdev->dev); | |
512 | WARN_ON(r < 0); | |
513 | return r < 0 ? r : 0; | |
514 | } | |
515 | ||
516 | void dispc_runtime_put(void) | |
517 | { | |
518 | int r; | |
519 | ||
520 | DSSDBG("dispc_runtime_put\n"); | |
521 | ||
0eaf9f52 | 522 | r = pm_runtime_put_sync(&dispc.pdev->dev); |
5be3aebd | 523 | WARN_ON(r < 0 && r != -ENOSYS); |
80c39712 TV |
524 | } |
525 | ||
3dcec4d6 TV |
526 | u32 dispc_mgr_get_vsync_irq(enum omap_channel channel) |
527 | { | |
efa70b3b | 528 | return mgr_desc[channel].vsync_irq; |
3dcec4d6 TV |
529 | } |
530 | ||
7d1365c9 TV |
531 | u32 dispc_mgr_get_framedone_irq(enum omap_channel channel) |
532 | { | |
efa70b3b | 533 | return mgr_desc[channel].framedone_irq; |
7d1365c9 TV |
534 | } |
535 | ||
26d9dd0d | 536 | bool dispc_mgr_go_busy(enum omap_channel channel) |
80c39712 | 537 | { |
efa70b3b | 538 | return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; |
80c39712 TV |
539 | } |
540 | ||
26d9dd0d | 541 | void dispc_mgr_go(enum omap_channel channel) |
80c39712 | 542 | { |
2a205f34 | 543 | bool enable_bit, go_bit; |
80c39712 | 544 | |
80c39712 | 545 | /* if the channel is not enabled, we don't need GO */ |
efa70b3b | 546 | enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1; |
2a205f34 SS |
547 | |
548 | if (!enable_bit) | |
e6d80f95 | 549 | return; |
80c39712 | 550 | |
efa70b3b | 551 | go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1; |
2a205f34 SS |
552 | |
553 | if (go_bit) { | |
80c39712 | 554 | DSSERR("GO bit not down for channel %d\n", channel); |
e6d80f95 | 555 | return; |
80c39712 TV |
556 | } |
557 | ||
efa70b3b | 558 | DSSDBG("GO %s\n", mgr_desc[channel].name); |
80c39712 | 559 | |
efa70b3b | 560 | mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1); |
80c39712 TV |
561 | } |
562 | ||
f0e5caab | 563 | static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 564 | { |
9b372c2d | 565 | dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value); |
80c39712 TV |
566 | } |
567 | ||
f0e5caab | 568 | static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 569 | { |
9b372c2d | 570 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value); |
80c39712 TV |
571 | } |
572 | ||
f0e5caab | 573 | static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value) |
80c39712 | 574 | { |
9b372c2d | 575 | dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value); |
80c39712 TV |
576 | } |
577 | ||
f0e5caab | 578 | static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
579 | { |
580 | BUG_ON(plane == OMAP_DSS_GFX); | |
581 | ||
582 | dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value); | |
583 | } | |
584 | ||
f0e5caab TV |
585 | static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg, |
586 | u32 value) | |
ab5ca071 AJ |
587 | { |
588 | BUG_ON(plane == OMAP_DSS_GFX); | |
589 | ||
590 | dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value); | |
591 | } | |
592 | ||
f0e5caab | 593 | static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value) |
ab5ca071 AJ |
594 | { |
595 | BUG_ON(plane == OMAP_DSS_GFX); | |
596 | ||
597 | dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value); | |
598 | } | |
599 | ||
debd9074 CM |
600 | static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc, |
601 | int fir_vinc, int five_taps, | |
602 | enum omap_color_component color_comp) | |
80c39712 | 603 | { |
debd9074 | 604 | const struct dispc_coef *h_coef, *v_coef; |
80c39712 TV |
605 | int i; |
606 | ||
debd9074 CM |
607 | h_coef = dispc_ovl_get_scale_coef(fir_hinc, true); |
608 | v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps); | |
80c39712 TV |
609 | |
610 | for (i = 0; i < 8; i++) { | |
611 | u32 h, hv; | |
612 | ||
debd9074 CM |
613 | h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0) |
614 | | FLD_VAL(h_coef[i].hc1_vc0, 15, 8) | |
615 | | FLD_VAL(h_coef[i].hc2_vc1, 23, 16) | |
616 | | FLD_VAL(h_coef[i].hc3_vc2, 31, 24); | |
617 | hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0) | |
618 | | FLD_VAL(v_coef[i].hc1_vc0, 15, 8) | |
619 | | FLD_VAL(v_coef[i].hc2_vc1, 23, 16) | |
620 | | FLD_VAL(v_coef[i].hc3_vc2, 31, 24); | |
80c39712 | 621 | |
0d66cbb5 | 622 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
f0e5caab TV |
623 | dispc_ovl_write_firh_reg(plane, i, h); |
624 | dispc_ovl_write_firhv_reg(plane, i, hv); | |
0d66cbb5 | 625 | } else { |
f0e5caab TV |
626 | dispc_ovl_write_firh2_reg(plane, i, h); |
627 | dispc_ovl_write_firhv2_reg(plane, i, hv); | |
0d66cbb5 AJ |
628 | } |
629 | ||
80c39712 TV |
630 | } |
631 | ||
66be8f6c GI |
632 | if (five_taps) { |
633 | for (i = 0; i < 8; i++) { | |
634 | u32 v; | |
debd9074 CM |
635 | v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0) |
636 | | FLD_VAL(v_coef[i].hc4_vc22, 15, 8); | |
0d66cbb5 | 637 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) |
f0e5caab | 638 | dispc_ovl_write_firv_reg(plane, i, v); |
0d66cbb5 | 639 | else |
f0e5caab | 640 | dispc_ovl_write_firv2_reg(plane, i, v); |
66be8f6c | 641 | } |
80c39712 TV |
642 | } |
643 | } | |
644 | ||
645 | static void _dispc_setup_color_conv_coef(void) | |
646 | { | |
ac01c29e | 647 | int i; |
80c39712 TV |
648 | const struct color_conv_coef { |
649 | int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb; | |
650 | int full_range; | |
651 | } ctbl_bt601_5 = { | |
652 | 298, 409, 0, 298, -208, -100, 298, 0, 517, 0, | |
653 | }; | |
654 | ||
655 | const struct color_conv_coef *ct; | |
656 | ||
657 | #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0)) | |
658 | ||
659 | ct = &ctbl_bt601_5; | |
660 | ||
ac01c29e AT |
661 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { |
662 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0), | |
663 | CVAL(ct->rcr, ct->ry)); | |
664 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1), | |
665 | CVAL(ct->gy, ct->rcb)); | |
666 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2), | |
667 | CVAL(ct->gcb, ct->gcr)); | |
668 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3), | |
669 | CVAL(ct->bcr, ct->by)); | |
670 | dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4), | |
671 | CVAL(0, ct->bcb)); | |
672 | ||
673 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range, | |
674 | 11, 11); | |
675 | } | |
80c39712 TV |
676 | |
677 | #undef CVAL | |
80c39712 TV |
678 | } |
679 | ||
680 | ||
f0e5caab | 681 | static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr) |
80c39712 | 682 | { |
9b372c2d | 683 | dispc_write_reg(DISPC_OVL_BA0(plane), paddr); |
80c39712 TV |
684 | } |
685 | ||
f0e5caab | 686 | static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr) |
80c39712 | 687 | { |
9b372c2d | 688 | dispc_write_reg(DISPC_OVL_BA1(plane), paddr); |
80c39712 TV |
689 | } |
690 | ||
f0e5caab | 691 | static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
692 | { |
693 | dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr); | |
694 | } | |
695 | ||
f0e5caab | 696 | static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr) |
ab5ca071 AJ |
697 | { |
698 | dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr); | |
699 | } | |
700 | ||
f0e5caab | 701 | static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y) |
80c39712 | 702 | { |
80c39712 | 703 | u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0); |
9b372c2d AT |
704 | |
705 | dispc_write_reg(DISPC_OVL_POSITION(plane), val); | |
80c39712 TV |
706 | } |
707 | ||
78b687fc AT |
708 | static void dispc_ovl_set_input_size(enum omap_plane plane, int width, |
709 | int height) | |
80c39712 | 710 | { |
80c39712 | 711 | u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
9b372c2d AT |
712 | |
713 | if (plane == OMAP_DSS_GFX) | |
714 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); | |
715 | else | |
716 | dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val); | |
80c39712 TV |
717 | } |
718 | ||
78b687fc AT |
719 | static void dispc_ovl_set_output_size(enum omap_plane plane, int width, |
720 | int height) | |
80c39712 TV |
721 | { |
722 | u32 val; | |
80c39712 TV |
723 | |
724 | BUG_ON(plane == OMAP_DSS_GFX); | |
725 | ||
726 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); | |
9b372c2d AT |
727 | |
728 | dispc_write_reg(DISPC_OVL_SIZE(plane), val); | |
80c39712 TV |
729 | } |
730 | ||
54128701 AT |
731 | static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder) |
732 | { | |
733 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); | |
734 | ||
735 | if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0) | |
736 | return; | |
737 | ||
738 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); | |
739 | } | |
740 | ||
741 | static void dispc_ovl_enable_zorder_planes(void) | |
742 | { | |
743 | int i; | |
744 | ||
745 | if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
746 | return; | |
747 | ||
748 | for (i = 0; i < dss_feat_get_num_ovls(); i++) | |
749 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); | |
750 | } | |
751 | ||
f0e5caab | 752 | static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable) |
fd28a390 | 753 | { |
f6dc8150 | 754 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); |
fd28a390 | 755 | |
f6dc8150 | 756 | if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0) |
fd28a390 R |
757 | return; |
758 | ||
9b372c2d | 759 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); |
fd28a390 R |
760 | } |
761 | ||
f0e5caab | 762 | static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha) |
80c39712 | 763 | { |
b8c095b4 | 764 | static const unsigned shifts[] = { 0, 8, 16, 24, }; |
fe3cc9d6 | 765 | int shift; |
f6dc8150 | 766 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); |
fe3cc9d6 | 767 | |
f6dc8150 | 768 | if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0) |
fd28a390 | 769 | return; |
a0acb557 | 770 | |
fe3cc9d6 TV |
771 | shift = shifts[plane]; |
772 | REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); | |
80c39712 TV |
773 | } |
774 | ||
f0e5caab | 775 | static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc) |
80c39712 | 776 | { |
9b372c2d | 777 | dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc); |
80c39712 TV |
778 | } |
779 | ||
f0e5caab | 780 | static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc) |
80c39712 | 781 | { |
9b372c2d | 782 | dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc); |
80c39712 TV |
783 | } |
784 | ||
f0e5caab | 785 | static void dispc_ovl_set_color_mode(enum omap_plane plane, |
80c39712 TV |
786 | enum omap_color_mode color_mode) |
787 | { | |
788 | u32 m = 0; | |
f20e4220 AJ |
789 | if (plane != OMAP_DSS_GFX) { |
790 | switch (color_mode) { | |
791 | case OMAP_DSS_COLOR_NV12: | |
792 | m = 0x0; break; | |
08f3267e | 793 | case OMAP_DSS_COLOR_RGBX16: |
f20e4220 AJ |
794 | m = 0x1; break; |
795 | case OMAP_DSS_COLOR_RGBA16: | |
796 | m = 0x2; break; | |
08f3267e | 797 | case OMAP_DSS_COLOR_RGB12U: |
f20e4220 AJ |
798 | m = 0x4; break; |
799 | case OMAP_DSS_COLOR_ARGB16: | |
800 | m = 0x5; break; | |
801 | case OMAP_DSS_COLOR_RGB16: | |
802 | m = 0x6; break; | |
803 | case OMAP_DSS_COLOR_ARGB16_1555: | |
804 | m = 0x7; break; | |
805 | case OMAP_DSS_COLOR_RGB24U: | |
806 | m = 0x8; break; | |
807 | case OMAP_DSS_COLOR_RGB24P: | |
808 | m = 0x9; break; | |
809 | case OMAP_DSS_COLOR_YUV2: | |
810 | m = 0xa; break; | |
811 | case OMAP_DSS_COLOR_UYVY: | |
812 | m = 0xb; break; | |
813 | case OMAP_DSS_COLOR_ARGB32: | |
814 | m = 0xc; break; | |
815 | case OMAP_DSS_COLOR_RGBA32: | |
816 | m = 0xd; break; | |
817 | case OMAP_DSS_COLOR_RGBX32: | |
818 | m = 0xe; break; | |
819 | case OMAP_DSS_COLOR_XRGB16_1555: | |
820 | m = 0xf; break; | |
821 | default: | |
c6eee968 | 822 | BUG(); return; |
f20e4220 AJ |
823 | } |
824 | } else { | |
825 | switch (color_mode) { | |
826 | case OMAP_DSS_COLOR_CLUT1: | |
827 | m = 0x0; break; | |
828 | case OMAP_DSS_COLOR_CLUT2: | |
829 | m = 0x1; break; | |
830 | case OMAP_DSS_COLOR_CLUT4: | |
831 | m = 0x2; break; | |
832 | case OMAP_DSS_COLOR_CLUT8: | |
833 | m = 0x3; break; | |
834 | case OMAP_DSS_COLOR_RGB12U: | |
835 | m = 0x4; break; | |
836 | case OMAP_DSS_COLOR_ARGB16: | |
837 | m = 0x5; break; | |
838 | case OMAP_DSS_COLOR_RGB16: | |
839 | m = 0x6; break; | |
840 | case OMAP_DSS_COLOR_ARGB16_1555: | |
841 | m = 0x7; break; | |
842 | case OMAP_DSS_COLOR_RGB24U: | |
843 | m = 0x8; break; | |
844 | case OMAP_DSS_COLOR_RGB24P: | |
845 | m = 0x9; break; | |
08f3267e | 846 | case OMAP_DSS_COLOR_RGBX16: |
f20e4220 | 847 | m = 0xa; break; |
08f3267e | 848 | case OMAP_DSS_COLOR_RGBA16: |
f20e4220 AJ |
849 | m = 0xb; break; |
850 | case OMAP_DSS_COLOR_ARGB32: | |
851 | m = 0xc; break; | |
852 | case OMAP_DSS_COLOR_RGBA32: | |
853 | m = 0xd; break; | |
854 | case OMAP_DSS_COLOR_RGBX32: | |
855 | m = 0xe; break; | |
856 | case OMAP_DSS_COLOR_XRGB16_1555: | |
857 | m = 0xf; break; | |
858 | default: | |
c6eee968 | 859 | BUG(); return; |
f20e4220 | 860 | } |
80c39712 TV |
861 | } |
862 | ||
9b372c2d | 863 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); |
80c39712 TV |
864 | } |
865 | ||
65e006ff CM |
866 | static void dispc_ovl_configure_burst_type(enum omap_plane plane, |
867 | enum omap_dss_rotation_type rotation_type) | |
868 | { | |
869 | if (dss_has_feature(FEAT_BURST_2D) == 0) | |
870 | return; | |
871 | ||
872 | if (rotation_type == OMAP_DSS_ROT_TILER) | |
873 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); | |
874 | else | |
875 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); | |
876 | } | |
877 | ||
f427984e | 878 | void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel) |
80c39712 TV |
879 | { |
880 | int shift; | |
881 | u32 val; | |
2a205f34 | 882 | int chan = 0, chan2 = 0; |
80c39712 TV |
883 | |
884 | switch (plane) { | |
885 | case OMAP_DSS_GFX: | |
886 | shift = 8; | |
887 | break; | |
888 | case OMAP_DSS_VIDEO1: | |
889 | case OMAP_DSS_VIDEO2: | |
b8c095b4 | 890 | case OMAP_DSS_VIDEO3: |
80c39712 TV |
891 | shift = 16; |
892 | break; | |
893 | default: | |
894 | BUG(); | |
895 | return; | |
896 | } | |
897 | ||
9b372c2d | 898 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
2a205f34 SS |
899 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
900 | switch (channel) { | |
901 | case OMAP_DSS_CHANNEL_LCD: | |
902 | chan = 0; | |
903 | chan2 = 0; | |
904 | break; | |
905 | case OMAP_DSS_CHANNEL_DIGIT: | |
906 | chan = 1; | |
907 | chan2 = 0; | |
908 | break; | |
909 | case OMAP_DSS_CHANNEL_LCD2: | |
910 | chan = 0; | |
911 | chan2 = 1; | |
912 | break; | |
e86d456a CM |
913 | case OMAP_DSS_CHANNEL_LCD3: |
914 | if (dss_has_feature(FEAT_MGR_LCD3)) { | |
915 | chan = 0; | |
916 | chan2 = 2; | |
917 | } else { | |
918 | BUG(); | |
919 | return; | |
920 | } | |
921 | break; | |
2a205f34 SS |
922 | default: |
923 | BUG(); | |
c6eee968 | 924 | return; |
2a205f34 SS |
925 | } |
926 | ||
927 | val = FLD_MOD(val, chan, shift, shift); | |
928 | val = FLD_MOD(val, chan2, 31, 30); | |
929 | } else { | |
930 | val = FLD_MOD(val, channel, shift, shift); | |
931 | } | |
9b372c2d | 932 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 TV |
933 | } |
934 | ||
2cc5d1af TV |
935 | static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane) |
936 | { | |
937 | int shift; | |
938 | u32 val; | |
939 | enum omap_channel channel; | |
940 | ||
941 | switch (plane) { | |
942 | case OMAP_DSS_GFX: | |
943 | shift = 8; | |
944 | break; | |
945 | case OMAP_DSS_VIDEO1: | |
946 | case OMAP_DSS_VIDEO2: | |
947 | case OMAP_DSS_VIDEO3: | |
948 | shift = 16; | |
949 | break; | |
950 | default: | |
951 | BUG(); | |
c6eee968 | 952 | return 0; |
2cc5d1af TV |
953 | } |
954 | ||
955 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); | |
956 | ||
e86d456a CM |
957 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
958 | if (FLD_GET(val, 31, 30) == 0) | |
959 | channel = FLD_GET(val, shift, shift); | |
960 | else if (FLD_GET(val, 31, 30) == 1) | |
961 | channel = OMAP_DSS_CHANNEL_LCD2; | |
962 | else | |
963 | channel = OMAP_DSS_CHANNEL_LCD3; | |
964 | } else if (dss_has_feature(FEAT_MGR_LCD2)) { | |
2cc5d1af TV |
965 | if (FLD_GET(val, 31, 30) == 0) |
966 | channel = FLD_GET(val, shift, shift); | |
967 | else | |
968 | channel = OMAP_DSS_CHANNEL_LCD2; | |
969 | } else { | |
970 | channel = FLD_GET(val, shift, shift); | |
971 | } | |
972 | ||
973 | return channel; | |
974 | } | |
975 | ||
f0e5caab | 976 | static void dispc_ovl_set_burst_size(enum omap_plane plane, |
80c39712 TV |
977 | enum omap_burst_size burst_size) |
978 | { | |
b8c095b4 | 979 | static const unsigned shifts[] = { 6, 14, 14, 14, }; |
80c39712 | 980 | int shift; |
80c39712 | 981 | |
fe3cc9d6 | 982 | shift = shifts[plane]; |
5ed8cf5b | 983 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift); |
80c39712 TV |
984 | } |
985 | ||
5ed8cf5b TV |
986 | static void dispc_configure_burst_sizes(void) |
987 | { | |
988 | int i; | |
989 | const int burst_size = BURST_SIZE_X8; | |
990 | ||
991 | /* Configure burst size always to maximum size */ | |
992 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) | |
f0e5caab | 993 | dispc_ovl_set_burst_size(i, burst_size); |
5ed8cf5b TV |
994 | } |
995 | ||
83fa2f2e | 996 | static u32 dispc_ovl_get_burst_size(enum omap_plane plane) |
5ed8cf5b TV |
997 | { |
998 | unsigned unit = dss_feat_get_burst_size_unit(); | |
999 | /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */ | |
1000 | return unit * 8; | |
1001 | } | |
1002 | ||
d3862610 M |
1003 | void dispc_enable_gamma_table(bool enable) |
1004 | { | |
1005 | /* | |
1006 | * This is partially implemented to support only disabling of | |
1007 | * the gamma table. | |
1008 | */ | |
1009 | if (enable) { | |
1010 | DSSWARN("Gamma table enabling for TV not yet supported"); | |
1011 | return; | |
1012 | } | |
1013 | ||
1014 | REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9); | |
1015 | } | |
1016 | ||
c64dca40 | 1017 | static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable) |
3c07cae2 | 1018 | { |
efa70b3b | 1019 | if (channel == OMAP_DSS_CHANNEL_DIGIT) |
3c07cae2 TV |
1020 | return; |
1021 | ||
efa70b3b | 1022 | mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable); |
3c07cae2 TV |
1023 | } |
1024 | ||
c64dca40 | 1025 | static void dispc_mgr_set_cpr_coef(enum omap_channel channel, |
3c07cae2 TV |
1026 | struct omap_dss_cpr_coefs *coefs) |
1027 | { | |
1028 | u32 coef_r, coef_g, coef_b; | |
1029 | ||
dd88b7a6 | 1030 | if (!dss_mgr_is_lcd(channel)) |
3c07cae2 TV |
1031 | return; |
1032 | ||
1033 | coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) | | |
1034 | FLD_VAL(coefs->rb, 9, 0); | |
1035 | coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) | | |
1036 | FLD_VAL(coefs->gb, 9, 0); | |
1037 | coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) | | |
1038 | FLD_VAL(coefs->bb, 9, 0); | |
1039 | ||
1040 | dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r); | |
1041 | dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g); | |
1042 | dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b); | |
1043 | } | |
1044 | ||
f0e5caab | 1045 | static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable) |
80c39712 TV |
1046 | { |
1047 | u32 val; | |
1048 | ||
1049 | BUG_ON(plane == OMAP_DSS_GFX); | |
1050 | ||
9b372c2d | 1051 | val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1052 | val = FLD_MOD(val, enable, 9, 9); |
9b372c2d | 1053 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val); |
80c39712 TV |
1054 | } |
1055 | ||
c3d92529 | 1056 | static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable) |
80c39712 | 1057 | { |
b8c095b4 | 1058 | static const unsigned shifts[] = { 5, 10, 10, 10 }; |
fe3cc9d6 | 1059 | int shift; |
80c39712 | 1060 | |
fe3cc9d6 TV |
1061 | shift = shifts[plane]; |
1062 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); | |
80c39712 TV |
1063 | } |
1064 | ||
8f366162 | 1065 | static void dispc_mgr_set_size(enum omap_channel channel, u16 width, |
e5c09e06 | 1066 | u16 height) |
80c39712 TV |
1067 | { |
1068 | u32 val; | |
80c39712 | 1069 | |
80c39712 | 1070 | val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0); |
8f366162 | 1071 | dispc_write_reg(DISPC_SIZE_MGR(channel), val); |
80c39712 TV |
1072 | } |
1073 | ||
42a6961c | 1074 | static void dispc_init_fifos(void) |
80c39712 | 1075 | { |
80c39712 | 1076 | u32 size; |
42a6961c | 1077 | int fifo; |
a0acb557 | 1078 | u8 start, end; |
5ed8cf5b TV |
1079 | u32 unit; |
1080 | ||
1081 | unit = dss_feat_get_buffer_size_unit(); | |
80c39712 | 1082 | |
a0acb557 | 1083 | dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end); |
80c39712 | 1084 | |
42a6961c TV |
1085 | for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { |
1086 | size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); | |
5ed8cf5b | 1087 | size *= unit; |
42a6961c TV |
1088 | dispc.fifo_size[fifo] = size; |
1089 | ||
1090 | /* | |
1091 | * By default fifos are mapped directly to overlays, fifo 0 to | |
1092 | * ovl 0, fifo 1 to ovl 1, etc. | |
1093 | */ | |
1094 | dispc.fifo_assignment[fifo] = fifo; | |
80c39712 | 1095 | } |
66a0f9e4 TV |
1096 | |
1097 | /* | |
1098 | * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo | |
1099 | * causes problems with certain use cases, like using the tiler in 2D | |
1100 | * mode. The below hack swaps the fifos of GFX and WB planes, thus | |
1101 | * giving GFX plane a larger fifo. WB but should work fine with a | |
1102 | * smaller fifo. | |
1103 | */ | |
1104 | if (dispc.feat->gfx_fifo_workaround) { | |
1105 | u32 v; | |
1106 | ||
1107 | v = dispc_read_reg(DISPC_GLOBAL_BUFFER); | |
1108 | ||
1109 | v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */ | |
1110 | v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */ | |
1111 | v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */ | |
1112 | v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */ | |
1113 | ||
1114 | dispc_write_reg(DISPC_GLOBAL_BUFFER, v); | |
1115 | ||
1116 | dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; | |
1117 | dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; | |
1118 | } | |
80c39712 TV |
1119 | } |
1120 | ||
83fa2f2e | 1121 | static u32 dispc_ovl_get_fifo_size(enum omap_plane plane) |
80c39712 | 1122 | { |
42a6961c TV |
1123 | int fifo; |
1124 | u32 size = 0; | |
1125 | ||
1126 | for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) { | |
1127 | if (dispc.fifo_assignment[fifo] == plane) | |
1128 | size += dispc.fifo_size[fifo]; | |
1129 | } | |
1130 | ||
1131 | return size; | |
80c39712 TV |
1132 | } |
1133 | ||
6f04e1bf | 1134 | void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high) |
80c39712 | 1135 | { |
a0acb557 | 1136 | u8 hi_start, hi_end, lo_start, lo_end; |
5ed8cf5b TV |
1137 | u32 unit; |
1138 | ||
1139 | unit = dss_feat_get_buffer_size_unit(); | |
1140 | ||
1141 | WARN_ON(low % unit != 0); | |
1142 | WARN_ON(high % unit != 0); | |
1143 | ||
1144 | low /= unit; | |
1145 | high /= unit; | |
a0acb557 | 1146 | |
9b372c2d AT |
1147 | dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end); |
1148 | dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end); | |
1149 | ||
3cb5d966 | 1150 | DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n", |
80c39712 | 1151 | plane, |
9b372c2d | 1152 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 | 1153 | lo_start, lo_end) * unit, |
9b372c2d | 1154 | REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), |
3cb5d966 TV |
1155 | hi_start, hi_end) * unit, |
1156 | low * unit, high * unit); | |
80c39712 | 1157 | |
9b372c2d | 1158 | dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane), |
a0acb557 AT |
1159 | FLD_VAL(high, hi_start, hi_end) | |
1160 | FLD_VAL(low, lo_start, lo_end)); | |
80c39712 TV |
1161 | } |
1162 | ||
1163 | void dispc_enable_fifomerge(bool enable) | |
1164 | { | |
e6b0f884 TV |
1165 | if (!dss_has_feature(FEAT_FIFO_MERGE)) { |
1166 | WARN_ON(enable); | |
1167 | return; | |
1168 | } | |
1169 | ||
80c39712 TV |
1170 | DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled"); |
1171 | REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14); | |
80c39712 TV |
1172 | } |
1173 | ||
83fa2f2e | 1174 | void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane, |
3568f2a4 TV |
1175 | u32 *fifo_low, u32 *fifo_high, bool use_fifomerge, |
1176 | bool manual_update) | |
83fa2f2e TV |
1177 | { |
1178 | /* | |
1179 | * All sizes are in bytes. Both the buffer and burst are made of | |
1180 | * buffer_units, and the fifo thresholds must be buffer_unit aligned. | |
1181 | */ | |
1182 | ||
1183 | unsigned buf_unit = dss_feat_get_buffer_size_unit(); | |
e0e405b9 TV |
1184 | unsigned ovl_fifo_size, total_fifo_size, burst_size; |
1185 | int i; | |
83fa2f2e TV |
1186 | |
1187 | burst_size = dispc_ovl_get_burst_size(plane); | |
e0e405b9 | 1188 | ovl_fifo_size = dispc_ovl_get_fifo_size(plane); |
83fa2f2e | 1189 | |
e0e405b9 TV |
1190 | if (use_fifomerge) { |
1191 | total_fifo_size = 0; | |
1192 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) | |
1193 | total_fifo_size += dispc_ovl_get_fifo_size(i); | |
1194 | } else { | |
1195 | total_fifo_size = ovl_fifo_size; | |
1196 | } | |
1197 | ||
1198 | /* | |
1199 | * We use the same low threshold for both fifomerge and non-fifomerge | |
1200 | * cases, but for fifomerge we calculate the high threshold using the | |
1201 | * combined fifo size | |
1202 | */ | |
1203 | ||
3568f2a4 | 1204 | if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) { |
e0e405b9 TV |
1205 | *fifo_low = ovl_fifo_size - burst_size * 2; |
1206 | *fifo_high = total_fifo_size - burst_size; | |
1207 | } else { | |
1208 | *fifo_low = ovl_fifo_size - burst_size; | |
1209 | *fifo_high = total_fifo_size - buf_unit; | |
1210 | } | |
83fa2f2e TV |
1211 | } |
1212 | ||
f0e5caab | 1213 | static void dispc_ovl_set_fir(enum omap_plane plane, |
0d66cbb5 AJ |
1214 | int hinc, int vinc, |
1215 | enum omap_color_component color_comp) | |
80c39712 TV |
1216 | { |
1217 | u32 val; | |
80c39712 | 1218 | |
0d66cbb5 AJ |
1219 | if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) { |
1220 | u8 hinc_start, hinc_end, vinc_start, vinc_end; | |
a0acb557 | 1221 | |
0d66cbb5 AJ |
1222 | dss_feat_get_reg_field(FEAT_REG_FIRHINC, |
1223 | &hinc_start, &hinc_end); | |
1224 | dss_feat_get_reg_field(FEAT_REG_FIRVINC, | |
1225 | &vinc_start, &vinc_end); | |
1226 | val = FLD_VAL(vinc, vinc_start, vinc_end) | | |
1227 | FLD_VAL(hinc, hinc_start, hinc_end); | |
a0acb557 | 1228 | |
0d66cbb5 AJ |
1229 | dispc_write_reg(DISPC_OVL_FIR(plane), val); |
1230 | } else { | |
1231 | val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0); | |
1232 | dispc_write_reg(DISPC_OVL_FIR2(plane), val); | |
1233 | } | |
80c39712 TV |
1234 | } |
1235 | ||
f0e5caab | 1236 | static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1237 | { |
1238 | u32 val; | |
87a7484b | 1239 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1240 | |
87a7484b AT |
1241 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1242 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1243 | ||
1244 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1245 | FLD_VAL(haccu, hor_start, hor_end); | |
1246 | ||
9b372c2d | 1247 | dispc_write_reg(DISPC_OVL_ACCU0(plane), val); |
80c39712 TV |
1248 | } |
1249 | ||
f0e5caab | 1250 | static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu) |
80c39712 TV |
1251 | { |
1252 | u32 val; | |
87a7484b | 1253 | u8 hor_start, hor_end, vert_start, vert_end; |
80c39712 | 1254 | |
87a7484b AT |
1255 | dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end); |
1256 | dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end); | |
1257 | ||
1258 | val = FLD_VAL(vaccu, vert_start, vert_end) | | |
1259 | FLD_VAL(haccu, hor_start, hor_end); | |
1260 | ||
9b372c2d | 1261 | dispc_write_reg(DISPC_OVL_ACCU1(plane), val); |
80c39712 TV |
1262 | } |
1263 | ||
f0e5caab TV |
1264 | static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu, |
1265 | int vaccu) | |
ab5ca071 AJ |
1266 | { |
1267 | u32 val; | |
1268 | ||
1269 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1270 | dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val); | |
1271 | } | |
1272 | ||
f0e5caab TV |
1273 | static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu, |
1274 | int vaccu) | |
ab5ca071 AJ |
1275 | { |
1276 | u32 val; | |
1277 | ||
1278 | val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0); | |
1279 | dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val); | |
1280 | } | |
80c39712 | 1281 | |
f0e5caab | 1282 | static void dispc_ovl_set_scale_param(enum omap_plane plane, |
80c39712 TV |
1283 | u16 orig_width, u16 orig_height, |
1284 | u16 out_width, u16 out_height, | |
0d66cbb5 AJ |
1285 | bool five_taps, u8 rotation, |
1286 | enum omap_color_component color_comp) | |
80c39712 | 1287 | { |
0d66cbb5 | 1288 | int fir_hinc, fir_vinc; |
80c39712 | 1289 | |
ed14a3ce AJ |
1290 | fir_hinc = 1024 * orig_width / out_width; |
1291 | fir_vinc = 1024 * orig_height / out_height; | |
80c39712 | 1292 | |
debd9074 CM |
1293 | dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps, |
1294 | color_comp); | |
f0e5caab | 1295 | dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp); |
0d66cbb5 AJ |
1296 | } |
1297 | ||
05dd0f53 CM |
1298 | static void dispc_ovl_set_accu_uv(enum omap_plane plane, |
1299 | u16 orig_width, u16 orig_height, u16 out_width, u16 out_height, | |
1300 | bool ilace, enum omap_color_mode color_mode, u8 rotation) | |
1301 | { | |
1302 | int h_accu2_0, h_accu2_1; | |
1303 | int v_accu2_0, v_accu2_1; | |
1304 | int chroma_hinc, chroma_vinc; | |
1305 | int idx; | |
1306 | ||
1307 | struct accu { | |
1308 | s8 h0_m, h0_n; | |
1309 | s8 h1_m, h1_n; | |
1310 | s8 v0_m, v0_n; | |
1311 | s8 v1_m, v1_n; | |
1312 | }; | |
1313 | ||
1314 | const struct accu *accu_table; | |
1315 | const struct accu *accu_val; | |
1316 | ||
1317 | static const struct accu accu_nv12[4] = { | |
1318 | { 0, 1, 0, 1 , -1, 2, 0, 1 }, | |
1319 | { 1, 2, -3, 4 , 0, 1, 0, 1 }, | |
1320 | { -1, 1, 0, 1 , -1, 2, 0, 1 }, | |
1321 | { -1, 2, -1, 2 , -1, 1, 0, 1 }, | |
1322 | }; | |
1323 | ||
1324 | static const struct accu accu_nv12_ilace[4] = { | |
1325 | { 0, 1, 0, 1 , -3, 4, -1, 4 }, | |
1326 | { -1, 4, -3, 4 , 0, 1, 0, 1 }, | |
1327 | { -1, 1, 0, 1 , -1, 4, -3, 4 }, | |
1328 | { -3, 4, -3, 4 , -1, 1, 0, 1 }, | |
1329 | }; | |
1330 | ||
1331 | static const struct accu accu_yuv[4] = { | |
1332 | { 0, 1, 0, 1, 0, 1, 0, 1 }, | |
1333 | { 0, 1, 0, 1, 0, 1, 0, 1 }, | |
1334 | { -1, 1, 0, 1, 0, 1, 0, 1 }, | |
1335 | { 0, 1, 0, 1, -1, 1, 0, 1 }, | |
1336 | }; | |
1337 | ||
1338 | switch (rotation) { | |
1339 | case OMAP_DSS_ROT_0: | |
1340 | idx = 0; | |
1341 | break; | |
1342 | case OMAP_DSS_ROT_90: | |
1343 | idx = 1; | |
1344 | break; | |
1345 | case OMAP_DSS_ROT_180: | |
1346 | idx = 2; | |
1347 | break; | |
1348 | case OMAP_DSS_ROT_270: | |
1349 | idx = 3; | |
1350 | break; | |
1351 | default: | |
1352 | BUG(); | |
c6eee968 | 1353 | return; |
05dd0f53 CM |
1354 | } |
1355 | ||
1356 | switch (color_mode) { | |
1357 | case OMAP_DSS_COLOR_NV12: | |
1358 | if (ilace) | |
1359 | accu_table = accu_nv12_ilace; | |
1360 | else | |
1361 | accu_table = accu_nv12; | |
1362 | break; | |
1363 | case OMAP_DSS_COLOR_YUV2: | |
1364 | case OMAP_DSS_COLOR_UYVY: | |
1365 | accu_table = accu_yuv; | |
1366 | break; | |
1367 | default: | |
1368 | BUG(); | |
c6eee968 | 1369 | return; |
05dd0f53 CM |
1370 | } |
1371 | ||
1372 | accu_val = &accu_table[idx]; | |
1373 | ||
1374 | chroma_hinc = 1024 * orig_width / out_width; | |
1375 | chroma_vinc = 1024 * orig_height / out_height; | |
1376 | ||
1377 | h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024; | |
1378 | h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024; | |
1379 | v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024; | |
1380 | v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024; | |
1381 | ||
1382 | dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0); | |
1383 | dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1); | |
1384 | } | |
1385 | ||
f0e5caab | 1386 | static void dispc_ovl_set_scaling_common(enum omap_plane plane, |
0d66cbb5 AJ |
1387 | u16 orig_width, u16 orig_height, |
1388 | u16 out_width, u16 out_height, | |
1389 | bool ilace, bool five_taps, | |
1390 | bool fieldmode, enum omap_color_mode color_mode, | |
1391 | u8 rotation) | |
1392 | { | |
1393 | int accu0 = 0; | |
1394 | int accu1 = 0; | |
1395 | u32 l; | |
80c39712 | 1396 | |
f0e5caab | 1397 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1398 | out_width, out_height, five_taps, |
1399 | rotation, DISPC_COLOR_COMPONENT_RGB_Y); | |
9b372c2d | 1400 | l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane)); |
80c39712 | 1401 | |
87a7484b AT |
1402 | /* RESIZEENABLE and VERTICALTAPS */ |
1403 | l &= ~((0x3 << 5) | (0x1 << 21)); | |
ed14a3ce AJ |
1404 | l |= (orig_width != out_width) ? (1 << 5) : 0; |
1405 | l |= (orig_height != out_height) ? (1 << 6) : 0; | |
87a7484b | 1406 | l |= five_taps ? (1 << 21) : 0; |
80c39712 | 1407 | |
87a7484b AT |
1408 | /* VRESIZECONF and HRESIZECONF */ |
1409 | if (dss_has_feature(FEAT_RESIZECONF)) { | |
1410 | l &= ~(0x3 << 7); | |
0d66cbb5 AJ |
1411 | l |= (orig_width <= out_width) ? 0 : (1 << 7); |
1412 | l |= (orig_height <= out_height) ? 0 : (1 << 8); | |
87a7484b | 1413 | } |
80c39712 | 1414 | |
87a7484b AT |
1415 | /* LINEBUFFERSPLIT */ |
1416 | if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) { | |
1417 | l &= ~(0x1 << 22); | |
1418 | l |= five_taps ? (1 << 22) : 0; | |
1419 | } | |
80c39712 | 1420 | |
9b372c2d | 1421 | dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l); |
80c39712 TV |
1422 | |
1423 | /* | |
1424 | * field 0 = even field = bottom field | |
1425 | * field 1 = odd field = top field | |
1426 | */ | |
1427 | if (ilace && !fieldmode) { | |
1428 | accu1 = 0; | |
0d66cbb5 | 1429 | accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff; |
80c39712 TV |
1430 | if (accu0 >= 1024/2) { |
1431 | accu1 = 1024/2; | |
1432 | accu0 -= accu1; | |
1433 | } | |
1434 | } | |
1435 | ||
f0e5caab TV |
1436 | dispc_ovl_set_vid_accu0(plane, 0, accu0); |
1437 | dispc_ovl_set_vid_accu1(plane, 0, accu1); | |
80c39712 TV |
1438 | } |
1439 | ||
f0e5caab | 1440 | static void dispc_ovl_set_scaling_uv(enum omap_plane plane, |
0d66cbb5 AJ |
1441 | u16 orig_width, u16 orig_height, |
1442 | u16 out_width, u16 out_height, | |
1443 | bool ilace, bool five_taps, | |
1444 | bool fieldmode, enum omap_color_mode color_mode, | |
1445 | u8 rotation) | |
1446 | { | |
1447 | int scale_x = out_width != orig_width; | |
1448 | int scale_y = out_height != orig_height; | |
1449 | ||
1450 | if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) | |
1451 | return; | |
1452 | if ((color_mode != OMAP_DSS_COLOR_YUV2 && | |
1453 | color_mode != OMAP_DSS_COLOR_UYVY && | |
1454 | color_mode != OMAP_DSS_COLOR_NV12)) { | |
1455 | /* reset chroma resampling for RGB formats */ | |
1456 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8); | |
1457 | return; | |
1458 | } | |
36377357 TV |
1459 | |
1460 | dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width, | |
1461 | out_height, ilace, color_mode, rotation); | |
1462 | ||
0d66cbb5 AJ |
1463 | switch (color_mode) { |
1464 | case OMAP_DSS_COLOR_NV12: | |
1465 | /* UV is subsampled by 2 vertically*/ | |
1466 | orig_height >>= 1; | |
1467 | /* UV is subsampled by 2 horz.*/ | |
1468 | orig_width >>= 1; | |
1469 | break; | |
1470 | case OMAP_DSS_COLOR_YUV2: | |
1471 | case OMAP_DSS_COLOR_UYVY: | |
1472 | /*For YUV422 with 90/270 rotation, | |
1473 | *we don't upsample chroma | |
1474 | */ | |
1475 | if (rotation == OMAP_DSS_ROT_0 || | |
1476 | rotation == OMAP_DSS_ROT_180) | |
1477 | /* UV is subsampled by 2 hrz*/ | |
1478 | orig_width >>= 1; | |
1479 | /* must use FIR for YUV422 if rotated */ | |
1480 | if (rotation != OMAP_DSS_ROT_0) | |
1481 | scale_x = scale_y = true; | |
1482 | break; | |
1483 | default: | |
1484 | BUG(); | |
c6eee968 | 1485 | return; |
0d66cbb5 AJ |
1486 | } |
1487 | ||
1488 | if (out_width != orig_width) | |
1489 | scale_x = true; | |
1490 | if (out_height != orig_height) | |
1491 | scale_y = true; | |
1492 | ||
f0e5caab | 1493 | dispc_ovl_set_scale_param(plane, orig_width, orig_height, |
0d66cbb5 AJ |
1494 | out_width, out_height, five_taps, |
1495 | rotation, DISPC_COLOR_COMPONENT_UV); | |
1496 | ||
1497 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), | |
1498 | (scale_x || scale_y) ? 1 : 0, 8, 8); | |
1499 | /* set H scaling */ | |
1500 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); | |
1501 | /* set V scaling */ | |
1502 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); | |
0d66cbb5 AJ |
1503 | } |
1504 | ||
f0e5caab | 1505 | static void dispc_ovl_set_scaling(enum omap_plane plane, |
0d66cbb5 AJ |
1506 | u16 orig_width, u16 orig_height, |
1507 | u16 out_width, u16 out_height, | |
1508 | bool ilace, bool five_taps, | |
1509 | bool fieldmode, enum omap_color_mode color_mode, | |
1510 | u8 rotation) | |
1511 | { | |
1512 | BUG_ON(plane == OMAP_DSS_GFX); | |
1513 | ||
f0e5caab | 1514 | dispc_ovl_set_scaling_common(plane, |
0d66cbb5 AJ |
1515 | orig_width, orig_height, |
1516 | out_width, out_height, | |
1517 | ilace, five_taps, | |
1518 | fieldmode, color_mode, | |
1519 | rotation); | |
1520 | ||
f0e5caab | 1521 | dispc_ovl_set_scaling_uv(plane, |
0d66cbb5 AJ |
1522 | orig_width, orig_height, |
1523 | out_width, out_height, | |
1524 | ilace, five_taps, | |
1525 | fieldmode, color_mode, | |
1526 | rotation); | |
1527 | } | |
1528 | ||
f0e5caab | 1529 | static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation, |
80c39712 TV |
1530 | bool mirroring, enum omap_color_mode color_mode) |
1531 | { | |
87a7484b AT |
1532 | bool row_repeat = false; |
1533 | int vidrot = 0; | |
1534 | ||
80c39712 TV |
1535 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1536 | color_mode == OMAP_DSS_COLOR_UYVY) { | |
80c39712 TV |
1537 | |
1538 | if (mirroring) { | |
1539 | switch (rotation) { | |
1540 | case OMAP_DSS_ROT_0: | |
1541 | vidrot = 2; | |
1542 | break; | |
1543 | case OMAP_DSS_ROT_90: | |
1544 | vidrot = 1; | |
1545 | break; | |
1546 | case OMAP_DSS_ROT_180: | |
1547 | vidrot = 0; | |
1548 | break; | |
1549 | case OMAP_DSS_ROT_270: | |
1550 | vidrot = 3; | |
1551 | break; | |
1552 | } | |
1553 | } else { | |
1554 | switch (rotation) { | |
1555 | case OMAP_DSS_ROT_0: | |
1556 | vidrot = 0; | |
1557 | break; | |
1558 | case OMAP_DSS_ROT_90: | |
1559 | vidrot = 1; | |
1560 | break; | |
1561 | case OMAP_DSS_ROT_180: | |
1562 | vidrot = 2; | |
1563 | break; | |
1564 | case OMAP_DSS_ROT_270: | |
1565 | vidrot = 3; | |
1566 | break; | |
1567 | } | |
1568 | } | |
1569 | ||
80c39712 | 1570 | if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270) |
87a7484b | 1571 | row_repeat = true; |
80c39712 | 1572 | else |
87a7484b | 1573 | row_repeat = false; |
80c39712 | 1574 | } |
87a7484b | 1575 | |
9b372c2d | 1576 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); |
87a7484b | 1577 | if (dss_has_feature(FEAT_ROWREPEATENABLE)) |
9b372c2d AT |
1578 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), |
1579 | row_repeat ? 1 : 0, 18, 18); | |
80c39712 TV |
1580 | } |
1581 | ||
1582 | static int color_mode_to_bpp(enum omap_color_mode color_mode) | |
1583 | { | |
1584 | switch (color_mode) { | |
1585 | case OMAP_DSS_COLOR_CLUT1: | |
1586 | return 1; | |
1587 | case OMAP_DSS_COLOR_CLUT2: | |
1588 | return 2; | |
1589 | case OMAP_DSS_COLOR_CLUT4: | |
1590 | return 4; | |
1591 | case OMAP_DSS_COLOR_CLUT8: | |
f20e4220 | 1592 | case OMAP_DSS_COLOR_NV12: |
80c39712 TV |
1593 | return 8; |
1594 | case OMAP_DSS_COLOR_RGB12U: | |
1595 | case OMAP_DSS_COLOR_RGB16: | |
1596 | case OMAP_DSS_COLOR_ARGB16: | |
1597 | case OMAP_DSS_COLOR_YUV2: | |
1598 | case OMAP_DSS_COLOR_UYVY: | |
f20e4220 AJ |
1599 | case OMAP_DSS_COLOR_RGBA16: |
1600 | case OMAP_DSS_COLOR_RGBX16: | |
1601 | case OMAP_DSS_COLOR_ARGB16_1555: | |
1602 | case OMAP_DSS_COLOR_XRGB16_1555: | |
80c39712 TV |
1603 | return 16; |
1604 | case OMAP_DSS_COLOR_RGB24P: | |
1605 | return 24; | |
1606 | case OMAP_DSS_COLOR_RGB24U: | |
1607 | case OMAP_DSS_COLOR_ARGB32: | |
1608 | case OMAP_DSS_COLOR_RGBA32: | |
1609 | case OMAP_DSS_COLOR_RGBX32: | |
1610 | return 32; | |
1611 | default: | |
1612 | BUG(); | |
c6eee968 | 1613 | return 0; |
80c39712 TV |
1614 | } |
1615 | } | |
1616 | ||
1617 | static s32 pixinc(int pixels, u8 ps) | |
1618 | { | |
1619 | if (pixels == 1) | |
1620 | return 1; | |
1621 | else if (pixels > 1) | |
1622 | return 1 + (pixels - 1) * ps; | |
1623 | else if (pixels < 0) | |
1624 | return 1 - (-pixels + 1) * ps; | |
1625 | else | |
1626 | BUG(); | |
c6eee968 | 1627 | return 0; |
80c39712 TV |
1628 | } |
1629 | ||
1630 | static void calc_vrfb_rotation_offset(u8 rotation, bool mirror, | |
1631 | u16 screen_width, | |
1632 | u16 width, u16 height, | |
1633 | enum omap_color_mode color_mode, bool fieldmode, | |
1634 | unsigned int field_offset, | |
1635 | unsigned *offset0, unsigned *offset1, | |
aed74b55 | 1636 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) |
80c39712 TV |
1637 | { |
1638 | u8 ps; | |
1639 | ||
1640 | /* FIXME CLUT formats */ | |
1641 | switch (color_mode) { | |
1642 | case OMAP_DSS_COLOR_CLUT1: | |
1643 | case OMAP_DSS_COLOR_CLUT2: | |
1644 | case OMAP_DSS_COLOR_CLUT4: | |
1645 | case OMAP_DSS_COLOR_CLUT8: | |
1646 | BUG(); | |
1647 | return; | |
1648 | case OMAP_DSS_COLOR_YUV2: | |
1649 | case OMAP_DSS_COLOR_UYVY: | |
1650 | ps = 4; | |
1651 | break; | |
1652 | default: | |
1653 | ps = color_mode_to_bpp(color_mode) / 8; | |
1654 | break; | |
1655 | } | |
1656 | ||
1657 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1658 | width, height); | |
1659 | ||
1660 | /* | |
1661 | * field 0 = even field = bottom field | |
1662 | * field 1 = odd field = top field | |
1663 | */ | |
1664 | switch (rotation + mirror * 4) { | |
1665 | case OMAP_DSS_ROT_0: | |
1666 | case OMAP_DSS_ROT_180: | |
1667 | /* | |
1668 | * If the pixel format is YUV or UYVY divide the width | |
1669 | * of the image by 2 for 0 and 180 degree rotation. | |
1670 | */ | |
1671 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1672 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1673 | width = width >> 1; | |
1674 | case OMAP_DSS_ROT_90: | |
1675 | case OMAP_DSS_ROT_270: | |
1676 | *offset1 = 0; | |
1677 | if (field_offset) | |
1678 | *offset0 = field_offset * screen_width * ps; | |
1679 | else | |
1680 | *offset0 = 0; | |
1681 | ||
aed74b55 CM |
1682 | *row_inc = pixinc(1 + |
1683 | (y_predecim * screen_width - x_predecim * width) + | |
1684 | (fieldmode ? screen_width : 0), ps); | |
1685 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1686 | break; |
1687 | ||
1688 | case OMAP_DSS_ROT_0 + 4: | |
1689 | case OMAP_DSS_ROT_180 + 4: | |
1690 | /* If the pixel format is YUV or UYVY divide the width | |
1691 | * of the image by 2 for 0 degree and 180 degree | |
1692 | */ | |
1693 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1694 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1695 | width = width >> 1; | |
1696 | case OMAP_DSS_ROT_90 + 4: | |
1697 | case OMAP_DSS_ROT_270 + 4: | |
1698 | *offset1 = 0; | |
1699 | if (field_offset) | |
1700 | *offset0 = field_offset * screen_width * ps; | |
1701 | else | |
1702 | *offset0 = 0; | |
aed74b55 CM |
1703 | *row_inc = pixinc(1 - |
1704 | (y_predecim * screen_width + x_predecim * width) - | |
1705 | (fieldmode ? screen_width : 0), ps); | |
1706 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1707 | break; |
1708 | ||
1709 | default: | |
1710 | BUG(); | |
c6eee968 | 1711 | return; |
80c39712 TV |
1712 | } |
1713 | } | |
1714 | ||
1715 | static void calc_dma_rotation_offset(u8 rotation, bool mirror, | |
1716 | u16 screen_width, | |
1717 | u16 width, u16 height, | |
1718 | enum omap_color_mode color_mode, bool fieldmode, | |
1719 | unsigned int field_offset, | |
1720 | unsigned *offset0, unsigned *offset1, | |
aed74b55 | 1721 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) |
80c39712 TV |
1722 | { |
1723 | u8 ps; | |
1724 | u16 fbw, fbh; | |
1725 | ||
1726 | /* FIXME CLUT formats */ | |
1727 | switch (color_mode) { | |
1728 | case OMAP_DSS_COLOR_CLUT1: | |
1729 | case OMAP_DSS_COLOR_CLUT2: | |
1730 | case OMAP_DSS_COLOR_CLUT4: | |
1731 | case OMAP_DSS_COLOR_CLUT8: | |
1732 | BUG(); | |
1733 | return; | |
1734 | default: | |
1735 | ps = color_mode_to_bpp(color_mode) / 8; | |
1736 | break; | |
1737 | } | |
1738 | ||
1739 | DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width, | |
1740 | width, height); | |
1741 | ||
1742 | /* width & height are overlay sizes, convert to fb sizes */ | |
1743 | ||
1744 | if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) { | |
1745 | fbw = width; | |
1746 | fbh = height; | |
1747 | } else { | |
1748 | fbw = height; | |
1749 | fbh = width; | |
1750 | } | |
1751 | ||
1752 | /* | |
1753 | * field 0 = even field = bottom field | |
1754 | * field 1 = odd field = top field | |
1755 | */ | |
1756 | switch (rotation + mirror * 4) { | |
1757 | case OMAP_DSS_ROT_0: | |
1758 | *offset1 = 0; | |
1759 | if (field_offset) | |
1760 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1761 | else | |
1762 | *offset0 = *offset1; | |
aed74b55 CM |
1763 | *row_inc = pixinc(1 + |
1764 | (y_predecim * screen_width - fbw * x_predecim) + | |
1765 | (fieldmode ? screen_width : 0), ps); | |
1766 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1767 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1768 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
1769 | else | |
1770 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1771 | break; |
1772 | case OMAP_DSS_ROT_90: | |
1773 | *offset1 = screen_width * (fbh - 1) * ps; | |
1774 | if (field_offset) | |
1775 | *offset0 = *offset1 + field_offset * ps; | |
1776 | else | |
1777 | *offset0 = *offset1; | |
aed74b55 CM |
1778 | *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) + |
1779 | y_predecim + (fieldmode ? 1 : 0), ps); | |
1780 | *pix_inc = pixinc(-x_predecim * screen_width, ps); | |
80c39712 TV |
1781 | break; |
1782 | case OMAP_DSS_ROT_180: | |
1783 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
1784 | if (field_offset) | |
1785 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
1786 | else | |
1787 | *offset0 = *offset1; | |
1788 | *row_inc = pixinc(-1 - | |
aed74b55 CM |
1789 | (y_predecim * screen_width - fbw * x_predecim) - |
1790 | (fieldmode ? screen_width : 0), ps); | |
1791 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1792 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1793 | *pix_inc = pixinc(-x_predecim, 2 * ps); | |
1794 | else | |
1795 | *pix_inc = pixinc(-x_predecim, ps); | |
80c39712 TV |
1796 | break; |
1797 | case OMAP_DSS_ROT_270: | |
1798 | *offset1 = (fbw - 1) * ps; | |
1799 | if (field_offset) | |
1800 | *offset0 = *offset1 - field_offset * ps; | |
1801 | else | |
1802 | *offset0 = *offset1; | |
aed74b55 CM |
1803 | *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) - |
1804 | y_predecim - (fieldmode ? 1 : 0), ps); | |
1805 | *pix_inc = pixinc(x_predecim * screen_width, ps); | |
80c39712 TV |
1806 | break; |
1807 | ||
1808 | /* mirroring */ | |
1809 | case OMAP_DSS_ROT_0 + 4: | |
1810 | *offset1 = (fbw - 1) * ps; | |
1811 | if (field_offset) | |
1812 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1813 | else | |
1814 | *offset0 = *offset1; | |
aed74b55 | 1815 | *row_inc = pixinc(y_predecim * screen_width * 2 - 1 + |
80c39712 TV |
1816 | (fieldmode ? screen_width : 0), |
1817 | ps); | |
aed74b55 CM |
1818 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1819 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1820 | *pix_inc = pixinc(-x_predecim, 2 * ps); | |
1821 | else | |
1822 | *pix_inc = pixinc(-x_predecim, ps); | |
80c39712 TV |
1823 | break; |
1824 | ||
1825 | case OMAP_DSS_ROT_90 + 4: | |
1826 | *offset1 = 0; | |
1827 | if (field_offset) | |
1828 | *offset0 = *offset1 + field_offset * ps; | |
1829 | else | |
1830 | *offset0 = *offset1; | |
aed74b55 CM |
1831 | *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) + |
1832 | y_predecim + (fieldmode ? 1 : 0), | |
80c39712 | 1833 | ps); |
aed74b55 | 1834 | *pix_inc = pixinc(x_predecim * screen_width, ps); |
80c39712 TV |
1835 | break; |
1836 | ||
1837 | case OMAP_DSS_ROT_180 + 4: | |
1838 | *offset1 = screen_width * (fbh - 1) * ps; | |
1839 | if (field_offset) | |
1840 | *offset0 = *offset1 - field_offset * screen_width * ps; | |
1841 | else | |
1842 | *offset0 = *offset1; | |
aed74b55 | 1843 | *row_inc = pixinc(1 - y_predecim * screen_width * 2 - |
80c39712 TV |
1844 | (fieldmode ? screen_width : 0), |
1845 | ps); | |
aed74b55 CM |
1846 | if (color_mode == OMAP_DSS_COLOR_YUV2 || |
1847 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1848 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
1849 | else | |
1850 | *pix_inc = pixinc(x_predecim, ps); | |
80c39712 TV |
1851 | break; |
1852 | ||
1853 | case OMAP_DSS_ROT_270 + 4: | |
1854 | *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps; | |
1855 | if (field_offset) | |
1856 | *offset0 = *offset1 - field_offset * ps; | |
1857 | else | |
1858 | *offset0 = *offset1; | |
aed74b55 CM |
1859 | *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) - |
1860 | y_predecim - (fieldmode ? 1 : 0), | |
80c39712 | 1861 | ps); |
aed74b55 | 1862 | *pix_inc = pixinc(-x_predecim * screen_width, ps); |
80c39712 TV |
1863 | break; |
1864 | ||
1865 | default: | |
1866 | BUG(); | |
c6eee968 | 1867 | return; |
80c39712 TV |
1868 | } |
1869 | } | |
1870 | ||
65e006ff CM |
1871 | static void calc_tiler_rotation_offset(u16 screen_width, u16 width, |
1872 | enum omap_color_mode color_mode, bool fieldmode, | |
1873 | unsigned int field_offset, unsigned *offset0, unsigned *offset1, | |
1874 | s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim) | |
1875 | { | |
1876 | u8 ps; | |
1877 | ||
1878 | switch (color_mode) { | |
1879 | case OMAP_DSS_COLOR_CLUT1: | |
1880 | case OMAP_DSS_COLOR_CLUT2: | |
1881 | case OMAP_DSS_COLOR_CLUT4: | |
1882 | case OMAP_DSS_COLOR_CLUT8: | |
1883 | BUG(); | |
1884 | return; | |
1885 | default: | |
1886 | ps = color_mode_to_bpp(color_mode) / 8; | |
1887 | break; | |
1888 | } | |
1889 | ||
1890 | DSSDBG("scrw %d, width %d\n", screen_width, width); | |
1891 | ||
1892 | /* | |
1893 | * field 0 = even field = bottom field | |
1894 | * field 1 = odd field = top field | |
1895 | */ | |
1896 | *offset1 = 0; | |
1897 | if (field_offset) | |
1898 | *offset0 = *offset1 + field_offset * screen_width * ps; | |
1899 | else | |
1900 | *offset0 = *offset1; | |
1901 | *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) + | |
1902 | (fieldmode ? screen_width : 0), ps); | |
1903 | if (color_mode == OMAP_DSS_COLOR_YUV2 || | |
1904 | color_mode == OMAP_DSS_COLOR_UYVY) | |
1905 | *pix_inc = pixinc(x_predecim, 2 * ps); | |
1906 | else | |
1907 | *pix_inc = pixinc(x_predecim, ps); | |
1908 | } | |
1909 | ||
7faa9233 CM |
1910 | /* |
1911 | * This function is used to avoid synclosts in OMAP3, because of some | |
1912 | * undocumented horizontal position and timing related limitations. | |
1913 | */ | |
81ab95b7 AT |
1914 | static int check_horiz_timing_omap3(enum omap_channel channel, |
1915 | const struct omap_video_timings *t, u16 pos_x, | |
7faa9233 CM |
1916 | u16 width, u16 height, u16 out_width, u16 out_height) |
1917 | { | |
1918 | int DS = DIV_ROUND_UP(height, out_height); | |
7faa9233 CM |
1919 | unsigned long nonactive, lclk, pclk; |
1920 | static const u8 limits[3] = { 8, 10, 20 }; | |
1921 | u64 val, blank; | |
1922 | int i; | |
1923 | ||
81ab95b7 | 1924 | nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width; |
7faa9233 | 1925 | pclk = dispc_mgr_pclk_rate(channel); |
dd88b7a6 | 1926 | if (dss_mgr_is_lcd(channel)) |
7faa9233 CM |
1927 | lclk = dispc_mgr_lclk_rate(channel); |
1928 | else | |
1929 | lclk = dispc_fclk_rate(); | |
1930 | ||
1931 | i = 0; | |
1932 | if (out_height < height) | |
1933 | i++; | |
1934 | if (out_width < width) | |
1935 | i++; | |
81ab95b7 | 1936 | blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk); |
7faa9233 CM |
1937 | DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]); |
1938 | if (blank <= limits[i]) | |
1939 | return -EINVAL; | |
1940 | ||
1941 | /* | |
1942 | * Pixel data should be prepared before visible display point starts. | |
1943 | * So, atleast DS-2 lines must have already been fetched by DISPC | |
1944 | * during nonactive - pos_x period. | |
1945 | */ | |
1946 | val = div_u64((u64)(nonactive - pos_x) * lclk, pclk); | |
1947 | DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n", | |
1948 | val, max(0, DS - 2) * width); | |
1949 | if (val < max(0, DS - 2) * width) | |
1950 | return -EINVAL; | |
1951 | ||
1952 | /* | |
1953 | * All lines need to be refilled during the nonactive period of which | |
1954 | * only one line can be loaded during the active period. So, atleast | |
1955 | * DS - 1 lines should be loaded during nonactive period. | |
1956 | */ | |
1957 | val = div_u64((u64)nonactive * lclk, pclk); | |
1958 | DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n", | |
1959 | val, max(0, DS - 1) * width); | |
1960 | if (val < max(0, DS - 1) * width) | |
1961 | return -EINVAL; | |
1962 | ||
1963 | return 0; | |
1964 | } | |
1965 | ||
8b53d991 | 1966 | static unsigned long calc_core_clk_five_taps(enum omap_channel channel, |
81ab95b7 AT |
1967 | const struct omap_video_timings *mgr_timings, u16 width, |
1968 | u16 height, u16 out_width, u16 out_height, | |
ff1b2cde | 1969 | enum omap_color_mode color_mode) |
80c39712 | 1970 | { |
8b53d991 | 1971 | u32 core_clk = 0; |
26d9dd0d | 1972 | u64 tmp, pclk = dispc_mgr_pclk_rate(channel); |
80c39712 | 1973 | |
7282f1b7 CM |
1974 | if (height <= out_height && width <= out_width) |
1975 | return (unsigned long) pclk; | |
1976 | ||
80c39712 | 1977 | if (height > out_height) { |
81ab95b7 | 1978 | unsigned int ppl = mgr_timings->x_res; |
80c39712 TV |
1979 | |
1980 | tmp = pclk * height * out_width; | |
1981 | do_div(tmp, 2 * out_height * ppl); | |
8b53d991 | 1982 | core_clk = tmp; |
80c39712 | 1983 | |
2d9c5597 VS |
1984 | if (height > 2 * out_height) { |
1985 | if (ppl == out_width) | |
1986 | return 0; | |
1987 | ||
80c39712 TV |
1988 | tmp = pclk * (height - 2 * out_height) * out_width; |
1989 | do_div(tmp, 2 * out_height * (ppl - out_width)); | |
8b53d991 | 1990 | core_clk = max_t(u32, core_clk, tmp); |
80c39712 TV |
1991 | } |
1992 | } | |
1993 | ||
1994 | if (width > out_width) { | |
1995 | tmp = pclk * width; | |
1996 | do_div(tmp, out_width); | |
8b53d991 | 1997 | core_clk = max_t(u32, core_clk, tmp); |
80c39712 TV |
1998 | |
1999 | if (color_mode == OMAP_DSS_COLOR_RGB24U) | |
8b53d991 | 2000 | core_clk <<= 1; |
80c39712 TV |
2001 | } |
2002 | ||
8b53d991 | 2003 | return core_clk; |
80c39712 TV |
2004 | } |
2005 | ||
dcbe765b CM |
2006 | static unsigned long calc_core_clk_24xx(enum omap_channel channel, u16 width, |
2007 | u16 height, u16 out_width, u16 out_height) | |
2008 | { | |
2009 | unsigned long pclk = dispc_mgr_pclk_rate(channel); | |
2010 | ||
2011 | if (height > out_height && width > out_width) | |
2012 | return pclk * 4; | |
2013 | else | |
2014 | return pclk * 2; | |
2015 | } | |
2016 | ||
2017 | static unsigned long calc_core_clk_34xx(enum omap_channel channel, u16 width, | |
ff1b2cde | 2018 | u16 height, u16 out_width, u16 out_height) |
80c39712 TV |
2019 | { |
2020 | unsigned int hf, vf; | |
79ee89cd | 2021 | unsigned long pclk = dispc_mgr_pclk_rate(channel); |
80c39712 TV |
2022 | |
2023 | /* | |
2024 | * FIXME how to determine the 'A' factor | |
2025 | * for the no downscaling case ? | |
2026 | */ | |
2027 | ||
2028 | if (width > 3 * out_width) | |
2029 | hf = 4; | |
2030 | else if (width > 2 * out_width) | |
2031 | hf = 3; | |
2032 | else if (width > out_width) | |
2033 | hf = 2; | |
2034 | else | |
2035 | hf = 1; | |
80c39712 TV |
2036 | if (height > out_height) |
2037 | vf = 2; | |
2038 | else | |
2039 | vf = 1; | |
2040 | ||
dcbe765b CM |
2041 | return pclk * vf * hf; |
2042 | } | |
2043 | ||
2044 | static unsigned long calc_core_clk_44xx(enum omap_channel channel, u16 width, | |
2045 | u16 height, u16 out_width, u16 out_height) | |
2046 | { | |
2047 | unsigned long pclk = dispc_mgr_pclk_rate(channel); | |
2048 | ||
2049 | if (width > out_width) | |
2050 | return DIV_ROUND_UP(pclk, out_width) * width; | |
2051 | else | |
2052 | return pclk; | |
2053 | } | |
2054 | ||
2055 | static int dispc_ovl_calc_scaling_24xx(enum omap_channel channel, | |
2056 | const struct omap_video_timings *mgr_timings, | |
2057 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2058 | enum omap_color_mode color_mode, bool *five_taps, | |
2059 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
2060 | u16 pos_x, unsigned long *core_clk) | |
2061 | { | |
2062 | int error; | |
2063 | u16 in_width, in_height; | |
2064 | int min_factor = min(*decim_x, *decim_y); | |
2065 | const int maxsinglelinewidth = | |
2066 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
2067 | *five_taps = false; | |
2068 | ||
2069 | do { | |
2070 | in_height = DIV_ROUND_UP(height, *decim_y); | |
2071 | in_width = DIV_ROUND_UP(width, *decim_x); | |
2072 | *core_clk = dispc.feat->calc_core_clk(channel, in_width, | |
2073 | in_height, out_width, out_height); | |
2074 | error = (in_width > maxsinglelinewidth || !*core_clk || | |
2075 | *core_clk > dispc_core_clk_rate()); | |
2076 | if (error) { | |
2077 | if (*decim_x == *decim_y) { | |
2078 | *decim_x = min_factor; | |
2079 | ++*decim_y; | |
2080 | } else { | |
2081 | swap(*decim_x, *decim_y); | |
2082 | if (*decim_x < *decim_y) | |
2083 | ++*decim_x; | |
2084 | } | |
2085 | } | |
2086 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | |
2087 | ||
2088 | if (in_width > maxsinglelinewidth) { | |
2089 | DSSERR("Cannot scale max input width exceeded"); | |
2090 | return -EINVAL; | |
2091 | } | |
2092 | return 0; | |
2093 | } | |
2094 | ||
2095 | static int dispc_ovl_calc_scaling_34xx(enum omap_channel channel, | |
2096 | const struct omap_video_timings *mgr_timings, | |
2097 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2098 | enum omap_color_mode color_mode, bool *five_taps, | |
2099 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
2100 | u16 pos_x, unsigned long *core_clk) | |
2101 | { | |
2102 | int error; | |
2103 | u16 in_width, in_height; | |
2104 | int min_factor = min(*decim_x, *decim_y); | |
2105 | const int maxsinglelinewidth = | |
2106 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
2107 | ||
2108 | do { | |
2109 | in_height = DIV_ROUND_UP(height, *decim_y); | |
2110 | in_width = DIV_ROUND_UP(width, *decim_x); | |
2111 | *core_clk = calc_core_clk_five_taps(channel, mgr_timings, | |
2112 | in_width, in_height, out_width, out_height, color_mode); | |
2113 | ||
2114 | error = check_horiz_timing_omap3(channel, mgr_timings, pos_x, | |
2115 | in_width, in_height, out_width, out_height); | |
2116 | ||
2117 | if (in_width > maxsinglelinewidth) | |
2118 | if (in_height > out_height && | |
2119 | in_height < out_height * 2) | |
2120 | *five_taps = false; | |
2121 | if (!*five_taps) | |
2122 | *core_clk = dispc.feat->calc_core_clk(channel, in_width, | |
2123 | in_height, out_width, out_height); | |
2124 | ||
2125 | error = (error || in_width > maxsinglelinewidth * 2 || | |
2126 | (in_width > maxsinglelinewidth && *five_taps) || | |
2127 | !*core_clk || *core_clk > dispc_core_clk_rate()); | |
2128 | if (error) { | |
2129 | if (*decim_x == *decim_y) { | |
2130 | *decim_x = min_factor; | |
2131 | ++*decim_y; | |
2132 | } else { | |
2133 | swap(*decim_x, *decim_y); | |
2134 | if (*decim_x < *decim_y) | |
2135 | ++*decim_x; | |
2136 | } | |
2137 | } | |
2138 | } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error); | |
2139 | ||
2140 | if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width, height, | |
2141 | out_width, out_height)){ | |
2142 | DSSERR("horizontal timing too tight\n"); | |
2143 | return -EINVAL; | |
7282f1b7 | 2144 | } |
dcbe765b CM |
2145 | |
2146 | if (in_width > (maxsinglelinewidth * 2)) { | |
2147 | DSSERR("Cannot setup scaling"); | |
2148 | DSSERR("width exceeds maximum width possible"); | |
2149 | return -EINVAL; | |
2150 | } | |
2151 | ||
2152 | if (in_width > maxsinglelinewidth && *five_taps) { | |
2153 | DSSERR("cannot setup scaling with five taps"); | |
2154 | return -EINVAL; | |
2155 | } | |
2156 | return 0; | |
2157 | } | |
2158 | ||
2159 | static int dispc_ovl_calc_scaling_44xx(enum omap_channel channel, | |
2160 | const struct omap_video_timings *mgr_timings, | |
2161 | u16 width, u16 height, u16 out_width, u16 out_height, | |
2162 | enum omap_color_mode color_mode, bool *five_taps, | |
2163 | int *x_predecim, int *y_predecim, int *decim_x, int *decim_y, | |
2164 | u16 pos_x, unsigned long *core_clk) | |
2165 | { | |
2166 | u16 in_width, in_width_max; | |
2167 | int decim_x_min = *decim_x; | |
2168 | u16 in_height = DIV_ROUND_UP(height, *decim_y); | |
2169 | const int maxsinglelinewidth = | |
2170 | dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH); | |
2171 | ||
2172 | in_width_max = dispc_core_clk_rate() / | |
2173 | DIV_ROUND_UP(dispc_mgr_pclk_rate(channel), out_width); | |
2174 | *decim_x = DIV_ROUND_UP(width, in_width_max); | |
2175 | ||
2176 | *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min; | |
2177 | if (*decim_x > *x_predecim) | |
2178 | return -EINVAL; | |
2179 | ||
2180 | do { | |
2181 | in_width = DIV_ROUND_UP(width, *decim_x); | |
2182 | } while (*decim_x <= *x_predecim && | |
2183 | in_width > maxsinglelinewidth && ++*decim_x); | |
2184 | ||
2185 | if (in_width > maxsinglelinewidth) { | |
2186 | DSSERR("Cannot scale width exceeds max line width"); | |
2187 | return -EINVAL; | |
2188 | } | |
2189 | ||
2190 | *core_clk = dispc.feat->calc_core_clk(channel, in_width, in_height, | |
2191 | out_width, out_height); | |
2192 | return 0; | |
80c39712 TV |
2193 | } |
2194 | ||
79ad75f2 | 2195 | static int dispc_ovl_calc_scaling(enum omap_plane plane, |
81ab95b7 AT |
2196 | enum omap_channel channel, |
2197 | const struct omap_video_timings *mgr_timings, | |
2198 | u16 width, u16 height, u16 out_width, u16 out_height, | |
aed74b55 | 2199 | enum omap_color_mode color_mode, bool *five_taps, |
d557a9cf CM |
2200 | int *x_predecim, int *y_predecim, u16 pos_x, |
2201 | enum omap_dss_rotation_type rotation_type) | |
79ad75f2 AT |
2202 | { |
2203 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); | |
0373cac6 | 2204 | const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE); |
aed74b55 | 2205 | const int max_decim_limit = 16; |
8b53d991 | 2206 | unsigned long core_clk = 0; |
dcbe765b | 2207 | int decim_x, decim_y, ret; |
79ad75f2 | 2208 | |
f95cb5eb TV |
2209 | if (width == out_width && height == out_height) |
2210 | return 0; | |
2211 | ||
2212 | if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) | |
2213 | return -EINVAL; | |
79ad75f2 | 2214 | |
aed74b55 | 2215 | *x_predecim = max_decim_limit; |
d557a9cf CM |
2216 | *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER && |
2217 | dss_has_feature(FEAT_BURST_2D)) ? 2 : max_decim_limit; | |
aed74b55 CM |
2218 | |
2219 | if (color_mode == OMAP_DSS_COLOR_CLUT1 || | |
2220 | color_mode == OMAP_DSS_COLOR_CLUT2 || | |
2221 | color_mode == OMAP_DSS_COLOR_CLUT4 || | |
2222 | color_mode == OMAP_DSS_COLOR_CLUT8) { | |
2223 | *x_predecim = 1; | |
2224 | *y_predecim = 1; | |
2225 | *five_taps = false; | |
2226 | return 0; | |
2227 | } | |
2228 | ||
2229 | decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale); | |
2230 | decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale); | |
2231 | ||
aed74b55 | 2232 | if (decim_x > *x_predecim || out_width > width * 8) |
79ad75f2 AT |
2233 | return -EINVAL; |
2234 | ||
aed74b55 | 2235 | if (decim_y > *y_predecim || out_height > height * 8) |
79ad75f2 AT |
2236 | return -EINVAL; |
2237 | ||
dcbe765b CM |
2238 | ret = dispc.feat->calc_scaling(channel, mgr_timings, width, height, |
2239 | out_width, out_height, color_mode, five_taps, x_predecim, | |
2240 | y_predecim, &decim_x, &decim_y, pos_x, &core_clk); | |
2241 | if (ret) | |
2242 | return ret; | |
79ad75f2 | 2243 | |
8b53d991 CM |
2244 | DSSDBG("required core clk rate = %lu Hz\n", core_clk); |
2245 | DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate()); | |
79ad75f2 | 2246 | |
8b53d991 | 2247 | if (!core_clk || core_clk > dispc_core_clk_rate()) { |
79ad75f2 | 2248 | DSSERR("failed to set up scaling, " |
8b53d991 CM |
2249 | "required core clk rate = %lu Hz, " |
2250 | "current core clk rate = %lu Hz\n", | |
2251 | core_clk, dispc_core_clk_rate()); | |
79ad75f2 AT |
2252 | return -EINVAL; |
2253 | } | |
2254 | ||
aed74b55 CM |
2255 | *x_predecim = decim_x; |
2256 | *y_predecim = decim_y; | |
79ad75f2 AT |
2257 | return 0; |
2258 | } | |
2259 | ||
8eeb7019 | 2260 | int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi, |
8050cbe4 | 2261 | bool replication, const struct omap_video_timings *mgr_timings) |
80c39712 | 2262 | { |
79ad75f2 | 2263 | struct omap_overlay *ovl = omap_dss_get_overlay(plane); |
7282f1b7 | 2264 | bool five_taps = true; |
80c39712 | 2265 | bool fieldmode = 0; |
79ad75f2 | 2266 | int r, cconv = 0; |
80c39712 TV |
2267 | unsigned offset0, offset1; |
2268 | s32 row_inc; | |
2269 | s32 pix_inc; | |
a4273b7c | 2270 | u16 frame_height = oi->height; |
80c39712 | 2271 | unsigned int field_offset = 0; |
aed74b55 CM |
2272 | u16 in_height = oi->height; |
2273 | u16 in_width = oi->width; | |
2274 | u16 out_width, out_height; | |
2cc5d1af | 2275 | enum omap_channel channel; |
aed74b55 | 2276 | int x_predecim = 1, y_predecim = 1; |
8050cbe4 | 2277 | bool ilace = mgr_timings->interlace; |
8eeb7019 | 2278 | u16 pos_y = oi->pos_y; |
2cc5d1af TV |
2279 | |
2280 | channel = dispc_ovl_get_channel_out(plane); | |
80c39712 | 2281 | |
a4273b7c | 2282 | DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> " |
f38545da TV |
2283 | "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n", |
2284 | plane, oi->paddr, oi->p_uv_addr, | |
c3d92529 AT |
2285 | oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height, |
2286 | oi->out_width, oi->out_height, oi->color_mode, oi->rotation, | |
f38545da | 2287 | oi->mirror, ilace, channel, replication); |
e6d80f95 | 2288 | |
a4273b7c | 2289 | if (oi->paddr == 0) |
80c39712 TV |
2290 | return -EINVAL; |
2291 | ||
aed74b55 CM |
2292 | out_width = oi->out_width == 0 ? oi->width : oi->out_width; |
2293 | out_height = oi->out_height == 0 ? oi->height : oi->out_height; | |
cf073668 | 2294 | |
aed74b55 | 2295 | if (ilace && oi->height == out_height) |
80c39712 TV |
2296 | fieldmode = 1; |
2297 | ||
2298 | if (ilace) { | |
2299 | if (fieldmode) | |
aed74b55 | 2300 | in_height /= 2; |
8eeb7019 | 2301 | pos_y /= 2; |
aed74b55 | 2302 | out_height /= 2; |
80c39712 TV |
2303 | |
2304 | DSSDBG("adjusting for ilace: height %d, pos_y %d, " | |
2305 | "out_height %d\n", | |
8eeb7019 | 2306 | in_height, pos_y, out_height); |
80c39712 TV |
2307 | } |
2308 | ||
a4273b7c | 2309 | if (!dss_feat_color_mode_supported(plane, oi->color_mode)) |
8dad2ab6 AT |
2310 | return -EINVAL; |
2311 | ||
81ab95b7 AT |
2312 | r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width, |
2313 | in_height, out_width, out_height, oi->color_mode, | |
d557a9cf CM |
2314 | &five_taps, &x_predecim, &y_predecim, oi->pos_x, |
2315 | oi->rotation_type); | |
79ad75f2 AT |
2316 | if (r) |
2317 | return r; | |
80c39712 | 2318 | |
aed74b55 CM |
2319 | in_width = DIV_ROUND_UP(in_width, x_predecim); |
2320 | in_height = DIV_ROUND_UP(in_height, y_predecim); | |
2321 | ||
79ad75f2 AT |
2322 | if (oi->color_mode == OMAP_DSS_COLOR_YUV2 || |
2323 | oi->color_mode == OMAP_DSS_COLOR_UYVY || | |
2324 | oi->color_mode == OMAP_DSS_COLOR_NV12) | |
2325 | cconv = 1; | |
80c39712 TV |
2326 | |
2327 | if (ilace && !fieldmode) { | |
2328 | /* | |
2329 | * when downscaling the bottom field may have to start several | |
2330 | * source lines below the top field. Unfortunately ACCUI | |
2331 | * registers will only hold the fractional part of the offset | |
2332 | * so the integer part must be added to the base address of the | |
2333 | * bottom field. | |
2334 | */ | |
aed74b55 | 2335 | if (!in_height || in_height == out_height) |
80c39712 TV |
2336 | field_offset = 0; |
2337 | else | |
aed74b55 | 2338 | field_offset = in_height / out_height / 2; |
80c39712 TV |
2339 | } |
2340 | ||
2341 | /* Fields are independent but interleaved in memory. */ | |
2342 | if (fieldmode) | |
2343 | field_offset = 1; | |
2344 | ||
c6eee968 TV |
2345 | offset0 = 0; |
2346 | offset1 = 0; | |
2347 | row_inc = 0; | |
2348 | pix_inc = 0; | |
2349 | ||
65e006ff CM |
2350 | if (oi->rotation_type == OMAP_DSS_ROT_TILER) |
2351 | calc_tiler_rotation_offset(oi->screen_width, in_width, | |
2352 | oi->color_mode, fieldmode, field_offset, | |
2353 | &offset0, &offset1, &row_inc, &pix_inc, | |
2354 | x_predecim, y_predecim); | |
2355 | else if (oi->rotation_type == OMAP_DSS_ROT_DMA) | |
a4273b7c | 2356 | calc_dma_rotation_offset(oi->rotation, oi->mirror, |
aed74b55 | 2357 | oi->screen_width, in_width, frame_height, |
a4273b7c | 2358 | oi->color_mode, fieldmode, field_offset, |
aed74b55 CM |
2359 | &offset0, &offset1, &row_inc, &pix_inc, |
2360 | x_predecim, y_predecim); | |
80c39712 | 2361 | else |
a4273b7c | 2362 | calc_vrfb_rotation_offset(oi->rotation, oi->mirror, |
aed74b55 | 2363 | oi->screen_width, in_width, frame_height, |
a4273b7c | 2364 | oi->color_mode, fieldmode, field_offset, |
aed74b55 CM |
2365 | &offset0, &offset1, &row_inc, &pix_inc, |
2366 | x_predecim, y_predecim); | |
80c39712 TV |
2367 | |
2368 | DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n", | |
2369 | offset0, offset1, row_inc, pix_inc); | |
2370 | ||
a4273b7c | 2371 | dispc_ovl_set_color_mode(plane, oi->color_mode); |
80c39712 | 2372 | |
65e006ff CM |
2373 | dispc_ovl_configure_burst_type(plane, oi->rotation_type); |
2374 | ||
a4273b7c AT |
2375 | dispc_ovl_set_ba0(plane, oi->paddr + offset0); |
2376 | dispc_ovl_set_ba1(plane, oi->paddr + offset1); | |
80c39712 | 2377 | |
a4273b7c AT |
2378 | if (OMAP_DSS_COLOR_NV12 == oi->color_mode) { |
2379 | dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0); | |
2380 | dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1); | |
0d66cbb5 AJ |
2381 | } |
2382 | ||
2383 | ||
f0e5caab TV |
2384 | dispc_ovl_set_row_inc(plane, row_inc); |
2385 | dispc_ovl_set_pix_inc(plane, pix_inc); | |
80c39712 | 2386 | |
aed74b55 CM |
2387 | DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width, |
2388 | in_height, out_width, out_height); | |
80c39712 | 2389 | |
8eeb7019 | 2390 | dispc_ovl_set_pos(plane, oi->pos_x, pos_y); |
80c39712 | 2391 | |
78b687fc | 2392 | dispc_ovl_set_input_size(plane, in_width, in_height); |
80c39712 | 2393 | |
79ad75f2 | 2394 | if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) { |
aed74b55 CM |
2395 | dispc_ovl_set_scaling(plane, in_width, in_height, out_width, |
2396 | out_height, ilace, five_taps, fieldmode, | |
a4273b7c | 2397 | oi->color_mode, oi->rotation); |
78b687fc AT |
2398 | |
2399 | dispc_ovl_set_output_size(plane, out_width, out_height); | |
f0e5caab | 2400 | dispc_ovl_set_vid_color_conv(plane, cconv); |
80c39712 TV |
2401 | } |
2402 | ||
a4273b7c AT |
2403 | dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror, |
2404 | oi->color_mode); | |
80c39712 | 2405 | |
54128701 | 2406 | dispc_ovl_set_zorder(plane, oi->zorder); |
a4273b7c AT |
2407 | dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha); |
2408 | dispc_ovl_setup_global_alpha(plane, oi->global_alpha); | |
80c39712 | 2409 | |
c3d92529 | 2410 | dispc_ovl_enable_replication(plane, replication); |
c3d92529 | 2411 | |
80c39712 TV |
2412 | return 0; |
2413 | } | |
2414 | ||
f0e5caab | 2415 | int dispc_ovl_enable(enum omap_plane plane, bool enable) |
80c39712 | 2416 | { |
e6d80f95 TV |
2417 | DSSDBG("dispc_enable_plane %d, %d\n", plane, enable); |
2418 | ||
9b372c2d | 2419 | REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); |
e6d80f95 TV |
2420 | |
2421 | return 0; | |
80c39712 TV |
2422 | } |
2423 | ||
2424 | static void dispc_disable_isr(void *data, u32 mask) | |
2425 | { | |
2426 | struct completion *compl = data; | |
2427 | complete(compl); | |
2428 | } | |
2429 | ||
2a205f34 | 2430 | static void _enable_lcd_out(enum omap_channel channel, bool enable) |
80c39712 | 2431 | { |
efa70b3b CM |
2432 | mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable); |
2433 | /* flush posted write */ | |
2434 | mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); | |
80c39712 TV |
2435 | } |
2436 | ||
26d9dd0d | 2437 | static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable) |
80c39712 TV |
2438 | { |
2439 | struct completion frame_done_completion; | |
2440 | bool is_on; | |
2441 | int r; | |
2a205f34 | 2442 | u32 irq; |
80c39712 | 2443 | |
80c39712 TV |
2444 | /* When we disable LCD output, we need to wait until frame is done. |
2445 | * Otherwise the DSS is still working, and turning off the clocks | |
2446 | * prevents DSS from going to OFF mode */ | |
efa70b3b | 2447 | is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); |
2a205f34 | 2448 | |
efa70b3b | 2449 | irq = mgr_desc[channel].framedone_irq; |
80c39712 TV |
2450 | |
2451 | if (!enable && is_on) { | |
2452 | init_completion(&frame_done_completion); | |
2453 | ||
2454 | r = omap_dispc_register_isr(dispc_disable_isr, | |
2a205f34 | 2455 | &frame_done_completion, irq); |
80c39712 TV |
2456 | |
2457 | if (r) | |
2458 | DSSERR("failed to register FRAMEDONE isr\n"); | |
2459 | } | |
2460 | ||
2a205f34 | 2461 | _enable_lcd_out(channel, enable); |
80c39712 TV |
2462 | |
2463 | if (!enable && is_on) { | |
2464 | if (!wait_for_completion_timeout(&frame_done_completion, | |
2465 | msecs_to_jiffies(100))) | |
2466 | DSSERR("timeout waiting for FRAME DONE\n"); | |
2467 | ||
2468 | r = omap_dispc_unregister_isr(dispc_disable_isr, | |
2a205f34 | 2469 | &frame_done_completion, irq); |
80c39712 TV |
2470 | |
2471 | if (r) | |
2472 | DSSERR("failed to unregister FRAMEDONE isr\n"); | |
2473 | } | |
80c39712 TV |
2474 | } |
2475 | ||
2476 | static void _enable_digit_out(bool enable) | |
2477 | { | |
2478 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1); | |
b6a44e77 TV |
2479 | /* flush posted write */ |
2480 | dispc_read_reg(DISPC_CONTROL); | |
80c39712 TV |
2481 | } |
2482 | ||
26d9dd0d | 2483 | static void dispc_mgr_enable_digit_out(bool enable) |
80c39712 TV |
2484 | { |
2485 | struct completion frame_done_completion; | |
e82b090b TV |
2486 | enum dss_hdmi_venc_clk_source_select src; |
2487 | int r, i; | |
2488 | u32 irq_mask; | |
2489 | int num_irqs; | |
80c39712 | 2490 | |
e6d80f95 | 2491 | if (REG_GET(DISPC_CONTROL, 1, 1) == enable) |
80c39712 | 2492 | return; |
80c39712 | 2493 | |
e82b090b TV |
2494 | src = dss_get_hdmi_venc_clk_source(); |
2495 | ||
80c39712 TV |
2496 | if (enable) { |
2497 | unsigned long flags; | |
2498 | /* When we enable digit output, we'll get an extra digit | |
2499 | * sync lost interrupt, that we need to ignore */ | |
2500 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
2501 | dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT; | |
2502 | _omap_dispc_set_irqs(); | |
2503 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
2504 | } | |
2505 | ||
2506 | /* When we disable digit output, we need to wait until fields are done. | |
2507 | * Otherwise the DSS is still working, and turning off the clocks | |
2508 | * prevents DSS from going to OFF mode. And when enabling, we need to | |
2509 | * wait for the extra sync losts */ | |
2510 | init_completion(&frame_done_completion); | |
2511 | ||
e82b090b TV |
2512 | if (src == DSS_HDMI_M_PCLK && enable == false) { |
2513 | irq_mask = DISPC_IRQ_FRAMEDONETV; | |
2514 | num_irqs = 1; | |
2515 | } else { | |
2516 | irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD; | |
2517 | /* XXX I understand from TRM that we should only wait for the | |
2518 | * current field to complete. But it seems we have to wait for | |
2519 | * both fields */ | |
2520 | num_irqs = 2; | |
2521 | } | |
2522 | ||
80c39712 | 2523 | r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion, |
e82b090b | 2524 | irq_mask); |
80c39712 | 2525 | if (r) |
e82b090b | 2526 | DSSERR("failed to register %x isr\n", irq_mask); |
80c39712 TV |
2527 | |
2528 | _enable_digit_out(enable); | |
2529 | ||
e82b090b TV |
2530 | for (i = 0; i < num_irqs; ++i) { |
2531 | if (!wait_for_completion_timeout(&frame_done_completion, | |
2532 | msecs_to_jiffies(100))) | |
2533 | DSSERR("timeout waiting for digit out to %s\n", | |
2534 | enable ? "start" : "stop"); | |
2535 | } | |
80c39712 | 2536 | |
e82b090b TV |
2537 | r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion, |
2538 | irq_mask); | |
80c39712 | 2539 | if (r) |
e82b090b | 2540 | DSSERR("failed to unregister %x isr\n", irq_mask); |
80c39712 TV |
2541 | |
2542 | if (enable) { | |
2543 | unsigned long flags; | |
2544 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
e82b090b | 2545 | dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT; |
80c39712 TV |
2546 | dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT); |
2547 | _omap_dispc_set_irqs(); | |
2548 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
2549 | } | |
80c39712 TV |
2550 | } |
2551 | ||
26d9dd0d | 2552 | bool dispc_mgr_is_enabled(enum omap_channel channel) |
a2faee84 | 2553 | { |
efa70b3b | 2554 | return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE); |
a2faee84 TV |
2555 | } |
2556 | ||
26d9dd0d | 2557 | void dispc_mgr_enable(enum omap_channel channel, bool enable) |
a2faee84 | 2558 | { |
dd88b7a6 | 2559 | if (dss_mgr_is_lcd(channel)) |
26d9dd0d | 2560 | dispc_mgr_enable_lcd_out(channel, enable); |
a2faee84 | 2561 | else if (channel == OMAP_DSS_CHANNEL_DIGIT) |
26d9dd0d | 2562 | dispc_mgr_enable_digit_out(enable); |
a2faee84 TV |
2563 | else |
2564 | BUG(); | |
2565 | } | |
2566 | ||
80c39712 TV |
2567 | void dispc_lcd_enable_signal_polarity(bool act_high) |
2568 | { | |
6ced40bf AT |
2569 | if (!dss_has_feature(FEAT_LCDENABLEPOL)) |
2570 | return; | |
2571 | ||
80c39712 | 2572 | REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29); |
80c39712 TV |
2573 | } |
2574 | ||
2575 | void dispc_lcd_enable_signal(bool enable) | |
2576 | { | |
6ced40bf AT |
2577 | if (!dss_has_feature(FEAT_LCDENABLESIGNAL)) |
2578 | return; | |
2579 | ||
80c39712 | 2580 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28); |
80c39712 TV |
2581 | } |
2582 | ||
2583 | void dispc_pck_free_enable(bool enable) | |
2584 | { | |
6ced40bf AT |
2585 | if (!dss_has_feature(FEAT_PCKFREEENABLE)) |
2586 | return; | |
2587 | ||
80c39712 | 2588 | REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27); |
80c39712 TV |
2589 | } |
2590 | ||
26d9dd0d | 2591 | void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable) |
80c39712 | 2592 | { |
efa70b3b | 2593 | mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); |
80c39712 TV |
2594 | } |
2595 | ||
2596 | ||
d21f43bc | 2597 | void dispc_mgr_set_lcd_type_tft(enum omap_channel channel) |
80c39712 | 2598 | { |
d21f43bc | 2599 | mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1); |
80c39712 TV |
2600 | } |
2601 | ||
2602 | void dispc_set_loadmode(enum omap_dss_load_mode mode) | |
2603 | { | |
80c39712 | 2604 | REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1); |
80c39712 TV |
2605 | } |
2606 | ||
2607 | ||
c64dca40 | 2608 | static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color) |
80c39712 | 2609 | { |
8613b000 | 2610 | dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color); |
80c39712 TV |
2611 | } |
2612 | ||
c64dca40 | 2613 | static void dispc_mgr_set_trans_key(enum omap_channel ch, |
80c39712 TV |
2614 | enum omap_dss_trans_key_type type, |
2615 | u32 trans_key) | |
2616 | { | |
efa70b3b | 2617 | mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type); |
80c39712 | 2618 | |
8613b000 | 2619 | dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key); |
80c39712 TV |
2620 | } |
2621 | ||
c64dca40 | 2622 | static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable) |
80c39712 | 2623 | { |
efa70b3b | 2624 | mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable); |
80c39712 | 2625 | } |
11354dd5 | 2626 | |
c64dca40 TV |
2627 | static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, |
2628 | bool enable) | |
80c39712 | 2629 | { |
11354dd5 | 2630 | if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER)) |
80c39712 TV |
2631 | return; |
2632 | ||
80c39712 TV |
2633 | if (ch == OMAP_DSS_CHANNEL_LCD) |
2634 | REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18); | |
2a205f34 | 2635 | else if (ch == OMAP_DSS_CHANNEL_DIGIT) |
80c39712 | 2636 | REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19); |
80c39712 | 2637 | } |
11354dd5 | 2638 | |
c64dca40 TV |
2639 | void dispc_mgr_setup(enum omap_channel channel, |
2640 | struct omap_overlay_manager_info *info) | |
2641 | { | |
2642 | dispc_mgr_set_default_color(channel, info->default_color); | |
2643 | dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key); | |
2644 | dispc_mgr_enable_trans_key(channel, info->trans_enabled); | |
2645 | dispc_mgr_enable_alpha_fixed_zorder(channel, | |
2646 | info->partial_alpha_enabled); | |
2647 | if (dss_has_feature(FEAT_CPR)) { | |
2648 | dispc_mgr_enable_cpr(channel, info->cpr_enable); | |
2649 | dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs); | |
2650 | } | |
2651 | } | |
80c39712 | 2652 | |
26d9dd0d | 2653 | void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines) |
80c39712 TV |
2654 | { |
2655 | int code; | |
2656 | ||
2657 | switch (data_lines) { | |
2658 | case 12: | |
2659 | code = 0; | |
2660 | break; | |
2661 | case 16: | |
2662 | code = 1; | |
2663 | break; | |
2664 | case 18: | |
2665 | code = 2; | |
2666 | break; | |
2667 | case 24: | |
2668 | code = 3; | |
2669 | break; | |
2670 | default: | |
2671 | BUG(); | |
2672 | return; | |
2673 | } | |
2674 | ||
efa70b3b | 2675 | mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code); |
80c39712 TV |
2676 | } |
2677 | ||
569969d6 | 2678 | void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode) |
80c39712 TV |
2679 | { |
2680 | u32 l; | |
569969d6 | 2681 | int gpout0, gpout1; |
80c39712 TV |
2682 | |
2683 | switch (mode) { | |
569969d6 AT |
2684 | case DSS_IO_PAD_MODE_RESET: |
2685 | gpout0 = 0; | |
2686 | gpout1 = 0; | |
80c39712 | 2687 | break; |
569969d6 AT |
2688 | case DSS_IO_PAD_MODE_RFBI: |
2689 | gpout0 = 1; | |
80c39712 TV |
2690 | gpout1 = 0; |
2691 | break; | |
569969d6 AT |
2692 | case DSS_IO_PAD_MODE_BYPASS: |
2693 | gpout0 = 1; | |
80c39712 TV |
2694 | gpout1 = 1; |
2695 | break; | |
80c39712 TV |
2696 | default: |
2697 | BUG(); | |
2698 | return; | |
2699 | } | |
2700 | ||
569969d6 AT |
2701 | l = dispc_read_reg(DISPC_CONTROL); |
2702 | l = FLD_MOD(l, gpout0, 15, 15); | |
2703 | l = FLD_MOD(l, gpout1, 16, 16); | |
2704 | dispc_write_reg(DISPC_CONTROL, l); | |
2705 | } | |
2706 | ||
2707 | void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable) | |
2708 | { | |
efa70b3b | 2709 | mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable); |
80c39712 TV |
2710 | } |
2711 | ||
8f366162 AT |
2712 | static bool _dispc_mgr_size_ok(u16 width, u16 height) |
2713 | { | |
2714 | return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) && | |
2715 | height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT); | |
2716 | } | |
2717 | ||
80c39712 TV |
2718 | static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp, |
2719 | int vsw, int vfp, int vbp) | |
2720 | { | |
dcbe765b CM |
2721 | if (hsw < 1 || hsw > dispc.feat->sw_max || |
2722 | hfp < 1 || hfp > dispc.feat->hp_max || | |
2723 | hbp < 1 || hbp > dispc.feat->hp_max || | |
2724 | vsw < 1 || vsw > dispc.feat->sw_max || | |
2725 | vfp < 0 || vfp > dispc.feat->vp_max || | |
2726 | vbp < 0 || vbp > dispc.feat->vp_max) | |
2727 | return false; | |
80c39712 TV |
2728 | return true; |
2729 | } | |
2730 | ||
8f366162 | 2731 | bool dispc_mgr_timings_ok(enum omap_channel channel, |
b917fa39 | 2732 | const struct omap_video_timings *timings) |
80c39712 | 2733 | { |
8f366162 AT |
2734 | bool timings_ok; |
2735 | ||
2736 | timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res); | |
2737 | ||
dd88b7a6 | 2738 | if (dss_mgr_is_lcd(channel)) |
8f366162 AT |
2739 | timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw, |
2740 | timings->hfp, timings->hbp, | |
2741 | timings->vsw, timings->vfp, | |
2742 | timings->vbp); | |
2743 | ||
2744 | return timings_ok; | |
80c39712 TV |
2745 | } |
2746 | ||
26d9dd0d | 2747 | static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw, |
655e2941 AT |
2748 | int hfp, int hbp, int vsw, int vfp, int vbp, |
2749 | enum omap_dss_signal_level vsync_level, | |
2750 | enum omap_dss_signal_level hsync_level, | |
2751 | enum omap_dss_signal_edge data_pclk_edge, | |
2752 | enum omap_dss_signal_level de_level, | |
2753 | enum omap_dss_signal_edge sync_pclk_edge) | |
2754 | ||
80c39712 | 2755 | { |
655e2941 AT |
2756 | u32 timing_h, timing_v, l; |
2757 | bool onoff, rf, ipc; | |
80c39712 | 2758 | |
dcbe765b CM |
2759 | timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) | |
2760 | FLD_VAL(hfp-1, dispc.feat->fp_start, 8) | | |
2761 | FLD_VAL(hbp-1, dispc.feat->bp_start, 20); | |
2762 | timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | | |
2763 | FLD_VAL(vfp, dispc.feat->fp_start, 8) | | |
2764 | FLD_VAL(vbp, dispc.feat->bp_start, 20); | |
80c39712 | 2765 | |
64ba4f74 SS |
2766 | dispc_write_reg(DISPC_TIMING_H(channel), timing_h); |
2767 | dispc_write_reg(DISPC_TIMING_V(channel), timing_v); | |
655e2941 AT |
2768 | |
2769 | switch (data_pclk_edge) { | |
2770 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | |
2771 | ipc = false; | |
2772 | break; | |
2773 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: | |
2774 | ipc = true; | |
2775 | break; | |
2776 | case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES: | |
2777 | default: | |
2778 | BUG(); | |
2779 | } | |
2780 | ||
2781 | switch (sync_pclk_edge) { | |
2782 | case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES: | |
2783 | onoff = false; | |
2784 | rf = false; | |
2785 | break; | |
2786 | case OMAPDSS_DRIVE_SIG_FALLING_EDGE: | |
2787 | onoff = true; | |
2788 | rf = false; | |
2789 | break; | |
2790 | case OMAPDSS_DRIVE_SIG_RISING_EDGE: | |
2791 | onoff = true; | |
2792 | rf = true; | |
2793 | break; | |
2794 | default: | |
2795 | BUG(); | |
2796 | }; | |
2797 | ||
2798 | l = dispc_read_reg(DISPC_POL_FREQ(channel)); | |
2799 | l |= FLD_VAL(onoff, 17, 17); | |
2800 | l |= FLD_VAL(rf, 16, 16); | |
2801 | l |= FLD_VAL(de_level, 15, 15); | |
2802 | l |= FLD_VAL(ipc, 14, 14); | |
2803 | l |= FLD_VAL(hsync_level, 13, 13); | |
2804 | l |= FLD_VAL(vsync_level, 12, 12); | |
2805 | dispc_write_reg(DISPC_POL_FREQ(channel), l); | |
80c39712 TV |
2806 | } |
2807 | ||
2808 | /* change name to mode? */ | |
c51d921a | 2809 | void dispc_mgr_set_timings(enum omap_channel channel, |
64ba4f74 | 2810 | struct omap_video_timings *timings) |
80c39712 TV |
2811 | { |
2812 | unsigned xtot, ytot; | |
2813 | unsigned long ht, vt; | |
2aefad49 | 2814 | struct omap_video_timings t = *timings; |
80c39712 | 2815 | |
2aefad49 | 2816 | DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res); |
80c39712 | 2817 | |
2aefad49 | 2818 | if (!dispc_mgr_timings_ok(channel, &t)) { |
8f366162 | 2819 | BUG(); |
c6eee968 TV |
2820 | return; |
2821 | } | |
80c39712 | 2822 | |
dd88b7a6 | 2823 | if (dss_mgr_is_lcd(channel)) { |
2aefad49 | 2824 | _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, |
655e2941 AT |
2825 | t.vfp, t.vbp, t.vsync_level, t.hsync_level, |
2826 | t.data_pclk_edge, t.de_level, t.sync_pclk_edge); | |
80c39712 | 2827 | |
2aefad49 AT |
2828 | xtot = t.x_res + t.hfp + t.hsw + t.hbp; |
2829 | ytot = t.y_res + t.vfp + t.vsw + t.vbp; | |
80c39712 | 2830 | |
c51d921a AT |
2831 | ht = (timings->pixel_clock * 1000) / xtot; |
2832 | vt = (timings->pixel_clock * 1000) / xtot / ytot; | |
2833 | ||
2834 | DSSDBG("pck %u\n", timings->pixel_clock); | |
2835 | DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n", | |
2aefad49 | 2836 | t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); |
655e2941 AT |
2837 | DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n", |
2838 | t.vsync_level, t.hsync_level, t.data_pclk_edge, | |
2839 | t.de_level, t.sync_pclk_edge); | |
80c39712 | 2840 | |
c51d921a | 2841 | DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt); |
2aefad49 | 2842 | } else { |
23c8f88e | 2843 | if (t.interlace == true) |
2aefad49 | 2844 | t.y_res /= 2; |
c51d921a | 2845 | } |
8f366162 | 2846 | |
2aefad49 | 2847 | dispc_mgr_set_size(channel, t.x_res, t.y_res); |
80c39712 TV |
2848 | } |
2849 | ||
26d9dd0d | 2850 | static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div, |
ff1b2cde | 2851 | u16 pck_div) |
80c39712 TV |
2852 | { |
2853 | BUG_ON(lck_div < 1); | |
9eaaf207 | 2854 | BUG_ON(pck_div < 1); |
80c39712 | 2855 | |
ce7fa5eb | 2856 | dispc_write_reg(DISPC_DIVISORo(channel), |
80c39712 | 2857 | FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0)); |
80c39712 TV |
2858 | } |
2859 | ||
26d9dd0d | 2860 | static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div, |
2a205f34 | 2861 | int *pck_div) |
80c39712 TV |
2862 | { |
2863 | u32 l; | |
ce7fa5eb | 2864 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 TV |
2865 | *lck_div = FLD_GET(l, 23, 16); |
2866 | *pck_div = FLD_GET(l, 7, 0); | |
2867 | } | |
2868 | ||
2869 | unsigned long dispc_fclk_rate(void) | |
2870 | { | |
a72b64b9 | 2871 | struct platform_device *dsidev; |
80c39712 TV |
2872 | unsigned long r = 0; |
2873 | ||
66534e8e | 2874 | switch (dss_get_dispc_clk_source()) { |
89a35e51 | 2875 | case OMAP_DSS_CLK_SRC_FCK: |
4fbafaf3 | 2876 | r = clk_get_rate(dispc.dss_clk); |
66534e8e | 2877 | break; |
89a35e51 | 2878 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
a72b64b9 AT |
2879 | dsidev = dsi_get_dsidev_from_id(0); |
2880 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
66534e8e | 2881 | break; |
5a8b572d AT |
2882 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
2883 | dsidev = dsi_get_dsidev_from_id(1); | |
2884 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
2885 | break; | |
66534e8e TA |
2886 | default: |
2887 | BUG(); | |
c6eee968 | 2888 | return 0; |
66534e8e TA |
2889 | } |
2890 | ||
80c39712 TV |
2891 | return r; |
2892 | } | |
2893 | ||
26d9dd0d | 2894 | unsigned long dispc_mgr_lclk_rate(enum omap_channel channel) |
80c39712 | 2895 | { |
a72b64b9 | 2896 | struct platform_device *dsidev; |
80c39712 TV |
2897 | int lcd; |
2898 | unsigned long r; | |
2899 | u32 l; | |
2900 | ||
ce7fa5eb | 2901 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 TV |
2902 | |
2903 | lcd = FLD_GET(l, 23, 16); | |
2904 | ||
ea75159e | 2905 | switch (dss_get_lcd_clk_source(channel)) { |
89a35e51 | 2906 | case OMAP_DSS_CLK_SRC_FCK: |
4fbafaf3 | 2907 | r = clk_get_rate(dispc.dss_clk); |
ea75159e | 2908 | break; |
89a35e51 | 2909 | case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC: |
a72b64b9 AT |
2910 | dsidev = dsi_get_dsidev_from_id(0); |
2911 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
ea75159e | 2912 | break; |
5a8b572d AT |
2913 | case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC: |
2914 | dsidev = dsi_get_dsidev_from_id(1); | |
2915 | r = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
2916 | break; | |
ea75159e TA |
2917 | default: |
2918 | BUG(); | |
c6eee968 | 2919 | return 0; |
ea75159e | 2920 | } |
80c39712 TV |
2921 | |
2922 | return r / lcd; | |
2923 | } | |
2924 | ||
26d9dd0d | 2925 | unsigned long dispc_mgr_pclk_rate(enum omap_channel channel) |
80c39712 | 2926 | { |
80c39712 | 2927 | unsigned long r; |
80c39712 | 2928 | |
dd88b7a6 | 2929 | if (dss_mgr_is_lcd(channel)) { |
c3dc6a7a AT |
2930 | int pcd; |
2931 | u32 l; | |
80c39712 | 2932 | |
c3dc6a7a | 2933 | l = dispc_read_reg(DISPC_DIVISORo(channel)); |
80c39712 | 2934 | |
c3dc6a7a | 2935 | pcd = FLD_GET(l, 7, 0); |
80c39712 | 2936 | |
c3dc6a7a AT |
2937 | r = dispc_mgr_lclk_rate(channel); |
2938 | ||
2939 | return r / pcd; | |
2940 | } else { | |
3fa03ba8 | 2941 | enum dss_hdmi_venc_clk_source_select source; |
c3dc6a7a | 2942 | |
3fa03ba8 AT |
2943 | source = dss_get_hdmi_venc_clk_source(); |
2944 | ||
2945 | switch (source) { | |
2946 | case DSS_VENC_TV_CLK: | |
c3dc6a7a | 2947 | return venc_get_pixel_clock(); |
3fa03ba8 | 2948 | case DSS_HDMI_M_PCLK: |
c3dc6a7a AT |
2949 | return hdmi_get_pixel_clock(); |
2950 | default: | |
2951 | BUG(); | |
c6eee968 | 2952 | return 0; |
c3dc6a7a AT |
2953 | } |
2954 | } | |
80c39712 TV |
2955 | } |
2956 | ||
8b53d991 CM |
2957 | unsigned long dispc_core_clk_rate(void) |
2958 | { | |
2959 | int lcd; | |
2960 | unsigned long fclk = dispc_fclk_rate(); | |
2961 | ||
2962 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) | |
2963 | lcd = REG_GET(DISPC_DIVISOR, 23, 16); | |
2964 | else | |
2965 | lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16); | |
2966 | ||
2967 | return fclk / lcd; | |
2968 | } | |
2969 | ||
6f1891fc | 2970 | static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel) |
80c39712 TV |
2971 | { |
2972 | int lcd, pcd; | |
6f1891fc CM |
2973 | enum omap_dss_clk_source lcd_clk_src; |
2974 | ||
2975 | seq_printf(s, "- %s -\n", mgr_desc[channel].name); | |
2976 | ||
2977 | lcd_clk_src = dss_get_lcd_clk_source(channel); | |
2978 | ||
2979 | seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name, | |
2980 | dss_get_generic_clk_source_name(lcd_clk_src), | |
2981 | dss_feat_get_clk_source_name(lcd_clk_src)); | |
2982 | ||
2983 | dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd); | |
2984 | ||
2985 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
2986 | dispc_mgr_lclk_rate(channel), lcd); | |
2987 | seq_printf(s, "pck\t\t%-16lupck div\t%u\n", | |
2988 | dispc_mgr_pclk_rate(channel), pcd); | |
2989 | } | |
2990 | ||
2991 | void dispc_dump_clocks(struct seq_file *s) | |
2992 | { | |
2993 | int lcd; | |
0cf35df3 | 2994 | u32 l; |
89a35e51 | 2995 | enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source(); |
80c39712 | 2996 | |
4fbafaf3 TV |
2997 | if (dispc_runtime_get()) |
2998 | return; | |
80c39712 | 2999 | |
80c39712 TV |
3000 | seq_printf(s, "- DISPC -\n"); |
3001 | ||
067a57e4 AT |
3002 | seq_printf(s, "dispc fclk source = %s (%s)\n", |
3003 | dss_get_generic_clk_source_name(dispc_clk_src), | |
3004 | dss_feat_get_clk_source_name(dispc_clk_src)); | |
80c39712 TV |
3005 | |
3006 | seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate()); | |
2a205f34 | 3007 | |
0cf35df3 MR |
3008 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { |
3009 | seq_printf(s, "- DISPC-CORE-CLK -\n"); | |
3010 | l = dispc_read_reg(DISPC_DIVISOR); | |
3011 | lcd = FLD_GET(l, 23, 16); | |
3012 | ||
3013 | seq_printf(s, "lck\t\t%-16lulck div\t%u\n", | |
3014 | (dispc_fclk_rate()/lcd), lcd); | |
3015 | } | |
2a205f34 | 3016 | |
6f1891fc | 3017 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD); |
ea75159e | 3018 | |
6f1891fc CM |
3019 | if (dss_has_feature(FEAT_MGR_LCD2)) |
3020 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2); | |
3021 | if (dss_has_feature(FEAT_MGR_LCD3)) | |
3022 | dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3); | |
4fbafaf3 TV |
3023 | |
3024 | dispc_runtime_put(); | |
80c39712 TV |
3025 | } |
3026 | ||
dfc0fd8d TV |
3027 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
3028 | void dispc_dump_irqs(struct seq_file *s) | |
3029 | { | |
3030 | unsigned long flags; | |
3031 | struct dispc_irq_stats stats; | |
3032 | ||
3033 | spin_lock_irqsave(&dispc.irq_stats_lock, flags); | |
3034 | ||
3035 | stats = dispc.irq_stats; | |
3036 | memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats)); | |
3037 | dispc.irq_stats.last_reset = jiffies; | |
3038 | ||
3039 | spin_unlock_irqrestore(&dispc.irq_stats_lock, flags); | |
3040 | ||
3041 | seq_printf(s, "period %u ms\n", | |
3042 | jiffies_to_msecs(jiffies - stats.last_reset)); | |
3043 | ||
3044 | seq_printf(s, "irqs %d\n", stats.irq_count); | |
3045 | #define PIS(x) \ | |
3046 | seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]); | |
3047 | ||
3048 | PIS(FRAMEDONE); | |
3049 | PIS(VSYNC); | |
3050 | PIS(EVSYNC_EVEN); | |
3051 | PIS(EVSYNC_ODD); | |
3052 | PIS(ACBIAS_COUNT_STAT); | |
3053 | PIS(PROG_LINE_NUM); | |
3054 | PIS(GFX_FIFO_UNDERFLOW); | |
3055 | PIS(GFX_END_WIN); | |
3056 | PIS(PAL_GAMMA_MASK); | |
3057 | PIS(OCP_ERR); | |
3058 | PIS(VID1_FIFO_UNDERFLOW); | |
3059 | PIS(VID1_END_WIN); | |
3060 | PIS(VID2_FIFO_UNDERFLOW); | |
3061 | PIS(VID2_END_WIN); | |
b8c095b4 AT |
3062 | if (dss_feat_get_num_ovls() > 3) { |
3063 | PIS(VID3_FIFO_UNDERFLOW); | |
3064 | PIS(VID3_END_WIN); | |
3065 | } | |
dfc0fd8d TV |
3066 | PIS(SYNC_LOST); |
3067 | PIS(SYNC_LOST_DIGIT); | |
3068 | PIS(WAKEUP); | |
2a205f34 SS |
3069 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
3070 | PIS(FRAMEDONE2); | |
3071 | PIS(VSYNC2); | |
3072 | PIS(ACBIAS_COUNT_STAT2); | |
3073 | PIS(SYNC_LOST2); | |
3074 | } | |
6f1891fc CM |
3075 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
3076 | PIS(FRAMEDONE3); | |
3077 | PIS(VSYNC3); | |
3078 | PIS(ACBIAS_COUNT_STAT3); | |
3079 | PIS(SYNC_LOST3); | |
3080 | } | |
dfc0fd8d TV |
3081 | #undef PIS |
3082 | } | |
dfc0fd8d TV |
3083 | #endif |
3084 | ||
e40402cf | 3085 | static void dispc_dump_regs(struct seq_file *s) |
80c39712 | 3086 | { |
4dd2da15 AT |
3087 | int i, j; |
3088 | const char *mgr_names[] = { | |
3089 | [OMAP_DSS_CHANNEL_LCD] = "LCD", | |
3090 | [OMAP_DSS_CHANNEL_DIGIT] = "TV", | |
3091 | [OMAP_DSS_CHANNEL_LCD2] = "LCD2", | |
6f1891fc | 3092 | [OMAP_DSS_CHANNEL_LCD3] = "LCD3", |
4dd2da15 AT |
3093 | }; |
3094 | const char *ovl_names[] = { | |
3095 | [OMAP_DSS_GFX] = "GFX", | |
3096 | [OMAP_DSS_VIDEO1] = "VID1", | |
3097 | [OMAP_DSS_VIDEO2] = "VID2", | |
b8c095b4 | 3098 | [OMAP_DSS_VIDEO3] = "VID3", |
4dd2da15 AT |
3099 | }; |
3100 | const char **p_names; | |
3101 | ||
9b372c2d | 3102 | #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r)) |
80c39712 | 3103 | |
4fbafaf3 TV |
3104 | if (dispc_runtime_get()) |
3105 | return; | |
80c39712 | 3106 | |
5010be80 | 3107 | /* DISPC common registers */ |
80c39712 TV |
3108 | DUMPREG(DISPC_REVISION); |
3109 | DUMPREG(DISPC_SYSCONFIG); | |
3110 | DUMPREG(DISPC_SYSSTATUS); | |
3111 | DUMPREG(DISPC_IRQSTATUS); | |
3112 | DUMPREG(DISPC_IRQENABLE); | |
3113 | DUMPREG(DISPC_CONTROL); | |
3114 | DUMPREG(DISPC_CONFIG); | |
3115 | DUMPREG(DISPC_CAPABLE); | |
80c39712 TV |
3116 | DUMPREG(DISPC_LINE_STATUS); |
3117 | DUMPREG(DISPC_LINE_NUMBER); | |
11354dd5 AT |
3118 | if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) || |
3119 | dss_has_feature(FEAT_ALPHA_FREE_ZORDER)) | |
332e9d70 | 3120 | DUMPREG(DISPC_GLOBAL_ALPHA); |
2a205f34 SS |
3121 | if (dss_has_feature(FEAT_MGR_LCD2)) { |
3122 | DUMPREG(DISPC_CONTROL2); | |
3123 | DUMPREG(DISPC_CONFIG2); | |
5010be80 | 3124 | } |
6f1891fc CM |
3125 | if (dss_has_feature(FEAT_MGR_LCD3)) { |
3126 | DUMPREG(DISPC_CONTROL3); | |
3127 | DUMPREG(DISPC_CONFIG3); | |
3128 | } | |
5010be80 AT |
3129 | |
3130 | #undef DUMPREG | |
3131 | ||
3132 | #define DISPC_REG(i, name) name(i) | |
4dd2da15 AT |
3133 | #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ |
3134 | 48 - strlen(#r) - strlen(p_names[i]), " ", \ | |
5010be80 AT |
3135 | dispc_read_reg(DISPC_REG(i, r))) |
3136 | ||
4dd2da15 | 3137 | p_names = mgr_names; |
5010be80 | 3138 | |
4dd2da15 AT |
3139 | /* DISPC channel specific registers */ |
3140 | for (i = 0; i < dss_feat_get_num_mgrs(); i++) { | |
3141 | DUMPREG(i, DISPC_DEFAULT_COLOR); | |
3142 | DUMPREG(i, DISPC_TRANS_COLOR); | |
3143 | DUMPREG(i, DISPC_SIZE_MGR); | |
80c39712 | 3144 | |
4dd2da15 AT |
3145 | if (i == OMAP_DSS_CHANNEL_DIGIT) |
3146 | continue; | |
5010be80 | 3147 | |
4dd2da15 AT |
3148 | DUMPREG(i, DISPC_DEFAULT_COLOR); |
3149 | DUMPREG(i, DISPC_TRANS_COLOR); | |
3150 | DUMPREG(i, DISPC_TIMING_H); | |
3151 | DUMPREG(i, DISPC_TIMING_V); | |
3152 | DUMPREG(i, DISPC_POL_FREQ); | |
3153 | DUMPREG(i, DISPC_DIVISORo); | |
3154 | DUMPREG(i, DISPC_SIZE_MGR); | |
5010be80 | 3155 | |
4dd2da15 AT |
3156 | DUMPREG(i, DISPC_DATA_CYCLE1); |
3157 | DUMPREG(i, DISPC_DATA_CYCLE2); | |
3158 | DUMPREG(i, DISPC_DATA_CYCLE3); | |
2a205f34 | 3159 | |
332e9d70 | 3160 | if (dss_has_feature(FEAT_CPR)) { |
4dd2da15 AT |
3161 | DUMPREG(i, DISPC_CPR_COEF_R); |
3162 | DUMPREG(i, DISPC_CPR_COEF_G); | |
3163 | DUMPREG(i, DISPC_CPR_COEF_B); | |
332e9d70 | 3164 | } |
2a205f34 | 3165 | } |
80c39712 | 3166 | |
4dd2da15 AT |
3167 | p_names = ovl_names; |
3168 | ||
3169 | for (i = 0; i < dss_feat_get_num_ovls(); i++) { | |
3170 | DUMPREG(i, DISPC_OVL_BA0); | |
3171 | DUMPREG(i, DISPC_OVL_BA1); | |
3172 | DUMPREG(i, DISPC_OVL_POSITION); | |
3173 | DUMPREG(i, DISPC_OVL_SIZE); | |
3174 | DUMPREG(i, DISPC_OVL_ATTRIBUTES); | |
3175 | DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD); | |
3176 | DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS); | |
3177 | DUMPREG(i, DISPC_OVL_ROW_INC); | |
3178 | DUMPREG(i, DISPC_OVL_PIXEL_INC); | |
3179 | if (dss_has_feature(FEAT_PRELOAD)) | |
3180 | DUMPREG(i, DISPC_OVL_PRELOAD); | |
3181 | ||
3182 | if (i == OMAP_DSS_GFX) { | |
3183 | DUMPREG(i, DISPC_OVL_WINDOW_SKIP); | |
3184 | DUMPREG(i, DISPC_OVL_TABLE_BA); | |
3185 | continue; | |
3186 | } | |
3187 | ||
3188 | DUMPREG(i, DISPC_OVL_FIR); | |
3189 | DUMPREG(i, DISPC_OVL_PICTURE_SIZE); | |
3190 | DUMPREG(i, DISPC_OVL_ACCU0); | |
3191 | DUMPREG(i, DISPC_OVL_ACCU1); | |
3192 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3193 | DUMPREG(i, DISPC_OVL_BA0_UV); | |
3194 | DUMPREG(i, DISPC_OVL_BA1_UV); | |
3195 | DUMPREG(i, DISPC_OVL_FIR2); | |
3196 | DUMPREG(i, DISPC_OVL_ACCU2_0); | |
3197 | DUMPREG(i, DISPC_OVL_ACCU2_1); | |
3198 | } | |
3199 | if (dss_has_feature(FEAT_ATTR2)) | |
3200 | DUMPREG(i, DISPC_OVL_ATTRIBUTES2); | |
3201 | if (dss_has_feature(FEAT_PRELOAD)) | |
3202 | DUMPREG(i, DISPC_OVL_PRELOAD); | |
ab5ca071 | 3203 | } |
5010be80 AT |
3204 | |
3205 | #undef DISPC_REG | |
3206 | #undef DUMPREG | |
3207 | ||
3208 | #define DISPC_REG(plane, name, i) name(plane, i) | |
3209 | #define DUMPREG(plane, name, i) \ | |
4dd2da15 AT |
3210 | seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \ |
3211 | 46 - strlen(#name) - strlen(p_names[plane]), " ", \ | |
5010be80 AT |
3212 | dispc_read_reg(DISPC_REG(plane, name, i))) |
3213 | ||
4dd2da15 | 3214 | /* Video pipeline coefficient registers */ |
332e9d70 | 3215 | |
4dd2da15 AT |
3216 | /* start from OMAP_DSS_VIDEO1 */ |
3217 | for (i = 1; i < dss_feat_get_num_ovls(); i++) { | |
3218 | for (j = 0; j < 8; j++) | |
3219 | DUMPREG(i, DISPC_OVL_FIR_COEF_H, j); | |
9b372c2d | 3220 | |
4dd2da15 AT |
3221 | for (j = 0; j < 8; j++) |
3222 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j); | |
5010be80 | 3223 | |
4dd2da15 AT |
3224 | for (j = 0; j < 5; j++) |
3225 | DUMPREG(i, DISPC_OVL_CONV_COEF, j); | |
ab5ca071 | 3226 | |
4dd2da15 AT |
3227 | if (dss_has_feature(FEAT_FIR_COEF_V)) { |
3228 | for (j = 0; j < 8; j++) | |
3229 | DUMPREG(i, DISPC_OVL_FIR_COEF_V, j); | |
3230 | } | |
3231 | ||
3232 | if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) { | |
3233 | for (j = 0; j < 8; j++) | |
3234 | DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j); | |
3235 | ||
3236 | for (j = 0; j < 8; j++) | |
3237 | DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j); | |
3238 | ||
3239 | for (j = 0; j < 8; j++) | |
3240 | DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j); | |
3241 | } | |
332e9d70 | 3242 | } |
80c39712 | 3243 | |
4fbafaf3 | 3244 | dispc_runtime_put(); |
5010be80 AT |
3245 | |
3246 | #undef DISPC_REG | |
80c39712 TV |
3247 | #undef DUMPREG |
3248 | } | |
3249 | ||
80c39712 | 3250 | /* with fck as input clock rate, find dispc dividers that produce req_pck */ |
6d523e7b | 3251 | void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck, |
80c39712 TV |
3252 | struct dispc_clock_info *cinfo) |
3253 | { | |
9eaaf207 | 3254 | u16 pcd_min, pcd_max; |
80c39712 TV |
3255 | unsigned long best_pck; |
3256 | u16 best_ld, cur_ld; | |
3257 | u16 best_pd, cur_pd; | |
3258 | ||
9eaaf207 TV |
3259 | pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD); |
3260 | pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD); | |
3261 | ||
80c39712 TV |
3262 | best_pck = 0; |
3263 | best_ld = 0; | |
3264 | best_pd = 0; | |
3265 | ||
3266 | for (cur_ld = 1; cur_ld <= 255; ++cur_ld) { | |
3267 | unsigned long lck = fck / cur_ld; | |
3268 | ||
9eaaf207 | 3269 | for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) { |
80c39712 TV |
3270 | unsigned long pck = lck / cur_pd; |
3271 | long old_delta = abs(best_pck - req_pck); | |
3272 | long new_delta = abs(pck - req_pck); | |
3273 | ||
3274 | if (best_pck == 0 || new_delta < old_delta) { | |
3275 | best_pck = pck; | |
3276 | best_ld = cur_ld; | |
3277 | best_pd = cur_pd; | |
3278 | ||
3279 | if (pck == req_pck) | |
3280 | goto found; | |
3281 | } | |
3282 | ||
3283 | if (pck < req_pck) | |
3284 | break; | |
3285 | } | |
3286 | ||
3287 | if (lck / pcd_min < req_pck) | |
3288 | break; | |
3289 | } | |
3290 | ||
3291 | found: | |
3292 | cinfo->lck_div = best_ld; | |
3293 | cinfo->pck_div = best_pd; | |
3294 | cinfo->lck = fck / cinfo->lck_div; | |
3295 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
3296 | } | |
3297 | ||
3298 | /* calculate clock rates using dividers in cinfo */ | |
3299 | int dispc_calc_clock_rates(unsigned long dispc_fclk_rate, | |
3300 | struct dispc_clock_info *cinfo) | |
3301 | { | |
3302 | if (cinfo->lck_div > 255 || cinfo->lck_div == 0) | |
3303 | return -EINVAL; | |
9eaaf207 | 3304 | if (cinfo->pck_div < 1 || cinfo->pck_div > 255) |
80c39712 TV |
3305 | return -EINVAL; |
3306 | ||
3307 | cinfo->lck = dispc_fclk_rate / cinfo->lck_div; | |
3308 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
3309 | ||
3310 | return 0; | |
3311 | } | |
3312 | ||
f0d08f89 | 3313 | void dispc_mgr_set_clock_div(enum omap_channel channel, |
ff1b2cde | 3314 | struct dispc_clock_info *cinfo) |
80c39712 TV |
3315 | { |
3316 | DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div); | |
3317 | DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div); | |
3318 | ||
26d9dd0d | 3319 | dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div); |
80c39712 TV |
3320 | } |
3321 | ||
26d9dd0d | 3322 | int dispc_mgr_get_clock_div(enum omap_channel channel, |
ff1b2cde | 3323 | struct dispc_clock_info *cinfo) |
80c39712 TV |
3324 | { |
3325 | unsigned long fck; | |
3326 | ||
3327 | fck = dispc_fclk_rate(); | |
3328 | ||
ce7fa5eb MR |
3329 | cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); |
3330 | cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0); | |
80c39712 TV |
3331 | |
3332 | cinfo->lck = fck / cinfo->lck_div; | |
3333 | cinfo->pck = cinfo->lck / cinfo->pck_div; | |
3334 | ||
3335 | return 0; | |
3336 | } | |
3337 | ||
3338 | /* dispc.irq_lock has to be locked by the caller */ | |
3339 | static void _omap_dispc_set_irqs(void) | |
3340 | { | |
3341 | u32 mask; | |
3342 | u32 old_mask; | |
3343 | int i; | |
3344 | struct omap_dispc_isr_data *isr_data; | |
3345 | ||
3346 | mask = dispc.irq_error_mask; | |
3347 | ||
3348 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
3349 | isr_data = &dispc.registered_isr[i]; | |
3350 | ||
3351 | if (isr_data->isr == NULL) | |
3352 | continue; | |
3353 | ||
3354 | mask |= isr_data->mask; | |
3355 | } | |
3356 | ||
80c39712 TV |
3357 | old_mask = dispc_read_reg(DISPC_IRQENABLE); |
3358 | /* clear the irqstatus for newly enabled irqs */ | |
3359 | dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask); | |
3360 | ||
3361 | dispc_write_reg(DISPC_IRQENABLE, mask); | |
80c39712 TV |
3362 | } |
3363 | ||
3364 | int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask) | |
3365 | { | |
3366 | int i; | |
3367 | int ret; | |
3368 | unsigned long flags; | |
3369 | struct omap_dispc_isr_data *isr_data; | |
3370 | ||
3371 | if (isr == NULL) | |
3372 | return -EINVAL; | |
3373 | ||
3374 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
3375 | ||
3376 | /* check for duplicate entry */ | |
3377 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
3378 | isr_data = &dispc.registered_isr[i]; | |
3379 | if (isr_data->isr == isr && isr_data->arg == arg && | |
3380 | isr_data->mask == mask) { | |
3381 | ret = -EINVAL; | |
3382 | goto err; | |
3383 | } | |
3384 | } | |
3385 | ||
3386 | isr_data = NULL; | |
3387 | ret = -EBUSY; | |
3388 | ||
3389 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
3390 | isr_data = &dispc.registered_isr[i]; | |
3391 | ||
3392 | if (isr_data->isr != NULL) | |
3393 | continue; | |
3394 | ||
3395 | isr_data->isr = isr; | |
3396 | isr_data->arg = arg; | |
3397 | isr_data->mask = mask; | |
3398 | ret = 0; | |
3399 | ||
3400 | break; | |
3401 | } | |
3402 | ||
b9cb0984 TV |
3403 | if (ret) |
3404 | goto err; | |
3405 | ||
80c39712 TV |
3406 | _omap_dispc_set_irqs(); |
3407 | ||
3408 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
3409 | ||
3410 | return 0; | |
3411 | err: | |
3412 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
3413 | ||
3414 | return ret; | |
3415 | } | |
3416 | EXPORT_SYMBOL(omap_dispc_register_isr); | |
3417 | ||
3418 | int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask) | |
3419 | { | |
3420 | int i; | |
3421 | unsigned long flags; | |
3422 | int ret = -EINVAL; | |
3423 | struct omap_dispc_isr_data *isr_data; | |
3424 | ||
3425 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
3426 | ||
3427 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
3428 | isr_data = &dispc.registered_isr[i]; | |
3429 | if (isr_data->isr != isr || isr_data->arg != arg || | |
3430 | isr_data->mask != mask) | |
3431 | continue; | |
3432 | ||
3433 | /* found the correct isr */ | |
3434 | ||
3435 | isr_data->isr = NULL; | |
3436 | isr_data->arg = NULL; | |
3437 | isr_data->mask = 0; | |
3438 | ||
3439 | ret = 0; | |
3440 | break; | |
3441 | } | |
3442 | ||
3443 | if (ret == 0) | |
3444 | _omap_dispc_set_irqs(); | |
3445 | ||
3446 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
3447 | ||
3448 | return ret; | |
3449 | } | |
3450 | EXPORT_SYMBOL(omap_dispc_unregister_isr); | |
3451 | ||
3452 | #ifdef DEBUG | |
3453 | static void print_irq_status(u32 status) | |
3454 | { | |
3455 | if ((status & dispc.irq_error_mask) == 0) | |
3456 | return; | |
3457 | ||
3458 | printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status); | |
3459 | ||
3460 | #define PIS(x) \ | |
3461 | if (status & DISPC_IRQ_##x) \ | |
3462 | printk(#x " "); | |
3463 | PIS(GFX_FIFO_UNDERFLOW); | |
3464 | PIS(OCP_ERR); | |
3465 | PIS(VID1_FIFO_UNDERFLOW); | |
3466 | PIS(VID2_FIFO_UNDERFLOW); | |
b8c095b4 AT |
3467 | if (dss_feat_get_num_ovls() > 3) |
3468 | PIS(VID3_FIFO_UNDERFLOW); | |
80c39712 TV |
3469 | PIS(SYNC_LOST); |
3470 | PIS(SYNC_LOST_DIGIT); | |
2a205f34 SS |
3471 | if (dss_has_feature(FEAT_MGR_LCD2)) |
3472 | PIS(SYNC_LOST2); | |
6f1891fc CM |
3473 | if (dss_has_feature(FEAT_MGR_LCD3)) |
3474 | PIS(SYNC_LOST3); | |
80c39712 TV |
3475 | #undef PIS |
3476 | ||
3477 | printk("\n"); | |
3478 | } | |
3479 | #endif | |
3480 | ||
3481 | /* Called from dss.c. Note that we don't touch clocks here, | |
3482 | * but we presume they are on because we got an IRQ. However, | |
3483 | * an irq handler may turn the clocks off, so we may not have | |
3484 | * clock later in the function. */ | |
affe360d | 3485 | static irqreturn_t omap_dispc_irq_handler(int irq, void *arg) |
80c39712 TV |
3486 | { |
3487 | int i; | |
affe360d | 3488 | u32 irqstatus, irqenable; |
80c39712 TV |
3489 | u32 handledirqs = 0; |
3490 | u32 unhandled_errors; | |
3491 | struct omap_dispc_isr_data *isr_data; | |
3492 | struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS]; | |
3493 | ||
3494 | spin_lock(&dispc.irq_lock); | |
3495 | ||
3496 | irqstatus = dispc_read_reg(DISPC_IRQSTATUS); | |
affe360d | 3497 | irqenable = dispc_read_reg(DISPC_IRQENABLE); |
3498 | ||
3499 | /* IRQ is not for us */ | |
3500 | if (!(irqstatus & irqenable)) { | |
3501 | spin_unlock(&dispc.irq_lock); | |
3502 | return IRQ_NONE; | |
3503 | } | |
80c39712 | 3504 | |
dfc0fd8d TV |
3505 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
3506 | spin_lock(&dispc.irq_stats_lock); | |
3507 | dispc.irq_stats.irq_count++; | |
3508 | dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs); | |
3509 | spin_unlock(&dispc.irq_stats_lock); | |
3510 | #endif | |
3511 | ||
80c39712 TV |
3512 | #ifdef DEBUG |
3513 | if (dss_debug) | |
3514 | print_irq_status(irqstatus); | |
3515 | #endif | |
3516 | /* Ack the interrupt. Do it here before clocks are possibly turned | |
3517 | * off */ | |
3518 | dispc_write_reg(DISPC_IRQSTATUS, irqstatus); | |
3519 | /* flush posted write */ | |
3520 | dispc_read_reg(DISPC_IRQSTATUS); | |
3521 | ||
3522 | /* make a copy and unlock, so that isrs can unregister | |
3523 | * themselves */ | |
3524 | memcpy(registered_isr, dispc.registered_isr, | |
3525 | sizeof(registered_isr)); | |
3526 | ||
3527 | spin_unlock(&dispc.irq_lock); | |
3528 | ||
3529 | for (i = 0; i < DISPC_MAX_NR_ISRS; i++) { | |
3530 | isr_data = ®istered_isr[i]; | |
3531 | ||
3532 | if (!isr_data->isr) | |
3533 | continue; | |
3534 | ||
3535 | if (isr_data->mask & irqstatus) { | |
3536 | isr_data->isr(isr_data->arg, irqstatus); | |
3537 | handledirqs |= isr_data->mask; | |
3538 | } | |
3539 | } | |
3540 | ||
3541 | spin_lock(&dispc.irq_lock); | |
3542 | ||
3543 | unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask; | |
3544 | ||
3545 | if (unhandled_errors) { | |
3546 | dispc.error_irqs |= unhandled_errors; | |
3547 | ||
3548 | dispc.irq_error_mask &= ~unhandled_errors; | |
3549 | _omap_dispc_set_irqs(); | |
3550 | ||
3551 | schedule_work(&dispc.error_work); | |
3552 | } | |
3553 | ||
3554 | spin_unlock(&dispc.irq_lock); | |
affe360d | 3555 | |
3556 | return IRQ_HANDLED; | |
80c39712 TV |
3557 | } |
3558 | ||
3559 | static void dispc_error_worker(struct work_struct *work) | |
3560 | { | |
3561 | int i; | |
3562 | u32 errors; | |
3563 | unsigned long flags; | |
fe3cc9d6 TV |
3564 | static const unsigned fifo_underflow_bits[] = { |
3565 | DISPC_IRQ_GFX_FIFO_UNDERFLOW, | |
3566 | DISPC_IRQ_VID1_FIFO_UNDERFLOW, | |
3567 | DISPC_IRQ_VID2_FIFO_UNDERFLOW, | |
b8c095b4 | 3568 | DISPC_IRQ_VID3_FIFO_UNDERFLOW, |
fe3cc9d6 TV |
3569 | }; |
3570 | ||
80c39712 TV |
3571 | spin_lock_irqsave(&dispc.irq_lock, flags); |
3572 | errors = dispc.error_irqs; | |
3573 | dispc.error_irqs = 0; | |
3574 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
3575 | ||
13eae1f9 DZ |
3576 | dispc_runtime_get(); |
3577 | ||
fe3cc9d6 TV |
3578 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) { |
3579 | struct omap_overlay *ovl; | |
3580 | unsigned bit; | |
80c39712 | 3581 | |
fe3cc9d6 TV |
3582 | ovl = omap_dss_get_overlay(i); |
3583 | bit = fifo_underflow_bits[i]; | |
80c39712 | 3584 | |
fe3cc9d6 TV |
3585 | if (bit & errors) { |
3586 | DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n", | |
3587 | ovl->name); | |
f0e5caab | 3588 | dispc_ovl_enable(ovl->id, false); |
26d9dd0d | 3589 | dispc_mgr_go(ovl->manager->id); |
d7ad718d | 3590 | msleep(50); |
80c39712 TV |
3591 | } |
3592 | } | |
3593 | ||
fe3cc9d6 TV |
3594 | for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { |
3595 | struct omap_overlay_manager *mgr; | |
3596 | unsigned bit; | |
80c39712 | 3597 | |
fe3cc9d6 | 3598 | mgr = omap_dss_get_overlay_manager(i); |
efa70b3b | 3599 | bit = mgr_desc[i].sync_lost_irq; |
80c39712 | 3600 | |
fe3cc9d6 | 3601 | if (bit & errors) { |
794bc4ee | 3602 | struct omap_dss_device *dssdev = mgr->get_device(mgr); |
fe3cc9d6 | 3603 | bool enable; |
80c39712 | 3604 | |
fe3cc9d6 TV |
3605 | DSSERR("SYNC_LOST on channel %s, restarting the output " |
3606 | "with video overlays disabled\n", | |
3607 | mgr->name); | |
2a205f34 | 3608 | |
fe3cc9d6 TV |
3609 | enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE; |
3610 | dssdev->driver->disable(dssdev); | |
2a205f34 | 3611 | |
2a205f34 SS |
3612 | for (i = 0; i < omap_dss_get_num_overlays(); ++i) { |
3613 | struct omap_overlay *ovl; | |
3614 | ovl = omap_dss_get_overlay(i); | |
3615 | ||
fe3cc9d6 TV |
3616 | if (ovl->id != OMAP_DSS_GFX && |
3617 | ovl->manager == mgr) | |
f0e5caab | 3618 | dispc_ovl_enable(ovl->id, false); |
2a205f34 SS |
3619 | } |
3620 | ||
26d9dd0d | 3621 | dispc_mgr_go(mgr->id); |
d7ad718d | 3622 | msleep(50); |
fe3cc9d6 | 3623 | |
2a205f34 SS |
3624 | if (enable) |
3625 | dssdev->driver->enable(dssdev); | |
3626 | } | |
3627 | } | |
3628 | ||
80c39712 TV |
3629 | if (errors & DISPC_IRQ_OCP_ERR) { |
3630 | DSSERR("OCP_ERR\n"); | |
3631 | for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) { | |
3632 | struct omap_overlay_manager *mgr; | |
794bc4ee AT |
3633 | struct omap_dss_device *dssdev; |
3634 | ||
80c39712 | 3635 | mgr = omap_dss_get_overlay_manager(i); |
794bc4ee AT |
3636 | dssdev = mgr->get_device(mgr); |
3637 | ||
3638 | if (dssdev && dssdev->driver) | |
3639 | dssdev->driver->disable(dssdev); | |
80c39712 TV |
3640 | } |
3641 | } | |
3642 | ||
3643 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
3644 | dispc.irq_error_mask |= errors; | |
3645 | _omap_dispc_set_irqs(); | |
3646 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
13eae1f9 DZ |
3647 | |
3648 | dispc_runtime_put(); | |
80c39712 TV |
3649 | } |
3650 | ||
3651 | int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout) | |
3652 | { | |
3653 | void dispc_irq_wait_handler(void *data, u32 mask) | |
3654 | { | |
3655 | complete((struct completion *)data); | |
3656 | } | |
3657 | ||
3658 | int r; | |
3659 | DECLARE_COMPLETION_ONSTACK(completion); | |
3660 | ||
3661 | r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, | |
3662 | irqmask); | |
3663 | ||
3664 | if (r) | |
3665 | return r; | |
3666 | ||
3667 | timeout = wait_for_completion_timeout(&completion, timeout); | |
3668 | ||
3669 | omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); | |
3670 | ||
3671 | if (timeout == 0) | |
3672 | return -ETIMEDOUT; | |
3673 | ||
3674 | if (timeout == -ERESTARTSYS) | |
3675 | return -ERESTARTSYS; | |
3676 | ||
3677 | return 0; | |
3678 | } | |
3679 | ||
3680 | int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask, | |
3681 | unsigned long timeout) | |
3682 | { | |
3683 | void dispc_irq_wait_handler(void *data, u32 mask) | |
3684 | { | |
3685 | complete((struct completion *)data); | |
3686 | } | |
3687 | ||
3688 | int r; | |
3689 | DECLARE_COMPLETION_ONSTACK(completion); | |
3690 | ||
3691 | r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion, | |
3692 | irqmask); | |
3693 | ||
3694 | if (r) | |
3695 | return r; | |
3696 | ||
3697 | timeout = wait_for_completion_interruptible_timeout(&completion, | |
3698 | timeout); | |
3699 | ||
3700 | omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask); | |
3701 | ||
3702 | if (timeout == 0) | |
3703 | return -ETIMEDOUT; | |
3704 | ||
3705 | if (timeout == -ERESTARTSYS) | |
3706 | return -ERESTARTSYS; | |
3707 | ||
3708 | return 0; | |
3709 | } | |
3710 | ||
80c39712 TV |
3711 | static void _omap_dispc_initialize_irq(void) |
3712 | { | |
3713 | unsigned long flags; | |
3714 | ||
3715 | spin_lock_irqsave(&dispc.irq_lock, flags); | |
3716 | ||
3717 | memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr)); | |
3718 | ||
3719 | dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR; | |
2a205f34 SS |
3720 | if (dss_has_feature(FEAT_MGR_LCD2)) |
3721 | dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2; | |
e86d456a CM |
3722 | if (dss_has_feature(FEAT_MGR_LCD3)) |
3723 | dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3; | |
b8c095b4 AT |
3724 | if (dss_feat_get_num_ovls() > 3) |
3725 | dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW; | |
80c39712 TV |
3726 | |
3727 | /* there's SYNC_LOST_DIGIT waiting after enabling the DSS, | |
3728 | * so clear it */ | |
3729 | dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS)); | |
3730 | ||
3731 | _omap_dispc_set_irqs(); | |
3732 | ||
3733 | spin_unlock_irqrestore(&dispc.irq_lock, flags); | |
3734 | } | |
3735 | ||
3736 | void dispc_enable_sidle(void) | |
3737 | { | |
3738 | REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */ | |
3739 | } | |
3740 | ||
3741 | void dispc_disable_sidle(void) | |
3742 | { | |
3743 | REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ | |
3744 | } | |
3745 | ||
3746 | static void _omap_dispc_initial_config(void) | |
3747 | { | |
3748 | u32 l; | |
3749 | ||
0cf35df3 MR |
3750 | /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */ |
3751 | if (dss_has_feature(FEAT_CORE_CLK_DIV)) { | |
3752 | l = dispc_read_reg(DISPC_DIVISOR); | |
3753 | /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */ | |
3754 | l = FLD_MOD(l, 1, 0, 0); | |
3755 | l = FLD_MOD(l, 1, 23, 16); | |
3756 | dispc_write_reg(DISPC_DIVISOR, l); | |
3757 | } | |
3758 | ||
80c39712 | 3759 | /* FUNCGATED */ |
6ced40bf AT |
3760 | if (dss_has_feature(FEAT_FUNCGATED)) |
3761 | REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9); | |
80c39712 | 3762 | |
80c39712 TV |
3763 | _dispc_setup_color_conv_coef(); |
3764 | ||
3765 | dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY); | |
3766 | ||
42a6961c | 3767 | dispc_init_fifos(); |
5ed8cf5b TV |
3768 | |
3769 | dispc_configure_burst_sizes(); | |
54128701 AT |
3770 | |
3771 | dispc_ovl_enable_zorder_planes(); | |
80c39712 TV |
3772 | } |
3773 | ||
dcbe765b CM |
3774 | static const struct dispc_features omap24xx_dispc_feats __initconst = { |
3775 | .sw_start = 5, | |
3776 | .fp_start = 15, | |
3777 | .bp_start = 27, | |
3778 | .sw_max = 64, | |
3779 | .vp_max = 255, | |
3780 | .hp_max = 256, | |
3781 | .calc_scaling = dispc_ovl_calc_scaling_24xx, | |
3782 | .calc_core_clk = calc_core_clk_24xx, | |
42a6961c | 3783 | .num_fifos = 3, |
dcbe765b CM |
3784 | }; |
3785 | ||
3786 | static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = { | |
3787 | .sw_start = 5, | |
3788 | .fp_start = 15, | |
3789 | .bp_start = 27, | |
3790 | .sw_max = 64, | |
3791 | .vp_max = 255, | |
3792 | .hp_max = 256, | |
3793 | .calc_scaling = dispc_ovl_calc_scaling_34xx, | |
3794 | .calc_core_clk = calc_core_clk_34xx, | |
42a6961c | 3795 | .num_fifos = 3, |
dcbe765b CM |
3796 | }; |
3797 | ||
3798 | static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = { | |
3799 | .sw_start = 7, | |
3800 | .fp_start = 19, | |
3801 | .bp_start = 31, | |
3802 | .sw_max = 256, | |
3803 | .vp_max = 4095, | |
3804 | .hp_max = 4096, | |
3805 | .calc_scaling = dispc_ovl_calc_scaling_34xx, | |
3806 | .calc_core_clk = calc_core_clk_34xx, | |
42a6961c | 3807 | .num_fifos = 3, |
dcbe765b CM |
3808 | }; |
3809 | ||
3810 | static const struct dispc_features omap44xx_dispc_feats __initconst = { | |
3811 | .sw_start = 7, | |
3812 | .fp_start = 19, | |
3813 | .bp_start = 31, | |
3814 | .sw_max = 256, | |
3815 | .vp_max = 4095, | |
3816 | .hp_max = 4096, | |
3817 | .calc_scaling = dispc_ovl_calc_scaling_44xx, | |
3818 | .calc_core_clk = calc_core_clk_44xx, | |
42a6961c | 3819 | .num_fifos = 5, |
66a0f9e4 | 3820 | .gfx_fifo_workaround = true, |
dcbe765b CM |
3821 | }; |
3822 | ||
3823 | static int __init dispc_init_features(struct device *dev) | |
3824 | { | |
3825 | const struct dispc_features *src; | |
3826 | struct dispc_features *dst; | |
3827 | ||
3828 | dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL); | |
3829 | if (!dst) { | |
3830 | dev_err(dev, "Failed to allocate DISPC Features\n"); | |
3831 | return -ENOMEM; | |
3832 | } | |
3833 | ||
3834 | if (cpu_is_omap24xx()) { | |
3835 | src = &omap24xx_dispc_feats; | |
3836 | } else if (cpu_is_omap34xx()) { | |
3837 | if (omap_rev() < OMAP3430_REV_ES3_0) | |
3838 | src = &omap34xx_rev1_0_dispc_feats; | |
3839 | else | |
3840 | src = &omap34xx_rev3_0_dispc_feats; | |
3841 | } else if (cpu_is_omap44xx()) { | |
3842 | src = &omap44xx_dispc_feats; | |
23362832 AT |
3843 | } else if (soc_is_omap54xx()) { |
3844 | src = &omap44xx_dispc_feats; | |
dcbe765b CM |
3845 | } else { |
3846 | return -ENODEV; | |
3847 | } | |
3848 | ||
3849 | memcpy(dst, src, sizeof(*dst)); | |
3850 | dispc.feat = dst; | |
3851 | ||
3852 | return 0; | |
3853 | } | |
3854 | ||
060b6d9c | 3855 | /* DISPC HW IP initialisation */ |
6e7e8f06 | 3856 | static int __init omap_dispchw_probe(struct platform_device *pdev) |
060b6d9c SG |
3857 | { |
3858 | u32 rev; | |
affe360d | 3859 | int r = 0; |
ea9da36a | 3860 | struct resource *dispc_mem; |
4fbafaf3 | 3861 | struct clk *clk; |
ea9da36a | 3862 | |
060b6d9c SG |
3863 | dispc.pdev = pdev; |
3864 | ||
dcbe765b CM |
3865 | r = dispc_init_features(&dispc.pdev->dev); |
3866 | if (r) | |
3867 | return r; | |
3868 | ||
060b6d9c SG |
3869 | spin_lock_init(&dispc.irq_lock); |
3870 | ||
3871 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
3872 | spin_lock_init(&dispc.irq_stats_lock); | |
3873 | dispc.irq_stats.last_reset = jiffies; | |
3874 | #endif | |
3875 | ||
3876 | INIT_WORK(&dispc.error_work, dispc_error_worker); | |
3877 | ||
ea9da36a SG |
3878 | dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0); |
3879 | if (!dispc_mem) { | |
3880 | DSSERR("can't get IORESOURCE_MEM DISPC\n"); | |
cd3b3449 | 3881 | return -EINVAL; |
ea9da36a | 3882 | } |
cd3b3449 | 3883 | |
6e2a14d2 JL |
3884 | dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start, |
3885 | resource_size(dispc_mem)); | |
060b6d9c SG |
3886 | if (!dispc.base) { |
3887 | DSSERR("can't ioremap DISPC\n"); | |
cd3b3449 | 3888 | return -ENOMEM; |
affe360d | 3889 | } |
cd3b3449 | 3890 | |
affe360d | 3891 | dispc.irq = platform_get_irq(dispc.pdev, 0); |
3892 | if (dispc.irq < 0) { | |
3893 | DSSERR("platform_get_irq failed\n"); | |
cd3b3449 | 3894 | return -ENODEV; |
affe360d | 3895 | } |
3896 | ||
6e2a14d2 JL |
3897 | r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler, |
3898 | IRQF_SHARED, "OMAP DISPC", dispc.pdev); | |
affe360d | 3899 | if (r < 0) { |
3900 | DSSERR("request_irq failed\n"); | |
cd3b3449 TV |
3901 | return r; |
3902 | } | |
3903 | ||
3904 | clk = clk_get(&pdev->dev, "fck"); | |
3905 | if (IS_ERR(clk)) { | |
3906 | DSSERR("can't get fck\n"); | |
3907 | r = PTR_ERR(clk); | |
3908 | return r; | |
060b6d9c SG |
3909 | } |
3910 | ||
cd3b3449 TV |
3911 | dispc.dss_clk = clk; |
3912 | ||
4fbafaf3 TV |
3913 | pm_runtime_enable(&pdev->dev); |
3914 | ||
3915 | r = dispc_runtime_get(); | |
3916 | if (r) | |
3917 | goto err_runtime_get; | |
060b6d9c SG |
3918 | |
3919 | _omap_dispc_initial_config(); | |
3920 | ||
3921 | _omap_dispc_initialize_irq(); | |
3922 | ||
060b6d9c | 3923 | rev = dispc_read_reg(DISPC_REVISION); |
a06b62f8 | 3924 | dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", |
060b6d9c SG |
3925 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
3926 | ||
4fbafaf3 | 3927 | dispc_runtime_put(); |
060b6d9c | 3928 | |
e40402cf TV |
3929 | dss_debugfs_create_file("dispc", dispc_dump_regs); |
3930 | ||
3931 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
3932 | dss_debugfs_create_file("dispc_irq", dispc_dump_irqs); | |
3933 | #endif | |
060b6d9c | 3934 | return 0; |
4fbafaf3 TV |
3935 | |
3936 | err_runtime_get: | |
3937 | pm_runtime_disable(&pdev->dev); | |
4fbafaf3 | 3938 | clk_put(dispc.dss_clk); |
affe360d | 3939 | return r; |
060b6d9c SG |
3940 | } |
3941 | ||
6e7e8f06 | 3942 | static int __exit omap_dispchw_remove(struct platform_device *pdev) |
060b6d9c | 3943 | { |
4fbafaf3 TV |
3944 | pm_runtime_disable(&pdev->dev); |
3945 | ||
3946 | clk_put(dispc.dss_clk); | |
3947 | ||
060b6d9c SG |
3948 | return 0; |
3949 | } | |
3950 | ||
4fbafaf3 TV |
3951 | static int dispc_runtime_suspend(struct device *dev) |
3952 | { | |
3953 | dispc_save_context(); | |
4fbafaf3 TV |
3954 | |
3955 | return 0; | |
3956 | } | |
3957 | ||
3958 | static int dispc_runtime_resume(struct device *dev) | |
3959 | { | |
49ea86f3 | 3960 | dispc_restore_context(); |
4fbafaf3 TV |
3961 | |
3962 | return 0; | |
3963 | } | |
3964 | ||
3965 | static const struct dev_pm_ops dispc_pm_ops = { | |
3966 | .runtime_suspend = dispc_runtime_suspend, | |
3967 | .runtime_resume = dispc_runtime_resume, | |
3968 | }; | |
3969 | ||
060b6d9c | 3970 | static struct platform_driver omap_dispchw_driver = { |
6e7e8f06 | 3971 | .remove = __exit_p(omap_dispchw_remove), |
060b6d9c SG |
3972 | .driver = { |
3973 | .name = "omapdss_dispc", | |
3974 | .owner = THIS_MODULE, | |
4fbafaf3 | 3975 | .pm = &dispc_pm_ops, |
060b6d9c SG |
3976 | }, |
3977 | }; | |
3978 | ||
6e7e8f06 | 3979 | int __init dispc_init_platform_driver(void) |
060b6d9c | 3980 | { |
11436e1d | 3981 | return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe); |
060b6d9c SG |
3982 | } |
3983 | ||
6e7e8f06 | 3984 | void __exit dispc_uninit_platform_driver(void) |
060b6d9c | 3985 | { |
04c742c3 | 3986 | platform_driver_unregister(&omap_dispchw_driver); |
060b6d9c | 3987 | } |