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OMAPDSS: apply fixes
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
33366d0e 38#include <linux/sizes.h>
80c39712 39
a0b38cc4 40#include <video/omapdss.h>
80c39712
TV		 41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
9b372c2d 44#include "dispc.h"
80c39712
TV		 45
46/* DISPC */
8613b000 47#define DISPC_SZ_REGS SZ_4K
80c39712 48
5ed8cf5b
TV		 49enum omap_burst_size {
50 BURST_SIZE_X2 = 0,
51 BURST_SIZE_X4 = 1,
52 BURST_SIZE_X8 = 2,
53};
54
80c39712
TV		 55#define REG_GET(idx, start, end) \
56 FLD_GET(dispc_read_reg(idx), start, end)
57
58#define REG_FLD_MOD(idx, val, start, end) \
59 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
60
dcbe765b
CM		 61struct dispc_features {
62 u8 sw_start;
63 u8 fp_start;
64 u8 bp_start;
65 u16 sw_max;
66 u16 vp_max;
67 u16 hp_max;
33b89928
AT		 68 u8 mgr_width_start;
69 u8 mgr_height_start;
70 u16 mgr_width_max;
71 u16 mgr_height_max;
ca5ca69c
AT		 72 unsigned long max_lcd_pclk;
73 unsigned long max_tv_pclk;
0c6921de 74 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 75 const struct omap_video_timings *mgr_timings,
76 u16 width, u16 height, u16 out_width, u16 out_height,
77 enum omap_color_mode color_mode, bool *five_taps,
78 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 79 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
8702ee50 80 unsigned long (*calc_core_clk) (unsigned long pclk,
8ba85306
AT		 81 u16 width, u16 height, u16 out_width, u16 out_height,
82 bool mem_to_mem);
42a6961c 83 u8 num_fifos;
66a0f9e4
TV		 84
85 /* swap GFX & WB fifos */
86 bool gfx_fifo_workaround:1;
cffa947d
TV		 87
88 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
89 bool no_framedone_tv:1;
d0df9a2c
AT		 90
91 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
92 bool mstandby_workaround:1;
dcbe765b
CM		 93};
94
42a6961c
TV		 95#define DISPC_MAX_NR_FIFOS 5
96
80c39712 97static struct {
060b6d9c 98 struct platform_device *pdev;
80c39712 99 void __iomem *base;
4fbafaf3
TV		 100
101 int ctx_loss_cnt;
102
affe360d 103 int irq;
80c39712 104
7b3926b3 105 unsigned long core_clk_rate;
5391e87d 106 unsigned long tv_pclk_rate;
7b3926b3 107
42a6961c
TV		 108 u32 fifo_size[DISPC_MAX_NR_FIFOS];
109 /* maps which plane is using a fifo. fifo-id -> plane-id */
110 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712 111
49ea86f3 112 bool ctx_valid;
80c39712 113 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 114
dcbe765b 115 const struct dispc_features *feat;
80c39712
TV		 116} dispc;
117
0d66cbb5
AJ		 118enum omap_color_component {
119 /* used for all color formats for OMAP3 and earlier
120 * and for RGB and Y color component on OMAP4
121 */
122 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
123 /* used for UV component for
124 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
125 * color formats on OMAP4
126 */
127 DISPC_COLOR_COMPONENT_UV = 1 << 1,
128};
129
efa70b3b
CM		 130enum mgr_reg_fields {
131 DISPC_MGR_FLD_ENABLE,
132 DISPC_MGR_FLD_STNTFT,
133 DISPC_MGR_FLD_GO,
134 DISPC_MGR_FLD_TFTDATALINES,
135 DISPC_MGR_FLD_STALLMODE,
136 DISPC_MGR_FLD_TCKENABLE,
137 DISPC_MGR_FLD_TCKSELECTION,
138 DISPC_MGR_FLD_CPR,
139 DISPC_MGR_FLD_FIFOHANDCHECK,
140 /* used to maintain a count of the above fields */
141 DISPC_MGR_FLD_NUM,
142};
143
144static const struct {
145 const char *name;
146 u32 vsync_irq;
147 u32 framedone_irq;
148 u32 sync_lost_irq;
149 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
150} mgr_desc[] = {
151 [OMAP_DSS_CHANNEL_LCD] = {
152 .name = "LCD",
153 .vsync_irq = DISPC_IRQ_VSYNC,
154 .framedone_irq = DISPC_IRQ_FRAMEDONE,
155 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
156 .reg_desc = {
157 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
158 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
159 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
160 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
161 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
162 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
163 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
164 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
165 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
166 },
167 },
168 [OMAP_DSS_CHANNEL_DIGIT] = {
169 .name = "DIGIT",
170 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
cffa947d 171 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
efa70b3b
CM		 172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
173 .reg_desc = {
174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
175 [DISPC_MGR_FLD_STNTFT] = { },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
177 [DISPC_MGR_FLD_TFTDATALINES] = { },
178 [DISPC_MGR_FLD_STALLMODE] = { },
179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
181 [DISPC_MGR_FLD_CPR] = { },
182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
183 },
184 },
185 [OMAP_DSS_CHANNEL_LCD2] = {
186 .name = "LCD2",
187 .vsync_irq = DISPC_IRQ_VSYNC2,
188 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
190 .reg_desc = {
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
192 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
194 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
195 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
198 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
200 },
201 },
e86d456a
CM		 202 [OMAP_DSS_CHANNEL_LCD3] = {
203 .name = "LCD3",
204 .vsync_irq = DISPC_IRQ_VSYNC3,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
207 .reg_desc = {
208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
217 },
218 },
efa70b3b
CM		 219};
220
6e5264b0
AT		 221struct color_conv_coef {
222 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
223 int full_range;
224};
225
3e8a6ff2
AT		 226static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
227static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 228
55978cc2 229static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 230{
55978cc2 231 __raw_writel(val, dispc.base + idx);
80c39712
TV		 232}
233
55978cc2 234static inline u32 dispc_read_reg(const u16 idx)
80c39712 235{
55978cc2 236 return __raw_readl(dispc.base + idx);
80c39712
TV		 237}
238
efa70b3b
CM		 239static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
240{
241 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
242 return REG_GET(rfld.reg, rfld.high, rfld.low);
243}
244
245static void mgr_fld_write(enum omap_channel channel,
246 enum mgr_reg_fields regfld, int val) {
247 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
248 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
249}
250
80c39712 251#define SR(reg) \
55978cc2 252 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 253#define RR(reg) \
55978cc2 254 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 255
4fbafaf3 256static void dispc_save_context(void)
80c39712 257{
c6104b8e 258 int i, j;
80c39712 259
4fbafaf3
TV		 260 DSSDBG("dispc_save_context\n");
261
80c39712
TV		 262 SR(IRQENABLE);
263 SR(CONTROL);
264 SR(CONFIG);
80c39712 265 SR(LINE_NUMBER);
11354dd5
AT		 266 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
267 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 268 SR(GLOBAL_ALPHA);
2a205f34
SS		 269 if (dss_has_feature(FEAT_MGR_LCD2)) {
270 SR(CONTROL2);
2a205f34
SS		 271 SR(CONFIG2);
272 }
e86d456a
CM		 273 if (dss_has_feature(FEAT_MGR_LCD3)) {
274 SR(CONTROL3);
275 SR(CONFIG3);
276 }
80c39712 277
c6104b8e
AT		 278 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
279 SR(DEFAULT_COLOR(i));
280 SR(TRANS_COLOR(i));
281 SR(SIZE_MGR(i));
282 if (i == OMAP_DSS_CHANNEL_DIGIT)
283 continue;
284 SR(TIMING_H(i));
285 SR(TIMING_V(i));
286 SR(POL_FREQ(i));
287 SR(DIVISORo(i));
288
289 SR(DATA_CYCLE1(i));
290 SR(DATA_CYCLE2(i));
291 SR(DATA_CYCLE3(i));
292
332e9d70 293 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 294 SR(CPR_COEF_R(i));
295 SR(CPR_COEF_G(i));
296 SR(CPR_COEF_B(i));
332e9d70 297 }
2a205f34 298 }
80c39712 299
c6104b8e
AT		 300 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
301 SR(OVL_BA0(i));
302 SR(OVL_BA1(i));
303 SR(OVL_POSITION(i));
304 SR(OVL_SIZE(i));
305 SR(OVL_ATTRIBUTES(i));
306 SR(OVL_FIFO_THRESHOLD(i));
307 SR(OVL_ROW_INC(i));
308 SR(OVL_PIXEL_INC(i));
309 if (dss_has_feature(FEAT_PRELOAD))
310 SR(OVL_PRELOAD(i));
311 if (i == OMAP_DSS_GFX) {
312 SR(OVL_WINDOW_SKIP(i));
313 SR(OVL_TABLE_BA(i));
314 continue;
315 }
316 SR(OVL_FIR(i));
317 SR(OVL_PICTURE_SIZE(i));
318 SR(OVL_ACCU0(i));
319 SR(OVL_ACCU1(i));
9b372c2d 320
c6104b8e
AT		 321 for (j = 0; j < 8; j++)
322 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 323
c6104b8e
AT		 324 for (j = 0; j < 8; j++)
325 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 326
c6104b8e
AT		 327 for (j = 0; j < 5; j++)
328 SR(OVL_CONV_COEF(i, j));
ab5ca071 329
c6104b8e
AT		 330 if (dss_has_feature(FEAT_FIR_COEF_V)) {
331 for (j = 0; j < 8; j++)
332 SR(OVL_FIR_COEF_V(i, j));
333 }
9b372c2d 334
c6104b8e
AT		 335 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
336 SR(OVL_BA0_UV(i));
337 SR(OVL_BA1_UV(i));
338 SR(OVL_FIR2(i));
339 SR(OVL_ACCU2_0(i));
340 SR(OVL_ACCU2_1(i));
ab5ca071 341
c6104b8e
AT		 342 for (j = 0; j < 8; j++)
343 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 344
c6104b8e
AT		 345 for (j = 0; j < 8; j++)
346 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 347
c6104b8e
AT		 348 for (j = 0; j < 8; j++)
349 SR(OVL_FIR_COEF_V2(i, j));
350 }
351 if (dss_has_feature(FEAT_ATTR2))
352 SR(OVL_ATTRIBUTES2(i));
ab5ca071 353 }
0cf35df3
MR		 354
355 if (dss_has_feature(FEAT_CORE_CLK_DIV))
356 SR(DIVISOR);
49ea86f3 357
bdb736ab 358 dispc.ctx_loss_cnt = dss_get_ctx_loss_count();
49ea86f3
TV		 359 dispc.ctx_valid = true;
360
361 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 362}
363
4fbafaf3 364static void dispc_restore_context(void)
80c39712 365{
c6104b8e 366 int i, j, ctx;
4fbafaf3
TV		 367
368 DSSDBG("dispc_restore_context\n");
369
49ea86f3
TV		 370 if (!dispc.ctx_valid)
371 return;
372
bdb736ab 373 ctx = dss_get_ctx_loss_count();
49ea86f3
TV		 374
375 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
376 return;
377
378 DSSDBG("ctx_loss_count: saved %d, current %d\n",
379 dispc.ctx_loss_cnt, ctx);
380
75c7d59d 381 /*RR(IRQENABLE);*/
80c39712
TV		 382 /*RR(CONTROL);*/
383 RR(CONFIG);
80c39712 384 RR(LINE_NUMBER);
11354dd5
AT		 385 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
386 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 387 RR(GLOBAL_ALPHA);
c6104b8e 388 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 389 RR(CONFIG2);
e86d456a
CM		 390 if (dss_has_feature(FEAT_MGR_LCD3))
391 RR(CONFIG3);
80c39712 392
c6104b8e
AT		 393 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
394 RR(DEFAULT_COLOR(i));
395 RR(TRANS_COLOR(i));
396 RR(SIZE_MGR(i));
397 if (i == OMAP_DSS_CHANNEL_DIGIT)
398 continue;
399 RR(TIMING_H(i));
400 RR(TIMING_V(i));
401 RR(POL_FREQ(i));
402 RR(DIVISORo(i));
403
404 RR(DATA_CYCLE1(i));
405 RR(DATA_CYCLE2(i));
406 RR(DATA_CYCLE3(i));
2a205f34 407
332e9d70 408 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 409 RR(CPR_COEF_R(i));
410 RR(CPR_COEF_G(i));
411 RR(CPR_COEF_B(i));
332e9d70 412 }
2a205f34 413 }
80c39712 414
c6104b8e
AT		 415 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
416 RR(OVL_BA0(i));
417 RR(OVL_BA1(i));
418 RR(OVL_POSITION(i));
419 RR(OVL_SIZE(i));
420 RR(OVL_ATTRIBUTES(i));
421 RR(OVL_FIFO_THRESHOLD(i));
422 RR(OVL_ROW_INC(i));
423 RR(OVL_PIXEL_INC(i));
424 if (dss_has_feature(FEAT_PRELOAD))
425 RR(OVL_PRELOAD(i));
426 if (i == OMAP_DSS_GFX) {
427 RR(OVL_WINDOW_SKIP(i));
428 RR(OVL_TABLE_BA(i));
429 continue;
430 }
431 RR(OVL_FIR(i));
432 RR(OVL_PICTURE_SIZE(i));
433 RR(OVL_ACCU0(i));
434 RR(OVL_ACCU1(i));
9b372c2d 435
c6104b8e
AT		 436 for (j = 0; j < 8; j++)
437 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 438
c6104b8e
AT		 439 for (j = 0; j < 8; j++)
440 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 441
c6104b8e
AT		 442 for (j = 0; j < 5; j++)
443 RR(OVL_CONV_COEF(i, j));
ab5ca071 444
c6104b8e
AT		 445 if (dss_has_feature(FEAT_FIR_COEF_V)) {
446 for (j = 0; j < 8; j++)
447 RR(OVL_FIR_COEF_V(i, j));
448 }
9b372c2d 449
c6104b8e
AT		 450 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
451 RR(OVL_BA0_UV(i));
452 RR(OVL_BA1_UV(i));
453 RR(OVL_FIR2(i));
454 RR(OVL_ACCU2_0(i));
455 RR(OVL_ACCU2_1(i));
ab5ca071 456
c6104b8e
AT		 457 for (j = 0; j < 8; j++)
458 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 459
c6104b8e
AT		 460 for (j = 0; j < 8; j++)
461 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 462
c6104b8e
AT		 463 for (j = 0; j < 8; j++)
464 RR(OVL_FIR_COEF_V2(i, j));
465 }
466 if (dss_has_feature(FEAT_ATTR2))
467 RR(OVL_ATTRIBUTES2(i));
ab5ca071 468 }
80c39712 469
0cf35df3
MR		 470 if (dss_has_feature(FEAT_CORE_CLK_DIV))
471 RR(DIVISOR);
472
80c39712
TV		 473 /* enable last, because LCD & DIGIT enable are here */
474 RR(CONTROL);
2a205f34
SS		 475 if (dss_has_feature(FEAT_MGR_LCD2))
476 RR(CONTROL2);
e86d456a
CM		 477 if (dss_has_feature(FEAT_MGR_LCD3))
478 RR(CONTROL3);
75c7d59d 479 /* clear spurious SYNC_LOST_DIGIT interrupts */
4e0397cf 480 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
75c7d59d
VS		 481
482 /*
483 * enable last so IRQs won't trigger before
484 * the context is fully restored
485 */
486 RR(IRQENABLE);
49ea86f3
TV		 487
488 DSSDBG("context restored\n");
80c39712
TV		 489}
490
491#undef SR
492#undef RR
493
4fbafaf3
TV		 494int dispc_runtime_get(void)
495{
496 int r;
497
498 DSSDBG("dispc_runtime_get\n");
499
500 r = pm_runtime_get_sync(&dispc.pdev->dev);
501 WARN_ON(r < 0);
502 return r < 0 ? r : 0;
503}
348be69d 504EXPORT_SYMBOL(dispc_runtime_get);
4fbafaf3
TV		 505
506void dispc_runtime_put(void)
507{
508 int r;
509
510 DSSDBG("dispc_runtime_put\n");
511
0eaf9f52 512 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 513 WARN_ON(r < 0 && r != -ENOSYS);
80c39712 514}
348be69d 515EXPORT_SYMBOL(dispc_runtime_put);
80c39712 516
3dcec4d6
TV		 517u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
518{
efa70b3b 519 return mgr_desc[channel].vsync_irq;
3dcec4d6 520}
348be69d 521EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
3dcec4d6 522
7d1365c9
TV		 523u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
524{
cffa947d
TV		 525 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
526 return 0;
527
efa70b3b 528 return mgr_desc[channel].framedone_irq;
7d1365c9 529}
348be69d 530EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
7d1365c9 531
cb699200
TV		 532u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
533{
534 return mgr_desc[channel].sync_lost_irq;
535}
348be69d 536EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
cb699200 537
0b23e5b8
AT		 538u32 dispc_wb_get_framedone_irq(void)
539{
540 return DISPC_IRQ_FRAMEDONEWB;
541}
542
26d9dd0d 543bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 544{
efa70b3b 545 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712 546}
348be69d 547EXPORT_SYMBOL(dispc_mgr_go_busy);
80c39712 548
26d9dd0d 549void dispc_mgr_go(enum omap_channel channel)
80c39712 550{
3c91ee8c
TV		 551 WARN_ON(dispc_mgr_is_enabled(channel) == false);
552 WARN_ON(dispc_mgr_go_busy(channel));
80c39712 553
efa70b3b 554 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 555
efa70b3b 556 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712 557}
348be69d 558EXPORT_SYMBOL(dispc_mgr_go);
80c39712 559
0b23e5b8
AT		 560bool dispc_wb_go_busy(void)
561{
562 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
563}
564
565void dispc_wb_go(void)
566{
567 enum omap_plane plane = OMAP_DSS_WB;
568 bool enable, go;
569
570 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
571
572 if (!enable)
573 return;
574
575 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
576 if (go) {
577 DSSERR("GO bit not down for WB\n");
578 return;
579 }
580
581 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
582}
583
f0e5caab 584static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 585{
9b372c2d 586 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 587}
588
f0e5caab 589static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 590{
9b372c2d 591 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 592}
593
f0e5caab 594static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 595{
9b372c2d 596 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 597}
598
f0e5caab 599static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 600{
601 BUG_ON(plane == OMAP_DSS_GFX);
602
603 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
604}
605
f0e5caab
TV		 606static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
607 u32 value)
ab5ca071
AJ		 608{
609 BUG_ON(plane == OMAP_DSS_GFX);
610
611 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
612}
613
f0e5caab 614static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 615{
616 BUG_ON(plane == OMAP_DSS_GFX);
617
618 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
619}
620
debd9074
CM		 621static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
622 int fir_vinc, int five_taps,
623 enum omap_color_component color_comp)
80c39712 624{
debd9074 625 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 626 int i;
627
debd9074
CM		 628 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
629 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 630
631 for (i = 0; i < 8; i++) {
632 u32 h, hv;
633
debd9074
CM		 634 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
635 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
636 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
637 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
638 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
639 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
640 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
641 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 642
0d66cbb5 643 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 644 dispc_ovl_write_firh_reg(plane, i, h);
645 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 646 } else {
f0e5caab
TV		 647 dispc_ovl_write_firh2_reg(plane, i, h);
648 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 649 }
650
80c39712
TV		 651 }
652
66be8f6c
GI		 653 if (five_taps) {
654 for (i = 0; i < 8; i++) {
655 u32 v;
debd9074
CM		 656 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
657 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 658 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 659 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 660 else
f0e5caab 661 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 662 }
80c39712
TV		 663 }
664}
665
80c39712 666
6e5264b0
AT		 667static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
668 const struct color_conv_coef *ct)
669{
80c39712
TV		 670#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
671
6e5264b0
AT		 672 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
673 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
674 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
675 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
676 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 677
6e5264b0 678 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 679
680#undef CVAL
80c39712
TV		 681}
682
6e5264b0
AT		 683static void dispc_setup_color_conv_coef(void)
684{
685 int i;
686 int num_ovl = dss_feat_get_num_ovls();
687 int num_wb = dss_feat_get_num_wbs();
688 const struct color_conv_coef ctbl_bt601_5_ovl = {
689 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
690 };
691 const struct color_conv_coef ctbl_bt601_5_wb = {
692 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
693 };
694
695 for (i = 1; i < num_ovl; i++)
696 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
697
698 for (; i < num_wb; i++)
699 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
700}
80c39712 701
f0e5caab 702static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 703{
9b372c2d 704 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 705}
706
f0e5caab 707static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 708{
9b372c2d 709 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 710}
711
f0e5caab 712static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 713{
714 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
715}
716
f0e5caab 717static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 718{
719 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
720}
721
d79db853
AT		 722static void dispc_ovl_set_pos(enum omap_plane plane,
723 enum omap_overlay_caps caps, int x, int y)
80c39712 724{
d79db853
AT		 725 u32 val;
726
727 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
728 return;
729
730 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 731
732 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 733}
734
78b687fc
AT		 735static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
736 int height)
80c39712 737{
80c39712 738 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 739
36d87d95 740 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 741 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
742 else
743 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 744}
745
78b687fc
AT		 746static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
747 int height)
80c39712
TV		 748{
749 u32 val;
80c39712
TV		 750
751 BUG_ON(plane == OMAP_DSS_GFX);
752
753 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 754
36d87d95
AT		 755 if (plane == OMAP_DSS_WB)
756 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
757 else
758 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 759}
760
5b54ed3e
AT		 761static void dispc_ovl_set_zorder(enum omap_plane plane,
762 enum omap_overlay_caps caps, u8 zorder)
54128701 763{
5b54ed3e 764 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 765 return;
766
767 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
768}
769
770static void dispc_ovl_enable_zorder_planes(void)
771{
772 int i;
773
774 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
775 return;
776
777 for (i = 0; i < dss_feat_get_num_ovls(); i++)
778 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
779}
780
5b54ed3e
AT		 781static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
782 enum omap_overlay_caps caps, bool enable)
fd28a390 783{
5b54ed3e 784 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 785 return;
786
9b372c2d 787 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 788}
789
5b54ed3e
AT		 790static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
791 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 792{
b8c095b4 793 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 794 int shift;
795
5b54ed3e 796 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 797 return;
a0acb557 798
fe3cc9d6
TV		 799 shift = shifts[plane];
800 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 801}
802
f0e5caab 803static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 804{
9b372c2d 805 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 806}
807
f0e5caab 808static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 809{
9b372c2d 810 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 811}
812
f0e5caab 813static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 814 enum omap_color_mode color_mode)
815{
816 u32 m = 0;
f20e4220
AJ		 817 if (plane != OMAP_DSS_GFX) {
818 switch (color_mode) {
819 case OMAP_DSS_COLOR_NV12:
820 m = 0x0; break;
08f3267e 821 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 822 m = 0x1; break;
823 case OMAP_DSS_COLOR_RGBA16:
824 m = 0x2; break;
08f3267e 825 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 826 m = 0x4; break;
827 case OMAP_DSS_COLOR_ARGB16:
828 m = 0x5; break;
829 case OMAP_DSS_COLOR_RGB16:
830 m = 0x6; break;
831 case OMAP_DSS_COLOR_ARGB16_1555:
832 m = 0x7; break;
833 case OMAP_DSS_COLOR_RGB24U:
834 m = 0x8; break;
835 case OMAP_DSS_COLOR_RGB24P:
836 m = 0x9; break;
837 case OMAP_DSS_COLOR_YUV2:
838 m = 0xa; break;
839 case OMAP_DSS_COLOR_UYVY:
840 m = 0xb; break;
841 case OMAP_DSS_COLOR_ARGB32:
842 m = 0xc; break;
843 case OMAP_DSS_COLOR_RGBA32:
844 m = 0xd; break;
845 case OMAP_DSS_COLOR_RGBX32:
846 m = 0xe; break;
847 case OMAP_DSS_COLOR_XRGB16_1555:
848 m = 0xf; break;
849 default:
c6eee968 850 BUG(); return;
f20e4220
AJ		 851 }
852 } else {
853 switch (color_mode) {
854 case OMAP_DSS_COLOR_CLUT1:
855 m = 0x0; break;
856 case OMAP_DSS_COLOR_CLUT2:
857 m = 0x1; break;
858 case OMAP_DSS_COLOR_CLUT4:
859 m = 0x2; break;
860 case OMAP_DSS_COLOR_CLUT8:
861 m = 0x3; break;
862 case OMAP_DSS_COLOR_RGB12U:
863 m = 0x4; break;
864 case OMAP_DSS_COLOR_ARGB16:
865 m = 0x5; break;
866 case OMAP_DSS_COLOR_RGB16:
867 m = 0x6; break;
868 case OMAP_DSS_COLOR_ARGB16_1555:
869 m = 0x7; break;
870 case OMAP_DSS_COLOR_RGB24U:
871 m = 0x8; break;
872 case OMAP_DSS_COLOR_RGB24P:
873 m = 0x9; break;
08f3267e 874 case OMAP_DSS_COLOR_RGBX16:
f20e4220 875 m = 0xa; break;
08f3267e 876 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 877 m = 0xb; break;
878 case OMAP_DSS_COLOR_ARGB32:
879 m = 0xc; break;
880 case OMAP_DSS_COLOR_RGBA32:
881 m = 0xd; break;
882 case OMAP_DSS_COLOR_RGBX32:
883 m = 0xe; break;
884 case OMAP_DSS_COLOR_XRGB16_1555:
885 m = 0xf; break;
886 default:
c6eee968 887 BUG(); return;
f20e4220 888 }
80c39712
TV		 889 }
890
9b372c2d 891 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 892}
893
65e006ff
CM		 894static void dispc_ovl_configure_burst_type(enum omap_plane plane,
895 enum omap_dss_rotation_type rotation_type)
896{
897 if (dss_has_feature(FEAT_BURST_2D) == 0)
898 return;
899
900 if (rotation_type == OMAP_DSS_ROT_TILER)
901 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
902 else
903 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
904}
905
f427984e 906void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 907{
908 int shift;
909 u32 val;
2a205f34 910 int chan = 0, chan2 = 0;
80c39712
TV		 911
912 switch (plane) {
913 case OMAP_DSS_GFX:
914 shift = 8;
915 break;
916 case OMAP_DSS_VIDEO1:
917 case OMAP_DSS_VIDEO2:
b8c095b4 918 case OMAP_DSS_VIDEO3:
80c39712
TV		 919 shift = 16;
920 break;
921 default:
922 BUG();
923 return;
924 }
925
9b372c2d 926 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 927 if (dss_has_feature(FEAT_MGR_LCD2)) {
928 switch (channel) {
929 case OMAP_DSS_CHANNEL_LCD:
930 chan = 0;
931 chan2 = 0;
932 break;
933 case OMAP_DSS_CHANNEL_DIGIT:
934 chan = 1;
935 chan2 = 0;
936 break;
937 case OMAP_DSS_CHANNEL_LCD2:
938 chan = 0;
939 chan2 = 1;
940 break;
e86d456a
CM		 941 case OMAP_DSS_CHANNEL_LCD3:
942 if (dss_has_feature(FEAT_MGR_LCD3)) {
943 chan = 0;
944 chan2 = 2;
945 } else {
946 BUG();
947 return;
948 }
949 break;
2a205f34
SS		 950 default:
951 BUG();
c6eee968 952 return;
2a205f34
SS		 953 }
954
955 val = FLD_MOD(val, chan, shift, shift);
956 val = FLD_MOD(val, chan2, 31, 30);
957 } else {
958 val = FLD_MOD(val, channel, shift, shift);
959 }
9b372c2d 960 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712 961}
348be69d 962EXPORT_SYMBOL(dispc_ovl_set_channel_out);
80c39712 963
2cc5d1af
TV		 964static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
965{
966 int shift;
967 u32 val;
968 enum omap_channel channel;
969
970 switch (plane) {
971 case OMAP_DSS_GFX:
972 shift = 8;
973 break;
974 case OMAP_DSS_VIDEO1:
975 case OMAP_DSS_VIDEO2:
976 case OMAP_DSS_VIDEO3:
977 shift = 16;
978 break;
979 default:
980 BUG();
c6eee968 981 return 0;
2cc5d1af
TV		 982 }
983
984 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
985
e86d456a
CM		 986 if (dss_has_feature(FEAT_MGR_LCD3)) {
987 if (FLD_GET(val, 31, 30) == 0)
988 channel = FLD_GET(val, shift, shift);
989 else if (FLD_GET(val, 31, 30) == 1)
990 channel = OMAP_DSS_CHANNEL_LCD2;
991 else
992 channel = OMAP_DSS_CHANNEL_LCD3;
993 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 994 if (FLD_GET(val, 31, 30) == 0)
995 channel = FLD_GET(val, shift, shift);
996 else
997 channel = OMAP_DSS_CHANNEL_LCD2;
998 } else {
999 channel = FLD_GET(val, shift, shift);
1000 }
1001
1002 return channel;
1003}
1004
d9ac773c
AT		 1005void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1006{
1007 enum omap_plane plane = OMAP_DSS_WB;
1008
1009 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1010}
1011
f0e5caab 1012static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1013 enum omap_burst_size burst_size)
1014{
8bbe09ee 1015 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1016 int shift;
80c39712 1017
fe3cc9d6 1018 shift = shifts[plane];
5ed8cf5b 1019 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1020}
1021
5ed8cf5b
TV		 1022static void dispc_configure_burst_sizes(void)
1023{
1024 int i;
1025 const int burst_size = BURST_SIZE_X8;
1026
1027 /* Configure burst size always to maximum size */
392faa0e 1028 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
f0e5caab 1029 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1030}
1031
83fa2f2e 1032static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1033{
1034 unsigned unit = dss_feat_get_burst_size_unit();
1035 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1036 return unit * 8;
1037}
1038
d3862610
M		 1039void dispc_enable_gamma_table(bool enable)
1040{
1041 /*
1042 * This is partially implemented to support only disabling of
1043 * the gamma table.
1044 */
1045 if (enable) {
1046 DSSWARN("Gamma table enabling for TV not yet supported");
1047 return;
1048 }
1049
1050 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1051}
1052
c64dca40 1053static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1054{
efa70b3b 1055 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1056 return;
1057
efa70b3b 1058 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1059}
1060
c64dca40 1061static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1062 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1063{
1064 u32 coef_r, coef_g, coef_b;
1065
dd88b7a6 1066 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1067 return;
1068
1069 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1070 FLD_VAL(coefs->rb, 9, 0);
1071 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1072 FLD_VAL(coefs->gb, 9, 0);
1073 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1074 FLD_VAL(coefs->bb, 9, 0);
1075
1076 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1077 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1078 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1079}
1080
f0e5caab 1081static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1082{
1083 u32 val;
1084
1085 BUG_ON(plane == OMAP_DSS_GFX);
1086
9b372c2d 1087 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1088 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1089 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1090}
1091
d79db853
AT		 1092static void dispc_ovl_enable_replication(enum omap_plane plane,
1093 enum omap_overlay_caps caps, bool enable)
80c39712 1094{
b8c095b4 1095 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1096 int shift;
80c39712 1097
d79db853
AT		 1098 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1099 return;
1100
fe3cc9d6
TV		 1101 shift = shifts[plane];
1102 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1103}
1104
8f366162 1105static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1106 u16 height)
80c39712
TV		 1107{
1108 u32 val;
80c39712 1109
33b89928
AT		 1110 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1111 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1112
8f366162 1113 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1114}
1115
42a6961c 1116static void dispc_init_fifos(void)
80c39712 1117{
80c39712 1118 u32 size;
42a6961c 1119 int fifo;
a0acb557 1120 u8 start, end;
5ed8cf5b
TV		 1121 u32 unit;
1122
1123 unit = dss_feat_get_buffer_size_unit();
80c39712 1124
a0acb557 1125 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1126
42a6961c
TV		 1127 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1128 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1129 size *= unit;
42a6961c
TV		 1130 dispc.fifo_size[fifo] = size;
1131
1132 /*
1133 * By default fifos are mapped directly to overlays, fifo 0 to
1134 * ovl 0, fifo 1 to ovl 1, etc.
1135 */
1136 dispc.fifo_assignment[fifo] = fifo;
80c39712 1137 }
66a0f9e4
TV		 1138
1139 /*
1140 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1141 * causes problems with certain use cases, like using the tiler in 2D
1142 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1143 * giving GFX plane a larger fifo. WB but should work fine with a
1144 * smaller fifo.
1145 */
1146 if (dispc.feat->gfx_fifo_workaround) {
1147 u32 v;
1148
1149 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1150
1151 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1152 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1153 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1154 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1155
1156 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1157
1158 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1159 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1160 }
80c39712
TV		 1161}
1162
83fa2f2e 1163static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1164{
42a6961c
TV		 1165 int fifo;
1166 u32 size = 0;
1167
1168 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1169 if (dispc.fifo_assignment[fifo] == plane)
1170 size += dispc.fifo_size[fifo];
1171 }
1172
1173 return size;
80c39712
TV		 1174}
1175
6f04e1bf 1176void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1177{
a0acb557 1178 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1179 u32 unit;
1180
1181 unit = dss_feat_get_buffer_size_unit();
1182
1183 WARN_ON(low % unit != 0);
1184 WARN_ON(high % unit != 0);
1185
1186 low /= unit;
1187 high /= unit;
a0acb557 1188
9b372c2d
AT		 1189 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1190 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1191
3cb5d966 1192 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1193 plane,
9b372c2d 1194 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1195 lo_start, lo_end) * unit,
9b372c2d 1196 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1197 hi_start, hi_end) * unit,
1198 low * unit, high * unit);
80c39712 1199
9b372c2d 1200 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1201 FLD_VAL(high, hi_start, hi_end) |
1202 FLD_VAL(low, lo_start, lo_end));
80c39712 1203}
8ee5c842 1204EXPORT_SYMBOL(dispc_ovl_set_fifo_threshold);
80c39712
TV		 1205
1206void dispc_enable_fifomerge(bool enable)
1207{
e6b0f884
TV		 1208 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1209 WARN_ON(enable);
1210 return;
1211 }
1212
80c39712
TV		 1213 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1214 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1215}
1216
83fa2f2e 1217void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1218 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1219 bool manual_update)
83fa2f2e
TV		 1220{
1221 /*
1222 * All sizes are in bytes. Both the buffer and burst are made of
1223 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1224 */
1225
1226 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1227 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1228 int i;
83fa2f2e
TV		 1229
1230 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1231 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1232
e0e405b9
TV		 1233 if (use_fifomerge) {
1234 total_fifo_size = 0;
392faa0e 1235 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
e0e405b9
TV		 1236 total_fifo_size += dispc_ovl_get_fifo_size(i);
1237 } else {
1238 total_fifo_size = ovl_fifo_size;
1239 }
1240
1241 /*
1242 * We use the same low threshold for both fifomerge and non-fifomerge
1243 * cases, but for fifomerge we calculate the high threshold using the
1244 * combined fifo size
1245 */
1246
3568f2a4 1247 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1248 *fifo_low = ovl_fifo_size - burst_size * 2;
1249 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1250 } else if (plane == OMAP_DSS_WB) {
1251 /*
1252 * Most optimal configuration for writeback is to push out data
1253 * to the interconnect the moment writeback pushes enough pixels
1254 * in the FIFO to form a burst
1255 */
1256 *fifo_low = 0;
1257 *fifo_high = burst_size;
e0e405b9
TV		 1258 } else {
1259 *fifo_low = ovl_fifo_size - burst_size;
1260 *fifo_high = total_fifo_size - buf_unit;
1261 }
83fa2f2e 1262}
8ee5c842 1263EXPORT_SYMBOL(dispc_ovl_compute_fifo_thresholds);
83fa2f2e 1264
f0e5caab 1265static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1266 int hinc, int vinc,
1267 enum omap_color_component color_comp)
80c39712
TV		 1268{
1269 u32 val;
80c39712 1270
0d66cbb5
AJ		 1271 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1272 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1273
0d66cbb5
AJ		 1274 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1275 &hinc_start, &hinc_end);
1276 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1277 &vinc_start, &vinc_end);
1278 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1279 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1280
0d66cbb5
AJ		 1281 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1282 } else {
1283 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1284 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1285 }
80c39712
TV		 1286}
1287
f0e5caab 1288static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1289{
1290 u32 val;
87a7484b 1291 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1292
87a7484b
AT		 1293 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1294 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1295
1296 val = FLD_VAL(vaccu, vert_start, vert_end) |
1297 FLD_VAL(haccu, hor_start, hor_end);
1298
9b372c2d 1299 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1300}
1301
f0e5caab 1302static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1303{
1304 u32 val;
87a7484b 1305 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1306
87a7484b
AT		 1307 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1308 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1309
1310 val = FLD_VAL(vaccu, vert_start, vert_end) |
1311 FLD_VAL(haccu, hor_start, hor_end);
1312
9b372c2d 1313 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1314}
1315
f0e5caab
TV		 1316static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1317 int vaccu)
ab5ca071
AJ		 1318{
1319 u32 val;
1320
1321 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1322 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1323}
1324
f0e5caab
TV		 1325static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1326 int vaccu)
ab5ca071
AJ		 1327{
1328 u32 val;
1329
1330 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1331 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1332}
80c39712 1333
f0e5caab 1334static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1335 u16 orig_width, u16 orig_height,
1336 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1337 bool five_taps, u8 rotation,
1338 enum omap_color_component color_comp)
80c39712 1339{
0d66cbb5 1340 int fir_hinc, fir_vinc;
80c39712 1341
ed14a3ce
AJ		 1342 fir_hinc = 1024 * orig_width / out_width;
1343 fir_vinc = 1024 * orig_height / out_height;
80c39712 1344
debd9074
CM		 1345 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1346 color_comp);
f0e5caab 1347 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1348}
1349
05dd0f53
CM		 1350static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1351 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1352 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1353{
1354 int h_accu2_0, h_accu2_1;
1355 int v_accu2_0, v_accu2_1;
1356 int chroma_hinc, chroma_vinc;
1357 int idx;
1358
1359 struct accu {
1360 s8 h0_m, h0_n;
1361 s8 h1_m, h1_n;
1362 s8 v0_m, v0_n;
1363 s8 v1_m, v1_n;
1364 };
1365
1366 const struct accu *accu_table;
1367 const struct accu *accu_val;
1368
1369 static const struct accu accu_nv12[4] = {
1370 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1371 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1372 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1373 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1374 };
1375
1376 static const struct accu accu_nv12_ilace[4] = {
1377 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1378 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1379 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1380 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1381 };
1382
1383 static const struct accu accu_yuv[4] = {
1384 { 0, 1, 0, 1, 0, 1, 0, 1 },
1385 { 0, 1, 0, 1, 0, 1, 0, 1 },
1386 { -1, 1, 0, 1, 0, 1, 0, 1 },
1387 { 0, 1, 0, 1, -1, 1, 0, 1 },
1388 };
1389
1390 switch (rotation) {
1391 case OMAP_DSS_ROT_0:
1392 idx = 0;
1393 break;
1394 case OMAP_DSS_ROT_90:
1395 idx = 1;
1396 break;
1397 case OMAP_DSS_ROT_180:
1398 idx = 2;
1399 break;
1400 case OMAP_DSS_ROT_270:
1401 idx = 3;
1402 break;
1403 default:
1404 BUG();
c6eee968 1405 return;
05dd0f53
CM		 1406 }
1407
1408 switch (color_mode) {
1409 case OMAP_DSS_COLOR_NV12:
1410 if (ilace)
1411 accu_table = accu_nv12_ilace;
1412 else
1413 accu_table = accu_nv12;
1414 break;
1415 case OMAP_DSS_COLOR_YUV2:
1416 case OMAP_DSS_COLOR_UYVY:
1417 accu_table = accu_yuv;
1418 break;
1419 default:
1420 BUG();
c6eee968 1421 return;
05dd0f53
CM		 1422 }
1423
1424 accu_val = &accu_table[idx];
1425
1426 chroma_hinc = 1024 * orig_width / out_width;
1427 chroma_vinc = 1024 * orig_height / out_height;
1428
1429 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1430 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1431 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1432 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1433
1434 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1435 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1436}
1437
f0e5caab 1438static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1439 u16 orig_width, u16 orig_height,
1440 u16 out_width, u16 out_height,
1441 bool ilace, bool five_taps,
1442 bool fieldmode, enum omap_color_mode color_mode,
1443 u8 rotation)
1444{
1445 int accu0 = 0;
1446 int accu1 = 0;
1447 u32 l;
80c39712 1448
f0e5caab 1449 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1450 out_width, out_height, five_taps,
1451 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1452 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1453
87a7484b
AT		 1454 /* RESIZEENABLE and VERTICALTAPS */
1455 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1456 l |= (orig_width != out_width) ? (1 << 5) : 0;
1457 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1458 l |= five_taps ? (1 << 21) : 0;
80c39712 1459
87a7484b
AT		 1460 /* VRESIZECONF and HRESIZECONF */
1461 if (dss_has_feature(FEAT_RESIZECONF)) {
1462 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1463 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1464 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1465 }
80c39712 1466
87a7484b
AT		 1467 /* LINEBUFFERSPLIT */
1468 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1469 l &= ~(0x1 << 22);
1470 l |= five_taps ? (1 << 22) : 0;
1471 }
80c39712 1472
9b372c2d 1473 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1474
1475 /*
1476 * field 0 = even field = bottom field
1477 * field 1 = odd field = top field
1478 */
1479 if (ilace && !fieldmode) {
1480 accu1 = 0;
0d66cbb5 1481 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1482 if (accu0 >= 1024/2) {
1483 accu1 = 1024/2;
1484 accu0 -= accu1;
1485 }
1486 }
1487
f0e5caab
TV		 1488 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1489 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1490}
1491
f0e5caab 1492static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1493 u16 orig_width, u16 orig_height,
1494 u16 out_width, u16 out_height,
1495 bool ilace, bool five_taps,
1496 bool fieldmode, enum omap_color_mode color_mode,
1497 u8 rotation)
1498{
1499 int scale_x = out_width != orig_width;
1500 int scale_y = out_height != orig_height;
f92afae2 1501 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1502
1503 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1504 return;
1505 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1506 color_mode != OMAP_DSS_COLOR_UYVY &&
1507 color_mode != OMAP_DSS_COLOR_NV12)) {
1508 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1509 if (plane != OMAP_DSS_WB)
1510 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1511 return;
1512 }
36377357
TV		 1513
1514 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1515 out_height, ilace, color_mode, rotation);
1516
0d66cbb5
AJ		 1517 switch (color_mode) {
1518 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1519 if (chroma_upscale) {
1520 /* UV is subsampled by 2 horizontally and vertically */
1521 orig_height >>= 1;
1522 orig_width >>= 1;
1523 } else {
1524 /* UV is downsampled by 2 horizontally and vertically */
1525 orig_height <<= 1;
1526 orig_width <<= 1;
1527 }
1528
0d66cbb5
AJ		 1529 break;
1530 case OMAP_DSS_COLOR_YUV2:
1531 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1532 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1533 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1534 rotation == OMAP_DSS_ROT_180) {
1535 if (chroma_upscale)
1536 /* UV is subsampled by 2 horizontally */
1537 orig_width >>= 1;
1538 else
1539 /* UV is downsampled by 2 horizontally */
1540 orig_width <<= 1;
1541 }
1542
0d66cbb5
AJ		 1543 /* must use FIR for YUV422 if rotated */
1544 if (rotation != OMAP_DSS_ROT_0)
1545 scale_x = scale_y = true;
20fbb50b 1546
0d66cbb5
AJ		 1547 break;
1548 default:
1549 BUG();
c6eee968 1550 return;
0d66cbb5
AJ		 1551 }
1552
1553 if (out_width != orig_width)
1554 scale_x = true;
1555 if (out_height != orig_height)
1556 scale_y = true;
1557
f0e5caab 1558 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1559 out_width, out_height, five_taps,
1560 rotation, DISPC_COLOR_COMPONENT_UV);
1561
2a5561b1
AT		 1562 if (plane != OMAP_DSS_WB)
1563 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1564 (scale_x || scale_y) ? 1 : 0, 8, 8);
1565
0d66cbb5
AJ		 1566 /* set H scaling */
1567 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1568 /* set V scaling */
1569 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1570}
1571
f0e5caab 1572static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1573 u16 orig_width, u16 orig_height,
1574 u16 out_width, u16 out_height,
1575 bool ilace, bool five_taps,
1576 bool fieldmode, enum omap_color_mode color_mode,
1577 u8 rotation)
1578{
1579 BUG_ON(plane == OMAP_DSS_GFX);
1580
f0e5caab 1581 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1582 orig_width, orig_height,
1583 out_width, out_height,
1584 ilace, five_taps,
1585 fieldmode, color_mode,
1586 rotation);
1587
f0e5caab 1588 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1589 orig_width, orig_height,
1590 out_width, out_height,
1591 ilace, five_taps,
1592 fieldmode, color_mode,
1593 rotation);
1594}
1595
f0e5caab 1596static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
c35eeb2e 1597 enum omap_dss_rotation_type rotation_type,
80c39712
TV		 1598 bool mirroring, enum omap_color_mode color_mode)
1599{
87a7484b
AT		 1600 bool row_repeat = false;
1601 int vidrot = 0;
1602
80c39712
TV		 1603 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1604 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1605
1606 if (mirroring) {
1607 switch (rotation) {
1608 case OMAP_DSS_ROT_0:
1609 vidrot = 2;
1610 break;
1611 case OMAP_DSS_ROT_90:
1612 vidrot = 1;
1613 break;
1614 case OMAP_DSS_ROT_180:
1615 vidrot = 0;
1616 break;
1617 case OMAP_DSS_ROT_270:
1618 vidrot = 3;
1619 break;
1620 }
1621 } else {
1622 switch (rotation) {
1623 case OMAP_DSS_ROT_0:
1624 vidrot = 0;
1625 break;
1626 case OMAP_DSS_ROT_90:
1627 vidrot = 1;
1628 break;
1629 case OMAP_DSS_ROT_180:
1630 vidrot = 2;
1631 break;
1632 case OMAP_DSS_ROT_270:
1633 vidrot = 3;
1634 break;
1635 }
1636 }
1637
80c39712 1638 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1639 row_repeat = true;
80c39712 1640 else
87a7484b 1641 row_repeat = false;
80c39712 1642 }
87a7484b 1643
9b372c2d 1644 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1645 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1646 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1647 row_repeat ? 1 : 0, 18, 18);
c35eeb2e
AT		 1648
1649 if (color_mode == OMAP_DSS_COLOR_NV12) {
1650 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1651 (rotation == OMAP_DSS_ROT_0 ||
1652 rotation == OMAP_DSS_ROT_180);
1653 /* DOUBLESTRIDE */
1654 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1655 }
1656
80c39712
TV		 1657}
1658
1659static int color_mode_to_bpp(enum omap_color_mode color_mode)
1660{
1661 switch (color_mode) {
1662 case OMAP_DSS_COLOR_CLUT1:
1663 return 1;
1664 case OMAP_DSS_COLOR_CLUT2:
1665 return 2;
1666 case OMAP_DSS_COLOR_CLUT4:
1667 return 4;
1668 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1669 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1670 return 8;
1671 case OMAP_DSS_COLOR_RGB12U:
1672 case OMAP_DSS_COLOR_RGB16:
1673 case OMAP_DSS_COLOR_ARGB16:
1674 case OMAP_DSS_COLOR_YUV2:
1675 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1676 case OMAP_DSS_COLOR_RGBA16:
1677 case OMAP_DSS_COLOR_RGBX16:
1678 case OMAP_DSS_COLOR_ARGB16_1555:
1679 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1680 return 16;
1681 case OMAP_DSS_COLOR_RGB24P:
1682 return 24;
1683 case OMAP_DSS_COLOR_RGB24U:
1684 case OMAP_DSS_COLOR_ARGB32:
1685 case OMAP_DSS_COLOR_RGBA32:
1686 case OMAP_DSS_COLOR_RGBX32:
1687 return 32;
1688 default:
1689 BUG();
c6eee968 1690 return 0;
80c39712
TV		 1691 }
1692}
1693
1694static s32 pixinc(int pixels, u8 ps)
1695{
1696 if (pixels == 1)
1697 return 1;
1698 else if (pixels > 1)
1699 return 1 + (pixels - 1) * ps;
1700 else if (pixels < 0)
1701 return 1 - (-pixels + 1) * ps;
1702 else
1703 BUG();
c6eee968 1704 return 0;
80c39712
TV		 1705}
1706
1707static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1708 u16 screen_width,
1709 u16 width, u16 height,
1710 enum omap_color_mode color_mode, bool fieldmode,
1711 unsigned int field_offset,
1712 unsigned *offset0, unsigned *offset1,
aed74b55 1713 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1714{
1715 u8 ps;
1716
1717 /* FIXME CLUT formats */
1718 switch (color_mode) {
1719 case OMAP_DSS_COLOR_CLUT1:
1720 case OMAP_DSS_COLOR_CLUT2:
1721 case OMAP_DSS_COLOR_CLUT4:
1722 case OMAP_DSS_COLOR_CLUT8:
1723 BUG();
1724 return;
1725 case OMAP_DSS_COLOR_YUV2:
1726 case OMAP_DSS_COLOR_UYVY:
1727 ps = 4;
1728 break;
1729 default:
1730 ps = color_mode_to_bpp(color_mode) / 8;
1731 break;
1732 }
1733
1734 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1735 width, height);
1736
1737 /*
1738 * field 0 = even field = bottom field
1739 * field 1 = odd field = top field
1740 */
1741 switch (rotation + mirror * 4) {
1742 case OMAP_DSS_ROT_0:
1743 case OMAP_DSS_ROT_180:
1744 /*
1745 * If the pixel format is YUV or UYVY divide the width
1746 * of the image by 2 for 0 and 180 degree rotation.
1747 */
1748 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1749 color_mode == OMAP_DSS_COLOR_UYVY)
1750 width = width >> 1;
1751 case OMAP_DSS_ROT_90:
1752 case OMAP_DSS_ROT_270:
1753 *offset1 = 0;
1754 if (field_offset)
1755 *offset0 = field_offset * screen_width * ps;
1756 else
1757 *offset0 = 0;
1758
aed74b55
CM		 1759 *row_inc = pixinc(1 +
1760 (y_predecim * screen_width - x_predecim * width) +
1761 (fieldmode ? screen_width : 0), ps);
1762 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1763 break;
1764
1765 case OMAP_DSS_ROT_0 + 4:
1766 case OMAP_DSS_ROT_180 + 4:
1767 /* If the pixel format is YUV or UYVY divide the width
1768 * of the image by 2 for 0 degree and 180 degree
1769 */
1770 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1771 color_mode == OMAP_DSS_COLOR_UYVY)
1772 width = width >> 1;
1773 case OMAP_DSS_ROT_90 + 4:
1774 case OMAP_DSS_ROT_270 + 4:
1775 *offset1 = 0;
1776 if (field_offset)
1777 *offset0 = field_offset * screen_width * ps;
1778 else
1779 *offset0 = 0;
aed74b55
CM		 1780 *row_inc = pixinc(1 -
1781 (y_predecim * screen_width + x_predecim * width) -
1782 (fieldmode ? screen_width : 0), ps);
1783 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1784 break;
1785
1786 default:
1787 BUG();
c6eee968 1788 return;
80c39712
TV		 1789 }
1790}
1791
1792static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1793 u16 screen_width,
1794 u16 width, u16 height,
1795 enum omap_color_mode color_mode, bool fieldmode,
1796 unsigned int field_offset,
1797 unsigned *offset0, unsigned *offset1,
aed74b55 1798 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1799{
1800 u8 ps;
1801 u16 fbw, fbh;
1802
1803 /* FIXME CLUT formats */
1804 switch (color_mode) {
1805 case OMAP_DSS_COLOR_CLUT1:
1806 case OMAP_DSS_COLOR_CLUT2:
1807 case OMAP_DSS_COLOR_CLUT4:
1808 case OMAP_DSS_COLOR_CLUT8:
1809 BUG();
1810 return;
1811 default:
1812 ps = color_mode_to_bpp(color_mode) / 8;
1813 break;
1814 }
1815
1816 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1817 width, height);
1818
1819 /* width & height are overlay sizes, convert to fb sizes */
1820
1821 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1822 fbw = width;
1823 fbh = height;
1824 } else {
1825 fbw = height;
1826 fbh = width;
1827 }
1828
1829 /*
1830 * field 0 = even field = bottom field
1831 * field 1 = odd field = top field
1832 */
1833 switch (rotation + mirror * 4) {
1834 case OMAP_DSS_ROT_0:
1835 *offset1 = 0;
1836 if (field_offset)
1837 *offset0 = *offset1 + field_offset * screen_width * ps;
1838 else
1839 *offset0 = *offset1;
aed74b55
CM		 1840 *row_inc = pixinc(1 +
1841 (y_predecim * screen_width - fbw * x_predecim) +
1842 (fieldmode ? screen_width : 0), ps);
1843 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1844 color_mode == OMAP_DSS_COLOR_UYVY)
1845 *pix_inc = pixinc(x_predecim, 2 * ps);
1846 else
1847 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1848 break;
1849 case OMAP_DSS_ROT_90:
1850 *offset1 = screen_width * (fbh - 1) * ps;
1851 if (field_offset)
1852 *offset0 = *offset1 + field_offset * ps;
1853 else
1854 *offset0 = *offset1;
aed74b55
CM		 1855 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1856 y_predecim + (fieldmode ? 1 : 0), ps);
1857 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1858 break;
1859 case OMAP_DSS_ROT_180:
1860 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1861 if (field_offset)
1862 *offset0 = *offset1 - field_offset * screen_width * ps;
1863 else
1864 *offset0 = *offset1;
1865 *row_inc = pixinc(-1 -
aed74b55
CM		 1866 (y_predecim * screen_width - fbw * x_predecim) -
1867 (fieldmode ? screen_width : 0), ps);
1868 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1869 color_mode == OMAP_DSS_COLOR_UYVY)
1870 *pix_inc = pixinc(-x_predecim, 2 * ps);
1871 else
1872 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1873 break;
1874 case OMAP_DSS_ROT_270:
1875 *offset1 = (fbw - 1) * ps;
1876 if (field_offset)
1877 *offset0 = *offset1 - field_offset * ps;
1878 else
1879 *offset0 = *offset1;
aed74b55
CM		 1880 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1881 y_predecim - (fieldmode ? 1 : 0), ps);
1882 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1883 break;
1884
1885 /* mirroring */
1886 case OMAP_DSS_ROT_0 + 4:
1887 *offset1 = (fbw - 1) * ps;
1888 if (field_offset)
1889 *offset0 = *offset1 + field_offset * screen_width * ps;
1890 else
1891 *offset0 = *offset1;
aed74b55 1892 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1893 (fieldmode ? screen_width : 0),
1894 ps);
aed74b55
CM		 1895 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1896 color_mode == OMAP_DSS_COLOR_UYVY)
1897 *pix_inc = pixinc(-x_predecim, 2 * ps);
1898 else
1899 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1900 break;
1901
1902 case OMAP_DSS_ROT_90 + 4:
1903 *offset1 = 0;
1904 if (field_offset)
1905 *offset0 = *offset1 + field_offset * ps;
1906 else
1907 *offset0 = *offset1;
aed74b55
CM		 1908 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1909 y_predecim + (fieldmode ? 1 : 0),
80c39712 1910 ps);
aed74b55 1911 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1912 break;
1913
1914 case OMAP_DSS_ROT_180 + 4:
1915 *offset1 = screen_width * (fbh - 1) * ps;
1916 if (field_offset)
1917 *offset0 = *offset1 - field_offset * screen_width * ps;
1918 else
1919 *offset0 = *offset1;
aed74b55 1920 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1921 (fieldmode ? screen_width : 0),
1922 ps);
aed74b55
CM		 1923 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1924 color_mode == OMAP_DSS_COLOR_UYVY)
1925 *pix_inc = pixinc(x_predecim, 2 * ps);
1926 else
1927 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1928 break;
1929
1930 case OMAP_DSS_ROT_270 + 4:
1931 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1932 if (field_offset)
1933 *offset0 = *offset1 - field_offset * ps;
1934 else
1935 *offset0 = *offset1;
aed74b55
CM		 1936 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1937 y_predecim - (fieldmode ? 1 : 0),
80c39712 1938 ps);
aed74b55 1939 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1940 break;
1941
1942 default:
1943 BUG();
c6eee968 1944 return;
80c39712
TV		 1945 }
1946}
1947
65e006ff
CM		 1948static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1949 enum omap_color_mode color_mode, bool fieldmode,
1950 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1951 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1952{
1953 u8 ps;
1954
1955 switch (color_mode) {
1956 case OMAP_DSS_COLOR_CLUT1:
1957 case OMAP_DSS_COLOR_CLUT2:
1958 case OMAP_DSS_COLOR_CLUT4:
1959 case OMAP_DSS_COLOR_CLUT8:
1960 BUG();
1961 return;
1962 default:
1963 ps = color_mode_to_bpp(color_mode) / 8;
1964 break;
1965 }
1966
1967 DSSDBG("scrw %d, width %d\n", screen_width, width);
1968
1969 /*
1970 * field 0 = even field = bottom field
1971 * field 1 = odd field = top field
1972 */
1973 *offset1 = 0;
1974 if (field_offset)
1975 *offset0 = *offset1 + field_offset * screen_width * ps;
1976 else
1977 *offset0 = *offset1;
1978 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1979 (fieldmode ? screen_width : 0), ps);
1980 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1981 color_mode == OMAP_DSS_COLOR_UYVY)
1982 *pix_inc = pixinc(x_predecim, 2 * ps);
1983 else
1984 *pix_inc = pixinc(x_predecim, ps);
1985}
1986
7faa9233
CM		 1987/*
1988 * This function is used to avoid synclosts in OMAP3, because of some
1989 * undocumented horizontal position and timing related limitations.
1990 */
465ec13f 1991static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
81ab95b7 1992 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1993 u16 width, u16 height, u16 out_width, u16 out_height)
1994{
230edc03 1995 const int ds = DIV_ROUND_UP(height, out_height);
3e8a6ff2 1996 unsigned long nonactive;
7faa9233
CM		 1997 static const u8 limits[3] = { 8, 10, 20 };
1998 u64 val, blank;
1999 int i;
2000
81ab95b7 2001 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2002
2003 i = 0;
2004 if (out_height < height)
2005 i++;
2006 if (out_width < width)
2007 i++;
81ab95b7 2008 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2009 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2010 if (blank <= limits[i])
2011 return -EINVAL;
2012
2013 /*
2014 * Pixel data should be prepared before visible display point starts.
2015 * So, atleast DS-2 lines must have already been fetched by DISPC
2016 * during nonactive - pos_x period.
2017 */
2018 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2019 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
230edc03
TV		 2020 val, max(0, ds - 2) * width);
2021 if (val < max(0, ds - 2) * width)
7faa9233
CM		 2022 return -EINVAL;
2023
2024 /*
2025 * All lines need to be refilled during the nonactive period of which
2026 * only one line can be loaded during the active period. So, atleast
2027 * DS - 1 lines should be loaded during nonactive period.
2028 */
2029 val = div_u64((u64)nonactive * lclk, pclk);
2030 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
230edc03
TV		 2031 val, max(0, ds - 1) * width);
2032 if (val < max(0, ds - 1) * width)
7faa9233
CM		 2033 return -EINVAL;
2034
2035 return 0;
2036}
2037
8702ee50 2038static unsigned long calc_core_clk_five_taps(unsigned long pclk,
81ab95b7
AT		 2039 const struct omap_video_timings *mgr_timings, u16 width,
2040 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2041 enum omap_color_mode color_mode)
80c39712 2042{
8b53d991 2043 u32 core_clk = 0;
3e8a6ff2 2044 u64 tmp;
80c39712 2045
7282f1b7
CM		 2046 if (height <= out_height && width <= out_width)
2047 return (unsigned long) pclk;
2048
80c39712 2049 if (height > out_height) {
81ab95b7 2050 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2051
2052 tmp = pclk * height * out_width;
2053 do_div(tmp, 2 * out_height * ppl);
8b53d991 2054 core_clk = tmp;
80c39712 2055
2d9c5597
VS		 2056 if (height > 2 * out_height) {
2057 if (ppl == out_width)
2058 return 0;
2059
80c39712
TV		 2060 tmp = pclk * (height - 2 * out_height) * out_width;
2061 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2062 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2063 }
2064 }
2065
2066 if (width > out_width) {
2067 tmp = pclk * width;
2068 do_div(tmp, out_width);
8b53d991 2069 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2070
2071 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2072 core_clk <<= 1;
80c39712
TV		 2073 }
2074
8b53d991 2075 return core_clk;
80c39712
TV		 2076}
2077
8702ee50 2078static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
8ba85306 2079 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2080{
dcbe765b
CM		 2081 if (height > out_height && width > out_width)
2082 return pclk * 4;
2083 else
2084 return pclk * 2;
2085}
2086
8702ee50 2087static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
8ba85306 2088 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2089{
2090 unsigned int hf, vf;
2091
2092 /*
2093 * FIXME how to determine the 'A' factor
2094 * for the no downscaling case ?
2095 */
2096
2097 if (width > 3 * out_width)
2098 hf = 4;
2099 else if (width > 2 * out_width)
2100 hf = 3;
2101 else if (width > out_width)
2102 hf = 2;
2103 else
2104 hf = 1;
80c39712
TV		 2105 if (height > out_height)
2106 vf = 2;
2107 else
2108 vf = 1;
2109
dcbe765b
CM		 2110 return pclk * vf * hf;
2111}
2112
8702ee50 2113static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
8ba85306 2114 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2115{
8ba85306
AT		 2116 /*
2117 * If the overlay/writeback is in mem to mem mode, there are no
2118 * downscaling limitations with respect to pixel clock, return 1 as
2119 * required core clock to represent that we have sufficient enough
2120 * core clock to do maximum downscaling
2121 */
2122 if (mem_to_mem)
2123 return 1;
2124
dcbe765b
CM		 2125 if (width > out_width)
2126 return DIV_ROUND_UP(pclk, out_width) * width;
2127 else
2128 return pclk;
2129}
2130
0c6921de 2131static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2132 const struct omap_video_timings *mgr_timings,
2133 u16 width, u16 height, u16 out_width, u16 out_height,
2134 enum omap_color_mode color_mode, bool *five_taps,
2135 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2136 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2137{
2138 int error;
2139 u16 in_width, in_height;
2140 int min_factor = min(*decim_x, *decim_y);
2141 const int maxsinglelinewidth =
2142 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2143
dcbe765b
CM		 2144 *five_taps = false;
2145
2146 do {
2147 in_height = DIV_ROUND_UP(height, *decim_y);
2148 in_width = DIV_ROUND_UP(width, *decim_x);
8702ee50 2149 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306 2150 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2151 error = (in_width > maxsinglelinewidth || !*core_clk ||
2152 *core_clk > dispc_core_clk_rate());
2153 if (error) {
2154 if (*decim_x == *decim_y) {
2155 *decim_x = min_factor;
2156 ++*decim_y;
2157 } else {
2158 swap(*decim_x, *decim_y);
2159 if (*decim_x < *decim_y)
2160 ++*decim_x;
2161 }
2162 }
2163 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2164
2165 if (in_width > maxsinglelinewidth) {
2166 DSSERR("Cannot scale max input width exceeded");
2167 return -EINVAL;
2168 }
2169 return 0;
2170}
2171
0c6921de 2172static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2173 const struct omap_video_timings *mgr_timings,
2174 u16 width, u16 height, u16 out_width, u16 out_height,
2175 enum omap_color_mode color_mode, bool *five_taps,
2176 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2177 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2178{
2179 int error;
2180 u16 in_width, in_height;
2181 int min_factor = min(*decim_x, *decim_y);
2182 const int maxsinglelinewidth =
2183 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2184
2185 do {
2186 in_height = DIV_ROUND_UP(height, *decim_y);
2187 in_width = DIV_ROUND_UP(width, *decim_x);
8702ee50 2188 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
dcbe765b
CM		 2189 in_width, in_height, out_width, out_height, color_mode);
2190
465ec13f 2191 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
3e8a6ff2
AT		 2192 pos_x, in_width, in_height, out_width,
2193 out_height);
dcbe765b
CM		 2194
2195 if (in_width > maxsinglelinewidth)
2196 if (in_height > out_height &&
2197 in_height < out_height * 2)
2198 *five_taps = false;
2199 if (!*five_taps)
8702ee50 2200 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
8ba85306
AT		 2201 in_height, out_width, out_height,
2202 mem_to_mem);
dcbe765b
CM		 2203
2204 error = (error || in_width > maxsinglelinewidth * 2 ||
2205 (in_width > maxsinglelinewidth && *five_taps) ||
2206 !*core_clk || *core_clk > dispc_core_clk_rate());
2207 if (error) {
2208 if (*decim_x == *decim_y) {
2209 *decim_x = min_factor;
2210 ++*decim_y;
2211 } else {
2212 swap(*decim_x, *decim_y);
2213 if (*decim_x < *decim_y)
2214 ++*decim_x;
2215 }
2216 }
2217 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2218
465ec13f
TV		 2219 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, width,
2220 height, out_width, out_height)){
dcbe765b
CM		 2221 DSSERR("horizontal timing too tight\n");
2222 return -EINVAL;
7282f1b7 2223 }
dcbe765b
CM		 2224
2225 if (in_width > (maxsinglelinewidth * 2)) {
2226 DSSERR("Cannot setup scaling");
2227 DSSERR("width exceeds maximum width possible");
2228 return -EINVAL;
2229 }
2230
2231 if (in_width > maxsinglelinewidth && *five_taps) {
2232 DSSERR("cannot setup scaling with five taps");
2233 return -EINVAL;
2234 }
2235 return 0;
2236}
2237
0c6921de 2238static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
dcbe765b
CM		 2239 const struct omap_video_timings *mgr_timings,
2240 u16 width, u16 height, u16 out_width, u16 out_height,
2241 enum omap_color_mode color_mode, bool *five_taps,
2242 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2243 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2244{
2245 u16 in_width, in_width_max;
2246 int decim_x_min = *decim_x;
2247 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2248 const int maxsinglelinewidth =
2249 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
8ba85306 2250 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2251
5d501085
AT		 2252 if (mem_to_mem) {
2253 in_width_max = out_width * maxdownscale;
2254 } else {
8ba85306
AT		 2255 in_width_max = dispc_core_clk_rate() /
2256 DIV_ROUND_UP(pclk, out_width);
5d501085 2257 }
dcbe765b 2258
dcbe765b
CM		 2259 *decim_x = DIV_ROUND_UP(width, in_width_max);
2260
2261 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2262 if (*decim_x > *x_predecim)
2263 return -EINVAL;
2264
2265 do {
2266 in_width = DIV_ROUND_UP(width, *decim_x);
2267 } while (*decim_x <= *x_predecim &&
2268 in_width > maxsinglelinewidth && ++*decim_x);
2269
2270 if (in_width > maxsinglelinewidth) {
2271 DSSERR("Cannot scale width exceeds max line width");
2272 return -EINVAL;
2273 }
2274
8702ee50 2275 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
8ba85306 2276 out_width, out_height, mem_to_mem);
dcbe765b 2277 return 0;
80c39712
TV		 2278}
2279
74e16458 2280static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
3e8a6ff2 2281 enum omap_overlay_caps caps,
81ab95b7
AT		 2282 const struct omap_video_timings *mgr_timings,
2283 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2284 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2285 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2286 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2287{
0373cac6 2288 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2289 const int max_decim_limit = 16;
8b53d991 2290 unsigned long core_clk = 0;
dcbe765b 2291 int decim_x, decim_y, ret;
79ad75f2 2292
f95cb5eb
TV		 2293 if (width == out_width && height == out_height)
2294 return 0;
2295
5b54ed3e 2296 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2297 return -EINVAL;
79ad75f2 2298
74e16458 2299 if (mem_to_mem) {
1c031441
AT		 2300 *x_predecim = *y_predecim = 1;
2301 } else {
2302 *x_predecim = max_decim_limit;
2303 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2304 dss_has_feature(FEAT_BURST_2D)) ?
2305 2 : max_decim_limit;
2306 }
aed74b55
CM		 2307
2308 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2309 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2310 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2311 color_mode == OMAP_DSS_COLOR_CLUT8) {
2312 *x_predecim = 1;
2313 *y_predecim = 1;
2314 *five_taps = false;
2315 return 0;
2316 }
2317
2318 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2319 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2320
aed74b55 2321 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2322 return -EINVAL;
2323
aed74b55 2324 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2325 return -EINVAL;
2326
0c6921de 2327 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
3e8a6ff2 2328 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2329 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2330 mem_to_mem);
dcbe765b
CM		 2331 if (ret)
2332 return ret;
79ad75f2 2333
8b53d991
CM		 2334 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2335 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2336
8b53d991 2337 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2338 DSSERR("failed to set up scaling, "
8b53d991
CM		 2339 "required core clk rate = %lu Hz, "
2340 "current core clk rate = %lu Hz\n",
2341 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2342 return -EINVAL;
2343 }
2344
aed74b55
CM		 2345 *x_predecim = decim_x;
2346 *y_predecim = decim_y;
79ad75f2
AT		 2347 return 0;
2348}
2349
f9b719b6
TV		 2350int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2351 const struct omap_overlay_info *oi,
2352 const struct omap_video_timings *timings,
2353 int *x_predecim, int *y_predecim)
2354{
2355 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2356 bool five_taps = true;
62a83183 2357 bool fieldmode = false;
f9b719b6
TV		 2358 u16 in_height = oi->height;
2359 u16 in_width = oi->width;
2360 bool ilace = timings->interlace;
2361 u16 out_width, out_height;
2362 int pos_x = oi->pos_x;
2363 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2364 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2365
2366 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2367 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2368
2369 if (ilace && oi->height == out_height)
62a83183 2370 fieldmode = true;
f9b719b6
TV		 2371
2372 if (ilace) {
2373 if (fieldmode)
2374 in_height /= 2;
2375 out_height /= 2;
2376
2377 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2378 in_height, out_height);
2379 }
2380
2381 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2382 return -EINVAL;
2383
2384 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2385 in_height, out_width, out_height, oi->color_mode,
2386 &five_taps, x_predecim, y_predecim, pos_x,
2387 oi->rotation_type, false);
2388}
348be69d 2389EXPORT_SYMBOL(dispc_ovl_check);
f9b719b6 2390
84a880fd 2391static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2392 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2393 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2394 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2395 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2396 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2397 bool replication, const struct omap_video_timings *mgr_timings,
2398 bool mem_to_mem)
80c39712 2399{
7282f1b7 2400 bool five_taps = true;
62a83183 2401 bool fieldmode = false;
79ad75f2 2402 int r, cconv = 0;
80c39712
TV		 2403 unsigned offset0, offset1;
2404 s32 row_inc;
2405 s32 pix_inc;
6be0d73e 2406 u16 frame_width, frame_height;
80c39712 2407 unsigned int field_offset = 0;
84a880fd
AT		 2408 u16 in_height = height;
2409 u16 in_width = width;
aed74b55 2410 int x_predecim = 1, y_predecim = 1;
8050cbe4 2411 bool ilace = mgr_timings->interlace;
74e16458
TV		 2412 unsigned long pclk = dispc_plane_pclk_rate(plane);
2413 unsigned long lclk = dispc_plane_lclk_rate(plane);
e6d80f95 2414
84a880fd 2415 if (paddr == 0)
80c39712
TV		 2416 return -EINVAL;
2417
84a880fd
AT		 2418 out_width = out_width == 0 ? width : out_width;
2419 out_height = out_height == 0 ? height : out_height;
cf073668 2420
84a880fd 2421 if (ilace && height == out_height)
62a83183 2422 fieldmode = true;
80c39712
TV		 2423
2424 if (ilace) {
2425 if (fieldmode)
aed74b55 2426 in_height /= 2;
8eeb7019 2427 pos_y /= 2;
aed74b55 2428 out_height /= 2;
80c39712
TV		 2429
2430 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2431 "out_height %d\n", in_height, pos_y,
2432 out_height);
80c39712
TV		 2433 }
2434
84a880fd 2435 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2436 return -EINVAL;
2437
74e16458 2438 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
84a880fd
AT		 2439 in_height, out_width, out_height, color_mode,
2440 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2441 rotation_type, mem_to_mem);
79ad75f2
AT		 2442 if (r)
2443 return r;
80c39712 2444
aed74b55
CM		 2445 in_width = DIV_ROUND_UP(in_width, x_predecim);
2446 in_height = DIV_ROUND_UP(in_height, y_predecim);
2447
84a880fd
AT		 2448 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2449 color_mode == OMAP_DSS_COLOR_UYVY ||
2450 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2451 cconv = 1;
80c39712
TV		 2452
2453 if (ilace && !fieldmode) {
2454 /*
2455 * when downscaling the bottom field may have to start several
2456 * source lines below the top field. Unfortunately ACCUI
2457 * registers will only hold the fractional part of the offset
2458 * so the integer part must be added to the base address of the
2459 * bottom field.
2460 */
aed74b55 2461 if (!in_height || in_height == out_height)
80c39712
TV		 2462 field_offset = 0;
2463 else
aed74b55 2464 field_offset = in_height / out_height / 2;
80c39712
TV		 2465 }
2466
2467 /* Fields are independent but interleaved in memory. */
2468 if (fieldmode)
2469 field_offset = 1;
2470
c6eee968
TV		 2471 offset0 = 0;
2472 offset1 = 0;
2473 row_inc = 0;
2474 pix_inc = 0;
2475
6be0d73e
AT		 2476 if (plane == OMAP_DSS_WB) {
2477 frame_width = out_width;
2478 frame_height = out_height;
2479 } else {
2480 frame_width = in_width;
2481 frame_height = height;
2482 }
2483
84a880fd 2484 if (rotation_type == OMAP_DSS_ROT_TILER)
6be0d73e 2485 calc_tiler_rotation_offset(screen_width, frame_width,
84a880fd 2486 color_mode, fieldmode, field_offset,
65e006ff
CM		 2487 &offset0, &offset1, &row_inc, &pix_inc,
2488 x_predecim, y_predecim);
84a880fd 2489 else if (rotation_type == OMAP_DSS_ROT_DMA)
6be0d73e
AT		 2490 calc_dma_rotation_offset(rotation, mirror, screen_width,
2491 frame_width, frame_height,
84a880fd 2492 color_mode, fieldmode, field_offset,
aed74b55
CM		 2493 &offset0, &offset1, &row_inc, &pix_inc,
2494 x_predecim, y_predecim);
80c39712 2495 else
84a880fd 2496 calc_vrfb_rotation_offset(rotation, mirror,
6be0d73e 2497 screen_width, frame_width, frame_height,
84a880fd 2498 color_mode, fieldmode, field_offset,
aed74b55
CM		 2499 &offset0, &offset1, &row_inc, &pix_inc,
2500 x_predecim, y_predecim);
80c39712
TV		 2501
2502 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2503 offset0, offset1, row_inc, pix_inc);
2504
84a880fd 2505 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2506
84a880fd 2507 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2508
84a880fd
AT		 2509 dispc_ovl_set_ba0(plane, paddr + offset0);
2510 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2511
84a880fd
AT		 2512 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2513 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2514 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2515 }
2516
f0e5caab
TV		 2517 dispc_ovl_set_row_inc(plane, row_inc);
2518 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2519
84a880fd 2520 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2521 in_height, out_width, out_height);
80c39712 2522
84a880fd 2523 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2524
78b687fc 2525 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2526
5b54ed3e 2527 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2528 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2529 out_height, ilace, five_taps, fieldmode,
84a880fd 2530 color_mode, rotation);
78b687fc 2531 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2532 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2533 }
2534
c35eeb2e
AT		 2535 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2536 color_mode);
80c39712 2537
84a880fd
AT		 2538 dispc_ovl_set_zorder(plane, caps, zorder);
2539 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2540 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2541
d79db853 2542 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2543
80c39712
TV		 2544 return 0;
2545}
2546
84a880fd 2547int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2548 bool replication, const struct omap_video_timings *mgr_timings,
2549 bool mem_to_mem)
84a880fd
AT		 2550{
2551 int r;
16bf20c7 2552 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2553 enum omap_channel channel;
2554
2555 channel = dispc_ovl_get_channel_out(plane);
2556
2557 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2558 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2559 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2560 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2561 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2562
16bf20c7 2563 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2564 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2565 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2566 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2567 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2568
2569 return r;
2570}
348be69d 2571EXPORT_SYMBOL(dispc_ovl_setup);
84a880fd 2572
749feffa 2573int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2574 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2575{
2576 int r;
9e4a0fc7 2577 u32 l;
749feffa
AT		 2578 enum omap_plane plane = OMAP_DSS_WB;
2579 const int pos_x = 0, pos_y = 0;
2580 const u8 zorder = 0, global_alpha = 0;
2581 const bool replication = false;
9e4a0fc7 2582 bool truncation;
749feffa
AT		 2583 int in_width = mgr_timings->x_res;
2584 int in_height = mgr_timings->y_res;
2585 enum omap_overlay_caps caps =
2586 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2587
2588 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2589 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2590 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2591 wi->mirror);
2592
2593 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2594 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2595 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2596 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2597 replication, mgr_timings, mem_to_mem);
2598
2599 switch (wi->color_mode) {
2600 case OMAP_DSS_COLOR_RGB16:
2601 case OMAP_DSS_COLOR_RGB24P:
2602 case OMAP_DSS_COLOR_ARGB16:
2603 case OMAP_DSS_COLOR_RGBA16:
2604 case OMAP_DSS_COLOR_RGB12U:
2605 case OMAP_DSS_COLOR_ARGB16_1555:
2606 case OMAP_DSS_COLOR_XRGB16_1555:
2607 case OMAP_DSS_COLOR_RGBX16:
2608 truncation = true;
2609 break;
2610 default:
2611 truncation = false;
2612 break;
2613 }
2614
2615 /* setup extra DISPC_WB_ATTRIBUTES */
2616 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2617 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2618 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2619 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2620
2621 return r;
2622}
2623
f0e5caab 2624int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2625{
e6d80f95
TV		 2626 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2627
9b372c2d 2628 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2629
2630 return 0;
80c39712 2631}
348be69d 2632EXPORT_SYMBOL(dispc_ovl_enable);
80c39712 2633
04bd8ac1
TV		 2634bool dispc_ovl_enabled(enum omap_plane plane)
2635{
2636 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2637}
348be69d 2638EXPORT_SYMBOL(dispc_ovl_enabled);
04bd8ac1 2639
f1a813d3 2640void dispc_mgr_enable(enum omap_channel channel, bool enable)
80c39712 2641{
efa70b3b
CM		 2642 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2643 /* flush posted write */
2644 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712 2645}
348be69d 2646EXPORT_SYMBOL(dispc_mgr_enable);
80c39712 2647
65398511
TV		 2648bool dispc_mgr_is_enabled(enum omap_channel channel)
2649{
2650 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2651}
348be69d 2652EXPORT_SYMBOL(dispc_mgr_is_enabled);
65398511 2653
0b23e5b8
AT		 2654void dispc_wb_enable(bool enable)
2655{
916188a4 2656 dispc_ovl_enable(OMAP_DSS_WB, enable);
0b23e5b8
AT		 2657}
2658
2659bool dispc_wb_is_enabled(void)
2660{
916188a4 2661 return dispc_ovl_enabled(OMAP_DSS_WB);
0b23e5b8
AT		 2662}
2663
fb2cec1f 2664static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2665{
6ced40bf
AT		 2666 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2667 return;
2668
80c39712 2669 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2670}
2671
2672void dispc_lcd_enable_signal(bool enable)
2673{
6ced40bf
AT		 2674 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2675 return;
2676
80c39712 2677 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2678}
2679
2680void dispc_pck_free_enable(bool enable)
2681{
6ced40bf
AT		 2682 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2683 return;
2684
80c39712 2685 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2686}
2687
fb2cec1f 2688static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2689{
efa70b3b 2690 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2691}
2692
2693
fb2cec1f 2694static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2695{
d21f43bc 2696 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2697}
2698
2699void dispc_set_loadmode(enum omap_dss_load_mode mode)
2700{
80c39712 2701 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2702}
2703
2704
c64dca40 2705static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2706{
8613b000 2707 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2708}
2709
c64dca40 2710static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2711 enum omap_dss_trans_key_type type,
2712 u32 trans_key)
2713{
efa70b3b 2714 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2715
8613b000 2716 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2717}
2718
c64dca40 2719static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2720{
efa70b3b 2721 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2722}
11354dd5 2723
c64dca40
TV		 2724static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2725 bool enable)
80c39712 2726{
11354dd5 2727 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2728 return;
2729
80c39712
TV		 2730 if (ch == OMAP_DSS_CHANNEL_LCD)
2731 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2732 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2733 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2734}
11354dd5 2735
c64dca40 2736void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2737 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2738{
2739 dispc_mgr_set_default_color(channel, info->default_color);
2740 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2741 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2742 dispc_mgr_enable_alpha_fixed_zorder(channel,
2743 info->partial_alpha_enabled);
2744 if (dss_has_feature(FEAT_CPR)) {
2745 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2746 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2747 }
2748}
348be69d 2749EXPORT_SYMBOL(dispc_mgr_setup);
80c39712 2750
fb2cec1f 2751static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2752{
2753 int code;
2754
2755 switch (data_lines) {
2756 case 12:
2757 code = 0;
2758 break;
2759 case 16:
2760 code = 1;
2761 break;
2762 case 18:
2763 code = 2;
2764 break;
2765 case 24:
2766 code = 3;
2767 break;
2768 default:
2769 BUG();
2770 return;
2771 }
2772
efa70b3b 2773 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2774}
2775
fb2cec1f 2776static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2777{
2778 u32 l;
569969d6 2779 int gpout0, gpout1;
80c39712
TV		 2780
2781 switch (mode) {
569969d6
AT		 2782 case DSS_IO_PAD_MODE_RESET:
2783 gpout0 = 0;
2784 gpout1 = 0;
80c39712 2785 break;
569969d6
AT		 2786 case DSS_IO_PAD_MODE_RFBI:
2787 gpout0 = 1;
80c39712
TV		 2788 gpout1 = 0;
2789 break;
569969d6
AT		 2790 case DSS_IO_PAD_MODE_BYPASS:
2791 gpout0 = 1;
80c39712
TV		 2792 gpout1 = 1;
2793 break;
80c39712
TV		 2794 default:
2795 BUG();
2796 return;
2797 }
2798
569969d6
AT		 2799 l = dispc_read_reg(DISPC_CONTROL);
2800 l = FLD_MOD(l, gpout0, 15, 15);
2801 l = FLD_MOD(l, gpout1, 16, 16);
2802 dispc_write_reg(DISPC_CONTROL, l);
2803}
2804
fb2cec1f 2805static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2806{
efa70b3b 2807 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2808}
2809
fb2cec1f
TV		 2810void dispc_mgr_set_lcd_config(enum omap_channel channel,
2811 const struct dss_lcd_mgr_config *config)
2812{
2813 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2814
2815 dispc_mgr_enable_stallmode(channel, config->stallmode);
2816 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2817
2818 dispc_mgr_set_clock_div(channel, &config->clock_info);
2819
2820 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2821
2822 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2823
2824 dispc_mgr_set_lcd_type_tft(channel);
2825}
348be69d 2826EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
fb2cec1f 2827
8f366162
AT		 2828static bool _dispc_mgr_size_ok(u16 width, u16 height)
2829{
33b89928
AT		 2830 return width <= dispc.feat->mgr_width_max &&
2831 height <= dispc.feat->mgr_height_max;
8f366162
AT		 2832}
2833
80c39712
TV		 2834static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2835 int vsw, int vfp, int vbp)
2836{
dcbe765b
CM		 2837 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2838 hfp < 1 || hfp > dispc.feat->hp_max ||
2839 hbp < 1 || hbp > dispc.feat->hp_max ||
2840 vsw < 1 || vsw > dispc.feat->sw_max ||
2841 vfp < 0 || vfp > dispc.feat->vp_max ||
2842 vbp < 0 || vbp > dispc.feat->vp_max)
2843 return false;
80c39712
TV		 2844 return true;
2845}
2846
ca5ca69c
AT		 2847static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2848 unsigned long pclk)
2849{
2850 if (dss_mgr_is_lcd(channel))
2851 return pclk <= dispc.feat->max_lcd_pclk ? true : false;
2852 else
2853 return pclk <= dispc.feat->max_tv_pclk ? true : false;
2854}
2855
8f366162 2856bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2857 const struct omap_video_timings *timings)
80c39712 2858{
8f366162
AT		 2859 bool timings_ok;
2860
2861 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2862
ca5ca69c
AT		 2863 timings_ok &= _dispc_mgr_pclk_ok(channel, timings->pixel_clock * 1000);
2864
2865 if (dss_mgr_is_lcd(channel)) {
2866 timings_ok &= _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2867 timings->hbp, timings->vsw, timings->vfp,
2868 timings->vbp);
2869 }
8f366162
AT		 2870
2871 return timings_ok;
80c39712
TV		 2872}
2873
26d9dd0d 2874static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2875 int hfp, int hbp, int vsw, int vfp, int vbp,
2876 enum omap_dss_signal_level vsync_level,
2877 enum omap_dss_signal_level hsync_level,
2878 enum omap_dss_signal_edge data_pclk_edge,
2879 enum omap_dss_signal_level de_level,
2880 enum omap_dss_signal_edge sync_pclk_edge)
2881
80c39712 2882{
655e2941
AT		 2883 u32 timing_h, timing_v, l;
2884 bool onoff, rf, ipc;
80c39712 2885
dcbe765b
CM		 2886 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2887 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2888 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2889 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2890 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2891 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 2892
64ba4f74
SS		 2893 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2894 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 2895
2896 switch (data_pclk_edge) {
2897 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2898 ipc = false;
2899 break;
2900 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2901 ipc = true;
2902 break;
2903 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2904 default:
2905 BUG();
2906 }
2907
2908 switch (sync_pclk_edge) {
2909 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2910 onoff = false;
2911 rf = false;
2912 break;
2913 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2914 onoff = true;
2915 rf = false;
2916 break;
2917 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2918 onoff = true;
2919 rf = true;
2920 break;
2921 default:
2922 BUG();
cf6ac4ce 2923 }
655e2941
AT		 2924
2925 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2926 l |= FLD_VAL(onoff, 17, 17);
2927 l |= FLD_VAL(rf, 16, 16);
2928 l |= FLD_VAL(de_level, 15, 15);
2929 l |= FLD_VAL(ipc, 14, 14);
2930 l |= FLD_VAL(hsync_level, 13, 13);
2931 l |= FLD_VAL(vsync_level, 12, 12);
2932 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2933}
2934
2935/* change name to mode? */
c51d921a 2936void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 2937 const struct omap_video_timings *timings)
80c39712
TV		 2938{
2939 unsigned xtot, ytot;
2940 unsigned long ht, vt;
2aefad49 2941 struct omap_video_timings t = *timings;
80c39712 2942
2aefad49 2943 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 2944
2aefad49 2945 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2946 BUG();
c6eee968
TV		 2947 return;
2948 }
80c39712 2949
dd88b7a6 2950 if (dss_mgr_is_lcd(channel)) {
2aefad49 2951 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 2952 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2953 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 2954
2aefad49
AT		 2955 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2956 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 2957
c51d921a
AT		 2958 ht = (timings->pixel_clock * 1000) / xtot;
2959 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2960
2961 DSSDBG("pck %u\n", timings->pixel_clock);
2962 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 2963 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 2964 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2965 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2966 t.de_level, t.sync_pclk_edge);
80c39712 2967
c51d921a 2968 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 2969 } else {
23c8f88e 2970 if (t.interlace == true)
2aefad49 2971 t.y_res /= 2;
c51d921a 2972 }
8f366162 2973
2aefad49 2974 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712 2975}
348be69d 2976EXPORT_SYMBOL(dispc_mgr_set_timings);
80c39712 2977
26d9dd0d 2978static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2979 u16 pck_div)
80c39712
TV		 2980{
2981 BUG_ON(lck_div < 1);
9eaaf207 2982 BUG_ON(pck_div < 1);
80c39712 2983
ce7fa5eb 2984 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2985 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
7b3926b3
TV		 2986
2987 if (dss_has_feature(FEAT_CORE_CLK_DIV) == false &&
2988 channel == OMAP_DSS_CHANNEL_LCD)
2989 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
80c39712
TV		 2990}
2991
26d9dd0d 2992static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2993 int *pck_div)
80c39712
TV		 2994{
2995 u32 l;
ce7fa5eb 2996 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2997 *lck_div = FLD_GET(l, 23, 16);
2998 *pck_div = FLD_GET(l, 7, 0);
2999}
3000
3001unsigned long dispc_fclk_rate(void)
3002{
a72b64b9 3003 struct platform_device *dsidev;
80c39712
TV		 3004 unsigned long r = 0;
3005
66534e8e 3006 switch (dss_get_dispc_clk_source()) {
89a35e51 3007 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3008 r = dss_get_dispc_clk_rate();
66534e8e 3009 break;
89a35e51 3010 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3011 dsidev = dsi_get_dsidev_from_id(0);
3012 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 3013 break;
5a8b572d
AT		 3014 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3015 dsidev = dsi_get_dsidev_from_id(1);
3016 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3017 break;
66534e8e
TA		 3018 default:
3019 BUG();
c6eee968 3020 return 0;
66534e8e
TA		 3021 }
3022
80c39712
TV		 3023 return r;
3024}
3025
26d9dd0d 3026unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3027{
a72b64b9 3028 struct platform_device *dsidev;
80c39712
TV		 3029 int lcd;
3030 unsigned long r;
3031 u32 l;
3032
c31cba8a
TV		 3033 if (dss_mgr_is_lcd(channel)) {
3034 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3035
c31cba8a 3036 lcd = FLD_GET(l, 23, 16);
80c39712 3037
c31cba8a
TV		 3038 switch (dss_get_lcd_clk_source(channel)) {
3039 case OMAP_DSS_CLK_SRC_FCK:
5aaee69d 3040 r = dss_get_dispc_clk_rate();
c31cba8a
TV		 3041 break;
3042 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3043 dsidev = dsi_get_dsidev_from_id(0);
3044 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3045 break;
3046 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3047 dsidev = dsi_get_dsidev_from_id(1);
3048 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3049 break;
3050 default:
3051 BUG();
3052 return 0;
3053 }
80c39712 3054
c31cba8a
TV		 3055 return r / lcd;
3056 } else {
3057 return dispc_fclk_rate();
3058 }
80c39712
TV		 3059}
3060
26d9dd0d 3061unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3062{
80c39712 3063 unsigned long r;
80c39712 3064
dd88b7a6 3065 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3066 int pcd;
3067 u32 l;
80c39712 3068
c3dc6a7a 3069 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3070
c3dc6a7a 3071 pcd = FLD_GET(l, 7, 0);
80c39712 3072
c3dc6a7a
AT		 3073 r = dispc_mgr_lclk_rate(channel);
3074
3075 return r / pcd;
3076 } else {
5391e87d 3077 return dispc.tv_pclk_rate;
c3dc6a7a 3078 }
80c39712
TV		 3079}
3080
5391e87d
TV		 3081void dispc_set_tv_pclk(unsigned long pclk)
3082{
3083 dispc.tv_pclk_rate = pclk;
3084}
3085
8b53d991
CM		 3086unsigned long dispc_core_clk_rate(void)
3087{
7b3926b3 3088 return dispc.core_clk_rate;
8b53d991
CM		 3089}
3090
3e8a6ff2
AT		 3091static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3092{
251886d8
TV		 3093 enum omap_channel channel;
3094
3095 if (plane == OMAP_DSS_WB)
3096 return 0;
3097
3098 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2
AT		 3099
3100 return dispc_mgr_pclk_rate(channel);
3101}
3102
3103static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3104{
251886d8
TV		 3105 enum omap_channel channel;
3106
3107 if (plane == OMAP_DSS_WB)
3108 return 0;
3109
3110 channel = dispc_ovl_get_channel_out(plane);
3e8a6ff2 3111
c31cba8a 3112 return dispc_mgr_lclk_rate(channel);
3e8a6ff2 3113}
c31cba8a 3114
6f1891fc 3115static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3116{
3117 int lcd, pcd;
6f1891fc
CM		 3118 enum omap_dss_clk_source lcd_clk_src;
3119
3120 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3121
3122 lcd_clk_src = dss_get_lcd_clk_source(channel);
3123
3124 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3125 dss_get_generic_clk_source_name(lcd_clk_src),
3126 dss_feat_get_clk_source_name(lcd_clk_src));
3127
3128 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3129
3130 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3131 dispc_mgr_lclk_rate(channel), lcd);
3132 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3133 dispc_mgr_pclk_rate(channel), pcd);
3134}
3135
3136void dispc_dump_clocks(struct seq_file *s)
3137{
3138 int lcd;
0cf35df3 3139 u32 l;
89a35e51 3140 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3141
4fbafaf3
TV		 3142 if (dispc_runtime_get())
3143 return;
80c39712 3144
80c39712
TV		 3145 seq_printf(s, "- DISPC -\n");
3146
067a57e4
AT		 3147 seq_printf(s, "dispc fclk source = %s (%s)\n",
3148 dss_get_generic_clk_source_name(dispc_clk_src),
3149 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3150
3151 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3152
0cf35df3
MR		 3153 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3154 seq_printf(s, "- DISPC-CORE-CLK -\n");
3155 l = dispc_read_reg(DISPC_DIVISOR);
3156 lcd = FLD_GET(l, 23, 16);
3157
3158 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3159 (dispc_fclk_rate()/lcd), lcd);
3160 }
2a205f34 3161
6f1891fc 3162 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3163
6f1891fc
CM		 3164 if (dss_has_feature(FEAT_MGR_LCD2))
3165 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3166 if (dss_has_feature(FEAT_MGR_LCD3))
3167 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3168
3169 dispc_runtime_put();
80c39712
TV		 3170}
3171
e40402cf 3172static void dispc_dump_regs(struct seq_file *s)
80c39712 3173{
4dd2da15
AT		 3174 int i, j;
3175 const char *mgr_names[] = {
3176 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3177 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3178 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3179 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3180 };
3181 const char *ovl_names[] = {
3182 [OMAP_DSS_GFX] = "GFX",
3183 [OMAP_DSS_VIDEO1] = "VID1",
3184 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3185 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3186 };
3187 const char **p_names;
3188
9b372c2d 3189#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3190
4fbafaf3
TV		 3191 if (dispc_runtime_get())
3192 return;
80c39712 3193
5010be80 3194 /* DISPC common registers */
80c39712
TV		 3195 DUMPREG(DISPC_REVISION);
3196 DUMPREG(DISPC_SYSCONFIG);
3197 DUMPREG(DISPC_SYSSTATUS);
3198 DUMPREG(DISPC_IRQSTATUS);
3199 DUMPREG(DISPC_IRQENABLE);
3200 DUMPREG(DISPC_CONTROL);
3201 DUMPREG(DISPC_CONFIG);
3202 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3203 DUMPREG(DISPC_LINE_STATUS);
3204 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3205 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3206 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3207 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3208 if (dss_has_feature(FEAT_MGR_LCD2)) {
3209 DUMPREG(DISPC_CONTROL2);
3210 DUMPREG(DISPC_CONFIG2);
5010be80 3211 }
6f1891fc
CM		 3212 if (dss_has_feature(FEAT_MGR_LCD3)) {
3213 DUMPREG(DISPC_CONTROL3);
3214 DUMPREG(DISPC_CONFIG3);
3215 }
5010be80
AT		 3216
3217#undef DUMPREG
3218
3219#define DISPC_REG(i, name) name(i)
4dd2da15 3220#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3221 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3222 dispc_read_reg(DISPC_REG(i, r)))
3223
4dd2da15 3224 p_names = mgr_names;
5010be80 3225
4dd2da15
AT		 3226 /* DISPC channel specific registers */
3227 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3228 DUMPREG(i, DISPC_DEFAULT_COLOR);
3229 DUMPREG(i, DISPC_TRANS_COLOR);
3230 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3231
4dd2da15
AT		 3232 if (i == OMAP_DSS_CHANNEL_DIGIT)
3233 continue;
5010be80 3234
4dd2da15
AT		 3235 DUMPREG(i, DISPC_DEFAULT_COLOR);
3236 DUMPREG(i, DISPC_TRANS_COLOR);
3237 DUMPREG(i, DISPC_TIMING_H);
3238 DUMPREG(i, DISPC_TIMING_V);
3239 DUMPREG(i, DISPC_POL_FREQ);
3240 DUMPREG(i, DISPC_DIVISORo);
3241 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3242
4dd2da15
AT		 3243 DUMPREG(i, DISPC_DATA_CYCLE1);
3244 DUMPREG(i, DISPC_DATA_CYCLE2);
3245 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3246
332e9d70 3247 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3248 DUMPREG(i, DISPC_CPR_COEF_R);
3249 DUMPREG(i, DISPC_CPR_COEF_G);
3250 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3251 }
2a205f34 3252 }
80c39712 3253
4dd2da15
AT		 3254 p_names = ovl_names;
3255
3256 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3257 DUMPREG(i, DISPC_OVL_BA0);
3258 DUMPREG(i, DISPC_OVL_BA1);
3259 DUMPREG(i, DISPC_OVL_POSITION);
3260 DUMPREG(i, DISPC_OVL_SIZE);
3261 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3262 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3263 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3264 DUMPREG(i, DISPC_OVL_ROW_INC);
3265 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3266 if (dss_has_feature(FEAT_PRELOAD))
3267 DUMPREG(i, DISPC_OVL_PRELOAD);
3268
3269 if (i == OMAP_DSS_GFX) {
3270 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3271 DUMPREG(i, DISPC_OVL_TABLE_BA);
3272 continue;
3273 }
3274
3275 DUMPREG(i, DISPC_OVL_FIR);
3276 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3277 DUMPREG(i, DISPC_OVL_ACCU0);
3278 DUMPREG(i, DISPC_OVL_ACCU1);
3279 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3280 DUMPREG(i, DISPC_OVL_BA0_UV);
3281 DUMPREG(i, DISPC_OVL_BA1_UV);
3282 DUMPREG(i, DISPC_OVL_FIR2);
3283 DUMPREG(i, DISPC_OVL_ACCU2_0);
3284 DUMPREG(i, DISPC_OVL_ACCU2_1);
3285 }
3286 if (dss_has_feature(FEAT_ATTR2))
3287 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3288 if (dss_has_feature(FEAT_PRELOAD))
3289 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3290 }
5010be80
AT		 3291
3292#undef DISPC_REG
3293#undef DUMPREG
3294
3295#define DISPC_REG(plane, name, i) name(plane, i)
3296#define DUMPREG(plane, name, i) \
4dd2da15 3297 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3298 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3299 dispc_read_reg(DISPC_REG(plane, name, i)))
3300
4dd2da15 3301 /* Video pipeline coefficient registers */
332e9d70 3302
4dd2da15
AT		 3303 /* start from OMAP_DSS_VIDEO1 */
3304 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3305 for (j = 0; j < 8; j++)
3306 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3307
4dd2da15
AT		 3308 for (j = 0; j < 8; j++)
3309 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3310
4dd2da15
AT		 3311 for (j = 0; j < 5; j++)
3312 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3313
4dd2da15
AT		 3314 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3315 for (j = 0; j < 8; j++)
3316 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3317 }
3318
3319 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3320 for (j = 0; j < 8; j++)
3321 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3322
3323 for (j = 0; j < 8; j++)
3324 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3325
3326 for (j = 0; j < 8; j++)
3327 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3328 }
332e9d70 3329 }
80c39712 3330
4fbafaf3 3331 dispc_runtime_put();
5010be80
AT		 3332
3333#undef DISPC_REG
80c39712
TV		 3334#undef DUMPREG
3335}
3336
80c39712
TV		 3337/* calculate clock rates using dividers in cinfo */
3338int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
80c39712
TV		 3339 struct dispc_clock_info *cinfo)
3340{
80c39712
TV		 3341 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3342 return -EINVAL;
9eaaf207 3343 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712 3344 return -EINVAL;
80c39712 3345
80c39712
TV		 3346 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3347 cinfo->pck = cinfo->lck / cinfo->pck_div;
9eaaf207 3348
80c39712
TV		 3349 return 0;
3350}
80c39712 3351
7c284e6e
TV		 3352bool dispc_div_calc(unsigned long dispc,
3353 unsigned long pck_min, unsigned long pck_max,
3354 dispc_div_calc_func func, void *data)
3355{
3356 int lckd, lckd_start, lckd_stop;
3357 int pckd, pckd_start, pckd_stop;
3358 unsigned long pck, lck;
3359 unsigned long lck_max;
3360 unsigned long pckd_hw_min, pckd_hw_max;
3361 unsigned min_fck_per_pck;
3362 unsigned long fck;
80c39712 3363
7c284e6e
TV		 3364#ifdef CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK
3365 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
3366#else
3367 min_fck_per_pck = 0;
3368#endif
80c39712 3369
7c284e6e
TV		 3370 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3371 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
80c39712 3372
7c284e6e 3373 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
80c39712 3374
7c284e6e
TV		 3375 pck_min = pck_min ? pck_min : 1;
3376 pck_max = pck_max ? pck_max : ULONG_MAX;
80c39712 3377
7c284e6e
TV		 3378 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3379 lckd_stop = min(dispc / pck_min, 255ul);
80c39712 3380
7c284e6e
TV		 3381 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3382 lck = dispc / lckd;
80c39712 3383
7c284e6e
TV		 3384 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3385 pckd_stop = min(lck / pck_min, pckd_hw_max);
80c39712 3386
7c284e6e
TV		 3387 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3388 pck = lck / pckd;
80c39712 3389
7c284e6e
TV		 3390 /*
3391 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3392 * clock, which means we're configuring DISPC fclk here
3393 * also. Thus we need to use the calculated lck. For
3394 * OMAP4+ the DISPC fclk is a separate clock.
3395 */
3396 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3397 fck = dispc_core_clk_rate();
3398 else
3399 fck = lck;
3400
3401 if (fck < pck * min_fck_per_pck)
3402 continue;
3403
3404 if (func(lckd, pckd, lck, pck, data))
3405 return true;
3406 }
3407 }
3408
3409 return false;
80c39712
TV		 3410}
3411
f0d08f89 3412void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3413 const struct dispc_clock_info *cinfo)
80c39712
TV		 3414{
3415 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3416 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3417
26d9dd0d 3418 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3419}
3420
26d9dd0d 3421int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3422 struct dispc_clock_info *cinfo)
80c39712
TV		 3423{
3424 unsigned long fck;
3425
3426 fck = dispc_fclk_rate();
3427
ce7fa5eb
MR		 3428 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3429 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3430
3431 cinfo->lck = fck / cinfo->lck_div;
3432 cinfo->pck = cinfo->lck / cinfo->pck_div;
3433
3434 return 0;
3435}
3436
4e0397cf
TV		 3437u32 dispc_read_irqstatus(void)
3438{
3439 return dispc_read_reg(DISPC_IRQSTATUS);
3440}
348be69d 3441EXPORT_SYMBOL(dispc_read_irqstatus);
4e0397cf
TV		 3442
3443void dispc_clear_irqstatus(u32 mask)
3444{
3445 dispc_write_reg(DISPC_IRQSTATUS, mask);
3446}
348be69d 3447EXPORT_SYMBOL(dispc_clear_irqstatus);
4e0397cf
TV		 3448
3449u32 dispc_read_irqenable(void)
3450{
3451 return dispc_read_reg(DISPC_IRQENABLE);
3452}
348be69d 3453EXPORT_SYMBOL(dispc_read_irqenable);
4e0397cf
TV		 3454
3455void dispc_write_irqenable(u32 mask)
3456{
3457 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3458
3459 /* clear the irqstatus for newly enabled irqs */
3460 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3461
3462 dispc_write_reg(DISPC_IRQENABLE, mask);
3463}
348be69d 3464EXPORT_SYMBOL(dispc_write_irqenable);
4e0397cf 3465
80c39712
TV		 3466void dispc_enable_sidle(void)
3467{
3468 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3469}
3470
3471void dispc_disable_sidle(void)
3472{
3473 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3474}
3475
3476static void _omap_dispc_initial_config(void)
3477{
3478 u32 l;
3479
0cf35df3
MR		 3480 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3481 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3482 l = dispc_read_reg(DISPC_DIVISOR);
3483 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3484 l = FLD_MOD(l, 1, 0, 0);
3485 l = FLD_MOD(l, 1, 23, 16);
3486 dispc_write_reg(DISPC_DIVISOR, l);
7b3926b3
TV		 3487
3488 dispc.core_clk_rate = dispc_fclk_rate();
0cf35df3
MR		 3489 }
3490
80c39712 3491 /* FUNCGATED */
6ced40bf
AT		 3492 if (dss_has_feature(FEAT_FUNCGATED))
3493 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3494
6e5264b0 3495 dispc_setup_color_conv_coef();
80c39712
TV		 3496
3497 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3498
42a6961c 3499 dispc_init_fifos();
5ed8cf5b
TV		 3500
3501 dispc_configure_burst_sizes();
54128701
AT		 3502
3503 dispc_ovl_enable_zorder_planes();
d0df9a2c
AT		 3504
3505 if (dispc.feat->mstandby_workaround)
3506 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
80c39712
TV		 3507}
3508
dcbe765b
CM		 3509static const struct dispc_features omap24xx_dispc_feats __initconst = {
3510 .sw_start = 5,
3511 .fp_start = 15,
3512 .bp_start = 27,
3513 .sw_max = 64,
3514 .vp_max = 255,
3515 .hp_max = 256,
33b89928
AT		 3516 .mgr_width_start = 10,
3517 .mgr_height_start = 26,
3518 .mgr_width_max = 2048,
3519 .mgr_height_max = 2048,
ca5ca69c 3520 .max_lcd_pclk = 66500000,
dcbe765b
CM		 3521 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3522 .calc_core_clk = calc_core_clk_24xx,
42a6961c 3523 .num_fifos = 3,
cffa947d 3524 .no_framedone_tv = true,
dcbe765b
CM		 3525};
3526
3527static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3528 .sw_start = 5,
3529 .fp_start = 15,
3530 .bp_start = 27,
3531 .sw_max = 64,
3532 .vp_max = 255,
3533 .hp_max = 256,
33b89928
AT		 3534 .mgr_width_start = 10,
3535 .mgr_height_start = 26,
3536 .mgr_width_max = 2048,
3537 .mgr_height_max = 2048,
ca5ca69c
AT		 3538 .max_lcd_pclk = 173000000,
3539 .max_tv_pclk = 59000000,
dcbe765b
CM		 3540 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3541 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3542 .num_fifos = 3,
cffa947d 3543 .no_framedone_tv = true,
dcbe765b
CM		 3544};
3545
3546static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3547 .sw_start = 7,
3548 .fp_start = 19,
3549 .bp_start = 31,
3550 .sw_max = 256,
3551 .vp_max = 4095,
3552 .hp_max = 4096,
33b89928
AT		 3553 .mgr_width_start = 10,
3554 .mgr_height_start = 26,
3555 .mgr_width_max = 2048,
3556 .mgr_height_max = 2048,
ca5ca69c
AT		 3557 .max_lcd_pclk = 173000000,
3558 .max_tv_pclk = 59000000,
dcbe765b
CM		 3559 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3560 .calc_core_clk = calc_core_clk_34xx,
42a6961c 3561 .num_fifos = 3,
cffa947d 3562 .no_framedone_tv = true,
dcbe765b
CM		 3563};
3564
3565static const struct dispc_features omap44xx_dispc_feats __initconst = {
3566 .sw_start = 7,
3567 .fp_start = 19,
3568 .bp_start = 31,
3569 .sw_max = 256,
3570 .vp_max = 4095,
3571 .hp_max = 4096,
33b89928
AT		 3572 .mgr_width_start = 10,
3573 .mgr_height_start = 26,
3574 .mgr_width_max = 2048,
3575 .mgr_height_max = 2048,
ca5ca69c
AT		 3576 .max_lcd_pclk = 170000000,
3577 .max_tv_pclk = 185625000,
dcbe765b
CM		 3578 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3579 .calc_core_clk = calc_core_clk_44xx,
42a6961c 3580 .num_fifos = 5,
66a0f9e4 3581 .gfx_fifo_workaround = true,
dcbe765b
CM		 3582};
3583
264236f8
AT		 3584static const struct dispc_features omap54xx_dispc_feats __initconst = {
3585 .sw_start = 7,
3586 .fp_start = 19,
3587 .bp_start = 31,
3588 .sw_max = 256,
3589 .vp_max = 4095,
3590 .hp_max = 4096,
3591 .mgr_width_start = 11,
3592 .mgr_height_start = 27,
3593 .mgr_width_max = 4096,
3594 .mgr_height_max = 4096,
ca5ca69c
AT		 3595 .max_lcd_pclk = 170000000,
3596 .max_tv_pclk = 186000000,
264236f8
AT		 3597 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3598 .calc_core_clk = calc_core_clk_44xx,
3599 .num_fifos = 5,
3600 .gfx_fifo_workaround = true,
d0df9a2c 3601 .mstandby_workaround = true,
264236f8
AT		 3602};
3603
84b47623 3604static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 3605{
3606 const struct dispc_features *src;
3607 struct dispc_features *dst;
3608
84b47623 3609 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 3610 if (!dst) {
84b47623 3611 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 3612 return -ENOMEM;
3613 }
3614
b2c7d54f 3615 switch (omapdss_get_version()) {
84b47623 3616 case OMAPDSS_VER_OMAP24xx:
dcbe765b 3617 src = &omap24xx_dispc_feats;
84b47623
TV		 3618 break;
3619
3620 case OMAPDSS_VER_OMAP34xx_ES1:
3621 src = &omap34xx_rev1_0_dispc_feats;
3622 break;
3623
3624 case OMAPDSS_VER_OMAP34xx_ES3:
3625 case OMAPDSS_VER_OMAP3630:
3626 case OMAPDSS_VER_AM35xx:
3627 src = &omap34xx_rev3_0_dispc_feats;
3628 break;
3629
3630 case OMAPDSS_VER_OMAP4430_ES1:
3631 case OMAPDSS_VER_OMAP4430_ES2:
3632 case OMAPDSS_VER_OMAP4:
dcbe765b 3633 src = &omap44xx_dispc_feats;
84b47623
TV		 3634 break;
3635
3636 case OMAPDSS_VER_OMAP5:
264236f8 3637 src = &omap54xx_dispc_feats;
84b47623
TV		 3638 break;
3639
3640 default:
dcbe765b
CM		 3641 return -ENODEV;
3642 }
3643
3644 memcpy(dst, src, sizeof(*dst));
3645 dispc.feat = dst;
3646
3647 return 0;
3648}
3649
96e2e637
TV		 3650int dispc_request_irq(irq_handler_t handler, void *dev_id)
3651{
3652 return devm_request_irq(&dispc.pdev->dev, dispc.irq, handler,
3653 IRQF_SHARED, "OMAP DISPC", dev_id);
3654}
348be69d 3655EXPORT_SYMBOL(dispc_request_irq);
96e2e637
TV		 3656
3657void dispc_free_irq(void *dev_id)
3658{
3659 devm_free_irq(&dispc.pdev->dev, dispc.irq, dev_id);
3660}
348be69d 3661EXPORT_SYMBOL(dispc_free_irq);
96e2e637 3662
060b6d9c 3663/* DISPC HW IP initialisation */
6e7e8f06 3664static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3665{
3666 u32 rev;
affe360d 3667 int r = 0;
ea9da36a
SG		 3668 struct resource *dispc_mem;
3669
060b6d9c
SG		 3670 dispc.pdev = pdev;
3671
84b47623 3672 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 3673 if (r)
3674 return r;
3675
ea9da36a
SG		 3676 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3677 if (!dispc_mem) {
3678 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3679 return -EINVAL;
ea9da36a 3680 }
cd3b3449 3681
6e2a14d2
JL		 3682 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3683 resource_size(dispc_mem));
060b6d9c
SG		 3684 if (!dispc.base) {
3685 DSSERR("can't ioremap DISPC\n");
cd3b3449 3686 return -ENOMEM;
affe360d 3687 }
cd3b3449 3688
affe360d 3689 dispc.irq = platform_get_irq(dispc.pdev, 0);
3690 if (dispc.irq < 0) {
3691 DSSERR("platform_get_irq failed\n");
cd3b3449 3692 return -ENODEV;
affe360d 3693 }
3694
4fbafaf3 3695 pm_runtime_enable(&pdev->dev);
48664b21 3696 pm_runtime_irq_safe(&pdev->dev);
4fbafaf3
TV		 3697
3698 r = dispc_runtime_get();
3699 if (r)
3700 goto err_runtime_get;
060b6d9c
SG		 3701
3702 _omap_dispc_initial_config();
3703
060b6d9c 3704 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3705 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3706 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3707
4fbafaf3 3708 dispc_runtime_put();
060b6d9c 3709
04b1fc02
TV		 3710 dss_init_overlay_managers();
3711
e40402cf
TV		 3712 dss_debugfs_create_file("dispc", dispc_dump_regs);
3713
060b6d9c 3714 return 0;
4fbafaf3
TV		 3715
3716err_runtime_get:
3717 pm_runtime_disable(&pdev->dev);
affe360d 3718 return r;
060b6d9c
SG		 3719}
3720
6e7e8f06 3721static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3722{
4fbafaf3
TV		 3723 pm_runtime_disable(&pdev->dev);
3724
04b1fc02
TV		 3725 dss_uninit_overlay_managers();
3726
060b6d9c
SG		 3727 return 0;
3728}
3729
4fbafaf3
TV		 3730static int dispc_runtime_suspend(struct device *dev)
3731{
3732 dispc_save_context();
4fbafaf3
TV		 3733
3734 return 0;
3735}
3736
3737static int dispc_runtime_resume(struct device *dev)
3738{
49ea86f3 3739 dispc_restore_context();
4fbafaf3
TV		 3740
3741 return 0;
3742}
3743
3744static const struct dev_pm_ops dispc_pm_ops = {
3745 .runtime_suspend = dispc_runtime_suspend,
3746 .runtime_resume = dispc_runtime_resume,
3747};
3748
060b6d9c 3749static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3750 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3751 .driver = {
3752 .name = "omapdss_dispc",
3753 .owner = THIS_MODULE,
4fbafaf3 3754 .pm = &dispc_pm_ops,
060b6d9c
SG		 3755 },
3756};
3757
6e7e8f06 3758int __init dispc_init_platform_driver(void)
060b6d9c 3759{
11436e1d 3760 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3761}
3762
6e7e8f06 3763void __exit dispc_uninit_platform_driver(void)
060b6d9c 3764{
04c742c3 3765 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3766}
Linux kernel - Deliverables
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