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Revert "OMAPDSS: APPLY: add fifo merge support funcs"
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
a0b38cc4 40#include <video/omapdss.h>
80c39712
TV		 41
42#include "dss.h"
a0acb557 43#include "dss_features.h"
9b372c2d 44#include "dispc.h"
80c39712
TV		 45
46/* DISPC */
8613b000 47#define DISPC_SZ_REGS SZ_4K
80c39712 48
80c39712
TV		 49#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
50 DISPC_IRQ_OCP_ERR | \
51 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
52 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
53 DISPC_IRQ_SYNC_LOST | \
54 DISPC_IRQ_SYNC_LOST_DIGIT)
55
56#define DISPC_MAX_NR_ISRS 8
57
58struct omap_dispc_isr_data {
59 omap_dispc_isr_t isr;
60 void *arg;
61 u32 mask;
62};
63
5ed8cf5b
TV		 64enum omap_burst_size {
65 BURST_SIZE_X2 = 0,
66 BURST_SIZE_X4 = 1,
67 BURST_SIZE_X8 = 2,
68};
69
80c39712
TV		 70#define REG_GET(idx, start, end) \
71 FLD_GET(dispc_read_reg(idx), start, end)
72
73#define REG_FLD_MOD(idx, val, start, end) \
74 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
75
dfc0fd8d
TV		 76struct dispc_irq_stats {
77 unsigned long last_reset;
78 unsigned irq_count;
79 unsigned irqs[32];
80};
81
dcbe765b
CM		 82struct dispc_features {
83 u8 sw_start;
84 u8 fp_start;
85 u8 bp_start;
86 u16 sw_max;
87 u16 vp_max;
88 u16 hp_max;
89 int (*calc_scaling) (enum omap_channel channel,
90 const struct omap_video_timings *mgr_timings,
91 u16 width, u16 height, u16 out_width, u16 out_height,
92 enum omap_color_mode color_mode, bool *five_taps,
93 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
94 u16 pos_x, unsigned long *core_clk);
95 unsigned long (*calc_core_clk) (enum omap_channel channel,
96 u16 width, u16 height, u16 out_width, u16 out_height);
97};
98
80c39712 99static struct {
060b6d9c 100 struct platform_device *pdev;
80c39712 101 void __iomem *base;
4fbafaf3
TV		 102
103 int ctx_loss_cnt;
104
affe360d 105 int irq;
4fbafaf3 106 struct clk *dss_clk;
80c39712 107
e13a138b 108 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 109
110 spinlock_t irq_lock;
111 u32 irq_error_mask;
112 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
113 u32 error_irqs;
114 struct work_struct error_work;
115
49ea86f3 116 bool ctx_valid;
80c39712 117 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 118
dcbe765b
CM		 119 const struct dispc_features *feat;
120
dfc0fd8d
TV		 121#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
122 spinlock_t irq_stats_lock;
123 struct dispc_irq_stats irq_stats;
124#endif
80c39712
TV		 125} dispc;
126
0d66cbb5
AJ		 127enum omap_color_component {
128 /* used for all color formats for OMAP3 and earlier
129 * and for RGB and Y color component on OMAP4
130 */
131 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
132 /* used for UV component for
133 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
134 * color formats on OMAP4
135 */
136 DISPC_COLOR_COMPONENT_UV = 1 << 1,
137};
138
efa70b3b
CM		 139enum mgr_reg_fields {
140 DISPC_MGR_FLD_ENABLE,
141 DISPC_MGR_FLD_STNTFT,
142 DISPC_MGR_FLD_GO,
143 DISPC_MGR_FLD_TFTDATALINES,
144 DISPC_MGR_FLD_STALLMODE,
145 DISPC_MGR_FLD_TCKENABLE,
146 DISPC_MGR_FLD_TCKSELECTION,
147 DISPC_MGR_FLD_CPR,
148 DISPC_MGR_FLD_FIFOHANDCHECK,
149 /* used to maintain a count of the above fields */
150 DISPC_MGR_FLD_NUM,
151};
152
153static const struct {
154 const char *name;
155 u32 vsync_irq;
156 u32 framedone_irq;
157 u32 sync_lost_irq;
158 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
159} mgr_desc[] = {
160 [OMAP_DSS_CHANNEL_LCD] = {
161 .name = "LCD",
162 .vsync_irq = DISPC_IRQ_VSYNC,
163 .framedone_irq = DISPC_IRQ_FRAMEDONE,
164 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
165 .reg_desc = {
166 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
167 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
168 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
169 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
170 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
171 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
172 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
173 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
174 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
175 },
176 },
177 [OMAP_DSS_CHANNEL_DIGIT] = {
178 .name = "DIGIT",
179 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
180 .framedone_irq = 0,
181 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
182 .reg_desc = {
183 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
184 [DISPC_MGR_FLD_STNTFT] = { },
185 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
186 [DISPC_MGR_FLD_TFTDATALINES] = { },
187 [DISPC_MGR_FLD_STALLMODE] = { },
188 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
189 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
190 [DISPC_MGR_FLD_CPR] = { },
191 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
192 },
193 },
194 [OMAP_DSS_CHANNEL_LCD2] = {
195 .name = "LCD2",
196 .vsync_irq = DISPC_IRQ_VSYNC2,
197 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
198 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
199 .reg_desc = {
200 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
201 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
202 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
203 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
204 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
205 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
206 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
207 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
208 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
209 },
210 },
e86d456a
CM		 211 [OMAP_DSS_CHANNEL_LCD3] = {
212 .name = "LCD3",
213 .vsync_irq = DISPC_IRQ_VSYNC3,
214 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
215 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
216 .reg_desc = {
217 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
218 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
219 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
220 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
221 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
222 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
223 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
224 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
225 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
226 },
227 },
efa70b3b
CM		 228};
229
80c39712
TV		 230static void _omap_dispc_set_irqs(void);
231
55978cc2 232static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 233{
55978cc2 234 __raw_writel(val, dispc.base + idx);
80c39712
TV		 235}
236
55978cc2 237static inline u32 dispc_read_reg(const u16 idx)
80c39712 238{
55978cc2 239 return __raw_readl(dispc.base + idx);
80c39712
TV		 240}
241
efa70b3b
CM		 242static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
243{
244 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
245 return REG_GET(rfld.reg, rfld.high, rfld.low);
246}
247
248static void mgr_fld_write(enum omap_channel channel,
249 enum mgr_reg_fields regfld, int val) {
250 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
251 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
252}
253
80c39712 254#define SR(reg) \
55978cc2 255 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 256#define RR(reg) \
55978cc2 257 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 258
4fbafaf3 259static void dispc_save_context(void)
80c39712 260{
c6104b8e 261 int i, j;
80c39712 262
4fbafaf3
TV		 263 DSSDBG("dispc_save_context\n");
264
80c39712
TV		 265 SR(IRQENABLE);
266 SR(CONTROL);
267 SR(CONFIG);
80c39712 268 SR(LINE_NUMBER);
11354dd5
AT		 269 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
270 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 271 SR(GLOBAL_ALPHA);
2a205f34
SS		 272 if (dss_has_feature(FEAT_MGR_LCD2)) {
273 SR(CONTROL2);
2a205f34
SS		 274 SR(CONFIG2);
275 }
e86d456a
CM		 276 if (dss_has_feature(FEAT_MGR_LCD3)) {
277 SR(CONTROL3);
278 SR(CONFIG3);
279 }
80c39712 280
c6104b8e
AT		 281 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
282 SR(DEFAULT_COLOR(i));
283 SR(TRANS_COLOR(i));
284 SR(SIZE_MGR(i));
285 if (i == OMAP_DSS_CHANNEL_DIGIT)
286 continue;
287 SR(TIMING_H(i));
288 SR(TIMING_V(i));
289 SR(POL_FREQ(i));
290 SR(DIVISORo(i));
291
292 SR(DATA_CYCLE1(i));
293 SR(DATA_CYCLE2(i));
294 SR(DATA_CYCLE3(i));
295
332e9d70 296 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 297 SR(CPR_COEF_R(i));
298 SR(CPR_COEF_G(i));
299 SR(CPR_COEF_B(i));
332e9d70 300 }
2a205f34 301 }
80c39712 302
c6104b8e
AT		 303 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
304 SR(OVL_BA0(i));
305 SR(OVL_BA1(i));
306 SR(OVL_POSITION(i));
307 SR(OVL_SIZE(i));
308 SR(OVL_ATTRIBUTES(i));
309 SR(OVL_FIFO_THRESHOLD(i));
310 SR(OVL_ROW_INC(i));
311 SR(OVL_PIXEL_INC(i));
312 if (dss_has_feature(FEAT_PRELOAD))
313 SR(OVL_PRELOAD(i));
314 if (i == OMAP_DSS_GFX) {
315 SR(OVL_WINDOW_SKIP(i));
316 SR(OVL_TABLE_BA(i));
317 continue;
318 }
319 SR(OVL_FIR(i));
320 SR(OVL_PICTURE_SIZE(i));
321 SR(OVL_ACCU0(i));
322 SR(OVL_ACCU1(i));
9b372c2d 323
c6104b8e
AT		 324 for (j = 0; j < 8; j++)
325 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 326
c6104b8e
AT		 327 for (j = 0; j < 8; j++)
328 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 329
c6104b8e
AT		 330 for (j = 0; j < 5; j++)
331 SR(OVL_CONV_COEF(i, j));
ab5ca071 332
c6104b8e
AT		 333 if (dss_has_feature(FEAT_FIR_COEF_V)) {
334 for (j = 0; j < 8; j++)
335 SR(OVL_FIR_COEF_V(i, j));
336 }
9b372c2d 337
c6104b8e
AT		 338 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
339 SR(OVL_BA0_UV(i));
340 SR(OVL_BA1_UV(i));
341 SR(OVL_FIR2(i));
342 SR(OVL_ACCU2_0(i));
343 SR(OVL_ACCU2_1(i));
ab5ca071 344
c6104b8e
AT		 345 for (j = 0; j < 8; j++)
346 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 347
c6104b8e
AT		 348 for (j = 0; j < 8; j++)
349 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 350
c6104b8e
AT		 351 for (j = 0; j < 8; j++)
352 SR(OVL_FIR_COEF_V2(i, j));
353 }
354 if (dss_has_feature(FEAT_ATTR2))
355 SR(OVL_ATTRIBUTES2(i));
ab5ca071 356 }
0cf35df3
MR		 357
358 if (dss_has_feature(FEAT_CORE_CLK_DIV))
359 SR(DIVISOR);
49ea86f3 360
00928eaf 361 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 362 dispc.ctx_valid = true;
363
364 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 365}
366
4fbafaf3 367static void dispc_restore_context(void)
80c39712 368{
c6104b8e 369 int i, j, ctx;
4fbafaf3
TV		 370
371 DSSDBG("dispc_restore_context\n");
372
49ea86f3
TV		 373 if (!dispc.ctx_valid)
374 return;
375
00928eaf 376 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 377
378 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
379 return;
380
381 DSSDBG("ctx_loss_count: saved %d, current %d\n",
382 dispc.ctx_loss_cnt, ctx);
383
75c7d59d 384 /*RR(IRQENABLE);*/
80c39712
TV		 385 /*RR(CONTROL);*/
386 RR(CONFIG);
80c39712 387 RR(LINE_NUMBER);
11354dd5
AT		 388 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
389 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 390 RR(GLOBAL_ALPHA);
c6104b8e 391 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 392 RR(CONFIG2);
e86d456a
CM		 393 if (dss_has_feature(FEAT_MGR_LCD3))
394 RR(CONFIG3);
80c39712 395
c6104b8e
AT		 396 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
397 RR(DEFAULT_COLOR(i));
398 RR(TRANS_COLOR(i));
399 RR(SIZE_MGR(i));
400 if (i == OMAP_DSS_CHANNEL_DIGIT)
401 continue;
402 RR(TIMING_H(i));
403 RR(TIMING_V(i));
404 RR(POL_FREQ(i));
405 RR(DIVISORo(i));
406
407 RR(DATA_CYCLE1(i));
408 RR(DATA_CYCLE2(i));
409 RR(DATA_CYCLE3(i));
2a205f34 410
332e9d70 411 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 412 RR(CPR_COEF_R(i));
413 RR(CPR_COEF_G(i));
414 RR(CPR_COEF_B(i));
332e9d70 415 }
2a205f34 416 }
80c39712 417
c6104b8e
AT		 418 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
419 RR(OVL_BA0(i));
420 RR(OVL_BA1(i));
421 RR(OVL_POSITION(i));
422 RR(OVL_SIZE(i));
423 RR(OVL_ATTRIBUTES(i));
424 RR(OVL_FIFO_THRESHOLD(i));
425 RR(OVL_ROW_INC(i));
426 RR(OVL_PIXEL_INC(i));
427 if (dss_has_feature(FEAT_PRELOAD))
428 RR(OVL_PRELOAD(i));
429 if (i == OMAP_DSS_GFX) {
430 RR(OVL_WINDOW_SKIP(i));
431 RR(OVL_TABLE_BA(i));
432 continue;
433 }
434 RR(OVL_FIR(i));
435 RR(OVL_PICTURE_SIZE(i));
436 RR(OVL_ACCU0(i));
437 RR(OVL_ACCU1(i));
9b372c2d 438
c6104b8e
AT		 439 for (j = 0; j < 8; j++)
440 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 441
c6104b8e
AT		 442 for (j = 0; j < 8; j++)
443 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 444
c6104b8e
AT		 445 for (j = 0; j < 5; j++)
446 RR(OVL_CONV_COEF(i, j));
ab5ca071 447
c6104b8e
AT		 448 if (dss_has_feature(FEAT_FIR_COEF_V)) {
449 for (j = 0; j < 8; j++)
450 RR(OVL_FIR_COEF_V(i, j));
451 }
9b372c2d 452
c6104b8e
AT		 453 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
454 RR(OVL_BA0_UV(i));
455 RR(OVL_BA1_UV(i));
456 RR(OVL_FIR2(i));
457 RR(OVL_ACCU2_0(i));
458 RR(OVL_ACCU2_1(i));
ab5ca071 459
c6104b8e
AT		 460 for (j = 0; j < 8; j++)
461 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 462
c6104b8e
AT		 463 for (j = 0; j < 8; j++)
464 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 465
c6104b8e
AT		 466 for (j = 0; j < 8; j++)
467 RR(OVL_FIR_COEF_V2(i, j));
468 }
469 if (dss_has_feature(FEAT_ATTR2))
470 RR(OVL_ATTRIBUTES2(i));
ab5ca071 471 }
80c39712 472
0cf35df3
MR		 473 if (dss_has_feature(FEAT_CORE_CLK_DIV))
474 RR(DIVISOR);
475
80c39712
TV		 476 /* enable last, because LCD & DIGIT enable are here */
477 RR(CONTROL);
2a205f34
SS		 478 if (dss_has_feature(FEAT_MGR_LCD2))
479 RR(CONTROL2);
e86d456a
CM		 480 if (dss_has_feature(FEAT_MGR_LCD3))
481 RR(CONTROL3);
75c7d59d
VS		 482 /* clear spurious SYNC_LOST_DIGIT interrupts */
483 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
484
485 /*
486 * enable last so IRQs won't trigger before
487 * the context is fully restored
488 */
489 RR(IRQENABLE);
49ea86f3
TV		 490
491 DSSDBG("context restored\n");
80c39712
TV		 492}
493
494#undef SR
495#undef RR
496
4fbafaf3
TV		 497int dispc_runtime_get(void)
498{
499 int r;
500
501 DSSDBG("dispc_runtime_get\n");
502
503 r = pm_runtime_get_sync(&dispc.pdev->dev);
504 WARN_ON(r < 0);
505 return r < 0 ? r : 0;
506}
507
508void dispc_runtime_put(void)
509{
510 int r;
511
512 DSSDBG("dispc_runtime_put\n");
513
0eaf9f52 514 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 515 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 516}
517
3dcec4d6
TV		 518u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
519{
efa70b3b 520 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 521}
522
7d1365c9
TV		 523u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
524{
efa70b3b 525 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 526}
527
26d9dd0d 528bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 529{
efa70b3b 530 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 531}
532
26d9dd0d 533void dispc_mgr_go(enum omap_channel channel)
80c39712 534{
2a205f34 535 bool enable_bit, go_bit;
80c39712 536
80c39712 537 /* if the channel is not enabled, we don't need GO */
efa70b3b 538 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
2a205f34
SS		 539
540 if (!enable_bit)
e6d80f95 541 return;
80c39712 542
efa70b3b 543 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
2a205f34
SS		 544
545 if (go_bit) {
80c39712 546 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 547 return;
80c39712
TV		 548 }
549
efa70b3b 550 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 551
efa70b3b 552 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 553}
554
f0e5caab 555static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 556{
9b372c2d 557 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 558}
559
f0e5caab 560static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 561{
9b372c2d 562 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 563}
564
f0e5caab 565static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 566{
9b372c2d 567 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 568}
569
f0e5caab 570static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 571{
572 BUG_ON(plane == OMAP_DSS_GFX);
573
574 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
575}
576
f0e5caab
TV		 577static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
578 u32 value)
ab5ca071
AJ		 579{
580 BUG_ON(plane == OMAP_DSS_GFX);
581
582 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
583}
584
f0e5caab 585static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 586{
587 BUG_ON(plane == OMAP_DSS_GFX);
588
589 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
590}
591
debd9074
CM		 592static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
593 int fir_vinc, int five_taps,
594 enum omap_color_component color_comp)
80c39712 595{
debd9074 596 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 597 int i;
598
debd9074
CM		 599 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
600 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 601
602 for (i = 0; i < 8; i++) {
603 u32 h, hv;
604
debd9074
CM		 605 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
606 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
607 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
608 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
609 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
610 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
611 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
612 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 613
0d66cbb5 614 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 615 dispc_ovl_write_firh_reg(plane, i, h);
616 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 617 } else {
f0e5caab
TV		 618 dispc_ovl_write_firh2_reg(plane, i, h);
619 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 620 }
621
80c39712
TV		 622 }
623
66be8f6c
GI		 624 if (five_taps) {
625 for (i = 0; i < 8; i++) {
626 u32 v;
debd9074
CM		 627 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
628 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 629 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 630 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 631 else
f0e5caab 632 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 633 }
80c39712
TV		 634 }
635}
636
637static void _dispc_setup_color_conv_coef(void)
638{
ac01c29e 639 int i;
80c39712
TV		 640 const struct color_conv_coef {
641 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
642 int full_range;
643 } ctbl_bt601_5 = {
644 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
645 };
646
647 const struct color_conv_coef *ct;
648
649#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
650
651 ct = &ctbl_bt601_5;
652
ac01c29e
AT		 653 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
654 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
655 CVAL(ct->rcr, ct->ry));
656 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
657 CVAL(ct->gy, ct->rcb));
658 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
659 CVAL(ct->gcb, ct->gcr));
660 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
661 CVAL(ct->bcr, ct->by));
662 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
663 CVAL(0, ct->bcb));
664
665 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
666 11, 11);
667 }
80c39712
TV		 668
669#undef CVAL
80c39712
TV		 670}
671
672
f0e5caab 673static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 674{
9b372c2d 675 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 676}
677
f0e5caab 678static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 679{
9b372c2d 680 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 681}
682
f0e5caab 683static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 684{
685 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
686}
687
f0e5caab 688static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 689{
690 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
691}
692
f0e5caab 693static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 694{
80c39712 695 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 696
697 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 698}
699
f0e5caab 700static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 701{
80c39712 702 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 703
704 if (plane == OMAP_DSS_GFX)
705 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
706 else
707 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 708}
709
f0e5caab 710static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 711{
712 u32 val;
80c39712
TV		 713
714 BUG_ON(plane == OMAP_DSS_GFX);
715
716 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 717
718 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 719}
720
54128701
AT		 721static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
722{
723 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
724
725 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
726 return;
727
728 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
729}
730
731static void dispc_ovl_enable_zorder_planes(void)
732{
733 int i;
734
735 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
736 return;
737
738 for (i = 0; i < dss_feat_get_num_ovls(); i++)
739 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
740}
741
f0e5caab 742static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 743{
f6dc8150 744 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 745
f6dc8150 746 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 747 return;
748
9b372c2d 749 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 750}
751
f0e5caab 752static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 753{
b8c095b4 754 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 755 int shift;
f6dc8150 756 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 757
f6dc8150 758 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 759 return;
a0acb557 760
fe3cc9d6
TV		 761 shift = shifts[plane];
762 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 763}
764
f0e5caab 765static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 766{
9b372c2d 767 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 768}
769
f0e5caab 770static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 771{
9b372c2d 772 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 773}
774
f0e5caab 775static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 776 enum omap_color_mode color_mode)
777{
778 u32 m = 0;
f20e4220
AJ		 779 if (plane != OMAP_DSS_GFX) {
780 switch (color_mode) {
781 case OMAP_DSS_COLOR_NV12:
782 m = 0x0; break;
08f3267e 783 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 784 m = 0x1; break;
785 case OMAP_DSS_COLOR_RGBA16:
786 m = 0x2; break;
08f3267e 787 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 788 m = 0x4; break;
789 case OMAP_DSS_COLOR_ARGB16:
790 m = 0x5; break;
791 case OMAP_DSS_COLOR_RGB16:
792 m = 0x6; break;
793 case OMAP_DSS_COLOR_ARGB16_1555:
794 m = 0x7; break;
795 case OMAP_DSS_COLOR_RGB24U:
796 m = 0x8; break;
797 case OMAP_DSS_COLOR_RGB24P:
798 m = 0x9; break;
799 case OMAP_DSS_COLOR_YUV2:
800 m = 0xa; break;
801 case OMAP_DSS_COLOR_UYVY:
802 m = 0xb; break;
803 case OMAP_DSS_COLOR_ARGB32:
804 m = 0xc; break;
805 case OMAP_DSS_COLOR_RGBA32:
806 m = 0xd; break;
807 case OMAP_DSS_COLOR_RGBX32:
808 m = 0xe; break;
809 case OMAP_DSS_COLOR_XRGB16_1555:
810 m = 0xf; break;
811 default:
c6eee968 812 BUG(); return;
f20e4220
AJ		 813 }
814 } else {
815 switch (color_mode) {
816 case OMAP_DSS_COLOR_CLUT1:
817 m = 0x0; break;
818 case OMAP_DSS_COLOR_CLUT2:
819 m = 0x1; break;
820 case OMAP_DSS_COLOR_CLUT4:
821 m = 0x2; break;
822 case OMAP_DSS_COLOR_CLUT8:
823 m = 0x3; break;
824 case OMAP_DSS_COLOR_RGB12U:
825 m = 0x4; break;
826 case OMAP_DSS_COLOR_ARGB16:
827 m = 0x5; break;
828 case OMAP_DSS_COLOR_RGB16:
829 m = 0x6; break;
830 case OMAP_DSS_COLOR_ARGB16_1555:
831 m = 0x7; break;
832 case OMAP_DSS_COLOR_RGB24U:
833 m = 0x8; break;
834 case OMAP_DSS_COLOR_RGB24P:
835 m = 0x9; break;
08f3267e 836 case OMAP_DSS_COLOR_RGBX16:
f20e4220 837 m = 0xa; break;
08f3267e 838 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 839 m = 0xb; break;
840 case OMAP_DSS_COLOR_ARGB32:
841 m = 0xc; break;
842 case OMAP_DSS_COLOR_RGBA32:
843 m = 0xd; break;
844 case OMAP_DSS_COLOR_RGBX32:
845 m = 0xe; break;
846 case OMAP_DSS_COLOR_XRGB16_1555:
847 m = 0xf; break;
848 default:
c6eee968 849 BUG(); return;
f20e4220 850 }
80c39712
TV		 851 }
852
9b372c2d 853 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 854}
855
65e006ff
CM		 856static void dispc_ovl_configure_burst_type(enum omap_plane plane,
857 enum omap_dss_rotation_type rotation_type)
858{
859 if (dss_has_feature(FEAT_BURST_2D) == 0)
860 return;
861
862 if (rotation_type == OMAP_DSS_ROT_TILER)
863 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
864 else
865 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
866}
867
f427984e 868void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 869{
870 int shift;
871 u32 val;
2a205f34 872 int chan = 0, chan2 = 0;
80c39712
TV		 873
874 switch (plane) {
875 case OMAP_DSS_GFX:
876 shift = 8;
877 break;
878 case OMAP_DSS_VIDEO1:
879 case OMAP_DSS_VIDEO2:
b8c095b4 880 case OMAP_DSS_VIDEO3:
80c39712
TV		 881 shift = 16;
882 break;
883 default:
884 BUG();
885 return;
886 }
887
9b372c2d 888 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 889 if (dss_has_feature(FEAT_MGR_LCD2)) {
890 switch (channel) {
891 case OMAP_DSS_CHANNEL_LCD:
892 chan = 0;
893 chan2 = 0;
894 break;
895 case OMAP_DSS_CHANNEL_DIGIT:
896 chan = 1;
897 chan2 = 0;
898 break;
899 case OMAP_DSS_CHANNEL_LCD2:
900 chan = 0;
901 chan2 = 1;
902 break;
e86d456a
CM		 903 case OMAP_DSS_CHANNEL_LCD3:
904 if (dss_has_feature(FEAT_MGR_LCD3)) {
905 chan = 0;
906 chan2 = 2;
907 } else {
908 BUG();
909 return;
910 }
911 break;
2a205f34
SS		 912 default:
913 BUG();
c6eee968 914 return;
2a205f34
SS		 915 }
916
917 val = FLD_MOD(val, chan, shift, shift);
918 val = FLD_MOD(val, chan2, 31, 30);
919 } else {
920 val = FLD_MOD(val, channel, shift, shift);
921 }
9b372c2d 922 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 923}
924
2cc5d1af
TV		 925static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
926{
927 int shift;
928 u32 val;
929 enum omap_channel channel;
930
931 switch (plane) {
932 case OMAP_DSS_GFX:
933 shift = 8;
934 break;
935 case OMAP_DSS_VIDEO1:
936 case OMAP_DSS_VIDEO2:
937 case OMAP_DSS_VIDEO3:
938 shift = 16;
939 break;
940 default:
941 BUG();
c6eee968 942 return 0;
2cc5d1af
TV		 943 }
944
945 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
946
e86d456a
CM		 947 if (dss_has_feature(FEAT_MGR_LCD3)) {
948 if (FLD_GET(val, 31, 30) == 0)
949 channel = FLD_GET(val, shift, shift);
950 else if (FLD_GET(val, 31, 30) == 1)
951 channel = OMAP_DSS_CHANNEL_LCD2;
952 else
953 channel = OMAP_DSS_CHANNEL_LCD3;
954 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 955 if (FLD_GET(val, 31, 30) == 0)
956 channel = FLD_GET(val, shift, shift);
957 else
958 channel = OMAP_DSS_CHANNEL_LCD2;
959 } else {
960 channel = FLD_GET(val, shift, shift);
961 }
962
963 return channel;
964}
965
f0e5caab 966static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 967 enum omap_burst_size burst_size)
968{
b8c095b4 969 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 970 int shift;
80c39712 971
fe3cc9d6 972 shift = shifts[plane];
5ed8cf5b 973 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 974}
975
5ed8cf5b
TV		 976static void dispc_configure_burst_sizes(void)
977{
978 int i;
979 const int burst_size = BURST_SIZE_X8;
980
981 /* Configure burst size always to maximum size */
982 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 983 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 984}
985
83fa2f2e 986static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 987{
988 unsigned unit = dss_feat_get_burst_size_unit();
989 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
990 return unit * 8;
991}
992
d3862610
M		 993void dispc_enable_gamma_table(bool enable)
994{
995 /*
996 * This is partially implemented to support only disabling of
997 * the gamma table.
998 */
999 if (enable) {
1000 DSSWARN("Gamma table enabling for TV not yet supported");
1001 return;
1002 }
1003
1004 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1005}
1006
c64dca40 1007static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1008{
efa70b3b 1009 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1010 return;
1011
efa70b3b 1012 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1013}
1014
c64dca40 1015static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 1016 struct omap_dss_cpr_coefs *coefs)
1017{
1018 u32 coef_r, coef_g, coef_b;
1019
dd88b7a6 1020 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1021 return;
1022
1023 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1024 FLD_VAL(coefs->rb, 9, 0);
1025 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1026 FLD_VAL(coefs->gb, 9, 0);
1027 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1028 FLD_VAL(coefs->bb, 9, 0);
1029
1030 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1031 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1032 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1033}
1034
f0e5caab 1035static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1036{
1037 u32 val;
1038
1039 BUG_ON(plane == OMAP_DSS_GFX);
1040
9b372c2d 1041 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1042 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1043 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1044}
1045
c3d92529 1046static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 1047{
b8c095b4 1048 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1049 int shift;
80c39712 1050
fe3cc9d6
TV		 1051 shift = shifts[plane];
1052 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1053}
1054
8f366162 1055static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1056 u16 height)
80c39712
TV		 1057{
1058 u32 val;
80c39712 1059
80c39712 1060 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 1061 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1062}
1063
1064static void dispc_read_plane_fifo_sizes(void)
1065{
80c39712
TV		 1066 u32 size;
1067 int plane;
a0acb557 1068 u8 start, end;
5ed8cf5b
TV		 1069 u32 unit;
1070
1071 unit = dss_feat_get_buffer_size_unit();
80c39712 1072
a0acb557 1073 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1074
e13a138b 1075 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 1076 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1077 size *= unit;
80c39712
TV		 1078 dispc.fifo_size[plane] = size;
1079 }
80c39712
TV		 1080}
1081
83fa2f2e 1082static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1083{
1084 return dispc.fifo_size[plane];
1085}
1086
6f04e1bf 1087void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1088{
a0acb557 1089 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1090 u32 unit;
1091
1092 unit = dss_feat_get_buffer_size_unit();
1093
1094 WARN_ON(low % unit != 0);
1095 WARN_ON(high % unit != 0);
1096
1097 low /= unit;
1098 high /= unit;
a0acb557 1099
9b372c2d
AT		 1100 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1101 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1102
3cb5d966 1103 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1104 plane,
9b372c2d 1105 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1106 lo_start, lo_end) * unit,
9b372c2d 1107 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1108 hi_start, hi_end) * unit,
1109 low * unit, high * unit);
80c39712 1110
9b372c2d 1111 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1112 FLD_VAL(high, hi_start, hi_end) |
1113 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1114}
1115
1116void dispc_enable_fifomerge(bool enable)
1117{
e6b0f884
TV		 1118 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1119 WARN_ON(enable);
1120 return;
1121 }
1122
80c39712
TV		 1123 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1124 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1125}
1126
83fa2f2e 1127void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1128 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1129 bool manual_update)
83fa2f2e
TV		 1130{
1131 /*
1132 * All sizes are in bytes. Both the buffer and burst are made of
1133 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1134 */
1135
1136 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1137 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1138 int i;
83fa2f2e
TV		 1139
1140 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1141 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1142
e0e405b9
TV		 1143 if (use_fifomerge) {
1144 total_fifo_size = 0;
1145 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1146 total_fifo_size += dispc_ovl_get_fifo_size(i);
1147 } else {
1148 total_fifo_size = ovl_fifo_size;
1149 }
1150
1151 /*
1152 * We use the same low threshold for both fifomerge and non-fifomerge
1153 * cases, but for fifomerge we calculate the high threshold using the
1154 * combined fifo size
1155 */
1156
3568f2a4 1157 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1158 *fifo_low = ovl_fifo_size - burst_size * 2;
1159 *fifo_high = total_fifo_size - burst_size;
1160 } else {
1161 *fifo_low = ovl_fifo_size - burst_size;
1162 *fifo_high = total_fifo_size - buf_unit;
1163 }
83fa2f2e
TV		 1164}
1165
f0e5caab 1166static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1167 int hinc, int vinc,
1168 enum omap_color_component color_comp)
80c39712
TV		 1169{
1170 u32 val;
80c39712 1171
0d66cbb5
AJ		 1172 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1173 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1174
0d66cbb5
AJ		 1175 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1176 &hinc_start, &hinc_end);
1177 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1178 &vinc_start, &vinc_end);
1179 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1180 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1181
0d66cbb5
AJ		 1182 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1183 } else {
1184 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1185 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1186 }
80c39712
TV		 1187}
1188
f0e5caab 1189static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1190{
1191 u32 val;
87a7484b 1192 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1193
87a7484b
AT		 1194 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1195 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1196
1197 val = FLD_VAL(vaccu, vert_start, vert_end) |
1198 FLD_VAL(haccu, hor_start, hor_end);
1199
9b372c2d 1200 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1201}
1202
f0e5caab 1203static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1204{
1205 u32 val;
87a7484b 1206 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1207
87a7484b
AT		 1208 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1209 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1210
1211 val = FLD_VAL(vaccu, vert_start, vert_end) |
1212 FLD_VAL(haccu, hor_start, hor_end);
1213
9b372c2d 1214 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1215}
1216
f0e5caab
TV		 1217static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1218 int vaccu)
ab5ca071
AJ		 1219{
1220 u32 val;
1221
1222 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1223 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1224}
1225
f0e5caab
TV		 1226static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1227 int vaccu)
ab5ca071
AJ		 1228{
1229 u32 val;
1230
1231 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1232 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1233}
80c39712 1234
f0e5caab 1235static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1236 u16 orig_width, u16 orig_height,
1237 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1238 bool five_taps, u8 rotation,
1239 enum omap_color_component color_comp)
80c39712 1240{
0d66cbb5 1241 int fir_hinc, fir_vinc;
80c39712 1242
ed14a3ce
AJ		 1243 fir_hinc = 1024 * orig_width / out_width;
1244 fir_vinc = 1024 * orig_height / out_height;
80c39712 1245
debd9074
CM		 1246 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1247 color_comp);
f0e5caab 1248 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1249}
1250
05dd0f53
CM		 1251static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1252 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1253 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1254{
1255 int h_accu2_0, h_accu2_1;
1256 int v_accu2_0, v_accu2_1;
1257 int chroma_hinc, chroma_vinc;
1258 int idx;
1259
1260 struct accu {
1261 s8 h0_m, h0_n;
1262 s8 h1_m, h1_n;
1263 s8 v0_m, v0_n;
1264 s8 v1_m, v1_n;
1265 };
1266
1267 const struct accu *accu_table;
1268 const struct accu *accu_val;
1269
1270 static const struct accu accu_nv12[4] = {
1271 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1272 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1273 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1274 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1275 };
1276
1277 static const struct accu accu_nv12_ilace[4] = {
1278 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1279 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1280 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1281 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1282 };
1283
1284 static const struct accu accu_yuv[4] = {
1285 { 0, 1, 0, 1, 0, 1, 0, 1 },
1286 { 0, 1, 0, 1, 0, 1, 0, 1 },
1287 { -1, 1, 0, 1, 0, 1, 0, 1 },
1288 { 0, 1, 0, 1, -1, 1, 0, 1 },
1289 };
1290
1291 switch (rotation) {
1292 case OMAP_DSS_ROT_0:
1293 idx = 0;
1294 break;
1295 case OMAP_DSS_ROT_90:
1296 idx = 1;
1297 break;
1298 case OMAP_DSS_ROT_180:
1299 idx = 2;
1300 break;
1301 case OMAP_DSS_ROT_270:
1302 idx = 3;
1303 break;
1304 default:
1305 BUG();
c6eee968 1306 return;
05dd0f53
CM		 1307 }
1308
1309 switch (color_mode) {
1310 case OMAP_DSS_COLOR_NV12:
1311 if (ilace)
1312 accu_table = accu_nv12_ilace;
1313 else
1314 accu_table = accu_nv12;
1315 break;
1316 case OMAP_DSS_COLOR_YUV2:
1317 case OMAP_DSS_COLOR_UYVY:
1318 accu_table = accu_yuv;
1319 break;
1320 default:
1321 BUG();
c6eee968 1322 return;
05dd0f53
CM		 1323 }
1324
1325 accu_val = &accu_table[idx];
1326
1327 chroma_hinc = 1024 * orig_width / out_width;
1328 chroma_vinc = 1024 * orig_height / out_height;
1329
1330 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1331 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1332 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1333 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1334
1335 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1336 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1337}
1338
f0e5caab 1339static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1340 u16 orig_width, u16 orig_height,
1341 u16 out_width, u16 out_height,
1342 bool ilace, bool five_taps,
1343 bool fieldmode, enum omap_color_mode color_mode,
1344 u8 rotation)
1345{
1346 int accu0 = 0;
1347 int accu1 = 0;
1348 u32 l;
80c39712 1349
f0e5caab 1350 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1351 out_width, out_height, five_taps,
1352 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1353 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1354
87a7484b
AT		 1355 /* RESIZEENABLE and VERTICALTAPS */
1356 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1357 l |= (orig_width != out_width) ? (1 << 5) : 0;
1358 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1359 l |= five_taps ? (1 << 21) : 0;
80c39712 1360
87a7484b
AT		 1361 /* VRESIZECONF and HRESIZECONF */
1362 if (dss_has_feature(FEAT_RESIZECONF)) {
1363 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1364 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1365 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1366 }
80c39712 1367
87a7484b
AT		 1368 /* LINEBUFFERSPLIT */
1369 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1370 l &= ~(0x1 << 22);
1371 l |= five_taps ? (1 << 22) : 0;
1372 }
80c39712 1373
9b372c2d 1374 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1375
1376 /*
1377 * field 0 = even field = bottom field
1378 * field 1 = odd field = top field
1379 */
1380 if (ilace && !fieldmode) {
1381 accu1 = 0;
0d66cbb5 1382 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1383 if (accu0 >= 1024/2) {
1384 accu1 = 1024/2;
1385 accu0 -= accu1;
1386 }
1387 }
1388
f0e5caab
TV		 1389 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1390 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1391}
1392
f0e5caab 1393static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1394 u16 orig_width, u16 orig_height,
1395 u16 out_width, u16 out_height,
1396 bool ilace, bool five_taps,
1397 bool fieldmode, enum omap_color_mode color_mode,
1398 u8 rotation)
1399{
1400 int scale_x = out_width != orig_width;
1401 int scale_y = out_height != orig_height;
1402
1403 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1404 return;
1405 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1406 color_mode != OMAP_DSS_COLOR_UYVY &&
1407 color_mode != OMAP_DSS_COLOR_NV12)) {
1408 /* reset chroma resampling for RGB formats */
1409 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1410 return;
1411 }
36377357
TV		 1412
1413 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1414 out_height, ilace, color_mode, rotation);
1415
0d66cbb5
AJ		 1416 switch (color_mode) {
1417 case OMAP_DSS_COLOR_NV12:
1418 /* UV is subsampled by 2 vertically*/
1419 orig_height >>= 1;
1420 /* UV is subsampled by 2 horz.*/
1421 orig_width >>= 1;
1422 break;
1423 case OMAP_DSS_COLOR_YUV2:
1424 case OMAP_DSS_COLOR_UYVY:
1425 /*For YUV422 with 90/270 rotation,
1426 *we don't upsample chroma
1427 */
1428 if (rotation == OMAP_DSS_ROT_0 ||
1429 rotation == OMAP_DSS_ROT_180)
1430 /* UV is subsampled by 2 hrz*/
1431 orig_width >>= 1;
1432 /* must use FIR for YUV422 if rotated */
1433 if (rotation != OMAP_DSS_ROT_0)
1434 scale_x = scale_y = true;
1435 break;
1436 default:
1437 BUG();
c6eee968 1438 return;
0d66cbb5
AJ		 1439 }
1440
1441 if (out_width != orig_width)
1442 scale_x = true;
1443 if (out_height != orig_height)
1444 scale_y = true;
1445
f0e5caab 1446 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1447 out_width, out_height, five_taps,
1448 rotation, DISPC_COLOR_COMPONENT_UV);
1449
1450 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1451 (scale_x || scale_y) ? 1 : 0, 8, 8);
1452 /* set H scaling */
1453 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1454 /* set V scaling */
1455 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1456}
1457
f0e5caab 1458static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1459 u16 orig_width, u16 orig_height,
1460 u16 out_width, u16 out_height,
1461 bool ilace, bool five_taps,
1462 bool fieldmode, enum omap_color_mode color_mode,
1463 u8 rotation)
1464{
1465 BUG_ON(plane == OMAP_DSS_GFX);
1466
f0e5caab 1467 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1468 orig_width, orig_height,
1469 out_width, out_height,
1470 ilace, five_taps,
1471 fieldmode, color_mode,
1472 rotation);
1473
f0e5caab 1474 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1475 orig_width, orig_height,
1476 out_width, out_height,
1477 ilace, five_taps,
1478 fieldmode, color_mode,
1479 rotation);
1480}
1481
f0e5caab 1482static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1483 bool mirroring, enum omap_color_mode color_mode)
1484{
87a7484b
AT		 1485 bool row_repeat = false;
1486 int vidrot = 0;
1487
80c39712
TV		 1488 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1489 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1490
1491 if (mirroring) {
1492 switch (rotation) {
1493 case OMAP_DSS_ROT_0:
1494 vidrot = 2;
1495 break;
1496 case OMAP_DSS_ROT_90:
1497 vidrot = 1;
1498 break;
1499 case OMAP_DSS_ROT_180:
1500 vidrot = 0;
1501 break;
1502 case OMAP_DSS_ROT_270:
1503 vidrot = 3;
1504 break;
1505 }
1506 } else {
1507 switch (rotation) {
1508 case OMAP_DSS_ROT_0:
1509 vidrot = 0;
1510 break;
1511 case OMAP_DSS_ROT_90:
1512 vidrot = 1;
1513 break;
1514 case OMAP_DSS_ROT_180:
1515 vidrot = 2;
1516 break;
1517 case OMAP_DSS_ROT_270:
1518 vidrot = 3;
1519 break;
1520 }
1521 }
1522
80c39712 1523 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1524 row_repeat = true;
80c39712 1525 else
87a7484b 1526 row_repeat = false;
80c39712 1527 }
87a7484b 1528
9b372c2d 1529 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1530 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1531 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1532 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1533}
1534
1535static int color_mode_to_bpp(enum omap_color_mode color_mode)
1536{
1537 switch (color_mode) {
1538 case OMAP_DSS_COLOR_CLUT1:
1539 return 1;
1540 case OMAP_DSS_COLOR_CLUT2:
1541 return 2;
1542 case OMAP_DSS_COLOR_CLUT4:
1543 return 4;
1544 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1545 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1546 return 8;
1547 case OMAP_DSS_COLOR_RGB12U:
1548 case OMAP_DSS_COLOR_RGB16:
1549 case OMAP_DSS_COLOR_ARGB16:
1550 case OMAP_DSS_COLOR_YUV2:
1551 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1552 case OMAP_DSS_COLOR_RGBA16:
1553 case OMAP_DSS_COLOR_RGBX16:
1554 case OMAP_DSS_COLOR_ARGB16_1555:
1555 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1556 return 16;
1557 case OMAP_DSS_COLOR_RGB24P:
1558 return 24;
1559 case OMAP_DSS_COLOR_RGB24U:
1560 case OMAP_DSS_COLOR_ARGB32:
1561 case OMAP_DSS_COLOR_RGBA32:
1562 case OMAP_DSS_COLOR_RGBX32:
1563 return 32;
1564 default:
1565 BUG();
c6eee968 1566 return 0;
80c39712
TV		 1567 }
1568}
1569
1570static s32 pixinc(int pixels, u8 ps)
1571{
1572 if (pixels == 1)
1573 return 1;
1574 else if (pixels > 1)
1575 return 1 + (pixels - 1) * ps;
1576 else if (pixels < 0)
1577 return 1 - (-pixels + 1) * ps;
1578 else
1579 BUG();
c6eee968 1580 return 0;
80c39712
TV		 1581}
1582
1583static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1584 u16 screen_width,
1585 u16 width, u16 height,
1586 enum omap_color_mode color_mode, bool fieldmode,
1587 unsigned int field_offset,
1588 unsigned *offset0, unsigned *offset1,
aed74b55 1589 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1590{
1591 u8 ps;
1592
1593 /* FIXME CLUT formats */
1594 switch (color_mode) {
1595 case OMAP_DSS_COLOR_CLUT1:
1596 case OMAP_DSS_COLOR_CLUT2:
1597 case OMAP_DSS_COLOR_CLUT4:
1598 case OMAP_DSS_COLOR_CLUT8:
1599 BUG();
1600 return;
1601 case OMAP_DSS_COLOR_YUV2:
1602 case OMAP_DSS_COLOR_UYVY:
1603 ps = 4;
1604 break;
1605 default:
1606 ps = color_mode_to_bpp(color_mode) / 8;
1607 break;
1608 }
1609
1610 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1611 width, height);
1612
1613 /*
1614 * field 0 = even field = bottom field
1615 * field 1 = odd field = top field
1616 */
1617 switch (rotation + mirror * 4) {
1618 case OMAP_DSS_ROT_0:
1619 case OMAP_DSS_ROT_180:
1620 /*
1621 * If the pixel format is YUV or UYVY divide the width
1622 * of the image by 2 for 0 and 180 degree rotation.
1623 */
1624 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1625 color_mode == OMAP_DSS_COLOR_UYVY)
1626 width = width >> 1;
1627 case OMAP_DSS_ROT_90:
1628 case OMAP_DSS_ROT_270:
1629 *offset1 = 0;
1630 if (field_offset)
1631 *offset0 = field_offset * screen_width * ps;
1632 else
1633 *offset0 = 0;
1634
aed74b55
CM		 1635 *row_inc = pixinc(1 +
1636 (y_predecim * screen_width - x_predecim * width) +
1637 (fieldmode ? screen_width : 0), ps);
1638 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1639 break;
1640
1641 case OMAP_DSS_ROT_0 + 4:
1642 case OMAP_DSS_ROT_180 + 4:
1643 /* If the pixel format is YUV or UYVY divide the width
1644 * of the image by 2 for 0 degree and 180 degree
1645 */
1646 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1647 color_mode == OMAP_DSS_COLOR_UYVY)
1648 width = width >> 1;
1649 case OMAP_DSS_ROT_90 + 4:
1650 case OMAP_DSS_ROT_270 + 4:
1651 *offset1 = 0;
1652 if (field_offset)
1653 *offset0 = field_offset * screen_width * ps;
1654 else
1655 *offset0 = 0;
aed74b55
CM		 1656 *row_inc = pixinc(1 -
1657 (y_predecim * screen_width + x_predecim * width) -
1658 (fieldmode ? screen_width : 0), ps);
1659 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1660 break;
1661
1662 default:
1663 BUG();
c6eee968 1664 return;
80c39712
TV		 1665 }
1666}
1667
1668static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1669 u16 screen_width,
1670 u16 width, u16 height,
1671 enum omap_color_mode color_mode, bool fieldmode,
1672 unsigned int field_offset,
1673 unsigned *offset0, unsigned *offset1,
aed74b55 1674 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1675{
1676 u8 ps;
1677 u16 fbw, fbh;
1678
1679 /* FIXME CLUT formats */
1680 switch (color_mode) {
1681 case OMAP_DSS_COLOR_CLUT1:
1682 case OMAP_DSS_COLOR_CLUT2:
1683 case OMAP_DSS_COLOR_CLUT4:
1684 case OMAP_DSS_COLOR_CLUT8:
1685 BUG();
1686 return;
1687 default:
1688 ps = color_mode_to_bpp(color_mode) / 8;
1689 break;
1690 }
1691
1692 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1693 width, height);
1694
1695 /* width & height are overlay sizes, convert to fb sizes */
1696
1697 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1698 fbw = width;
1699 fbh = height;
1700 } else {
1701 fbw = height;
1702 fbh = width;
1703 }
1704
1705 /*
1706 * field 0 = even field = bottom field
1707 * field 1 = odd field = top field
1708 */
1709 switch (rotation + mirror * 4) {
1710 case OMAP_DSS_ROT_0:
1711 *offset1 = 0;
1712 if (field_offset)
1713 *offset0 = *offset1 + field_offset * screen_width * ps;
1714 else
1715 *offset0 = *offset1;
aed74b55
CM		 1716 *row_inc = pixinc(1 +
1717 (y_predecim * screen_width - fbw * x_predecim) +
1718 (fieldmode ? screen_width : 0), ps);
1719 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1720 color_mode == OMAP_DSS_COLOR_UYVY)
1721 *pix_inc = pixinc(x_predecim, 2 * ps);
1722 else
1723 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1724 break;
1725 case OMAP_DSS_ROT_90:
1726 *offset1 = screen_width * (fbh - 1) * ps;
1727 if (field_offset)
1728 *offset0 = *offset1 + field_offset * ps;
1729 else
1730 *offset0 = *offset1;
aed74b55
CM		 1731 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1732 y_predecim + (fieldmode ? 1 : 0), ps);
1733 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1734 break;
1735 case OMAP_DSS_ROT_180:
1736 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1737 if (field_offset)
1738 *offset0 = *offset1 - field_offset * screen_width * ps;
1739 else
1740 *offset0 = *offset1;
1741 *row_inc = pixinc(-1 -
aed74b55
CM		 1742 (y_predecim * screen_width - fbw * x_predecim) -
1743 (fieldmode ? screen_width : 0), ps);
1744 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1745 color_mode == OMAP_DSS_COLOR_UYVY)
1746 *pix_inc = pixinc(-x_predecim, 2 * ps);
1747 else
1748 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1749 break;
1750 case OMAP_DSS_ROT_270:
1751 *offset1 = (fbw - 1) * ps;
1752 if (field_offset)
1753 *offset0 = *offset1 - field_offset * ps;
1754 else
1755 *offset0 = *offset1;
aed74b55
CM		 1756 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1757 y_predecim - (fieldmode ? 1 : 0), ps);
1758 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1759 break;
1760
1761 /* mirroring */
1762 case OMAP_DSS_ROT_0 + 4:
1763 *offset1 = (fbw - 1) * ps;
1764 if (field_offset)
1765 *offset0 = *offset1 + field_offset * screen_width * ps;
1766 else
1767 *offset0 = *offset1;
aed74b55 1768 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1769 (fieldmode ? screen_width : 0),
1770 ps);
aed74b55
CM		 1771 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1772 color_mode == OMAP_DSS_COLOR_UYVY)
1773 *pix_inc = pixinc(-x_predecim, 2 * ps);
1774 else
1775 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1776 break;
1777
1778 case OMAP_DSS_ROT_90 + 4:
1779 *offset1 = 0;
1780 if (field_offset)
1781 *offset0 = *offset1 + field_offset * ps;
1782 else
1783 *offset0 = *offset1;
aed74b55
CM		 1784 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1785 y_predecim + (fieldmode ? 1 : 0),
80c39712 1786 ps);
aed74b55 1787 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1788 break;
1789
1790 case OMAP_DSS_ROT_180 + 4:
1791 *offset1 = screen_width * (fbh - 1) * ps;
1792 if (field_offset)
1793 *offset0 = *offset1 - field_offset * screen_width * ps;
1794 else
1795 *offset0 = *offset1;
aed74b55 1796 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1797 (fieldmode ? screen_width : 0),
1798 ps);
aed74b55
CM		 1799 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1800 color_mode == OMAP_DSS_COLOR_UYVY)
1801 *pix_inc = pixinc(x_predecim, 2 * ps);
1802 else
1803 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1804 break;
1805
1806 case OMAP_DSS_ROT_270 + 4:
1807 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1808 if (field_offset)
1809 *offset0 = *offset1 - field_offset * ps;
1810 else
1811 *offset0 = *offset1;
aed74b55
CM		 1812 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1813 y_predecim - (fieldmode ? 1 : 0),
80c39712 1814 ps);
aed74b55 1815 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1816 break;
1817
1818 default:
1819 BUG();
c6eee968 1820 return;
80c39712
TV		 1821 }
1822}
1823
65e006ff
CM		 1824static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1825 enum omap_color_mode color_mode, bool fieldmode,
1826 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1827 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1828{
1829 u8 ps;
1830
1831 switch (color_mode) {
1832 case OMAP_DSS_COLOR_CLUT1:
1833 case OMAP_DSS_COLOR_CLUT2:
1834 case OMAP_DSS_COLOR_CLUT4:
1835 case OMAP_DSS_COLOR_CLUT8:
1836 BUG();
1837 return;
1838 default:
1839 ps = color_mode_to_bpp(color_mode) / 8;
1840 break;
1841 }
1842
1843 DSSDBG("scrw %d, width %d\n", screen_width, width);
1844
1845 /*
1846 * field 0 = even field = bottom field
1847 * field 1 = odd field = top field
1848 */
1849 *offset1 = 0;
1850 if (field_offset)
1851 *offset0 = *offset1 + field_offset * screen_width * ps;
1852 else
1853 *offset0 = *offset1;
1854 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1855 (fieldmode ? screen_width : 0), ps);
1856 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1857 color_mode == OMAP_DSS_COLOR_UYVY)
1858 *pix_inc = pixinc(x_predecim, 2 * ps);
1859 else
1860 *pix_inc = pixinc(x_predecim, ps);
1861}
1862
7faa9233
CM		 1863/*
1864 * This function is used to avoid synclosts in OMAP3, because of some
1865 * undocumented horizontal position and timing related limitations.
1866 */
81ab95b7
AT		 1867static int check_horiz_timing_omap3(enum omap_channel channel,
1868 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1869 u16 width, u16 height, u16 out_width, u16 out_height)
1870{
1871 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1872 unsigned long nonactive, lclk, pclk;
1873 static const u8 limits[3] = { 8, 10, 20 };
1874 u64 val, blank;
1875 int i;
1876
81ab95b7 1877 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233 1878 pclk = dispc_mgr_pclk_rate(channel);
dd88b7a6 1879 if (dss_mgr_is_lcd(channel))
7faa9233
CM		 1880 lclk = dispc_mgr_lclk_rate(channel);
1881 else
1882 lclk = dispc_fclk_rate();
1883
1884 i = 0;
1885 if (out_height < height)
1886 i++;
1887 if (out_width < width)
1888 i++;
81ab95b7 1889 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1890 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1891 if (blank <= limits[i])
1892 return -EINVAL;
1893
1894 /*
1895 * Pixel data should be prepared before visible display point starts.
1896 * So, atleast DS-2 lines must have already been fetched by DISPC
1897 * during nonactive - pos_x period.
1898 */
1899 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1900 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1901 val, max(0, DS - 2) * width);
1902 if (val < max(0, DS - 2) * width)
1903 return -EINVAL;
1904
1905 /*
1906 * All lines need to be refilled during the nonactive period of which
1907 * only one line can be loaded during the active period. So, atleast
1908 * DS - 1 lines should be loaded during nonactive period.
1909 */
1910 val = div_u64((u64)nonactive * lclk, pclk);
1911 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1912 val, max(0, DS - 1) * width);
1913 if (val < max(0, DS - 1) * width)
1914 return -EINVAL;
1915
1916 return 0;
1917}
1918
8b53d991 1919static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1920 const struct omap_video_timings *mgr_timings, u16 width,
1921 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1922 enum omap_color_mode color_mode)
80c39712 1923{
8b53d991 1924 u32 core_clk = 0;
26d9dd0d 1925 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1926
7282f1b7
CM		 1927 if (height <= out_height && width <= out_width)
1928 return (unsigned long) pclk;
1929
80c39712 1930 if (height > out_height) {
81ab95b7 1931 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1932
1933 tmp = pclk * height * out_width;
1934 do_div(tmp, 2 * out_height * ppl);
8b53d991 1935 core_clk = tmp;
80c39712 1936
2d9c5597
VS		 1937 if (height > 2 * out_height) {
1938 if (ppl == out_width)
1939 return 0;
1940
80c39712
TV		 1941 tmp = pclk * (height - 2 * out_height) * out_width;
1942 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1943 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1944 }
1945 }
1946
1947 if (width > out_width) {
1948 tmp = pclk * width;
1949 do_div(tmp, out_width);
8b53d991 1950 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1951
1952 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1953 core_clk <<= 1;
80c39712
TV		 1954 }
1955
8b53d991 1956 return core_clk;
80c39712
TV		 1957}
1958
dcbe765b
CM		 1959static unsigned long calc_core_clk_24xx(enum omap_channel channel, u16 width,
1960 u16 height, u16 out_width, u16 out_height)
1961{
1962 unsigned long pclk = dispc_mgr_pclk_rate(channel);
1963
1964 if (height > out_height && width > out_width)
1965 return pclk * 4;
1966 else
1967 return pclk * 2;
1968}
1969
1970static unsigned long calc_core_clk_34xx(enum omap_channel channel, u16 width,
ff1b2cde 1971 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1972{
1973 unsigned int hf, vf;
79ee89cd 1974 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1975
1976 /*
1977 * FIXME how to determine the 'A' factor
1978 * for the no downscaling case ?
1979 */
1980
1981 if (width > 3 * out_width)
1982 hf = 4;
1983 else if (width > 2 * out_width)
1984 hf = 3;
1985 else if (width > out_width)
1986 hf = 2;
1987 else
1988 hf = 1;
80c39712
TV		 1989 if (height > out_height)
1990 vf = 2;
1991 else
1992 vf = 1;
1993
dcbe765b
CM		 1994 return pclk * vf * hf;
1995}
1996
1997static unsigned long calc_core_clk_44xx(enum omap_channel channel, u16 width,
1998 u16 height, u16 out_width, u16 out_height)
1999{
2000 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2001
2002 if (width > out_width)
2003 return DIV_ROUND_UP(pclk, out_width) * width;
2004 else
2005 return pclk;
2006}
2007
2008static int dispc_ovl_calc_scaling_24xx(enum omap_channel channel,
2009 const struct omap_video_timings *mgr_timings,
2010 u16 width, u16 height, u16 out_width, u16 out_height,
2011 enum omap_color_mode color_mode, bool *five_taps,
2012 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2013 u16 pos_x, unsigned long *core_clk)
2014{
2015 int error;
2016 u16 in_width, in_height;
2017 int min_factor = min(*decim_x, *decim_y);
2018 const int maxsinglelinewidth =
2019 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2020 *five_taps = false;
2021
2022 do {
2023 in_height = DIV_ROUND_UP(height, *decim_y);
2024 in_width = DIV_ROUND_UP(width, *decim_x);
2025 *core_clk = dispc.feat->calc_core_clk(channel, in_width,
2026 in_height, out_width, out_height);
2027 error = (in_width > maxsinglelinewidth || !*core_clk ||
2028 *core_clk > dispc_core_clk_rate());
2029 if (error) {
2030 if (*decim_x == *decim_y) {
2031 *decim_x = min_factor;
2032 ++*decim_y;
2033 } else {
2034 swap(*decim_x, *decim_y);
2035 if (*decim_x < *decim_y)
2036 ++*decim_x;
2037 }
2038 }
2039 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2040
2041 if (in_width > maxsinglelinewidth) {
2042 DSSERR("Cannot scale max input width exceeded");
2043 return -EINVAL;
2044 }
2045 return 0;
2046}
2047
2048static int dispc_ovl_calc_scaling_34xx(enum omap_channel channel,
2049 const struct omap_video_timings *mgr_timings,
2050 u16 width, u16 height, u16 out_width, u16 out_height,
2051 enum omap_color_mode color_mode, bool *five_taps,
2052 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2053 u16 pos_x, unsigned long *core_clk)
2054{
2055 int error;
2056 u16 in_width, in_height;
2057 int min_factor = min(*decim_x, *decim_y);
2058 const int maxsinglelinewidth =
2059 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2060
2061 do {
2062 in_height = DIV_ROUND_UP(height, *decim_y);
2063 in_width = DIV_ROUND_UP(width, *decim_x);
2064 *core_clk = calc_core_clk_five_taps(channel, mgr_timings,
2065 in_width, in_height, out_width, out_height, color_mode);
2066
2067 error = check_horiz_timing_omap3(channel, mgr_timings, pos_x,
2068 in_width, in_height, out_width, out_height);
2069
2070 if (in_width > maxsinglelinewidth)
2071 if (in_height > out_height &&
2072 in_height < out_height * 2)
2073 *five_taps = false;
2074 if (!*five_taps)
2075 *core_clk = dispc.feat->calc_core_clk(channel, in_width,
2076 in_height, out_width, out_height);
2077
2078 error = (error || in_width > maxsinglelinewidth * 2 ||
2079 (in_width > maxsinglelinewidth && *five_taps) ||
2080 !*core_clk || *core_clk > dispc_core_clk_rate());
2081 if (error) {
2082 if (*decim_x == *decim_y) {
2083 *decim_x = min_factor;
2084 ++*decim_y;
2085 } else {
2086 swap(*decim_x, *decim_y);
2087 if (*decim_x < *decim_y)
2088 ++*decim_x;
2089 }
2090 }
2091 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2092
2093 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width, height,
2094 out_width, out_height)){
2095 DSSERR("horizontal timing too tight\n");
2096 return -EINVAL;
7282f1b7 2097 }
dcbe765b
CM		 2098
2099 if (in_width > (maxsinglelinewidth * 2)) {
2100 DSSERR("Cannot setup scaling");
2101 DSSERR("width exceeds maximum width possible");
2102 return -EINVAL;
2103 }
2104
2105 if (in_width > maxsinglelinewidth && *five_taps) {
2106 DSSERR("cannot setup scaling with five taps");
2107 return -EINVAL;
2108 }
2109 return 0;
2110}
2111
2112static int dispc_ovl_calc_scaling_44xx(enum omap_channel channel,
2113 const struct omap_video_timings *mgr_timings,
2114 u16 width, u16 height, u16 out_width, u16 out_height,
2115 enum omap_color_mode color_mode, bool *five_taps,
2116 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2117 u16 pos_x, unsigned long *core_clk)
2118{
2119 u16 in_width, in_width_max;
2120 int decim_x_min = *decim_x;
2121 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2122 const int maxsinglelinewidth =
2123 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2124
2125 in_width_max = dispc_core_clk_rate() /
2126 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel), out_width);
2127 *decim_x = DIV_ROUND_UP(width, in_width_max);
2128
2129 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2130 if (*decim_x > *x_predecim)
2131 return -EINVAL;
2132
2133 do {
2134 in_width = DIV_ROUND_UP(width, *decim_x);
2135 } while (*decim_x <= *x_predecim &&
2136 in_width > maxsinglelinewidth && ++*decim_x);
2137
2138 if (in_width > maxsinglelinewidth) {
2139 DSSERR("Cannot scale width exceeds max line width");
2140 return -EINVAL;
2141 }
2142
2143 *core_clk = dispc.feat->calc_core_clk(channel, in_width, in_height,
2144 out_width, out_height);
2145 return 0;
80c39712
TV		 2146}
2147
79ad75f2 2148static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 2149 enum omap_channel channel,
2150 const struct omap_video_timings *mgr_timings,
2151 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2152 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 2153 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 2154{
2155 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 2156 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2157 const int max_decim_limit = 16;
8b53d991 2158 unsigned long core_clk = 0;
dcbe765b 2159 int decim_x, decim_y, ret;
79ad75f2 2160
f95cb5eb
TV		 2161 if (width == out_width && height == out_height)
2162 return 0;
2163
2164 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2165 return -EINVAL;
79ad75f2 2166
aed74b55
CM		 2167 *x_predecim = max_decim_limit;
2168 *y_predecim = max_decim_limit;
2169
2170 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2171 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2172 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2173 color_mode == OMAP_DSS_COLOR_CLUT8) {
2174 *x_predecim = 1;
2175 *y_predecim = 1;
2176 *five_taps = false;
2177 return 0;
2178 }
2179
2180 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2181 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2182
aed74b55 2183 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2184 return -EINVAL;
2185
aed74b55 2186 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2187 return -EINVAL;
2188
dcbe765b
CM		 2189 ret = dispc.feat->calc_scaling(channel, mgr_timings, width, height,
2190 out_width, out_height, color_mode, five_taps, x_predecim,
2191 y_predecim, &decim_x, &decim_y, pos_x, &core_clk);
2192 if (ret)
2193 return ret;
79ad75f2 2194
8b53d991
CM		 2195 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2196 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2197
8b53d991 2198 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2199 DSSERR("failed to set up scaling, "
8b53d991
CM		 2200 "required core clk rate = %lu Hz, "
2201 "current core clk rate = %lu Hz\n",
2202 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2203 return -EINVAL;
2204 }
2205
aed74b55
CM		 2206 *x_predecim = decim_x;
2207 *y_predecim = decim_y;
79ad75f2
AT		 2208 return 0;
2209}
2210
a4273b7c 2211int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
8050cbe4 2212 bool replication, const struct omap_video_timings *mgr_timings)
80c39712 2213{
79ad75f2 2214 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 2215 bool five_taps = true;
80c39712 2216 bool fieldmode = 0;
79ad75f2 2217 int r, cconv = 0;
80c39712
TV		 2218 unsigned offset0, offset1;
2219 s32 row_inc;
2220 s32 pix_inc;
a4273b7c 2221 u16 frame_height = oi->height;
80c39712 2222 unsigned int field_offset = 0;
aed74b55
CM		 2223 u16 in_height = oi->height;
2224 u16 in_width = oi->width;
2225 u16 out_width, out_height;
2cc5d1af 2226 enum omap_channel channel;
aed74b55 2227 int x_predecim = 1, y_predecim = 1;
8050cbe4 2228 bool ilace = mgr_timings->interlace;
2cc5d1af
TV		 2229
2230 channel = dispc_ovl_get_channel_out(plane);
80c39712 2231
a4273b7c 2232 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 2233 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2234 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 2235 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2236 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 2237 oi->mirror, ilace, channel, replication);
e6d80f95 2238
a4273b7c 2239 if (oi->paddr == 0)
80c39712
TV		 2240 return -EINVAL;
2241
aed74b55
CM		 2242 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2243 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 2244
aed74b55 2245 if (ilace && oi->height == out_height)
80c39712
TV		 2246 fieldmode = 1;
2247
2248 if (ilace) {
2249 if (fieldmode)
aed74b55 2250 in_height /= 2;
a4273b7c 2251 oi->pos_y /= 2;
aed74b55 2252 out_height /= 2;
80c39712
TV		 2253
2254 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2255 "out_height %d\n",
aed74b55 2256 in_height, oi->pos_y, out_height);
80c39712
TV		 2257 }
2258
a4273b7c 2259 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2260 return -EINVAL;
2261
81ab95b7
AT		 2262 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2263 in_height, out_width, out_height, oi->color_mode,
2264 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 2265 if (r)
2266 return r;
80c39712 2267
aed74b55
CM		 2268 in_width = DIV_ROUND_UP(in_width, x_predecim);
2269 in_height = DIV_ROUND_UP(in_height, y_predecim);
2270
79ad75f2
AT		 2271 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2272 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2273 oi->color_mode == OMAP_DSS_COLOR_NV12)
2274 cconv = 1;
80c39712
TV		 2275
2276 if (ilace && !fieldmode) {
2277 /*
2278 * when downscaling the bottom field may have to start several
2279 * source lines below the top field. Unfortunately ACCUI
2280 * registers will only hold the fractional part of the offset
2281 * so the integer part must be added to the base address of the
2282 * bottom field.
2283 */
aed74b55 2284 if (!in_height || in_height == out_height)
80c39712
TV		 2285 field_offset = 0;
2286 else
aed74b55 2287 field_offset = in_height / out_height / 2;
80c39712
TV		 2288 }
2289
2290 /* Fields are independent but interleaved in memory. */
2291 if (fieldmode)
2292 field_offset = 1;
2293
c6eee968
TV		 2294 offset0 = 0;
2295 offset1 = 0;
2296 row_inc = 0;
2297 pix_inc = 0;
2298
65e006ff
CM		 2299 if (oi->rotation_type == OMAP_DSS_ROT_TILER)
2300 calc_tiler_rotation_offset(oi->screen_width, in_width,
2301 oi->color_mode, fieldmode, field_offset,
2302 &offset0, &offset1, &row_inc, &pix_inc,
2303 x_predecim, y_predecim);
2304 else if (oi->rotation_type == OMAP_DSS_ROT_DMA)
a4273b7c 2305 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2306 oi->screen_width, in_width, frame_height,
a4273b7c 2307 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2308 &offset0, &offset1, &row_inc, &pix_inc,
2309 x_predecim, y_predecim);
80c39712 2310 else
a4273b7c 2311 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2312 oi->screen_width, in_width, frame_height,
a4273b7c 2313 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2314 &offset0, &offset1, &row_inc, &pix_inc,
2315 x_predecim, y_predecim);
80c39712
TV		 2316
2317 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2318 offset0, offset1, row_inc, pix_inc);
2319
a4273b7c 2320 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2321
65e006ff
CM		 2322 dispc_ovl_configure_burst_type(plane, oi->rotation_type);
2323
a4273b7c
AT		 2324 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2325 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2326
a4273b7c
AT		 2327 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2328 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2329 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2330 }
2331
2332
f0e5caab
TV		 2333 dispc_ovl_set_row_inc(plane, row_inc);
2334 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2335
aed74b55
CM		 2336 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2337 in_height, out_width, out_height);
80c39712 2338
a4273b7c 2339 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2340
aed74b55 2341 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2342
79ad75f2 2343 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2344 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2345 out_height, ilace, five_taps, fieldmode,
a4273b7c 2346 oi->color_mode, oi->rotation);
aed74b55 2347 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2348 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2349 }
2350
a4273b7c
AT		 2351 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2352 oi->color_mode);
80c39712 2353
54128701 2354 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2355 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2356 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2357
c3d92529 2358 dispc_ovl_enable_replication(plane, replication);
c3d92529 2359
80c39712
TV		 2360 return 0;
2361}
2362
f0e5caab 2363int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2364{
e6d80f95
TV		 2365 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2366
9b372c2d 2367 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2368
2369 return 0;
80c39712
TV		 2370}
2371
2372static void dispc_disable_isr(void *data, u32 mask)
2373{
2374 struct completion *compl = data;
2375 complete(compl);
2376}
2377
2a205f34 2378static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2379{
efa70b3b
CM		 2380 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2381 /* flush posted write */
2382 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2383}
2384
26d9dd0d 2385static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2386{
2387 struct completion frame_done_completion;
2388 bool is_on;
2389 int r;
2a205f34 2390 u32 irq;
80c39712 2391
80c39712
TV		 2392 /* When we disable LCD output, we need to wait until frame is done.
2393 * Otherwise the DSS is still working, and turning off the clocks
2394 * prevents DSS from going to OFF mode */
efa70b3b 2395 is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2a205f34 2396
efa70b3b 2397 irq = mgr_desc[channel].framedone_irq;
80c39712
TV		 2398
2399 if (!enable && is_on) {
2400 init_completion(&frame_done_completion);
2401
2402 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2403 &frame_done_completion, irq);
80c39712
TV		 2404
2405 if (r)
2406 DSSERR("failed to register FRAMEDONE isr\n");
2407 }
2408
2a205f34 2409 _enable_lcd_out(channel, enable);
80c39712
TV		 2410
2411 if (!enable && is_on) {
2412 if (!wait_for_completion_timeout(&frame_done_completion,
2413 msecs_to_jiffies(100)))
2414 DSSERR("timeout waiting for FRAME DONE\n");
2415
2416 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2417 &frame_done_completion, irq);
80c39712
TV		 2418
2419 if (r)
2420 DSSERR("failed to unregister FRAMEDONE isr\n");
2421 }
80c39712
TV		 2422}
2423
2424static void _enable_digit_out(bool enable)
2425{
2426 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2427 /* flush posted write */
2428 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2429}
2430
26d9dd0d 2431static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2432{
2433 struct completion frame_done_completion;
e82b090b
TV		 2434 enum dss_hdmi_venc_clk_source_select src;
2435 int r, i;
2436 u32 irq_mask;
2437 int num_irqs;
80c39712 2438
e6d80f95 2439 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2440 return;
80c39712 2441
e82b090b
TV		 2442 src = dss_get_hdmi_venc_clk_source();
2443
80c39712
TV		 2444 if (enable) {
2445 unsigned long flags;
2446 /* When we enable digit output, we'll get an extra digit
2447 * sync lost interrupt, that we need to ignore */
2448 spin_lock_irqsave(&dispc.irq_lock, flags);
2449 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2450 _omap_dispc_set_irqs();
2451 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2452 }
2453
2454 /* When we disable digit output, we need to wait until fields are done.
2455 * Otherwise the DSS is still working, and turning off the clocks
2456 * prevents DSS from going to OFF mode. And when enabling, we need to
2457 * wait for the extra sync losts */
2458 init_completion(&frame_done_completion);
2459
e82b090b
TV		 2460 if (src == DSS_HDMI_M_PCLK && enable == false) {
2461 irq_mask = DISPC_IRQ_FRAMEDONETV;
2462 num_irqs = 1;
2463 } else {
2464 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2465 /* XXX I understand from TRM that we should only wait for the
2466 * current field to complete. But it seems we have to wait for
2467 * both fields */
2468 num_irqs = 2;
2469 }
2470
80c39712 2471 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2472 irq_mask);
80c39712 2473 if (r)
e82b090b 2474 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2475
2476 _enable_digit_out(enable);
2477
e82b090b
TV		 2478 for (i = 0; i < num_irqs; ++i) {
2479 if (!wait_for_completion_timeout(&frame_done_completion,
2480 msecs_to_jiffies(100)))
2481 DSSERR("timeout waiting for digit out to %s\n",
2482 enable ? "start" : "stop");
2483 }
80c39712 2484
e82b090b
TV		 2485 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2486 irq_mask);
80c39712 2487 if (r)
e82b090b 2488 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2489
2490 if (enable) {
2491 unsigned long flags;
2492 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2493 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2494 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2495 _omap_dispc_set_irqs();
2496 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2497 }
80c39712
TV		 2498}
2499
26d9dd0d 2500bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84 2501{
efa70b3b 2502 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
a2faee84
TV		 2503}
2504
26d9dd0d 2505void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2506{
dd88b7a6 2507 if (dss_mgr_is_lcd(channel))
26d9dd0d 2508 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2509 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2510 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2511 else
2512 BUG();
2513}
2514
80c39712
TV		 2515void dispc_lcd_enable_signal_polarity(bool act_high)
2516{
6ced40bf
AT		 2517 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2518 return;
2519
80c39712 2520 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2521}
2522
2523void dispc_lcd_enable_signal(bool enable)
2524{
6ced40bf
AT		 2525 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2526 return;
2527
80c39712 2528 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2529}
2530
2531void dispc_pck_free_enable(bool enable)
2532{
6ced40bf
AT		 2533 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2534 return;
2535
80c39712 2536 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2537}
2538
26d9dd0d 2539void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2540{
efa70b3b 2541 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2542}
2543
2544
d21f43bc 2545void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2546{
d21f43bc 2547 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2548}
2549
2550void dispc_set_loadmode(enum omap_dss_load_mode mode)
2551{
80c39712 2552 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2553}
2554
2555
c64dca40 2556static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2557{
8613b000 2558 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2559}
2560
c64dca40 2561static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2562 enum omap_dss_trans_key_type type,
2563 u32 trans_key)
2564{
efa70b3b 2565 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2566
8613b000 2567 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2568}
2569
c64dca40 2570static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2571{
efa70b3b 2572 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2573}
11354dd5 2574
c64dca40
TV		 2575static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2576 bool enable)
80c39712 2577{
11354dd5 2578 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2579 return;
2580
80c39712
TV		 2581 if (ch == OMAP_DSS_CHANNEL_LCD)
2582 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2583 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2584 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2585}
11354dd5 2586
c64dca40
TV		 2587void dispc_mgr_setup(enum omap_channel channel,
2588 struct omap_overlay_manager_info *info)
2589{
2590 dispc_mgr_set_default_color(channel, info->default_color);
2591 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2592 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2593 dispc_mgr_enable_alpha_fixed_zorder(channel,
2594 info->partial_alpha_enabled);
2595 if (dss_has_feature(FEAT_CPR)) {
2596 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2597 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2598 }
2599}
80c39712 2600
26d9dd0d 2601void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2602{
2603 int code;
2604
2605 switch (data_lines) {
2606 case 12:
2607 code = 0;
2608 break;
2609 case 16:
2610 code = 1;
2611 break;
2612 case 18:
2613 code = 2;
2614 break;
2615 case 24:
2616 code = 3;
2617 break;
2618 default:
2619 BUG();
2620 return;
2621 }
2622
efa70b3b 2623 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2624}
2625
569969d6 2626void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2627{
2628 u32 l;
569969d6 2629 int gpout0, gpout1;
80c39712
TV		 2630
2631 switch (mode) {
569969d6
AT		 2632 case DSS_IO_PAD_MODE_RESET:
2633 gpout0 = 0;
2634 gpout1 = 0;
80c39712 2635 break;
569969d6
AT		 2636 case DSS_IO_PAD_MODE_RFBI:
2637 gpout0 = 1;
80c39712
TV		 2638 gpout1 = 0;
2639 break;
569969d6
AT		 2640 case DSS_IO_PAD_MODE_BYPASS:
2641 gpout0 = 1;
80c39712
TV		 2642 gpout1 = 1;
2643 break;
80c39712
TV		 2644 default:
2645 BUG();
2646 return;
2647 }
2648
569969d6
AT		 2649 l = dispc_read_reg(DISPC_CONTROL);
2650 l = FLD_MOD(l, gpout0, 15, 15);
2651 l = FLD_MOD(l, gpout1, 16, 16);
2652 dispc_write_reg(DISPC_CONTROL, l);
2653}
2654
2655void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2656{
efa70b3b 2657 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2658}
2659
8f366162
AT		 2660static bool _dispc_mgr_size_ok(u16 width, u16 height)
2661{
2662 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2663 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2664}
2665
80c39712
TV		 2666static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2667 int vsw, int vfp, int vbp)
2668{
dcbe765b
CM		 2669 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2670 hfp < 1 || hfp > dispc.feat->hp_max ||
2671 hbp < 1 || hbp > dispc.feat->hp_max ||
2672 vsw < 1 || vsw > dispc.feat->sw_max ||
2673 vfp < 0 || vfp > dispc.feat->vp_max ||
2674 vbp < 0 || vbp > dispc.feat->vp_max)
2675 return false;
80c39712
TV		 2676 return true;
2677}
2678
8f366162 2679bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2680 const struct omap_video_timings *timings)
80c39712 2681{
8f366162
AT		 2682 bool timings_ok;
2683
2684 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2685
dd88b7a6 2686 if (dss_mgr_is_lcd(channel))
8f366162
AT		 2687 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2688 timings->hfp, timings->hbp,
2689 timings->vsw, timings->vfp,
2690 timings->vbp);
2691
2692 return timings_ok;
80c39712
TV		 2693}
2694
26d9dd0d 2695static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 2696 int hfp, int hbp, int vsw, int vfp, int vbp,
2697 enum omap_dss_signal_level vsync_level,
2698 enum omap_dss_signal_level hsync_level,
2699 enum omap_dss_signal_edge data_pclk_edge,
2700 enum omap_dss_signal_level de_level,
2701 enum omap_dss_signal_edge sync_pclk_edge)
2702
80c39712 2703{
655e2941
AT		 2704 u32 timing_h, timing_v, l;
2705 bool onoff, rf, ipc;
80c39712 2706
dcbe765b
CM		 2707 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
2708 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
2709 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
2710 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
2711 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
2712 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 2713
64ba4f74
SS		 2714 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2715 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 2716
2717 switch (data_pclk_edge) {
2718 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2719 ipc = false;
2720 break;
2721 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2722 ipc = true;
2723 break;
2724 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2725 default:
2726 BUG();
2727 }
2728
2729 switch (sync_pclk_edge) {
2730 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
2731 onoff = false;
2732 rf = false;
2733 break;
2734 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
2735 onoff = true;
2736 rf = false;
2737 break;
2738 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
2739 onoff = true;
2740 rf = true;
2741 break;
2742 default:
2743 BUG();
2744 };
2745
2746 l = dispc_read_reg(DISPC_POL_FREQ(channel));
2747 l |= FLD_VAL(onoff, 17, 17);
2748 l |= FLD_VAL(rf, 16, 16);
2749 l |= FLD_VAL(de_level, 15, 15);
2750 l |= FLD_VAL(ipc, 14, 14);
2751 l |= FLD_VAL(hsync_level, 13, 13);
2752 l |= FLD_VAL(vsync_level, 12, 12);
2753 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2754}
2755
2756/* change name to mode? */
c51d921a 2757void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2758 struct omap_video_timings *timings)
80c39712
TV		 2759{
2760 unsigned xtot, ytot;
2761 unsigned long ht, vt;
2aefad49 2762 struct omap_video_timings t = *timings;
80c39712 2763
2aefad49 2764 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 2765
2aefad49 2766 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 2767 BUG();
c6eee968
TV		 2768 return;
2769 }
80c39712 2770
dd88b7a6 2771 if (dss_mgr_is_lcd(channel)) {
2aefad49 2772 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 2773 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
2774 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 2775
2aefad49
AT		 2776 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2777 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 2778
c51d921a
AT		 2779 ht = (timings->pixel_clock * 1000) / xtot;
2780 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2781
2782 DSSDBG("pck %u\n", timings->pixel_clock);
2783 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 2784 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 2785 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
2786 t.vsync_level, t.hsync_level, t.data_pclk_edge,
2787 t.de_level, t.sync_pclk_edge);
80c39712 2788
c51d921a 2789 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 2790 } else {
23c8f88e 2791 if (t.interlace == true)
2aefad49 2792 t.y_res /= 2;
c51d921a 2793 }
8f366162 2794
2aefad49 2795 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 2796}
2797
26d9dd0d 2798static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2799 u16 pck_div)
80c39712
TV		 2800{
2801 BUG_ON(lck_div < 1);
9eaaf207 2802 BUG_ON(pck_div < 1);
80c39712 2803
ce7fa5eb 2804 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2805 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2806}
2807
26d9dd0d 2808static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2809 int *pck_div)
80c39712
TV		 2810{
2811 u32 l;
ce7fa5eb 2812 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2813 *lck_div = FLD_GET(l, 23, 16);
2814 *pck_div = FLD_GET(l, 7, 0);
2815}
2816
2817unsigned long dispc_fclk_rate(void)
2818{
a72b64b9 2819 struct platform_device *dsidev;
80c39712
TV		 2820 unsigned long r = 0;
2821
66534e8e 2822 switch (dss_get_dispc_clk_source()) {
89a35e51 2823 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2824 r = clk_get_rate(dispc.dss_clk);
66534e8e 2825 break;
89a35e51 2826 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2827 dsidev = dsi_get_dsidev_from_id(0);
2828 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2829 break;
5a8b572d
AT		 2830 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2831 dsidev = dsi_get_dsidev_from_id(1);
2832 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2833 break;
66534e8e
TA		 2834 default:
2835 BUG();
c6eee968 2836 return 0;
66534e8e
TA		 2837 }
2838
80c39712
TV		 2839 return r;
2840}
2841
26d9dd0d 2842unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2843{
a72b64b9 2844 struct platform_device *dsidev;
80c39712
TV		 2845 int lcd;
2846 unsigned long r;
2847 u32 l;
2848
ce7fa5eb 2849 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2850
2851 lcd = FLD_GET(l, 23, 16);
2852
ea75159e 2853 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2854 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2855 r = clk_get_rate(dispc.dss_clk);
ea75159e 2856 break;
89a35e51 2857 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2858 dsidev = dsi_get_dsidev_from_id(0);
2859 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2860 break;
5a8b572d
AT		 2861 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2862 dsidev = dsi_get_dsidev_from_id(1);
2863 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2864 break;
ea75159e
TA		 2865 default:
2866 BUG();
c6eee968 2867 return 0;
ea75159e 2868 }
80c39712
TV		 2869
2870 return r / lcd;
2871}
2872
26d9dd0d 2873unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2874{
80c39712 2875 unsigned long r;
80c39712 2876
dd88b7a6 2877 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 2878 int pcd;
2879 u32 l;
80c39712 2880
c3dc6a7a 2881 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2882
c3dc6a7a 2883 pcd = FLD_GET(l, 7, 0);
80c39712 2884
c3dc6a7a
AT		 2885 r = dispc_mgr_lclk_rate(channel);
2886
2887 return r / pcd;
2888 } else {
3fa03ba8 2889 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2890
3fa03ba8
AT		 2891 source = dss_get_hdmi_venc_clk_source();
2892
2893 switch (source) {
2894 case DSS_VENC_TV_CLK:
c3dc6a7a 2895 return venc_get_pixel_clock();
3fa03ba8 2896 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2897 return hdmi_get_pixel_clock();
2898 default:
2899 BUG();
c6eee968 2900 return 0;
c3dc6a7a
AT		 2901 }
2902 }
80c39712
TV		 2903}
2904
8b53d991
CM		 2905unsigned long dispc_core_clk_rate(void)
2906{
2907 int lcd;
2908 unsigned long fclk = dispc_fclk_rate();
2909
2910 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2911 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2912 else
2913 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2914
2915 return fclk / lcd;
2916}
2917
6f1891fc 2918static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 2919{
2920 int lcd, pcd;
6f1891fc
CM		 2921 enum omap_dss_clk_source lcd_clk_src;
2922
2923 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
2924
2925 lcd_clk_src = dss_get_lcd_clk_source(channel);
2926
2927 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
2928 dss_get_generic_clk_source_name(lcd_clk_src),
2929 dss_feat_get_clk_source_name(lcd_clk_src));
2930
2931 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
2932
2933 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2934 dispc_mgr_lclk_rate(channel), lcd);
2935 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2936 dispc_mgr_pclk_rate(channel), pcd);
2937}
2938
2939void dispc_dump_clocks(struct seq_file *s)
2940{
2941 int lcd;
0cf35df3 2942 u32 l;
89a35e51 2943 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 2944
4fbafaf3
TV		 2945 if (dispc_runtime_get())
2946 return;
80c39712 2947
80c39712
TV		 2948 seq_printf(s, "- DISPC -\n");
2949
067a57e4
AT		 2950 seq_printf(s, "dispc fclk source = %s (%s)\n",
2951 dss_get_generic_clk_source_name(dispc_clk_src),
2952 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2953
2954 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2955
0cf35df3
MR		 2956 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2957 seq_printf(s, "- DISPC-CORE-CLK -\n");
2958 l = dispc_read_reg(DISPC_DIVISOR);
2959 lcd = FLD_GET(l, 23, 16);
2960
2961 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2962 (dispc_fclk_rate()/lcd), lcd);
2963 }
2a205f34 2964
6f1891fc 2965 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 2966
6f1891fc
CM		 2967 if (dss_has_feature(FEAT_MGR_LCD2))
2968 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
2969 if (dss_has_feature(FEAT_MGR_LCD3))
2970 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 2971
2972 dispc_runtime_put();
80c39712
TV		 2973}
2974
dfc0fd8d
TV		 2975#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2976void dispc_dump_irqs(struct seq_file *s)
2977{
2978 unsigned long flags;
2979 struct dispc_irq_stats stats;
2980
2981 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2982
2983 stats = dispc.irq_stats;
2984 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2985 dispc.irq_stats.last_reset = jiffies;
2986
2987 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2988
2989 seq_printf(s, "period %u ms\n",
2990 jiffies_to_msecs(jiffies - stats.last_reset));
2991
2992 seq_printf(s, "irqs %d\n", stats.irq_count);
2993#define PIS(x) \
2994 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2995
2996 PIS(FRAMEDONE);
2997 PIS(VSYNC);
2998 PIS(EVSYNC_EVEN);
2999 PIS(EVSYNC_ODD);
3000 PIS(ACBIAS_COUNT_STAT);
3001 PIS(PROG_LINE_NUM);
3002 PIS(GFX_FIFO_UNDERFLOW);
3003 PIS(GFX_END_WIN);
3004 PIS(PAL_GAMMA_MASK);
3005 PIS(OCP_ERR);
3006 PIS(VID1_FIFO_UNDERFLOW);
3007 PIS(VID1_END_WIN);
3008 PIS(VID2_FIFO_UNDERFLOW);
3009 PIS(VID2_END_WIN);
b8c095b4
AT		 3010 if (dss_feat_get_num_ovls() > 3) {
3011 PIS(VID3_FIFO_UNDERFLOW);
3012 PIS(VID3_END_WIN);
3013 }
dfc0fd8d
TV		 3014 PIS(SYNC_LOST);
3015 PIS(SYNC_LOST_DIGIT);
3016 PIS(WAKEUP);
2a205f34
SS		 3017 if (dss_has_feature(FEAT_MGR_LCD2)) {
3018 PIS(FRAMEDONE2);
3019 PIS(VSYNC2);
3020 PIS(ACBIAS_COUNT_STAT2);
3021 PIS(SYNC_LOST2);
3022 }
6f1891fc
CM		 3023 if (dss_has_feature(FEAT_MGR_LCD3)) {
3024 PIS(FRAMEDONE3);
3025 PIS(VSYNC3);
3026 PIS(ACBIAS_COUNT_STAT3);
3027 PIS(SYNC_LOST3);
3028 }
dfc0fd8d
TV		 3029#undef PIS
3030}
dfc0fd8d
TV		 3031#endif
3032
e40402cf 3033static void dispc_dump_regs(struct seq_file *s)
80c39712 3034{
4dd2da15
AT		 3035 int i, j;
3036 const char *mgr_names[] = {
3037 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3038 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3039 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3040 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3041 };
3042 const char *ovl_names[] = {
3043 [OMAP_DSS_GFX] = "GFX",
3044 [OMAP_DSS_VIDEO1] = "VID1",
3045 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3046 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3047 };
3048 const char **p_names;
3049
9b372c2d 3050#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3051
4fbafaf3
TV		 3052 if (dispc_runtime_get())
3053 return;
80c39712 3054
5010be80 3055 /* DISPC common registers */
80c39712
TV		 3056 DUMPREG(DISPC_REVISION);
3057 DUMPREG(DISPC_SYSCONFIG);
3058 DUMPREG(DISPC_SYSSTATUS);
3059 DUMPREG(DISPC_IRQSTATUS);
3060 DUMPREG(DISPC_IRQENABLE);
3061 DUMPREG(DISPC_CONTROL);
3062 DUMPREG(DISPC_CONFIG);
3063 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3064 DUMPREG(DISPC_LINE_STATUS);
3065 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3066 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3067 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3068 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3069 if (dss_has_feature(FEAT_MGR_LCD2)) {
3070 DUMPREG(DISPC_CONTROL2);
3071 DUMPREG(DISPC_CONFIG2);
5010be80 3072 }
6f1891fc
CM		 3073 if (dss_has_feature(FEAT_MGR_LCD3)) {
3074 DUMPREG(DISPC_CONTROL3);
3075 DUMPREG(DISPC_CONFIG3);
3076 }
5010be80
AT		 3077
3078#undef DUMPREG
3079
3080#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 3081#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3082 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 3083 dispc_read_reg(DISPC_REG(i, r)))
3084
4dd2da15 3085 p_names = mgr_names;
5010be80 3086
4dd2da15
AT		 3087 /* DISPC channel specific registers */
3088 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3089 DUMPREG(i, DISPC_DEFAULT_COLOR);
3090 DUMPREG(i, DISPC_TRANS_COLOR);
3091 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3092
4dd2da15
AT		 3093 if (i == OMAP_DSS_CHANNEL_DIGIT)
3094 continue;
5010be80 3095
4dd2da15
AT		 3096 DUMPREG(i, DISPC_DEFAULT_COLOR);
3097 DUMPREG(i, DISPC_TRANS_COLOR);
3098 DUMPREG(i, DISPC_TIMING_H);
3099 DUMPREG(i, DISPC_TIMING_V);
3100 DUMPREG(i, DISPC_POL_FREQ);
3101 DUMPREG(i, DISPC_DIVISORo);
3102 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3103
4dd2da15
AT		 3104 DUMPREG(i, DISPC_DATA_CYCLE1);
3105 DUMPREG(i, DISPC_DATA_CYCLE2);
3106 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3107
332e9d70 3108 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3109 DUMPREG(i, DISPC_CPR_COEF_R);
3110 DUMPREG(i, DISPC_CPR_COEF_G);
3111 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3112 }
2a205f34 3113 }
80c39712 3114
4dd2da15
AT		 3115 p_names = ovl_names;
3116
3117 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3118 DUMPREG(i, DISPC_OVL_BA0);
3119 DUMPREG(i, DISPC_OVL_BA1);
3120 DUMPREG(i, DISPC_OVL_POSITION);
3121 DUMPREG(i, DISPC_OVL_SIZE);
3122 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3123 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3124 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3125 DUMPREG(i, DISPC_OVL_ROW_INC);
3126 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3127 if (dss_has_feature(FEAT_PRELOAD))
3128 DUMPREG(i, DISPC_OVL_PRELOAD);
3129
3130 if (i == OMAP_DSS_GFX) {
3131 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3132 DUMPREG(i, DISPC_OVL_TABLE_BA);
3133 continue;
3134 }
3135
3136 DUMPREG(i, DISPC_OVL_FIR);
3137 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3138 DUMPREG(i, DISPC_OVL_ACCU0);
3139 DUMPREG(i, DISPC_OVL_ACCU1);
3140 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3141 DUMPREG(i, DISPC_OVL_BA0_UV);
3142 DUMPREG(i, DISPC_OVL_BA1_UV);
3143 DUMPREG(i, DISPC_OVL_FIR2);
3144 DUMPREG(i, DISPC_OVL_ACCU2_0);
3145 DUMPREG(i, DISPC_OVL_ACCU2_1);
3146 }
3147 if (dss_has_feature(FEAT_ATTR2))
3148 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3149 if (dss_has_feature(FEAT_PRELOAD))
3150 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3151 }
5010be80
AT		 3152
3153#undef DISPC_REG
3154#undef DUMPREG
3155
3156#define DISPC_REG(plane, name, i) name(plane, i)
3157#define DUMPREG(plane, name, i) \
4dd2da15
AT		 3158 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3159 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 3160 dispc_read_reg(DISPC_REG(plane, name, i)))
3161
4dd2da15 3162 /* Video pipeline coefficient registers */
332e9d70 3163
4dd2da15
AT		 3164 /* start from OMAP_DSS_VIDEO1 */
3165 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3166 for (j = 0; j < 8; j++)
3167 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3168
4dd2da15
AT		 3169 for (j = 0; j < 8; j++)
3170 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3171
4dd2da15
AT		 3172 for (j = 0; j < 5; j++)
3173 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3174
4dd2da15
AT		 3175 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3176 for (j = 0; j < 8; j++)
3177 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3178 }
3179
3180 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3181 for (j = 0; j < 8; j++)
3182 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3183
3184 for (j = 0; j < 8; j++)
3185 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3186
3187 for (j = 0; j < 8; j++)
3188 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3189 }
332e9d70 3190 }
80c39712 3191
4fbafaf3 3192 dispc_runtime_put();
5010be80
AT		 3193
3194#undef DISPC_REG
80c39712
TV		 3195#undef DUMPREG
3196}
3197
80c39712 3198/* with fck as input clock rate, find dispc dividers that produce req_pck */
6d523e7b 3199void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
80c39712
TV		 3200 struct dispc_clock_info *cinfo)
3201{
9eaaf207 3202 u16 pcd_min, pcd_max;
80c39712
TV		 3203 unsigned long best_pck;
3204 u16 best_ld, cur_ld;
3205 u16 best_pd, cur_pd;
3206
9eaaf207
TV		 3207 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3208 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3209
80c39712
TV		 3210 best_pck = 0;
3211 best_ld = 0;
3212 best_pd = 0;
3213
3214 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3215 unsigned long lck = fck / cur_ld;
3216
9eaaf207 3217 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3218 unsigned long pck = lck / cur_pd;
3219 long old_delta = abs(best_pck - req_pck);
3220 long new_delta = abs(pck - req_pck);
3221
3222 if (best_pck == 0 || new_delta < old_delta) {
3223 best_pck = pck;
3224 best_ld = cur_ld;
3225 best_pd = cur_pd;
3226
3227 if (pck == req_pck)
3228 goto found;
3229 }
3230
3231 if (pck < req_pck)
3232 break;
3233 }
3234
3235 if (lck / pcd_min < req_pck)
3236 break;
3237 }
3238
3239found:
3240 cinfo->lck_div = best_ld;
3241 cinfo->pck_div = best_pd;
3242 cinfo->lck = fck / cinfo->lck_div;
3243 cinfo->pck = cinfo->lck / cinfo->pck_div;
3244}
3245
3246/* calculate clock rates using dividers in cinfo */
3247int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3248 struct dispc_clock_info *cinfo)
3249{
3250 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3251 return -EINVAL;
9eaaf207 3252 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3253 return -EINVAL;
3254
3255 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3256 cinfo->pck = cinfo->lck / cinfo->pck_div;
3257
3258 return 0;
3259}
3260
f0d08f89 3261void dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3262 struct dispc_clock_info *cinfo)
80c39712
TV		 3263{
3264 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3265 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3266
26d9dd0d 3267 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3268}
3269
26d9dd0d 3270int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3271 struct dispc_clock_info *cinfo)
80c39712
TV		 3272{
3273 unsigned long fck;
3274
3275 fck = dispc_fclk_rate();
3276
ce7fa5eb
MR		 3277 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3278 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3279
3280 cinfo->lck = fck / cinfo->lck_div;
3281 cinfo->pck = cinfo->lck / cinfo->pck_div;
3282
3283 return 0;
3284}
3285
3286/* dispc.irq_lock has to be locked by the caller */
3287static void _omap_dispc_set_irqs(void)
3288{
3289 u32 mask;
3290 u32 old_mask;
3291 int i;
3292 struct omap_dispc_isr_data *isr_data;
3293
3294 mask = dispc.irq_error_mask;
3295
3296 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3297 isr_data = &dispc.registered_isr[i];
3298
3299 if (isr_data->isr == NULL)
3300 continue;
3301
3302 mask |= isr_data->mask;
3303 }
3304
80c39712
TV		 3305 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3306 /* clear the irqstatus for newly enabled irqs */
3307 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3308
3309 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3310}
3311
3312int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3313{
3314 int i;
3315 int ret;
3316 unsigned long flags;
3317 struct omap_dispc_isr_data *isr_data;
3318
3319 if (isr == NULL)
3320 return -EINVAL;
3321
3322 spin_lock_irqsave(&dispc.irq_lock, flags);
3323
3324 /* check for duplicate entry */
3325 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3326 isr_data = &dispc.registered_isr[i];
3327 if (isr_data->isr == isr && isr_data->arg == arg &&
3328 isr_data->mask == mask) {
3329 ret = -EINVAL;
3330 goto err;
3331 }
3332 }
3333
3334 isr_data = NULL;
3335 ret = -EBUSY;
3336
3337 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3338 isr_data = &dispc.registered_isr[i];
3339
3340 if (isr_data->isr != NULL)
3341 continue;
3342
3343 isr_data->isr = isr;
3344 isr_data->arg = arg;
3345 isr_data->mask = mask;
3346 ret = 0;
3347
3348 break;
3349 }
3350
b9cb0984
TV		 3351 if (ret)
3352 goto err;
3353
80c39712
TV		 3354 _omap_dispc_set_irqs();
3355
3356 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3357
3358 return 0;
3359err:
3360 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3361
3362 return ret;
3363}
3364EXPORT_SYMBOL(omap_dispc_register_isr);
3365
3366int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3367{
3368 int i;
3369 unsigned long flags;
3370 int ret = -EINVAL;
3371 struct omap_dispc_isr_data *isr_data;
3372
3373 spin_lock_irqsave(&dispc.irq_lock, flags);
3374
3375 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3376 isr_data = &dispc.registered_isr[i];
3377 if (isr_data->isr != isr || isr_data->arg != arg ||
3378 isr_data->mask != mask)
3379 continue;
3380
3381 /* found the correct isr */
3382
3383 isr_data->isr = NULL;
3384 isr_data->arg = NULL;
3385 isr_data->mask = 0;
3386
3387 ret = 0;
3388 break;
3389 }
3390
3391 if (ret == 0)
3392 _omap_dispc_set_irqs();
3393
3394 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3395
3396 return ret;
3397}
3398EXPORT_SYMBOL(omap_dispc_unregister_isr);
3399
3400#ifdef DEBUG
3401static void print_irq_status(u32 status)
3402{
3403 if ((status & dispc.irq_error_mask) == 0)
3404 return;
3405
3406 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3407
3408#define PIS(x) \
3409 if (status & DISPC_IRQ_##x) \
3410 printk(#x " ");
3411 PIS(GFX_FIFO_UNDERFLOW);
3412 PIS(OCP_ERR);
3413 PIS(VID1_FIFO_UNDERFLOW);
3414 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3415 if (dss_feat_get_num_ovls() > 3)
3416 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3417 PIS(SYNC_LOST);
3418 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3419 if (dss_has_feature(FEAT_MGR_LCD2))
3420 PIS(SYNC_LOST2);
6f1891fc
CM		 3421 if (dss_has_feature(FEAT_MGR_LCD3))
3422 PIS(SYNC_LOST3);
80c39712
TV		 3423#undef PIS
3424
3425 printk("\n");
3426}
3427#endif
3428
3429/* Called from dss.c. Note that we don't touch clocks here,
3430 * but we presume they are on because we got an IRQ. However,
3431 * an irq handler may turn the clocks off, so we may not have
3432 * clock later in the function. */
affe360d 3433static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3434{
3435 int i;
affe360d 3436 u32 irqstatus, irqenable;
80c39712
TV		 3437 u32 handledirqs = 0;
3438 u32 unhandled_errors;
3439 struct omap_dispc_isr_data *isr_data;
3440 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3441
3442 spin_lock(&dispc.irq_lock);
3443
3444 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3445 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3446
3447 /* IRQ is not for us */
3448 if (!(irqstatus & irqenable)) {
3449 spin_unlock(&dispc.irq_lock);
3450 return IRQ_NONE;
3451 }
80c39712 3452
dfc0fd8d
TV		 3453#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3454 spin_lock(&dispc.irq_stats_lock);
3455 dispc.irq_stats.irq_count++;
3456 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3457 spin_unlock(&dispc.irq_stats_lock);
3458#endif
3459
80c39712
TV		 3460#ifdef DEBUG
3461 if (dss_debug)
3462 print_irq_status(irqstatus);
3463#endif
3464 /* Ack the interrupt. Do it here before clocks are possibly turned
3465 * off */
3466 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3467 /* flush posted write */
3468 dispc_read_reg(DISPC_IRQSTATUS);
3469
3470 /* make a copy and unlock, so that isrs can unregister
3471 * themselves */
3472 memcpy(registered_isr, dispc.registered_isr,
3473 sizeof(registered_isr));
3474
3475 spin_unlock(&dispc.irq_lock);
3476
3477 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3478 isr_data = &registered_isr[i];
3479
3480 if (!isr_data->isr)
3481 continue;
3482
3483 if (isr_data->mask & irqstatus) {
3484 isr_data->isr(isr_data->arg, irqstatus);
3485 handledirqs |= isr_data->mask;
3486 }
3487 }
3488
3489 spin_lock(&dispc.irq_lock);
3490
3491 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3492
3493 if (unhandled_errors) {
3494 dispc.error_irqs |= unhandled_errors;
3495
3496 dispc.irq_error_mask &= ~unhandled_errors;
3497 _omap_dispc_set_irqs();
3498
3499 schedule_work(&dispc.error_work);
3500 }
3501
3502 spin_unlock(&dispc.irq_lock);
affe360d 3503
3504 return IRQ_HANDLED;
80c39712
TV		 3505}
3506
3507static void dispc_error_worker(struct work_struct *work)
3508{
3509 int i;
3510 u32 errors;
3511 unsigned long flags;
fe3cc9d6
TV		 3512 static const unsigned fifo_underflow_bits[] = {
3513 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3514 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3515 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3516 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3517 };
3518
80c39712
TV		 3519 spin_lock_irqsave(&dispc.irq_lock, flags);
3520 errors = dispc.error_irqs;
3521 dispc.error_irqs = 0;
3522 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3523
13eae1f9
DZ		 3524 dispc_runtime_get();
3525
fe3cc9d6
TV		 3526 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3527 struct omap_overlay *ovl;
3528 unsigned bit;
80c39712 3529
fe3cc9d6
TV		 3530 ovl = omap_dss_get_overlay(i);
3531 bit = fifo_underflow_bits[i];
80c39712 3532
fe3cc9d6
TV		 3533 if (bit & errors) {
3534 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3535 ovl->name);
f0e5caab 3536 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3537 dispc_mgr_go(ovl->manager->id);
d7ad718d 3538 msleep(50);
80c39712
TV		 3539 }
3540 }
3541
fe3cc9d6
TV		 3542 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3543 struct omap_overlay_manager *mgr;
3544 unsigned bit;
80c39712 3545
fe3cc9d6 3546 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3547 bit = mgr_desc[i].sync_lost_irq;
80c39712 3548
fe3cc9d6
TV		 3549 if (bit & errors) {
3550 struct omap_dss_device *dssdev = mgr->device;
3551 bool enable;
80c39712 3552
fe3cc9d6
TV		 3553 DSSERR("SYNC_LOST on channel %s, restarting the output "
3554 "with video overlays disabled\n",
3555 mgr->name);
2a205f34 3556
fe3cc9d6
TV		 3557 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3558 dssdev->driver->disable(dssdev);
2a205f34 3559
2a205f34
SS		 3560 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3561 struct omap_overlay *ovl;
3562 ovl = omap_dss_get_overlay(i);
3563
fe3cc9d6
TV		 3564 if (ovl->id != OMAP_DSS_GFX &&
3565 ovl->manager == mgr)
f0e5caab 3566 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3567 }
3568
26d9dd0d 3569 dispc_mgr_go(mgr->id);
d7ad718d 3570 msleep(50);
fe3cc9d6 3571
2a205f34
SS		 3572 if (enable)
3573 dssdev->driver->enable(dssdev);
3574 }
3575 }
3576
80c39712
TV		 3577 if (errors & DISPC_IRQ_OCP_ERR) {
3578 DSSERR("OCP_ERR\n");
3579 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3580 struct omap_overlay_manager *mgr;
3581 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3582 if (mgr->device && mgr->device->driver)
3583 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3584 }
3585 }
3586
3587 spin_lock_irqsave(&dispc.irq_lock, flags);
3588 dispc.irq_error_mask |= errors;
3589 _omap_dispc_set_irqs();
3590 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3591
3592 dispc_runtime_put();
80c39712
TV		 3593}
3594
3595int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3596{
3597 void dispc_irq_wait_handler(void *data, u32 mask)
3598 {
3599 complete((struct completion *)data);
3600 }
3601
3602 int r;
3603 DECLARE_COMPLETION_ONSTACK(completion);
3604
3605 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3606 irqmask);
3607
3608 if (r)
3609 return r;
3610
3611 timeout = wait_for_completion_timeout(&completion, timeout);
3612
3613 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3614
3615 if (timeout == 0)
3616 return -ETIMEDOUT;
3617
3618 if (timeout == -ERESTARTSYS)
3619 return -ERESTARTSYS;
3620
3621 return 0;
3622}
3623
3624int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3625 unsigned long timeout)
3626{
3627 void dispc_irq_wait_handler(void *data, u32 mask)
3628 {
3629 complete((struct completion *)data);
3630 }
3631
3632 int r;
3633 DECLARE_COMPLETION_ONSTACK(completion);
3634
3635 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3636 irqmask);
3637
3638 if (r)
3639 return r;
3640
3641 timeout = wait_for_completion_interruptible_timeout(&completion,
3642 timeout);
3643
3644 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3645
3646 if (timeout == 0)
3647 return -ETIMEDOUT;
3648
3649 if (timeout == -ERESTARTSYS)
3650 return -ERESTARTSYS;
3651
3652 return 0;
3653}
3654
80c39712
TV		 3655static void _omap_dispc_initialize_irq(void)
3656{
3657 unsigned long flags;
3658
3659 spin_lock_irqsave(&dispc.irq_lock, flags);
3660
3661 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3662
3663 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3664 if (dss_has_feature(FEAT_MGR_LCD2))
3665 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
e86d456a
CM		 3666 if (dss_has_feature(FEAT_MGR_LCD3))
3667 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
b8c095b4
AT		 3668 if (dss_feat_get_num_ovls() > 3)
3669 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3670
3671 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3672 * so clear it */
3673 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3674
3675 _omap_dispc_set_irqs();
3676
3677 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3678}
3679
3680void dispc_enable_sidle(void)
3681{
3682 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3683}
3684
3685void dispc_disable_sidle(void)
3686{
3687 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3688}
3689
3690static void _omap_dispc_initial_config(void)
3691{
3692 u32 l;
3693
0cf35df3
MR		 3694 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3695 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3696 l = dispc_read_reg(DISPC_DIVISOR);
3697 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3698 l = FLD_MOD(l, 1, 0, 0);
3699 l = FLD_MOD(l, 1, 23, 16);
3700 dispc_write_reg(DISPC_DIVISOR, l);
3701 }
3702
80c39712 3703 /* FUNCGATED */
6ced40bf
AT		 3704 if (dss_has_feature(FEAT_FUNCGATED))
3705 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3706
80c39712
TV		 3707 _dispc_setup_color_conv_coef();
3708
3709 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3710
3711 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3712
3713 dispc_configure_burst_sizes();
54128701
AT		 3714
3715 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3716}
3717
dcbe765b
CM		 3718static const struct dispc_features omap24xx_dispc_feats __initconst = {
3719 .sw_start = 5,
3720 .fp_start = 15,
3721 .bp_start = 27,
3722 .sw_max = 64,
3723 .vp_max = 255,
3724 .hp_max = 256,
3725 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3726 .calc_core_clk = calc_core_clk_24xx,
3727};
3728
3729static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
3730 .sw_start = 5,
3731 .fp_start = 15,
3732 .bp_start = 27,
3733 .sw_max = 64,
3734 .vp_max = 255,
3735 .hp_max = 256,
3736 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3737 .calc_core_clk = calc_core_clk_34xx,
3738};
3739
3740static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
3741 .sw_start = 7,
3742 .fp_start = 19,
3743 .bp_start = 31,
3744 .sw_max = 256,
3745 .vp_max = 4095,
3746 .hp_max = 4096,
3747 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3748 .calc_core_clk = calc_core_clk_34xx,
3749};
3750
3751static const struct dispc_features omap44xx_dispc_feats __initconst = {
3752 .sw_start = 7,
3753 .fp_start = 19,
3754 .bp_start = 31,
3755 .sw_max = 256,
3756 .vp_max = 4095,
3757 .hp_max = 4096,
3758 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3759 .calc_core_clk = calc_core_clk_44xx,
3760};
3761
3762static int __init dispc_init_features(struct device *dev)
3763{
3764 const struct dispc_features *src;
3765 struct dispc_features *dst;
3766
3767 dst = devm_kzalloc(dev, sizeof(*dst), GFP_KERNEL);
3768 if (!dst) {
3769 dev_err(dev, "Failed to allocate DISPC Features\n");
3770 return -ENOMEM;
3771 }
3772
3773 if (cpu_is_omap24xx()) {
3774 src = &omap24xx_dispc_feats;
3775 } else if (cpu_is_omap34xx()) {
3776 if (omap_rev() < OMAP3430_REV_ES3_0)
3777 src = &omap34xx_rev1_0_dispc_feats;
3778 else
3779 src = &omap34xx_rev3_0_dispc_feats;
3780 } else if (cpu_is_omap44xx()) {
3781 src = &omap44xx_dispc_feats;
3782 } else {
3783 return -ENODEV;
3784 }
3785
3786 memcpy(dst, src, sizeof(*dst));
3787 dispc.feat = dst;
3788
3789 return 0;
3790}
3791
060b6d9c 3792/* DISPC HW IP initialisation */
6e7e8f06 3793static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 3794{
3795 u32 rev;
affe360d 3796 int r = 0;
ea9da36a 3797 struct resource *dispc_mem;
4fbafaf3 3798 struct clk *clk;
ea9da36a 3799
060b6d9c
SG		 3800 dispc.pdev = pdev;
3801
dcbe765b
CM		 3802 r = dispc_init_features(&dispc.pdev->dev);
3803 if (r)
3804 return r;
3805
060b6d9c
SG		 3806 spin_lock_init(&dispc.irq_lock);
3807
3808#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3809 spin_lock_init(&dispc.irq_stats_lock);
3810 dispc.irq_stats.last_reset = jiffies;
3811#endif
3812
3813 INIT_WORK(&dispc.error_work, dispc_error_worker);
3814
ea9da36a
SG		 3815 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3816 if (!dispc_mem) {
3817 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3818 return -EINVAL;
ea9da36a 3819 }
cd3b3449 3820
6e2a14d2
JL		 3821 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3822 resource_size(dispc_mem));
060b6d9c
SG		 3823 if (!dispc.base) {
3824 DSSERR("can't ioremap DISPC\n");
cd3b3449 3825 return -ENOMEM;
affe360d 3826 }
cd3b3449 3827
affe360d 3828 dispc.irq = platform_get_irq(dispc.pdev, 0);
3829 if (dispc.irq < 0) {
3830 DSSERR("platform_get_irq failed\n");
cd3b3449 3831 return -ENODEV;
affe360d 3832 }
3833
6e2a14d2
JL		 3834 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3835 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3836 if (r < 0) {
3837 DSSERR("request_irq failed\n");
cd3b3449
TV		 3838 return r;
3839 }
3840
3841 clk = clk_get(&pdev->dev, "fck");
3842 if (IS_ERR(clk)) {
3843 DSSERR("can't get fck\n");
3844 r = PTR_ERR(clk);
3845 return r;
060b6d9c
SG		 3846 }
3847
cd3b3449
TV		 3848 dispc.dss_clk = clk;
3849
4fbafaf3
TV		 3850 pm_runtime_enable(&pdev->dev);
3851
3852 r = dispc_runtime_get();
3853 if (r)
3854 goto err_runtime_get;
060b6d9c
SG		 3855
3856 _omap_dispc_initial_config();
3857
3858 _omap_dispc_initialize_irq();
3859
060b6d9c 3860 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3861 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3862 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3863
4fbafaf3 3864 dispc_runtime_put();
060b6d9c 3865
e40402cf
TV		 3866 dss_debugfs_create_file("dispc", dispc_dump_regs);
3867
3868#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3869 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3870#endif
060b6d9c 3871 return 0;
4fbafaf3
TV		 3872
3873err_runtime_get:
3874 pm_runtime_disable(&pdev->dev);
4fbafaf3 3875 clk_put(dispc.dss_clk);
affe360d 3876 return r;
060b6d9c
SG		 3877}
3878
6e7e8f06 3879static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 3880{
4fbafaf3
TV		 3881 pm_runtime_disable(&pdev->dev);
3882
3883 clk_put(dispc.dss_clk);
3884
060b6d9c
SG		 3885 return 0;
3886}
3887
4fbafaf3
TV		 3888static int dispc_runtime_suspend(struct device *dev)
3889{
3890 dispc_save_context();
4fbafaf3
TV		 3891
3892 return 0;
3893}
3894
3895static int dispc_runtime_resume(struct device *dev)
3896{
49ea86f3 3897 dispc_restore_context();
4fbafaf3
TV		 3898
3899 return 0;
3900}
3901
3902static const struct dev_pm_ops dispc_pm_ops = {
3903 .runtime_suspend = dispc_runtime_suspend,
3904 .runtime_resume = dispc_runtime_resume,
3905};
3906
060b6d9c 3907static struct platform_driver omap_dispchw_driver = {
6e7e8f06 3908 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 3909 .driver = {
3910 .name = "omapdss_dispc",
3911 .owner = THIS_MODULE,
4fbafaf3 3912 .pm = &dispc_pm_ops,
060b6d9c
SG		 3913 },
3914};
3915
6e7e8f06 3916int __init dispc_init_platform_driver(void)
060b6d9c 3917{
11436e1d 3918 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 3919}
3920
6e7e8f06 3921void __exit dispc_uninit_platform_driver(void)
060b6d9c 3922{
04c742c3 3923 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 3924}
Linux kernel - Deliverables
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