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OMAP: DSS2: DISPC: Shorten _dispc_set_color_conv_coef()
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
28#include <linux/clk.h>
29#include <linux/io.h>
30#include <linux/jiffies.h>
31#include <linux/seq_file.h>
32#include <linux/delay.h>
33#include <linux/workqueue.h>
ab83b14c 34#include <linux/hardirq.h>
affe360d 35#include <linux/interrupt.h>
24e6289c 36#include <linux/platform_device.h>
4fbafaf3 37#include <linux/pm_runtime.h>
80c39712
TV		 38
39#include <plat/sram.h>
40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
66be8f6c
GI		 66struct dispc_h_coef {
67 s8 hc4;
68 s8 hc3;
69 u8 hc2;
70 s8 hc1;
71 s8 hc0;
72};
73
74struct dispc_v_coef {
75 s8 vc22;
76 s8 vc2;
77 u8 vc1;
78 s8 vc0;
79 s8 vc00;
80};
81
5ed8cf5b
TV		 82enum omap_burst_size {
83 BURST_SIZE_X2 = 0,
84 BURST_SIZE_X4 = 1,
85 BURST_SIZE_X8 = 2,
86};
87
80c39712
TV		 88#define REG_GET(idx, start, end) \
89 FLD_GET(dispc_read_reg(idx), start, end)
90
91#define REG_FLD_MOD(idx, val, start, end) \
92 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
93
dfc0fd8d
TV		 94struct dispc_irq_stats {
95 unsigned long last_reset;
96 unsigned irq_count;
97 unsigned irqs[32];
98};
99
80c39712 100static struct {
060b6d9c 101 struct platform_device *pdev;
80c39712 102 void __iomem *base;
4fbafaf3
TV		 103
104 int ctx_loss_cnt;
105
affe360d 106 int irq;
4fbafaf3 107 struct clk *dss_clk;
80c39712
TV		 108
109 u32 fifo_size[3];
110
111 spinlock_t irq_lock;
112 u32 irq_error_mask;
113 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
114 u32 error_irqs;
115 struct work_struct error_work;
116
49ea86f3 117 bool ctx_valid;
80c39712 118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 119
120#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
121 spinlock_t irq_stats_lock;
122 struct dispc_irq_stats irq_stats;
123#endif
80c39712
TV		 124} dispc;
125
0d66cbb5
AJ		 126enum omap_color_component {
127 /* used for all color formats for OMAP3 and earlier
128 * and for RGB and Y color component on OMAP4
129 */
130 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
131 /* used for UV component for
132 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
133 * color formats on OMAP4
134 */
135 DISPC_COLOR_COMPONENT_UV = 1 << 1,
136};
137
80c39712
TV		 138static void _omap_dispc_set_irqs(void);
139
55978cc2 140static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 141{
55978cc2 142 __raw_writel(val, dispc.base + idx);
80c39712
TV		 143}
144
55978cc2 145static inline u32 dispc_read_reg(const u16 idx)
80c39712 146{
55978cc2 147 return __raw_readl(dispc.base + idx);
80c39712
TV		 148}
149
49ea86f3
TV		 150static int dispc_get_ctx_loss_count(void)
151{
152 struct device *dev = &dispc.pdev->dev;
153 struct omap_display_platform_data *pdata = dev->platform_data;
154 struct omap_dss_board_info *board_data = pdata->board_data;
155 int cnt;
156
157 if (!board_data->get_context_loss_count)
158 return -ENOENT;
159
160 cnt = board_data->get_context_loss_count(dev);
161
162 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
163
164 return cnt;
165}
166
80c39712 167#define SR(reg) \
55978cc2 168 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 169#define RR(reg) \
55978cc2 170 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 171
4fbafaf3 172static void dispc_save_context(void)
80c39712 173{
c6104b8e 174 int i, j;
80c39712 175
4fbafaf3
TV		 176 DSSDBG("dispc_save_context\n");
177
80c39712
TV		 178 SR(IRQENABLE);
179 SR(CONTROL);
180 SR(CONFIG);
80c39712 181 SR(LINE_NUMBER);
332e9d70
TV		 182 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
183 SR(GLOBAL_ALPHA);
2a205f34
SS		 184 if (dss_has_feature(FEAT_MGR_LCD2)) {
185 SR(CONTROL2);
2a205f34
SS		 186 SR(CONFIG2);
187 }
80c39712 188
c6104b8e
AT		 189 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
190 SR(DEFAULT_COLOR(i));
191 SR(TRANS_COLOR(i));
192 SR(SIZE_MGR(i));
193 if (i == OMAP_DSS_CHANNEL_DIGIT)
194 continue;
195 SR(TIMING_H(i));
196 SR(TIMING_V(i));
197 SR(POL_FREQ(i));
198 SR(DIVISORo(i));
199
200 SR(DATA_CYCLE1(i));
201 SR(DATA_CYCLE2(i));
202 SR(DATA_CYCLE3(i));
203
332e9d70 204 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 205 SR(CPR_COEF_R(i));
206 SR(CPR_COEF_G(i));
207 SR(CPR_COEF_B(i));
332e9d70 208 }
2a205f34 209 }
80c39712 210
c6104b8e
AT		 211 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
212 SR(OVL_BA0(i));
213 SR(OVL_BA1(i));
214 SR(OVL_POSITION(i));
215 SR(OVL_SIZE(i));
216 SR(OVL_ATTRIBUTES(i));
217 SR(OVL_FIFO_THRESHOLD(i));
218 SR(OVL_ROW_INC(i));
219 SR(OVL_PIXEL_INC(i));
220 if (dss_has_feature(FEAT_PRELOAD))
221 SR(OVL_PRELOAD(i));
222 if (i == OMAP_DSS_GFX) {
223 SR(OVL_WINDOW_SKIP(i));
224 SR(OVL_TABLE_BA(i));
225 continue;
226 }
227 SR(OVL_FIR(i));
228 SR(OVL_PICTURE_SIZE(i));
229 SR(OVL_ACCU0(i));
230 SR(OVL_ACCU1(i));
9b372c2d 231
c6104b8e
AT		 232 for (j = 0; j < 8; j++)
233 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 234
c6104b8e
AT		 235 for (j = 0; j < 8; j++)
236 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 237
c6104b8e
AT		 238 for (j = 0; j < 5; j++)
239 SR(OVL_CONV_COEF(i, j));
ab5ca071 240
c6104b8e
AT		 241 if (dss_has_feature(FEAT_FIR_COEF_V)) {
242 for (j = 0; j < 8; j++)
243 SR(OVL_FIR_COEF_V(i, j));
244 }
9b372c2d 245
c6104b8e
AT		 246 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
247 SR(OVL_BA0_UV(i));
248 SR(OVL_BA1_UV(i));
249 SR(OVL_FIR2(i));
250 SR(OVL_ACCU2_0(i));
251 SR(OVL_ACCU2_1(i));
ab5ca071 252
c6104b8e
AT		 253 for (j = 0; j < 8; j++)
254 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 255
c6104b8e
AT		 256 for (j = 0; j < 8; j++)
257 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 258
c6104b8e
AT		 259 for (j = 0; j < 8; j++)
260 SR(OVL_FIR_COEF_V2(i, j));
261 }
262 if (dss_has_feature(FEAT_ATTR2))
263 SR(OVL_ATTRIBUTES2(i));
ab5ca071 264 }
0cf35df3
MR		 265
266 if (dss_has_feature(FEAT_CORE_CLK_DIV))
267 SR(DIVISOR);
49ea86f3
TV		 268
269 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
270 dispc.ctx_valid = true;
271
272 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 273}
274
4fbafaf3 275static void dispc_restore_context(void)
80c39712 276{
c6104b8e 277 int i, j, ctx;
4fbafaf3
TV		 278
279 DSSDBG("dispc_restore_context\n");
280
49ea86f3
TV		 281 if (!dispc.ctx_valid)
282 return;
283
284 ctx = dispc_get_ctx_loss_count();
285
286 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
287 return;
288
289 DSSDBG("ctx_loss_count: saved %d, current %d\n",
290 dispc.ctx_loss_cnt, ctx);
291
75c7d59d 292 /*RR(IRQENABLE);*/
80c39712
TV		 293 /*RR(CONTROL);*/
294 RR(CONFIG);
80c39712 295 RR(LINE_NUMBER);
332e9d70
TV		 296 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
297 RR(GLOBAL_ALPHA);
c6104b8e 298 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 299 RR(CONFIG2);
80c39712 300
c6104b8e
AT		 301 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
302 RR(DEFAULT_COLOR(i));
303 RR(TRANS_COLOR(i));
304 RR(SIZE_MGR(i));
305 if (i == OMAP_DSS_CHANNEL_DIGIT)
306 continue;
307 RR(TIMING_H(i));
308 RR(TIMING_V(i));
309 RR(POL_FREQ(i));
310 RR(DIVISORo(i));
311
312 RR(DATA_CYCLE1(i));
313 RR(DATA_CYCLE2(i));
314 RR(DATA_CYCLE3(i));
2a205f34 315
332e9d70 316 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 317 RR(CPR_COEF_R(i));
318 RR(CPR_COEF_G(i));
319 RR(CPR_COEF_B(i));
332e9d70 320 }
2a205f34 321 }
80c39712 322
c6104b8e
AT		 323 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
324 RR(OVL_BA0(i));
325 RR(OVL_BA1(i));
326 RR(OVL_POSITION(i));
327 RR(OVL_SIZE(i));
328 RR(OVL_ATTRIBUTES(i));
329 RR(OVL_FIFO_THRESHOLD(i));
330 RR(OVL_ROW_INC(i));
331 RR(OVL_PIXEL_INC(i));
332 if (dss_has_feature(FEAT_PRELOAD))
333 RR(OVL_PRELOAD(i));
334 if (i == OMAP_DSS_GFX) {
335 RR(OVL_WINDOW_SKIP(i));
336 RR(OVL_TABLE_BA(i));
337 continue;
338 }
339 RR(OVL_FIR(i));
340 RR(OVL_PICTURE_SIZE(i));
341 RR(OVL_ACCU0(i));
342 RR(OVL_ACCU1(i));
9b372c2d 343
c6104b8e
AT		 344 for (j = 0; j < 8; j++)
345 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 346
c6104b8e
AT		 347 for (j = 0; j < 8; j++)
348 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 349
c6104b8e
AT		 350 for (j = 0; j < 5; j++)
351 RR(OVL_CONV_COEF(i, j));
ab5ca071 352
c6104b8e
AT		 353 if (dss_has_feature(FEAT_FIR_COEF_V)) {
354 for (j = 0; j < 8; j++)
355 RR(OVL_FIR_COEF_V(i, j));
356 }
9b372c2d 357
c6104b8e
AT		 358 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
359 RR(OVL_BA0_UV(i));
360 RR(OVL_BA1_UV(i));
361 RR(OVL_FIR2(i));
362 RR(OVL_ACCU2_0(i));
363 RR(OVL_ACCU2_1(i));
ab5ca071 364
c6104b8e
AT		 365 for (j = 0; j < 8; j++)
366 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 367
c6104b8e
AT		 368 for (j = 0; j < 8; j++)
369 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 370
c6104b8e
AT		 371 for (j = 0; j < 8; j++)
372 RR(OVL_FIR_COEF_V2(i, j));
373 }
374 if (dss_has_feature(FEAT_ATTR2))
375 RR(OVL_ATTRIBUTES2(i));
ab5ca071 376 }
80c39712 377
0cf35df3
MR		 378 if (dss_has_feature(FEAT_CORE_CLK_DIV))
379 RR(DIVISOR);
380
80c39712
TV		 381 /* enable last, because LCD & DIGIT enable are here */
382 RR(CONTROL);
2a205f34
SS		 383 if (dss_has_feature(FEAT_MGR_LCD2))
384 RR(CONTROL2);
75c7d59d
VS		 385 /* clear spurious SYNC_LOST_DIGIT interrupts */
386 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
387
388 /*
389 * enable last so IRQs won't trigger before
390 * the context is fully restored
391 */
392 RR(IRQENABLE);
49ea86f3
TV		 393
394 DSSDBG("context restored\n");
80c39712
TV		 395}
396
397#undef SR
398#undef RR
399
4fbafaf3
TV		 400int dispc_runtime_get(void)
401{
402 int r;
403
404 DSSDBG("dispc_runtime_get\n");
405
406 r = pm_runtime_get_sync(&dispc.pdev->dev);
407 WARN_ON(r < 0);
408 return r < 0 ? r : 0;
409}
410
411void dispc_runtime_put(void)
412{
413 int r;
414
415 DSSDBG("dispc_runtime_put\n");
416
417 r = pm_runtime_put(&dispc.pdev->dev);
418 WARN_ON(r < 0);
80c39712
TV		 419}
420
4fbafaf3 421
80c39712
TV		 422bool dispc_go_busy(enum omap_channel channel)
423{
424 int bit;
425
2a205f34
SS		 426 if (channel == OMAP_DSS_CHANNEL_LCD ||
427 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 428 bit = 5; /* GOLCD */
429 else
430 bit = 6; /* GODIGIT */
431
2a205f34
SS		 432 if (channel == OMAP_DSS_CHANNEL_LCD2)
433 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
434 else
435 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 436}
437
438void dispc_go(enum omap_channel channel)
439{
440 int bit;
2a205f34 441 bool enable_bit, go_bit;
80c39712 442
2a205f34
SS		 443 if (channel == OMAP_DSS_CHANNEL_LCD ||
444 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 445 bit = 0; /* LCDENABLE */
446 else
447 bit = 1; /* DIGITALENABLE */
448
449 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 450 if (channel == OMAP_DSS_CHANNEL_LCD2)
451 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
452 else
453 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
454
455 if (!enable_bit)
e6d80f95 456 return;
80c39712 457
2a205f34
SS		 458 if (channel == OMAP_DSS_CHANNEL_LCD ||
459 channel == OMAP_DSS_CHANNEL_LCD2)
80c39712
TV		 460 bit = 5; /* GOLCD */
461 else
462 bit = 6; /* GODIGIT */
463
2a205f34
SS		 464 if (channel == OMAP_DSS_CHANNEL_LCD2)
465 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
466 else
467 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
468
469 if (go_bit) {
80c39712 470 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 471 return;
80c39712
TV		 472 }
473
2a205f34
SS		 474 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
475 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 476
2a205f34
SS		 477 if (channel == OMAP_DSS_CHANNEL_LCD2)
478 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
479 else
480 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 481}
482
483static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
484{
9b372c2d 485 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 486}
487
488static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
489{
9b372c2d 490 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 491}
492
493static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
494{
9b372c2d 495 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 496}
497
ab5ca071
AJ		 498static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
499{
500 BUG_ON(plane == OMAP_DSS_GFX);
501
502 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
503}
504
505static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
506{
507 BUG_ON(plane == OMAP_DSS_GFX);
508
509 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
510}
511
512static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
513{
514 BUG_ON(plane == OMAP_DSS_GFX);
515
516 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
517}
518
80c39712 519static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
0d66cbb5
AJ		 520 int vscaleup, int five_taps,
521 enum omap_color_component color_comp)
80c39712
TV		 522{
523 /* Coefficients for horizontal up-sampling */
66be8f6c
GI		 524 static const struct dispc_h_coef coef_hup[8] = {
525 { 0, 0, 128, 0, 0 },
526 { -1, 13, 124, -8, 0 },
527 { -2, 30, 112, -11, -1 },
528 { -5, 51, 95, -11, -2 },
529 { 0, -9, 73, 73, -9 },
530 { -2, -11, 95, 51, -5 },
531 { -1, -11, 112, 30, -2 },
532 { 0, -8, 124, 13, -1 },
80c39712
TV		 533 };
534
66be8f6c
GI		 535 /* Coefficients for vertical up-sampling */
536 static const struct dispc_v_coef coef_vup_3tap[8] = {
537 { 0, 0, 128, 0, 0 },
538 { 0, 3, 123, 2, 0 },
539 { 0, 12, 111, 5, 0 },
540 { 0, 32, 89, 7, 0 },
541 { 0, 0, 64, 64, 0 },
542 { 0, 7, 89, 32, 0 },
543 { 0, 5, 111, 12, 0 },
544 { 0, 2, 123, 3, 0 },
80c39712
TV		 545 };
546
66be8f6c
GI		 547 static const struct dispc_v_coef coef_vup_5tap[8] = {
548 { 0, 0, 128, 0, 0 },
549 { -1, 13, 124, -8, 0 },
550 { -2, 30, 112, -11, -1 },
551 { -5, 51, 95, -11, -2 },
552 { 0, -9, 73, 73, -9 },
553 { -2, -11, 95, 51, -5 },
554 { -1, -11, 112, 30, -2 },
555 { 0, -8, 124, 13, -1 },
80c39712
TV		 556 };
557
66be8f6c
GI		 558 /* Coefficients for horizontal down-sampling */
559 static const struct dispc_h_coef coef_hdown[8] = {
560 { 0, 36, 56, 36, 0 },
561 { 4, 40, 55, 31, -2 },
562 { 8, 44, 54, 27, -5 },
563 { 12, 48, 53, 22, -7 },
564 { -9, 17, 52, 51, 17 },
565 { -7, 22, 53, 48, 12 },
566 { -5, 27, 54, 44, 8 },
567 { -2, 31, 55, 40, 4 },
80c39712
TV		 568 };
569
66be8f6c
GI		 570 /* Coefficients for vertical down-sampling */
571 static const struct dispc_v_coef coef_vdown_3tap[8] = {
572 { 0, 36, 56, 36, 0 },
573 { 0, 40, 57, 31, 0 },
574 { 0, 45, 56, 27, 0 },
575 { 0, 50, 55, 23, 0 },
576 { 0, 18, 55, 55, 0 },
577 { 0, 23, 55, 50, 0 },
578 { 0, 27, 56, 45, 0 },
579 { 0, 31, 57, 40, 0 },
80c39712
TV		 580 };
581
66be8f6c
GI		 582 static const struct dispc_v_coef coef_vdown_5tap[8] = {
583 { 0, 36, 56, 36, 0 },
584 { 4, 40, 55, 31, -2 },
585 { 8, 44, 54, 27, -5 },
586 { 12, 48, 53, 22, -7 },
587 { -9, 17, 52, 51, 17 },
588 { -7, 22, 53, 48, 12 },
589 { -5, 27, 54, 44, 8 },
590 { -2, 31, 55, 40, 4 },
80c39712
TV		 591 };
592
66be8f6c
GI		 593 const struct dispc_h_coef *h_coef;
594 const struct dispc_v_coef *v_coef;
80c39712
TV		 595 int i;
596
597 if (hscaleup)
598 h_coef = coef_hup;
599 else
600 h_coef = coef_hdown;
601
66be8f6c
GI		 602 if (vscaleup)
603 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
604 else
605 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
80c39712
TV		 606
607 for (i = 0; i < 8; i++) {
608 u32 h, hv;
609
66be8f6c
GI		 610 h = FLD_VAL(h_coef[i].hc0, 7, 0)
611 | FLD_VAL(h_coef[i].hc1, 15, 8)
612 | FLD_VAL(h_coef[i].hc2, 23, 16)
613 | FLD_VAL(h_coef[i].hc3, 31, 24);
614 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
615 | FLD_VAL(v_coef[i].vc0, 15, 8)
616 | FLD_VAL(v_coef[i].vc1, 23, 16)
617 | FLD_VAL(v_coef[i].vc2, 31, 24);
80c39712 618
0d66cbb5
AJ		 619 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
620 _dispc_write_firh_reg(plane, i, h);
621 _dispc_write_firhv_reg(plane, i, hv);
622 } else {
623 _dispc_write_firh2_reg(plane, i, h);
624 _dispc_write_firhv2_reg(plane, i, hv);
625 }
626
80c39712
TV		 627 }
628
66be8f6c
GI		 629 if (five_taps) {
630 for (i = 0; i < 8; i++) {
631 u32 v;
632 v = FLD_VAL(v_coef[i].vc00, 7, 0)
633 | FLD_VAL(v_coef[i].vc22, 15, 8);
0d66cbb5
AJ		 634 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
635 _dispc_write_firv_reg(plane, i, v);
636 else
637 _dispc_write_firv2_reg(plane, i, v);
66be8f6c 638 }
80c39712
TV		 639 }
640}
641
642static void _dispc_setup_color_conv_coef(void)
643{
ac01c29e 644 int i;
80c39712
TV		 645 const struct color_conv_coef {
646 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
647 int full_range;
648 } ctbl_bt601_5 = {
649 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
650 };
651
652 const struct color_conv_coef *ct;
653
654#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
655
656 ct = &ctbl_bt601_5;
657
ac01c29e
AT		 658 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
659 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
660 CVAL(ct->rcr, ct->ry));
661 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
662 CVAL(ct->gy, ct->rcb));
663 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
664 CVAL(ct->gcb, ct->gcr));
665 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
666 CVAL(ct->bcr, ct->by));
667 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
668 CVAL(0, ct->bcb));
669
670 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
671 11, 11);
672 }
80c39712
TV		 673
674#undef CVAL
80c39712
TV		 675}
676
677
678static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
679{
9b372c2d 680 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 681}
682
683static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
684{
9b372c2d 685 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 686}
687
ab5ca071
AJ		 688static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
689{
690 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
691}
692
693static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
694{
695 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
696}
697
80c39712
TV		 698static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
699{
80c39712 700 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 701
702 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 703}
704
705static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
706{
80c39712 707 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 708
709 if (plane == OMAP_DSS_GFX)
710 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
711 else
712 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 713}
714
715static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
716{
717 u32 val;
80c39712
TV		 718
719 BUG_ON(plane == OMAP_DSS_GFX);
720
721 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 722
723 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 724}
725
fd28a390
R		 726static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
727{
728 if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
729 return;
730
731 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
732 plane == OMAP_DSS_VIDEO1)
733 return;
734
9b372c2d 735 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 736}
737
80c39712
TV		 738static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
739{
a0acb557 740 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 741 return;
742
fd28a390
R		 743 if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
744 plane == OMAP_DSS_VIDEO1)
745 return;
a0acb557 746
80c39712
TV		 747 if (plane == OMAP_DSS_GFX)
748 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
749 else if (plane == OMAP_DSS_VIDEO2)
750 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
751}
752
753static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
754{
9b372c2d 755 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 756}
757
758static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
759{
9b372c2d 760 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 761}
762
763static void _dispc_set_color_mode(enum omap_plane plane,
764 enum omap_color_mode color_mode)
765{
766 u32 m = 0;
f20e4220
AJ		 767 if (plane != OMAP_DSS_GFX) {
768 switch (color_mode) {
769 case OMAP_DSS_COLOR_NV12:
770 m = 0x0; break;
771 case OMAP_DSS_COLOR_RGB12U:
772 m = 0x1; break;
773 case OMAP_DSS_COLOR_RGBA16:
774 m = 0x2; break;
775 case OMAP_DSS_COLOR_RGBX16:
776 m = 0x4; break;
777 case OMAP_DSS_COLOR_ARGB16:
778 m = 0x5; break;
779 case OMAP_DSS_COLOR_RGB16:
780 m = 0x6; break;
781 case OMAP_DSS_COLOR_ARGB16_1555:
782 m = 0x7; break;
783 case OMAP_DSS_COLOR_RGB24U:
784 m = 0x8; break;
785 case OMAP_DSS_COLOR_RGB24P:
786 m = 0x9; break;
787 case OMAP_DSS_COLOR_YUV2:
788 m = 0xa; break;
789 case OMAP_DSS_COLOR_UYVY:
790 m = 0xb; break;
791 case OMAP_DSS_COLOR_ARGB32:
792 m = 0xc; break;
793 case OMAP_DSS_COLOR_RGBA32:
794 m = 0xd; break;
795 case OMAP_DSS_COLOR_RGBX32:
796 m = 0xe; break;
797 case OMAP_DSS_COLOR_XRGB16_1555:
798 m = 0xf; break;
799 default:
800 BUG(); break;
801 }
802 } else {
803 switch (color_mode) {
804 case OMAP_DSS_COLOR_CLUT1:
805 m = 0x0; break;
806 case OMAP_DSS_COLOR_CLUT2:
807 m = 0x1; break;
808 case OMAP_DSS_COLOR_CLUT4:
809 m = 0x2; break;
810 case OMAP_DSS_COLOR_CLUT8:
811 m = 0x3; break;
812 case OMAP_DSS_COLOR_RGB12U:
813 m = 0x4; break;
814 case OMAP_DSS_COLOR_ARGB16:
815 m = 0x5; break;
816 case OMAP_DSS_COLOR_RGB16:
817 m = 0x6; break;
818 case OMAP_DSS_COLOR_ARGB16_1555:
819 m = 0x7; break;
820 case OMAP_DSS_COLOR_RGB24U:
821 m = 0x8; break;
822 case OMAP_DSS_COLOR_RGB24P:
823 m = 0x9; break;
824 case OMAP_DSS_COLOR_YUV2:
825 m = 0xa; break;
826 case OMAP_DSS_COLOR_UYVY:
827 m = 0xb; break;
828 case OMAP_DSS_COLOR_ARGB32:
829 m = 0xc; break;
830 case OMAP_DSS_COLOR_RGBA32:
831 m = 0xd; break;
832 case OMAP_DSS_COLOR_RGBX32:
833 m = 0xe; break;
834 case OMAP_DSS_COLOR_XRGB16_1555:
835 m = 0xf; break;
836 default:
837 BUG(); break;
838 }
80c39712
TV		 839 }
840
9b372c2d 841 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 842}
843
e6d80f95 844void dispc_set_channel_out(enum omap_plane plane,
80c39712
TV		 845 enum omap_channel channel)
846{
847 int shift;
848 u32 val;
2a205f34 849 int chan = 0, chan2 = 0;
80c39712
TV		 850
851 switch (plane) {
852 case OMAP_DSS_GFX:
853 shift = 8;
854 break;
855 case OMAP_DSS_VIDEO1:
856 case OMAP_DSS_VIDEO2:
857 shift = 16;
858 break;
859 default:
860 BUG();
861 return;
862 }
863
9b372c2d 864 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 865 if (dss_has_feature(FEAT_MGR_LCD2)) {
866 switch (channel) {
867 case OMAP_DSS_CHANNEL_LCD:
868 chan = 0;
869 chan2 = 0;
870 break;
871 case OMAP_DSS_CHANNEL_DIGIT:
872 chan = 1;
873 chan2 = 0;
874 break;
875 case OMAP_DSS_CHANNEL_LCD2:
876 chan = 0;
877 chan2 = 1;
878 break;
879 default:
880 BUG();
881 }
882
883 val = FLD_MOD(val, chan, shift, shift);
884 val = FLD_MOD(val, chan2, 31, 30);
885 } else {
886 val = FLD_MOD(val, channel, shift, shift);
887 }
9b372c2d 888 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 889}
890
5ed8cf5b 891static void dispc_set_burst_size(enum omap_plane plane,
80c39712
TV		 892 enum omap_burst_size burst_size)
893{
894 int shift;
80c39712 895
80c39712
TV		 896 switch (plane) {
897 case OMAP_DSS_GFX:
898 shift = 6;
899 break;
900 case OMAP_DSS_VIDEO1:
901 case OMAP_DSS_VIDEO2:
902 shift = 14;
903 break;
904 default:
905 BUG();
906 return;
907 }
908
5ed8cf5b 909 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 910}
911
5ed8cf5b
TV		 912static void dispc_configure_burst_sizes(void)
913{
914 int i;
915 const int burst_size = BURST_SIZE_X8;
916
917 /* Configure burst size always to maximum size */
918 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
919 dispc_set_burst_size(i, burst_size);
920}
921
922u32 dispc_get_burst_size(enum omap_plane plane)
923{
924 unsigned unit = dss_feat_get_burst_size_unit();
925 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
926 return unit * 8;
927}
928
d3862610
M		 929void dispc_enable_gamma_table(bool enable)
930{
931 /*
932 * This is partially implemented to support only disabling of
933 * the gamma table.
934 */
935 if (enable) {
936 DSSWARN("Gamma table enabling for TV not yet supported");
937 return;
938 }
939
940 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
941}
942
3c07cae2
TV		 943void dispc_enable_cpr(enum omap_channel channel, bool enable)
944{
945 u16 reg;
946
947 if (channel == OMAP_DSS_CHANNEL_LCD)
948 reg = DISPC_CONFIG;
949 else if (channel == OMAP_DSS_CHANNEL_LCD2)
950 reg = DISPC_CONFIG2;
951 else
952 return;
953
954 REG_FLD_MOD(reg, enable, 15, 15);
955}
956
957void dispc_set_cpr_coef(enum omap_channel channel,
958 struct omap_dss_cpr_coefs *coefs)
959{
960 u32 coef_r, coef_g, coef_b;
961
962 if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2)
963 return;
964
965 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
966 FLD_VAL(coefs->rb, 9, 0);
967 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
968 FLD_VAL(coefs->gb, 9, 0);
969 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
970 FLD_VAL(coefs->bb, 9, 0);
971
972 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
973 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
974 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
975}
976
80c39712
TV		 977static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
978{
979 u32 val;
980
981 BUG_ON(plane == OMAP_DSS_GFX);
982
9b372c2d 983 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 984 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 985 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 986}
987
988void dispc_enable_replication(enum omap_plane plane, bool enable)
989{
990 int bit;
991
992 if (plane == OMAP_DSS_GFX)
993 bit = 5;
994 else
995 bit = 10;
996
9b372c2d 997 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
80c39712
TV		 998}
999
64ba4f74 1000void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
80c39712
TV		 1001{
1002 u32 val;
1003 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1004 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1005 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1006}
1007
1008void dispc_set_digit_size(u16 width, u16 height)
1009{
1010 u32 val;
1011 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1012 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
702d1448 1013 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
80c39712
TV		 1014}
1015
1016static void dispc_read_plane_fifo_sizes(void)
1017{
80c39712
TV		 1018 u32 size;
1019 int plane;
a0acb557 1020 u8 start, end;
5ed8cf5b
TV		 1021 u32 unit;
1022
1023 unit = dss_feat_get_buffer_size_unit();
80c39712 1024
a0acb557 1025 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1026
a0acb557 1027 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
5ed8cf5b
TV		 1028 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1029 size *= unit;
80c39712
TV		 1030 dispc.fifo_size[plane] = size;
1031 }
80c39712
TV		 1032}
1033
1034u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1035{
1036 return dispc.fifo_size[plane];
1037}
1038
5ed8cf5b 1039void dispc_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1040{
a0acb557 1041 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1042 u32 unit;
1043
1044 unit = dss_feat_get_buffer_size_unit();
1045
1046 WARN_ON(low % unit != 0);
1047 WARN_ON(high % unit != 0);
1048
1049 low /= unit;
1050 high /= unit;
a0acb557 1051
9b372c2d
AT		 1052 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1053 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1054
80c39712
TV		 1055 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1056 plane,
9b372c2d
AT		 1057 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1058 lo_start, lo_end),
1059 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1060 hi_start, hi_end),
80c39712
TV		 1061 low, high);
1062
9b372c2d 1063 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1064 FLD_VAL(high, hi_start, hi_end) |
1065 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1066}
1067
1068void dispc_enable_fifomerge(bool enable)
1069{
80c39712
TV		 1070 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1071 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1072}
1073
0d66cbb5
AJ		 1074static void _dispc_set_fir(enum omap_plane plane,
1075 int hinc, int vinc,
1076 enum omap_color_component color_comp)
80c39712
TV		 1077{
1078 u32 val;
80c39712 1079
0d66cbb5
AJ		 1080 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1081 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1082
0d66cbb5
AJ		 1083 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1084 &hinc_start, &hinc_end);
1085 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1086 &vinc_start, &vinc_end);
1087 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1088 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1089
0d66cbb5
AJ		 1090 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1091 } else {
1092 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1093 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1094 }
80c39712
TV		 1095}
1096
1097static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1098{
1099 u32 val;
87a7484b 1100 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1101
87a7484b
AT		 1102 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1103 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1104
1105 val = FLD_VAL(vaccu, vert_start, vert_end) |
1106 FLD_VAL(haccu, hor_start, hor_end);
1107
9b372c2d 1108 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1109}
1110
1111static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1112{
1113 u32 val;
87a7484b 1114 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1115
87a7484b
AT		 1116 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1117 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1118
1119 val = FLD_VAL(vaccu, vert_start, vert_end) |
1120 FLD_VAL(haccu, hor_start, hor_end);
1121
9b372c2d 1122 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1123}
1124
ab5ca071
AJ		 1125static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
1126{
1127 u32 val;
1128
1129 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1130 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1131}
1132
1133static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
1134{
1135 u32 val;
1136
1137 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1138 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1139}
80c39712 1140
0d66cbb5 1141static void _dispc_set_scale_param(enum omap_plane plane,
80c39712
TV		 1142 u16 orig_width, u16 orig_height,
1143 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1144 bool five_taps, u8 rotation,
1145 enum omap_color_component color_comp)
80c39712 1146{
0d66cbb5 1147 int fir_hinc, fir_vinc;
80c39712 1148 int hscaleup, vscaleup;
80c39712
TV		 1149
1150 hscaleup = orig_width <= out_width;
1151 vscaleup = orig_height <= out_height;
1152
0d66cbb5 1153 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
80c39712 1154
ed14a3ce
AJ		 1155 fir_hinc = 1024 * orig_width / out_width;
1156 fir_vinc = 1024 * orig_height / out_height;
80c39712 1157
0d66cbb5
AJ		 1158 _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1159}
1160
1161static void _dispc_set_scaling_common(enum omap_plane plane,
1162 u16 orig_width, u16 orig_height,
1163 u16 out_width, u16 out_height,
1164 bool ilace, bool five_taps,
1165 bool fieldmode, enum omap_color_mode color_mode,
1166 u8 rotation)
1167{
1168 int accu0 = 0;
1169 int accu1 = 0;
1170 u32 l;
80c39712 1171
0d66cbb5
AJ		 1172 _dispc_set_scale_param(plane, orig_width, orig_height,
1173 out_width, out_height, five_taps,
1174 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1175 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1176
87a7484b
AT		 1177 /* RESIZEENABLE and VERTICALTAPS */
1178 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1179 l |= (orig_width != out_width) ? (1 << 5) : 0;
1180 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1181 l |= five_taps ? (1 << 21) : 0;
80c39712 1182
87a7484b
AT		 1183 /* VRESIZECONF and HRESIZECONF */
1184 if (dss_has_feature(FEAT_RESIZECONF)) {
1185 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1186 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1187 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1188 }
80c39712 1189
87a7484b
AT		 1190 /* LINEBUFFERSPLIT */
1191 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1192 l &= ~(0x1 << 22);
1193 l |= five_taps ? (1 << 22) : 0;
1194 }
80c39712 1195
9b372c2d 1196 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1197
1198 /*
1199 * field 0 = even field = bottom field
1200 * field 1 = odd field = top field
1201 */
1202 if (ilace && !fieldmode) {
1203 accu1 = 0;
0d66cbb5 1204 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1205 if (accu0 >= 1024/2) {
1206 accu1 = 1024/2;
1207 accu0 -= accu1;
1208 }
1209 }
1210
1211 _dispc_set_vid_accu0(plane, 0, accu0);
1212 _dispc_set_vid_accu1(plane, 0, accu1);
1213}
1214
0d66cbb5
AJ		 1215static void _dispc_set_scaling_uv(enum omap_plane plane,
1216 u16 orig_width, u16 orig_height,
1217 u16 out_width, u16 out_height,
1218 bool ilace, bool five_taps,
1219 bool fieldmode, enum omap_color_mode color_mode,
1220 u8 rotation)
1221{
1222 int scale_x = out_width != orig_width;
1223 int scale_y = out_height != orig_height;
1224
1225 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1226 return;
1227 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1228 color_mode != OMAP_DSS_COLOR_UYVY &&
1229 color_mode != OMAP_DSS_COLOR_NV12)) {
1230 /* reset chroma resampling for RGB formats */
1231 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1232 return;
1233 }
1234 switch (color_mode) {
1235 case OMAP_DSS_COLOR_NV12:
1236 /* UV is subsampled by 2 vertically*/
1237 orig_height >>= 1;
1238 /* UV is subsampled by 2 horz.*/
1239 orig_width >>= 1;
1240 break;
1241 case OMAP_DSS_COLOR_YUV2:
1242 case OMAP_DSS_COLOR_UYVY:
1243 /*For YUV422 with 90/270 rotation,
1244 *we don't upsample chroma
1245 */
1246 if (rotation == OMAP_DSS_ROT_0 ||
1247 rotation == OMAP_DSS_ROT_180)
1248 /* UV is subsampled by 2 hrz*/
1249 orig_width >>= 1;
1250 /* must use FIR for YUV422 if rotated */
1251 if (rotation != OMAP_DSS_ROT_0)
1252 scale_x = scale_y = true;
1253 break;
1254 default:
1255 BUG();
1256 }
1257
1258 if (out_width != orig_width)
1259 scale_x = true;
1260 if (out_height != orig_height)
1261 scale_y = true;
1262
1263 _dispc_set_scale_param(plane, orig_width, orig_height,
1264 out_width, out_height, five_taps,
1265 rotation, DISPC_COLOR_COMPONENT_UV);
1266
1267 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1268 (scale_x || scale_y) ? 1 : 0, 8, 8);
1269 /* set H scaling */
1270 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1271 /* set V scaling */
1272 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1273
1274 _dispc_set_vid_accu2_0(plane, 0x80, 0);
1275 _dispc_set_vid_accu2_1(plane, 0x80, 0);
1276}
1277
1278static void _dispc_set_scaling(enum omap_plane plane,
1279 u16 orig_width, u16 orig_height,
1280 u16 out_width, u16 out_height,
1281 bool ilace, bool five_taps,
1282 bool fieldmode, enum omap_color_mode color_mode,
1283 u8 rotation)
1284{
1285 BUG_ON(plane == OMAP_DSS_GFX);
1286
1287 _dispc_set_scaling_common(plane,
1288 orig_width, orig_height,
1289 out_width, out_height,
1290 ilace, five_taps,
1291 fieldmode, color_mode,
1292 rotation);
1293
1294 _dispc_set_scaling_uv(plane,
1295 orig_width, orig_height,
1296 out_width, out_height,
1297 ilace, five_taps,
1298 fieldmode, color_mode,
1299 rotation);
1300}
1301
80c39712
TV		 1302static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1303 bool mirroring, enum omap_color_mode color_mode)
1304{
87a7484b
AT		 1305 bool row_repeat = false;
1306 int vidrot = 0;
1307
80c39712
TV		 1308 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1309 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1310
1311 if (mirroring) {
1312 switch (rotation) {
1313 case OMAP_DSS_ROT_0:
1314 vidrot = 2;
1315 break;
1316 case OMAP_DSS_ROT_90:
1317 vidrot = 1;
1318 break;
1319 case OMAP_DSS_ROT_180:
1320 vidrot = 0;
1321 break;
1322 case OMAP_DSS_ROT_270:
1323 vidrot = 3;
1324 break;
1325 }
1326 } else {
1327 switch (rotation) {
1328 case OMAP_DSS_ROT_0:
1329 vidrot = 0;
1330 break;
1331 case OMAP_DSS_ROT_90:
1332 vidrot = 1;
1333 break;
1334 case OMAP_DSS_ROT_180:
1335 vidrot = 2;
1336 break;
1337 case OMAP_DSS_ROT_270:
1338 vidrot = 3;
1339 break;
1340 }
1341 }
1342
80c39712 1343 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1344 row_repeat = true;
80c39712 1345 else
87a7484b 1346 row_repeat = false;
80c39712 1347 }
87a7484b 1348
9b372c2d 1349 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1350 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1351 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1352 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1353}
1354
1355static int color_mode_to_bpp(enum omap_color_mode color_mode)
1356{
1357 switch (color_mode) {
1358 case OMAP_DSS_COLOR_CLUT1:
1359 return 1;
1360 case OMAP_DSS_COLOR_CLUT2:
1361 return 2;
1362 case OMAP_DSS_COLOR_CLUT4:
1363 return 4;
1364 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1365 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1366 return 8;
1367 case OMAP_DSS_COLOR_RGB12U:
1368 case OMAP_DSS_COLOR_RGB16:
1369 case OMAP_DSS_COLOR_ARGB16:
1370 case OMAP_DSS_COLOR_YUV2:
1371 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1372 case OMAP_DSS_COLOR_RGBA16:
1373 case OMAP_DSS_COLOR_RGBX16:
1374 case OMAP_DSS_COLOR_ARGB16_1555:
1375 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1376 return 16;
1377 case OMAP_DSS_COLOR_RGB24P:
1378 return 24;
1379 case OMAP_DSS_COLOR_RGB24U:
1380 case OMAP_DSS_COLOR_ARGB32:
1381 case OMAP_DSS_COLOR_RGBA32:
1382 case OMAP_DSS_COLOR_RGBX32:
1383 return 32;
1384 default:
1385 BUG();
1386 }
1387}
1388
1389static s32 pixinc(int pixels, u8 ps)
1390{
1391 if (pixels == 1)
1392 return 1;
1393 else if (pixels > 1)
1394 return 1 + (pixels - 1) * ps;
1395 else if (pixels < 0)
1396 return 1 - (-pixels + 1) * ps;
1397 else
1398 BUG();
1399}
1400
1401static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1402 u16 screen_width,
1403 u16 width, u16 height,
1404 enum omap_color_mode color_mode, bool fieldmode,
1405 unsigned int field_offset,
1406 unsigned *offset0, unsigned *offset1,
1407 s32 *row_inc, s32 *pix_inc)
1408{
1409 u8 ps;
1410
1411 /* FIXME CLUT formats */
1412 switch (color_mode) {
1413 case OMAP_DSS_COLOR_CLUT1:
1414 case OMAP_DSS_COLOR_CLUT2:
1415 case OMAP_DSS_COLOR_CLUT4:
1416 case OMAP_DSS_COLOR_CLUT8:
1417 BUG();
1418 return;
1419 case OMAP_DSS_COLOR_YUV2:
1420 case OMAP_DSS_COLOR_UYVY:
1421 ps = 4;
1422 break;
1423 default:
1424 ps = color_mode_to_bpp(color_mode) / 8;
1425 break;
1426 }
1427
1428 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1429 width, height);
1430
1431 /*
1432 * field 0 = even field = bottom field
1433 * field 1 = odd field = top field
1434 */
1435 switch (rotation + mirror * 4) {
1436 case OMAP_DSS_ROT_0:
1437 case OMAP_DSS_ROT_180:
1438 /*
1439 * If the pixel format is YUV or UYVY divide the width
1440 * of the image by 2 for 0 and 180 degree rotation.
1441 */
1442 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1443 color_mode == OMAP_DSS_COLOR_UYVY)
1444 width = width >> 1;
1445 case OMAP_DSS_ROT_90:
1446 case OMAP_DSS_ROT_270:
1447 *offset1 = 0;
1448 if (field_offset)
1449 *offset0 = field_offset * screen_width * ps;
1450 else
1451 *offset0 = 0;
1452
1453 *row_inc = pixinc(1 + (screen_width - width) +
1454 (fieldmode ? screen_width : 0),
1455 ps);
1456 *pix_inc = pixinc(1, ps);
1457 break;
1458
1459 case OMAP_DSS_ROT_0 + 4:
1460 case OMAP_DSS_ROT_180 + 4:
1461 /* If the pixel format is YUV or UYVY divide the width
1462 * of the image by 2 for 0 degree and 180 degree
1463 */
1464 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1465 color_mode == OMAP_DSS_COLOR_UYVY)
1466 width = width >> 1;
1467 case OMAP_DSS_ROT_90 + 4:
1468 case OMAP_DSS_ROT_270 + 4:
1469 *offset1 = 0;
1470 if (field_offset)
1471 *offset0 = field_offset * screen_width * ps;
1472 else
1473 *offset0 = 0;
1474 *row_inc = pixinc(1 - (screen_width + width) -
1475 (fieldmode ? screen_width : 0),
1476 ps);
1477 *pix_inc = pixinc(1, ps);
1478 break;
1479
1480 default:
1481 BUG();
1482 }
1483}
1484
1485static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1486 u16 screen_width,
1487 u16 width, u16 height,
1488 enum omap_color_mode color_mode, bool fieldmode,
1489 unsigned int field_offset,
1490 unsigned *offset0, unsigned *offset1,
1491 s32 *row_inc, s32 *pix_inc)
1492{
1493 u8 ps;
1494 u16 fbw, fbh;
1495
1496 /* FIXME CLUT formats */
1497 switch (color_mode) {
1498 case OMAP_DSS_COLOR_CLUT1:
1499 case OMAP_DSS_COLOR_CLUT2:
1500 case OMAP_DSS_COLOR_CLUT4:
1501 case OMAP_DSS_COLOR_CLUT8:
1502 BUG();
1503 return;
1504 default:
1505 ps = color_mode_to_bpp(color_mode) / 8;
1506 break;
1507 }
1508
1509 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1510 width, height);
1511
1512 /* width & height are overlay sizes, convert to fb sizes */
1513
1514 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1515 fbw = width;
1516 fbh = height;
1517 } else {
1518 fbw = height;
1519 fbh = width;
1520 }
1521
1522 /*
1523 * field 0 = even field = bottom field
1524 * field 1 = odd field = top field
1525 */
1526 switch (rotation + mirror * 4) {
1527 case OMAP_DSS_ROT_0:
1528 *offset1 = 0;
1529 if (field_offset)
1530 *offset0 = *offset1 + field_offset * screen_width * ps;
1531 else
1532 *offset0 = *offset1;
1533 *row_inc = pixinc(1 + (screen_width - fbw) +
1534 (fieldmode ? screen_width : 0),
1535 ps);
1536 *pix_inc = pixinc(1, ps);
1537 break;
1538 case OMAP_DSS_ROT_90:
1539 *offset1 = screen_width * (fbh - 1) * ps;
1540 if (field_offset)
1541 *offset0 = *offset1 + field_offset * ps;
1542 else
1543 *offset0 = *offset1;
1544 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1545 (fieldmode ? 1 : 0), ps);
1546 *pix_inc = pixinc(-screen_width, ps);
1547 break;
1548 case OMAP_DSS_ROT_180:
1549 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1550 if (field_offset)
1551 *offset0 = *offset1 - field_offset * screen_width * ps;
1552 else
1553 *offset0 = *offset1;
1554 *row_inc = pixinc(-1 -
1555 (screen_width - fbw) -
1556 (fieldmode ? screen_width : 0),
1557 ps);
1558 *pix_inc = pixinc(-1, ps);
1559 break;
1560 case OMAP_DSS_ROT_270:
1561 *offset1 = (fbw - 1) * ps;
1562 if (field_offset)
1563 *offset0 = *offset1 - field_offset * ps;
1564 else
1565 *offset0 = *offset1;
1566 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1567 (fieldmode ? 1 : 0), ps);
1568 *pix_inc = pixinc(screen_width, ps);
1569 break;
1570
1571 /* mirroring */
1572 case OMAP_DSS_ROT_0 + 4:
1573 *offset1 = (fbw - 1) * ps;
1574 if (field_offset)
1575 *offset0 = *offset1 + field_offset * screen_width * ps;
1576 else
1577 *offset0 = *offset1;
1578 *row_inc = pixinc(screen_width * 2 - 1 +
1579 (fieldmode ? screen_width : 0),
1580 ps);
1581 *pix_inc = pixinc(-1, ps);
1582 break;
1583
1584 case OMAP_DSS_ROT_90 + 4:
1585 *offset1 = 0;
1586 if (field_offset)
1587 *offset0 = *offset1 + field_offset * ps;
1588 else
1589 *offset0 = *offset1;
1590 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1591 (fieldmode ? 1 : 0),
1592 ps);
1593 *pix_inc = pixinc(screen_width, ps);
1594 break;
1595
1596 case OMAP_DSS_ROT_180 + 4:
1597 *offset1 = screen_width * (fbh - 1) * ps;
1598 if (field_offset)
1599 *offset0 = *offset1 - field_offset * screen_width * ps;
1600 else
1601 *offset0 = *offset1;
1602 *row_inc = pixinc(1 - screen_width * 2 -
1603 (fieldmode ? screen_width : 0),
1604 ps);
1605 *pix_inc = pixinc(1, ps);
1606 break;
1607
1608 case OMAP_DSS_ROT_270 + 4:
1609 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1610 if (field_offset)
1611 *offset0 = *offset1 - field_offset * ps;
1612 else
1613 *offset0 = *offset1;
1614 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1615 (fieldmode ? 1 : 0),
1616 ps);
1617 *pix_inc = pixinc(-screen_width, ps);
1618 break;
1619
1620 default:
1621 BUG();
1622 }
1623}
1624
ff1b2cde
SS		 1625static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1626 u16 height, u16 out_width, u16 out_height,
1627 enum omap_color_mode color_mode)
80c39712
TV		 1628{
1629 u32 fclk = 0;
1630 /* FIXME venc pclk? */
ff1b2cde 1631 u64 tmp, pclk = dispc_pclk_rate(channel);
80c39712
TV		 1632
1633 if (height > out_height) {
1634 /* FIXME get real display PPL */
1635 unsigned int ppl = 800;
1636
1637 tmp = pclk * height * out_width;
1638 do_div(tmp, 2 * out_height * ppl);
1639 fclk = tmp;
1640
2d9c5597
VS		 1641 if (height > 2 * out_height) {
1642 if (ppl == out_width)
1643 return 0;
1644
80c39712
TV		 1645 tmp = pclk * (height - 2 * out_height) * out_width;
1646 do_div(tmp, 2 * out_height * (ppl - out_width));
1647 fclk = max(fclk, (u32) tmp);
1648 }
1649 }
1650
1651 if (width > out_width) {
1652 tmp = pclk * width;
1653 do_div(tmp, out_width);
1654 fclk = max(fclk, (u32) tmp);
1655
1656 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1657 fclk <<= 1;
1658 }
1659
1660 return fclk;
1661}
1662
ff1b2cde
SS		 1663static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1664 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1665{
1666 unsigned int hf, vf;
1667
1668 /*
1669 * FIXME how to determine the 'A' factor
1670 * for the no downscaling case ?
1671 */
1672
1673 if (width > 3 * out_width)
1674 hf = 4;
1675 else if (width > 2 * out_width)
1676 hf = 3;
1677 else if (width > out_width)
1678 hf = 2;
1679 else
1680 hf = 1;
1681
1682 if (height > out_height)
1683 vf = 2;
1684 else
1685 vf = 1;
1686
1687 /* FIXME venc pclk? */
ff1b2cde 1688 return dispc_pclk_rate(channel) * vf * hf;
80c39712
TV		 1689}
1690
e6d80f95 1691int dispc_setup_plane(enum omap_plane plane,
80c39712
TV		 1692 u32 paddr, u16 screen_width,
1693 u16 pos_x, u16 pos_y,
1694 u16 width, u16 height,
1695 u16 out_width, u16 out_height,
1696 enum omap_color_mode color_mode,
1697 bool ilace,
1698 enum omap_dss_rotation_type rotation_type,
e6d80f95 1699 u8 rotation, bool mirror,
18faa1b6 1700 u8 global_alpha, u8 pre_mult_alpha,
0d66cbb5 1701 enum omap_channel channel, u32 puv_addr)
80c39712
TV		 1702{
1703 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1704 bool five_taps = 0;
1705 bool fieldmode = 0;
1706 int cconv = 0;
1707 unsigned offset0, offset1;
1708 s32 row_inc;
1709 s32 pix_inc;
1710 u16 frame_height = height;
1711 unsigned int field_offset = 0;
1712
e6d80f95
TV		 1713 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
1714 "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
1715 plane, paddr, screen_width, pos_x, pos_y,
1716 width, height,
1717 out_width, out_height,
1718 ilace, color_mode,
1719 rotation, mirror, channel);
1720
80c39712
TV		 1721 if (paddr == 0)
1722 return -EINVAL;
1723
1724 if (ilace && height == out_height)
1725 fieldmode = 1;
1726
1727 if (ilace) {
1728 if (fieldmode)
1729 height /= 2;
1730 pos_y /= 2;
1731 out_height /= 2;
1732
1733 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1734 "out_height %d\n",
1735 height, pos_y, out_height);
1736 }
1737
8dad2ab6
AT		 1738 if (!dss_feat_color_mode_supported(plane, color_mode))
1739 return -EINVAL;
1740
80c39712
TV		 1741 if (plane == OMAP_DSS_GFX) {
1742 if (width != out_width || height != out_height)
1743 return -EINVAL;
80c39712
TV		 1744 } else {
1745 /* video plane */
1746
1747 unsigned long fclk = 0;
1748
1749 if (out_width < width / maxdownscale ||
1750 out_width > width * 8)
1751 return -EINVAL;
1752
1753 if (out_height < height / maxdownscale ||
1754 out_height > height * 8)
1755 return -EINVAL;
1756
8dad2ab6 1757 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
0d66cbb5
AJ		 1758 color_mode == OMAP_DSS_COLOR_UYVY ||
1759 color_mode == OMAP_DSS_COLOR_NV12)
80c39712 1760 cconv = 1;
80c39712
TV		 1761
1762 /* Must use 5-tap filter? */
1763 five_taps = height > out_height * 2;
1764
1765 if (!five_taps) {
18faa1b6
SS		 1766 fclk = calc_fclk(channel, width, height, out_width,
1767 out_height);
80c39712
TV		 1768
1769 /* Try 5-tap filter if 3-tap fclk is too high */
1770 if (cpu_is_omap34xx() && height > out_height &&
1771 fclk > dispc_fclk_rate())
1772 five_taps = true;
1773 }
1774
1775 if (width > (2048 >> five_taps)) {
1776 DSSERR("failed to set up scaling, fclk too low\n");
1777 return -EINVAL;
1778 }
1779
1780 if (five_taps)
18faa1b6
SS		 1781 fclk = calc_fclk_five_taps(channel, width, height,
1782 out_width, out_height, color_mode);
80c39712
TV		 1783
1784 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1785 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1786
2d9c5597 1787 if (!fclk || fclk > dispc_fclk_rate()) {
80c39712
TV		 1788 DSSERR("failed to set up scaling, "
1789 "required fclk rate = %lu Hz, "
1790 "current fclk rate = %lu Hz\n",
1791 fclk, dispc_fclk_rate());
1792 return -EINVAL;
1793 }
1794 }
1795
1796 if (ilace && !fieldmode) {
1797 /*
1798 * when downscaling the bottom field may have to start several
1799 * source lines below the top field. Unfortunately ACCUI
1800 * registers will only hold the fractional part of the offset
1801 * so the integer part must be added to the base address of the
1802 * bottom field.
1803 */
1804 if (!height || height == out_height)
1805 field_offset = 0;
1806 else
1807 field_offset = height / out_height / 2;
1808 }
1809
1810 /* Fields are independent but interleaved in memory. */
1811 if (fieldmode)
1812 field_offset = 1;
1813
1814 if (rotation_type == OMAP_DSS_ROT_DMA)
1815 calc_dma_rotation_offset(rotation, mirror,
1816 screen_width, width, frame_height, color_mode,
1817 fieldmode, field_offset,
1818 &offset0, &offset1, &row_inc, &pix_inc);
1819 else
1820 calc_vrfb_rotation_offset(rotation, mirror,
1821 screen_width, width, frame_height, color_mode,
1822 fieldmode, field_offset,
1823 &offset0, &offset1, &row_inc, &pix_inc);
1824
1825 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1826 offset0, offset1, row_inc, pix_inc);
1827
1828 _dispc_set_color_mode(plane, color_mode);
1829
1830 _dispc_set_plane_ba0(plane, paddr + offset0);
1831 _dispc_set_plane_ba1(plane, paddr + offset1);
1832
0d66cbb5
AJ		 1833 if (OMAP_DSS_COLOR_NV12 == color_mode) {
1834 _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
1835 _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
1836 }
1837
1838
80c39712
TV		 1839 _dispc_set_row_inc(plane, row_inc);
1840 _dispc_set_pix_inc(plane, pix_inc);
1841
1842 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1843 out_width, out_height);
1844
1845 _dispc_set_plane_pos(plane, pos_x, pos_y);
1846
1847 _dispc_set_pic_size(plane, width, height);
1848
1849 if (plane != OMAP_DSS_GFX) {
1850 _dispc_set_scaling(plane, width, height,
1851 out_width, out_height,
0d66cbb5
AJ		 1852 ilace, five_taps, fieldmode,
1853 color_mode, rotation);
80c39712
TV		 1854 _dispc_set_vid_size(plane, out_width, out_height);
1855 _dispc_set_vid_color_conv(plane, cconv);
1856 }
1857
1858 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1859
fd28a390
R		 1860 _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1861 _dispc_setup_global_alpha(plane, global_alpha);
80c39712
TV		 1862
1863 return 0;
1864}
1865
e6d80f95 1866int dispc_enable_plane(enum omap_plane plane, bool enable)
80c39712 1867{
e6d80f95
TV		 1868 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1869
9b372c2d 1870 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 1871
1872 return 0;
80c39712
TV		 1873}
1874
1875static void dispc_disable_isr(void *data, u32 mask)
1876{
1877 struct completion *compl = data;
1878 complete(compl);
1879}
1880
2a205f34 1881static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 1882{
2a205f34
SS		 1883 if (channel == OMAP_DSS_CHANNEL_LCD2)
1884 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1885 else
1886 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
80c39712
TV		 1887}
1888
2a205f34 1889static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 1890{
1891 struct completion frame_done_completion;
1892 bool is_on;
1893 int r;
2a205f34 1894 u32 irq;
80c39712 1895
80c39712
TV		 1896 /* When we disable LCD output, we need to wait until frame is done.
1897 * Otherwise the DSS is still working, and turning off the clocks
1898 * prevents DSS from going to OFF mode */
2a205f34
SS		 1899 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1900 REG_GET(DISPC_CONTROL2, 0, 0) :
1901 REG_GET(DISPC_CONTROL, 0, 0);
1902
1903 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1904 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 1905
1906 if (!enable && is_on) {
1907 init_completion(&frame_done_completion);
1908
1909 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 1910 &frame_done_completion, irq);
80c39712
TV		 1911
1912 if (r)
1913 DSSERR("failed to register FRAMEDONE isr\n");
1914 }
1915
2a205f34 1916 _enable_lcd_out(channel, enable);
80c39712
TV		 1917
1918 if (!enable && is_on) {
1919 if (!wait_for_completion_timeout(&frame_done_completion,
1920 msecs_to_jiffies(100)))
1921 DSSERR("timeout waiting for FRAME DONE\n");
1922
1923 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 1924 &frame_done_completion, irq);
80c39712
TV		 1925
1926 if (r)
1927 DSSERR("failed to unregister FRAMEDONE isr\n");
1928 }
80c39712
TV		 1929}
1930
1931static void _enable_digit_out(bool enable)
1932{
1933 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1934}
1935
a2faee84 1936static void dispc_enable_digit_out(bool enable)
80c39712
TV		 1937{
1938 struct completion frame_done_completion;
1939 int r;
1940
e6d80f95 1941 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 1942 return;
80c39712
TV		 1943
1944 if (enable) {
1945 unsigned long flags;
1946 /* When we enable digit output, we'll get an extra digit
1947 * sync lost interrupt, that we need to ignore */
1948 spin_lock_irqsave(&dispc.irq_lock, flags);
1949 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1950 _omap_dispc_set_irqs();
1951 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1952 }
1953
1954 /* When we disable digit output, we need to wait until fields are done.
1955 * Otherwise the DSS is still working, and turning off the clocks
1956 * prevents DSS from going to OFF mode. And when enabling, we need to
1957 * wait for the extra sync losts */
1958 init_completion(&frame_done_completion);
1959
1960 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1961 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1962 if (r)
1963 DSSERR("failed to register EVSYNC isr\n");
1964
1965 _enable_digit_out(enable);
1966
1967 /* XXX I understand from TRM that we should only wait for the
1968 * current field to complete. But it seems we have to wait
1969 * for both fields */
1970 if (!wait_for_completion_timeout(&frame_done_completion,
1971 msecs_to_jiffies(100)))
1972 DSSERR("timeout waiting for EVSYNC\n");
1973
1974 if (!wait_for_completion_timeout(&frame_done_completion,
1975 msecs_to_jiffies(100)))
1976 DSSERR("timeout waiting for EVSYNC\n");
1977
1978 r = omap_dispc_unregister_isr(dispc_disable_isr,
1979 &frame_done_completion,
1980 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1981 if (r)
1982 DSSERR("failed to unregister EVSYNC isr\n");
1983
1984 if (enable) {
1985 unsigned long flags;
1986 spin_lock_irqsave(&dispc.irq_lock, flags);
1987 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 1988 if (dss_has_feature(FEAT_MGR_LCD2))
1989 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 1990 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1991 _omap_dispc_set_irqs();
1992 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1993 }
80c39712
TV		 1994}
1995
a2faee84
TV		 1996bool dispc_is_channel_enabled(enum omap_channel channel)
1997{
1998 if (channel == OMAP_DSS_CHANNEL_LCD)
1999 return !!REG_GET(DISPC_CONTROL, 0, 0);
2000 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2001 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2002 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2003 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2004 else
2005 BUG();
2006}
2007
2008void dispc_enable_channel(enum omap_channel channel, bool enable)
2009{
2a205f34
SS		 2010 if (channel == OMAP_DSS_CHANNEL_LCD ||
2011 channel == OMAP_DSS_CHANNEL_LCD2)
2012 dispc_enable_lcd_out(channel, enable);
a2faee84
TV		 2013 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2014 dispc_enable_digit_out(enable);
2015 else
2016 BUG();
2017}
2018
80c39712
TV		 2019void dispc_lcd_enable_signal_polarity(bool act_high)
2020{
6ced40bf
AT		 2021 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2022 return;
2023
80c39712 2024 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2025}
2026
2027void dispc_lcd_enable_signal(bool enable)
2028{
6ced40bf
AT		 2029 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2030 return;
2031
80c39712 2032 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2033}
2034
2035void dispc_pck_free_enable(bool enable)
2036{
6ced40bf
AT		 2037 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2038 return;
2039
80c39712 2040 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2041}
2042
64ba4f74 2043void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2044{
2a205f34
SS		 2045 if (channel == OMAP_DSS_CHANNEL_LCD2)
2046 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2047 else
2048 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2049}
2050
2051
64ba4f74
SS		 2052void dispc_set_lcd_display_type(enum omap_channel channel,
2053 enum omap_lcd_display_type type)
80c39712
TV		 2054{
2055 int mode;
2056
2057 switch (type) {
2058 case OMAP_DSS_LCD_DISPLAY_STN:
2059 mode = 0;
2060 break;
2061
2062 case OMAP_DSS_LCD_DISPLAY_TFT:
2063 mode = 1;
2064 break;
2065
2066 default:
2067 BUG();
2068 return;
2069 }
2070
2a205f34
SS		 2071 if (channel == OMAP_DSS_CHANNEL_LCD2)
2072 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2073 else
2074 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2075}
2076
2077void dispc_set_loadmode(enum omap_dss_load_mode mode)
2078{
80c39712 2079 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2080}
2081
2082
2083void dispc_set_default_color(enum omap_channel channel, u32 color)
2084{
8613b000 2085 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2086}
2087
2088u32 dispc_get_default_color(enum omap_channel channel)
2089{
80c39712
TV		 2090 u32 l;
2091
2092 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2a205f34
SS		 2093 channel != OMAP_DSS_CHANNEL_LCD &&
2094 channel != OMAP_DSS_CHANNEL_LCD2);
80c39712 2095
8613b000 2096 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
80c39712
TV		 2097
2098 return l;
2099}
2100
2101void dispc_set_trans_key(enum omap_channel ch,
2102 enum omap_dss_trans_key_type type,
2103 u32 trans_key)
2104{
80c39712
TV		 2105 if (ch == OMAP_DSS_CHANNEL_LCD)
2106 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2107 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2108 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2109 else /* OMAP_DSS_CHANNEL_LCD2 */
2110 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2111
8613b000 2112 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2113}
2114
2115void dispc_get_trans_key(enum omap_channel ch,
2116 enum omap_dss_trans_key_type *type,
2117 u32 *trans_key)
2118{
80c39712
TV		 2119 if (type) {
2120 if (ch == OMAP_DSS_CHANNEL_LCD)
2121 *type = REG_GET(DISPC_CONFIG, 11, 11);
2122 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2123 *type = REG_GET(DISPC_CONFIG, 13, 13);
2a205f34
SS		 2124 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2125 *type = REG_GET(DISPC_CONFIG2, 11, 11);
80c39712
TV		 2126 else
2127 BUG();
2128 }
2129
2130 if (trans_key)
8613b000 2131 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
80c39712
TV		 2132}
2133
2134void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2135{
80c39712
TV		 2136 if (ch == OMAP_DSS_CHANNEL_LCD)
2137 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2138 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2139 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2140 else /* OMAP_DSS_CHANNEL_LCD2 */
2141 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712
TV		 2142}
2143void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2144{
a0acb557 2145 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2146 return;
2147
80c39712
TV		 2148 if (ch == OMAP_DSS_CHANNEL_LCD)
2149 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2150 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2151 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2a205f34
SS		 2152 else /* OMAP_DSS_CHANNEL_LCD2 */
2153 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
80c39712
TV		 2154}
2155bool dispc_alpha_blending_enabled(enum omap_channel ch)
2156{
2157 bool enabled;
2158
a0acb557 2159 if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
80c39712
TV		 2160 return false;
2161
80c39712
TV		 2162 if (ch == OMAP_DSS_CHANNEL_LCD)
2163 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2164 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
712247a6 2165 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2a205f34
SS		 2166 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2167 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
80c39712
TV		 2168 else
2169 BUG();
80c39712
TV		 2170
2171 return enabled;
80c39712
TV		 2172}
2173
2174
2175bool dispc_trans_key_enabled(enum omap_channel ch)
2176{
2177 bool enabled;
2178
80c39712
TV		 2179 if (ch == OMAP_DSS_CHANNEL_LCD)
2180 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2181 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2182 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2a205f34
SS		 2183 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2184 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
80c39712
TV		 2185 else
2186 BUG();
80c39712
TV		 2187
2188 return enabled;
2189}
2190
2191
64ba4f74 2192void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2193{
2194 int code;
2195
2196 switch (data_lines) {
2197 case 12:
2198 code = 0;
2199 break;
2200 case 16:
2201 code = 1;
2202 break;
2203 case 18:
2204 code = 2;
2205 break;
2206 case 24:
2207 code = 3;
2208 break;
2209 default:
2210 BUG();
2211 return;
2212 }
2213
2a205f34
SS		 2214 if (channel == OMAP_DSS_CHANNEL_LCD2)
2215 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2216 else
2217 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2218}
2219
64ba4f74
SS		 2220void dispc_set_parallel_interface_mode(enum omap_channel channel,
2221 enum omap_parallel_interface_mode mode)
80c39712
TV		 2222{
2223 u32 l;
2224 int stallmode;
2225 int gpout0 = 1;
2226 int gpout1;
2227
2228 switch (mode) {
2229 case OMAP_DSS_PARALLELMODE_BYPASS:
2230 stallmode = 0;
2231 gpout1 = 1;
2232 break;
2233
2234 case OMAP_DSS_PARALLELMODE_RFBI:
2235 stallmode = 1;
2236 gpout1 = 0;
2237 break;
2238
2239 case OMAP_DSS_PARALLELMODE_DSI:
2240 stallmode = 1;
2241 gpout1 = 1;
2242 break;
2243
2244 default:
2245 BUG();
2246 return;
2247 }
2248
2a205f34
SS		 2249 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2250 l = dispc_read_reg(DISPC_CONTROL2);
2251 l = FLD_MOD(l, stallmode, 11, 11);
2252 dispc_write_reg(DISPC_CONTROL2, l);
2253 } else {
2254 l = dispc_read_reg(DISPC_CONTROL);
2255 l = FLD_MOD(l, stallmode, 11, 11);
64ba4f74
SS		 2256 l = FLD_MOD(l, gpout0, 15, 15);
2257 l = FLD_MOD(l, gpout1, 16, 16);
2a205f34 2258 dispc_write_reg(DISPC_CONTROL, l);
64ba4f74 2259 }
80c39712
TV		 2260}
2261
2262static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2263 int vsw, int vfp, int vbp)
2264{
2265 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2266 if (hsw < 1 || hsw > 64 ||
2267 hfp < 1 || hfp > 256 ||
2268 hbp < 1 || hbp > 256 ||
2269 vsw < 1 || vsw > 64 ||
2270 vfp < 0 || vfp > 255 ||
2271 vbp < 0 || vbp > 255)
2272 return false;
2273 } else {
2274 if (hsw < 1 || hsw > 256 ||
2275 hfp < 1 || hfp > 4096 ||
2276 hbp < 1 || hbp > 4096 ||
2277 vsw < 1 || vsw > 256 ||
2278 vfp < 0 || vfp > 4095 ||
2279 vbp < 0 || vbp > 4095)
2280 return false;
2281 }
2282
2283 return true;
2284}
2285
2286bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2287{
2288 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2289 timings->hbp, timings->vsw,
2290 timings->vfp, timings->vbp);
2291}
2292
64ba4f74
SS		 2293static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2294 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2295{
2296 u32 timing_h, timing_v;
2297
2298 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2299 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2300 FLD_VAL(hbp-1, 27, 20);
2301
2302 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2303 FLD_VAL(vbp, 27, 20);
2304 } else {
2305 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2306 FLD_VAL(hbp-1, 31, 20);
2307
2308 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2309 FLD_VAL(vbp, 31, 20);
2310 }
2311
64ba4f74
SS		 2312 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2313 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2314}
2315
2316/* change name to mode? */
64ba4f74
SS		 2317void dispc_set_lcd_timings(enum omap_channel channel,
2318 struct omap_video_timings *timings)
80c39712
TV		 2319{
2320 unsigned xtot, ytot;
2321 unsigned long ht, vt;
2322
2323 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2324 timings->hbp, timings->vsw,
2325 timings->vfp, timings->vbp))
2326 BUG();
2327
64ba4f74
SS		 2328 _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2329 timings->hbp, timings->vsw, timings->vfp,
2330 timings->vbp);
80c39712 2331
64ba4f74 2332 dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2333
2334 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2335 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2336
2337 ht = (timings->pixel_clock * 1000) / xtot;
2338 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2339
2a205f34
SS		 2340 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2341 timings->y_res);
80c39712
TV		 2342 DSSDBG("pck %u\n", timings->pixel_clock);
2343 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2344 timings->hsw, timings->hfp, timings->hbp,
2345 timings->vsw, timings->vfp, timings->vbp);
2346
2347 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2348}
2349
ff1b2cde
SS		 2350static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2351 u16 pck_div)
80c39712
TV		 2352{
2353 BUG_ON(lck_div < 1);
2354 BUG_ON(pck_div < 2);
2355
ce7fa5eb 2356 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2357 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2358}
2359
2a205f34
SS		 2360static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2361 int *pck_div)
80c39712
TV		 2362{
2363 u32 l;
ce7fa5eb 2364 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2365 *lck_div = FLD_GET(l, 23, 16);
2366 *pck_div = FLD_GET(l, 7, 0);
2367}
2368
2369unsigned long dispc_fclk_rate(void)
2370{
a72b64b9 2371 struct platform_device *dsidev;
80c39712
TV		 2372 unsigned long r = 0;
2373
66534e8e 2374 switch (dss_get_dispc_clk_source()) {
89a35e51 2375 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2376 r = clk_get_rate(dispc.dss_clk);
66534e8e 2377 break;
89a35e51 2378 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2379 dsidev = dsi_get_dsidev_from_id(0);
2380 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2381 break;
5a8b572d
AT		 2382 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2383 dsidev = dsi_get_dsidev_from_id(1);
2384 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2385 break;
66534e8e
TA		 2386 default:
2387 BUG();
2388 }
2389
80c39712
TV		 2390 return r;
2391}
2392
ff1b2cde 2393unsigned long dispc_lclk_rate(enum omap_channel channel)
80c39712 2394{
a72b64b9 2395 struct platform_device *dsidev;
80c39712
TV		 2396 int lcd;
2397 unsigned long r;
2398 u32 l;
2399
ce7fa5eb 2400 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2401
2402 lcd = FLD_GET(l, 23, 16);
2403
ea75159e 2404 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2405 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2406 r = clk_get_rate(dispc.dss_clk);
ea75159e 2407 break;
89a35e51 2408 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2409 dsidev = dsi_get_dsidev_from_id(0);
2410 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2411 break;
5a8b572d
AT		 2412 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2413 dsidev = dsi_get_dsidev_from_id(1);
2414 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2415 break;
ea75159e
TA		 2416 default:
2417 BUG();
2418 }
80c39712
TV		 2419
2420 return r / lcd;
2421}
2422
ff1b2cde 2423unsigned long dispc_pclk_rate(enum omap_channel channel)
80c39712 2424{
ea75159e 2425 int pcd;
80c39712
TV		 2426 unsigned long r;
2427 u32 l;
2428
ce7fa5eb 2429 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2430
80c39712
TV		 2431 pcd = FLD_GET(l, 7, 0);
2432
ea75159e 2433 r = dispc_lclk_rate(channel);
80c39712 2434
ea75159e 2435 return r / pcd;
80c39712
TV		 2436}
2437
2438void dispc_dump_clocks(struct seq_file *s)
2439{
2440 int lcd, pcd;
0cf35df3 2441 u32 l;
89a35e51
AT		 2442 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2443 enum omap_dss_clk_source lcd_clk_src;
80c39712 2444
4fbafaf3
TV		 2445 if (dispc_runtime_get())
2446 return;
80c39712 2447
80c39712
TV		 2448 seq_printf(s, "- DISPC -\n");
2449
067a57e4
AT		 2450 seq_printf(s, "dispc fclk source = %s (%s)\n",
2451 dss_get_generic_clk_source_name(dispc_clk_src),
2452 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2453
2454 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2455
0cf35df3
MR		 2456 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2457 seq_printf(s, "- DISPC-CORE-CLK -\n");
2458 l = dispc_read_reg(DISPC_DIVISOR);
2459 lcd = FLD_GET(l, 23, 16);
2460
2461 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2462 (dispc_fclk_rate()/lcd), lcd);
2463 }
2a205f34
SS		 2464 seq_printf(s, "- LCD1 -\n");
2465
ea75159e
TA		 2466 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2467
2468 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2469 dss_get_generic_clk_source_name(lcd_clk_src),
2470 dss_feat_get_clk_source_name(lcd_clk_src));
2471
2a205f34
SS		 2472 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2473
ff1b2cde
SS		 2474 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2475 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2476 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2477 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2478 if (dss_has_feature(FEAT_MGR_LCD2)) {
2479 seq_printf(s, "- LCD2 -\n");
2480
ea75159e
TA		 2481 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2482
2483 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2484 dss_get_generic_clk_source_name(lcd_clk_src),
2485 dss_feat_get_clk_source_name(lcd_clk_src));
2486
2a205f34 2487 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2488
2a205f34
SS		 2489 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2490 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2491 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2492 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2493 }
4fbafaf3
TV		 2494
2495 dispc_runtime_put();
80c39712
TV		 2496}
2497
dfc0fd8d
TV		 2498#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2499void dispc_dump_irqs(struct seq_file *s)
2500{
2501 unsigned long flags;
2502 struct dispc_irq_stats stats;
2503
2504 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2505
2506 stats = dispc.irq_stats;
2507 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2508 dispc.irq_stats.last_reset = jiffies;
2509
2510 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2511
2512 seq_printf(s, "period %u ms\n",
2513 jiffies_to_msecs(jiffies - stats.last_reset));
2514
2515 seq_printf(s, "irqs %d\n", stats.irq_count);
2516#define PIS(x) \
2517 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2518
2519 PIS(FRAMEDONE);
2520 PIS(VSYNC);
2521 PIS(EVSYNC_EVEN);
2522 PIS(EVSYNC_ODD);
2523 PIS(ACBIAS_COUNT_STAT);
2524 PIS(PROG_LINE_NUM);
2525 PIS(GFX_FIFO_UNDERFLOW);
2526 PIS(GFX_END_WIN);
2527 PIS(PAL_GAMMA_MASK);
2528 PIS(OCP_ERR);
2529 PIS(VID1_FIFO_UNDERFLOW);
2530 PIS(VID1_END_WIN);
2531 PIS(VID2_FIFO_UNDERFLOW);
2532 PIS(VID2_END_WIN);
2533 PIS(SYNC_LOST);
2534 PIS(SYNC_LOST_DIGIT);
2535 PIS(WAKEUP);
2a205f34
SS		 2536 if (dss_has_feature(FEAT_MGR_LCD2)) {
2537 PIS(FRAMEDONE2);
2538 PIS(VSYNC2);
2539 PIS(ACBIAS_COUNT_STAT2);
2540 PIS(SYNC_LOST2);
2541 }
dfc0fd8d
TV		 2542#undef PIS
2543}
dfc0fd8d
TV		 2544#endif
2545
80c39712
TV		 2546void dispc_dump_regs(struct seq_file *s)
2547{
4dd2da15
AT		 2548 int i, j;
2549 const char *mgr_names[] = {
2550 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2551 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2552 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2553 };
2554 const char *ovl_names[] = {
2555 [OMAP_DSS_GFX] = "GFX",
2556 [OMAP_DSS_VIDEO1] = "VID1",
2557 [OMAP_DSS_VIDEO2] = "VID2",
2558 };
2559 const char **p_names;
2560
9b372c2d 2561#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2562
4fbafaf3
TV		 2563 if (dispc_runtime_get())
2564 return;
80c39712 2565
5010be80 2566 /* DISPC common registers */
80c39712
TV		 2567 DUMPREG(DISPC_REVISION);
2568 DUMPREG(DISPC_SYSCONFIG);
2569 DUMPREG(DISPC_SYSSTATUS);
2570 DUMPREG(DISPC_IRQSTATUS);
2571 DUMPREG(DISPC_IRQENABLE);
2572 DUMPREG(DISPC_CONTROL);
2573 DUMPREG(DISPC_CONFIG);
2574 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2575 DUMPREG(DISPC_LINE_STATUS);
2576 DUMPREG(DISPC_LINE_NUMBER);
332e9d70
TV		 2577 if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2578 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2579 if (dss_has_feature(FEAT_MGR_LCD2)) {
2580 DUMPREG(DISPC_CONTROL2);
2581 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2582 }
2583
2584#undef DUMPREG
2585
2586#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2587#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2588 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2589 dispc_read_reg(DISPC_REG(i, r)))
2590
4dd2da15 2591 p_names = mgr_names;
5010be80 2592
4dd2da15
AT		 2593 /* DISPC channel specific registers */
2594 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2595 DUMPREG(i, DISPC_DEFAULT_COLOR);
2596 DUMPREG(i, DISPC_TRANS_COLOR);
2597 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2598
4dd2da15
AT		 2599 if (i == OMAP_DSS_CHANNEL_DIGIT)
2600 continue;
5010be80 2601
4dd2da15
AT		 2602 DUMPREG(i, DISPC_DEFAULT_COLOR);
2603 DUMPREG(i, DISPC_TRANS_COLOR);
2604 DUMPREG(i, DISPC_TIMING_H);
2605 DUMPREG(i, DISPC_TIMING_V);
2606 DUMPREG(i, DISPC_POL_FREQ);
2607 DUMPREG(i, DISPC_DIVISORo);
2608 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2609
4dd2da15
AT		 2610 DUMPREG(i, DISPC_DATA_CYCLE1);
2611 DUMPREG(i, DISPC_DATA_CYCLE2);
2612 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2613
332e9d70 2614 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2615 DUMPREG(i, DISPC_CPR_COEF_R);
2616 DUMPREG(i, DISPC_CPR_COEF_G);
2617 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2618 }
2a205f34 2619 }
80c39712 2620
4dd2da15
AT		 2621 p_names = ovl_names;
2622
2623 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2624 DUMPREG(i, DISPC_OVL_BA0);
2625 DUMPREG(i, DISPC_OVL_BA1);
2626 DUMPREG(i, DISPC_OVL_POSITION);
2627 DUMPREG(i, DISPC_OVL_SIZE);
2628 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2629 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2630 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2631 DUMPREG(i, DISPC_OVL_ROW_INC);
2632 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2633 if (dss_has_feature(FEAT_PRELOAD))
2634 DUMPREG(i, DISPC_OVL_PRELOAD);
2635
2636 if (i == OMAP_DSS_GFX) {
2637 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2638 DUMPREG(i, DISPC_OVL_TABLE_BA);
2639 continue;
2640 }
2641
2642 DUMPREG(i, DISPC_OVL_FIR);
2643 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2644 DUMPREG(i, DISPC_OVL_ACCU0);
2645 DUMPREG(i, DISPC_OVL_ACCU1);
2646 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2647 DUMPREG(i, DISPC_OVL_BA0_UV);
2648 DUMPREG(i, DISPC_OVL_BA1_UV);
2649 DUMPREG(i, DISPC_OVL_FIR2);
2650 DUMPREG(i, DISPC_OVL_ACCU2_0);
2651 DUMPREG(i, DISPC_OVL_ACCU2_1);
2652 }
2653 if (dss_has_feature(FEAT_ATTR2))
2654 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2655 if (dss_has_feature(FEAT_PRELOAD))
2656 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2657 }
5010be80
AT		 2658
2659#undef DISPC_REG
2660#undef DUMPREG
2661
2662#define DISPC_REG(plane, name, i) name(plane, i)
2663#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2664 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2665 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2666 dispc_read_reg(DISPC_REG(plane, name, i)))
2667
4dd2da15 2668 /* Video pipeline coefficient registers */
332e9d70 2669
4dd2da15
AT		 2670 /* start from OMAP_DSS_VIDEO1 */
2671 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2672 for (j = 0; j < 8; j++)
2673 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2674
4dd2da15
AT		 2675 for (j = 0; j < 8; j++)
2676 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2677
4dd2da15
AT		 2678 for (j = 0; j < 5; j++)
2679 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2680
4dd2da15
AT		 2681 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2682 for (j = 0; j < 8; j++)
2683 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2684 }
2685
2686 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2687 for (j = 0; j < 8; j++)
2688 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2689
2690 for (j = 0; j < 8; j++)
2691 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2692
2693 for (j = 0; j < 8; j++)
2694 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2695 }
332e9d70 2696 }
80c39712 2697
4fbafaf3 2698 dispc_runtime_put();
5010be80
AT		 2699
2700#undef DISPC_REG
80c39712
TV		 2701#undef DUMPREG
2702}
2703
ff1b2cde
SS		 2704static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2705 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
80c39712
TV		 2706{
2707 u32 l = 0;
2708
2709 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2710 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2711
2712 l |= FLD_VAL(onoff, 17, 17);
2713 l |= FLD_VAL(rf, 16, 16);
2714 l |= FLD_VAL(ieo, 15, 15);
2715 l |= FLD_VAL(ipc, 14, 14);
2716 l |= FLD_VAL(ihs, 13, 13);
2717 l |= FLD_VAL(ivs, 12, 12);
2718 l |= FLD_VAL(acbi, 11, 8);
2719 l |= FLD_VAL(acb, 7, 0);
2720
ff1b2cde 2721 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2722}
2723
ff1b2cde
SS		 2724void dispc_set_pol_freq(enum omap_channel channel,
2725 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2726{
ff1b2cde 2727 _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2728 (config & OMAP_DSS_LCD_RF) != 0,
2729 (config & OMAP_DSS_LCD_IEO) != 0,
2730 (config & OMAP_DSS_LCD_IPC) != 0,
2731 (config & OMAP_DSS_LCD_IHS) != 0,
2732 (config & OMAP_DSS_LCD_IVS) != 0,
2733 acbi, acb);
2734}
2735
2736/* with fck as input clock rate, find dispc dividers that produce req_pck */
2737void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2738 struct dispc_clock_info *cinfo)
2739{
2740 u16 pcd_min = is_tft ? 2 : 3;
2741 unsigned long best_pck;
2742 u16 best_ld, cur_ld;
2743 u16 best_pd, cur_pd;
2744
2745 best_pck = 0;
2746 best_ld = 0;
2747 best_pd = 0;
2748
2749 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2750 unsigned long lck = fck / cur_ld;
2751
2752 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2753 unsigned long pck = lck / cur_pd;
2754 long old_delta = abs(best_pck - req_pck);
2755 long new_delta = abs(pck - req_pck);
2756
2757 if (best_pck == 0 || new_delta < old_delta) {
2758 best_pck = pck;
2759 best_ld = cur_ld;
2760 best_pd = cur_pd;
2761
2762 if (pck == req_pck)
2763 goto found;
2764 }
2765
2766 if (pck < req_pck)
2767 break;
2768 }
2769
2770 if (lck / pcd_min < req_pck)
2771 break;
2772 }
2773
2774found:
2775 cinfo->lck_div = best_ld;
2776 cinfo->pck_div = best_pd;
2777 cinfo->lck = fck / cinfo->lck_div;
2778 cinfo->pck = cinfo->lck / cinfo->pck_div;
2779}
2780
2781/* calculate clock rates using dividers in cinfo */
2782int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2783 struct dispc_clock_info *cinfo)
2784{
2785 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2786 return -EINVAL;
2787 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2788 return -EINVAL;
2789
2790 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2791 cinfo->pck = cinfo->lck / cinfo->pck_div;
2792
2793 return 0;
2794}
2795
ff1b2cde
SS		 2796int dispc_set_clock_div(enum omap_channel channel,
2797 struct dispc_clock_info *cinfo)
80c39712
TV		 2798{
2799 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2800 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2801
ff1b2cde 2802 dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 2803
2804 return 0;
2805}
2806
ff1b2cde
SS		 2807int dispc_get_clock_div(enum omap_channel channel,
2808 struct dispc_clock_info *cinfo)
80c39712
TV		 2809{
2810 unsigned long fck;
2811
2812 fck = dispc_fclk_rate();
2813
ce7fa5eb
MR		 2814 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2815 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 2816
2817 cinfo->lck = fck / cinfo->lck_div;
2818 cinfo->pck = cinfo->lck / cinfo->pck_div;
2819
2820 return 0;
2821}
2822
2823/* dispc.irq_lock has to be locked by the caller */
2824static void _omap_dispc_set_irqs(void)
2825{
2826 u32 mask;
2827 u32 old_mask;
2828 int i;
2829 struct omap_dispc_isr_data *isr_data;
2830
2831 mask = dispc.irq_error_mask;
2832
2833 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2834 isr_data = &dispc.registered_isr[i];
2835
2836 if (isr_data->isr == NULL)
2837 continue;
2838
2839 mask |= isr_data->mask;
2840 }
2841
80c39712
TV		 2842 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2843 /* clear the irqstatus for newly enabled irqs */
2844 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2845
2846 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 2847}
2848
2849int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2850{
2851 int i;
2852 int ret;
2853 unsigned long flags;
2854 struct omap_dispc_isr_data *isr_data;
2855
2856 if (isr == NULL)
2857 return -EINVAL;
2858
2859 spin_lock_irqsave(&dispc.irq_lock, flags);
2860
2861 /* check for duplicate entry */
2862 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2863 isr_data = &dispc.registered_isr[i];
2864 if (isr_data->isr == isr && isr_data->arg == arg &&
2865 isr_data->mask == mask) {
2866 ret = -EINVAL;
2867 goto err;
2868 }
2869 }
2870
2871 isr_data = NULL;
2872 ret = -EBUSY;
2873
2874 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2875 isr_data = &dispc.registered_isr[i];
2876
2877 if (isr_data->isr != NULL)
2878 continue;
2879
2880 isr_data->isr = isr;
2881 isr_data->arg = arg;
2882 isr_data->mask = mask;
2883 ret = 0;
2884
2885 break;
2886 }
2887
b9cb0984
TV		 2888 if (ret)
2889 goto err;
2890
80c39712
TV		 2891 _omap_dispc_set_irqs();
2892
2893 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2894
2895 return 0;
2896err:
2897 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2898
2899 return ret;
2900}
2901EXPORT_SYMBOL(omap_dispc_register_isr);
2902
2903int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2904{
2905 int i;
2906 unsigned long flags;
2907 int ret = -EINVAL;
2908 struct omap_dispc_isr_data *isr_data;
2909
2910 spin_lock_irqsave(&dispc.irq_lock, flags);
2911
2912 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2913 isr_data = &dispc.registered_isr[i];
2914 if (isr_data->isr != isr || isr_data->arg != arg ||
2915 isr_data->mask != mask)
2916 continue;
2917
2918 /* found the correct isr */
2919
2920 isr_data->isr = NULL;
2921 isr_data->arg = NULL;
2922 isr_data->mask = 0;
2923
2924 ret = 0;
2925 break;
2926 }
2927
2928 if (ret == 0)
2929 _omap_dispc_set_irqs();
2930
2931 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2932
2933 return ret;
2934}
2935EXPORT_SYMBOL(omap_dispc_unregister_isr);
2936
2937#ifdef DEBUG
2938static void print_irq_status(u32 status)
2939{
2940 if ((status & dispc.irq_error_mask) == 0)
2941 return;
2942
2943 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2944
2945#define PIS(x) \
2946 if (status & DISPC_IRQ_##x) \
2947 printk(#x " ");
2948 PIS(GFX_FIFO_UNDERFLOW);
2949 PIS(OCP_ERR);
2950 PIS(VID1_FIFO_UNDERFLOW);
2951 PIS(VID2_FIFO_UNDERFLOW);
2952 PIS(SYNC_LOST);
2953 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 2954 if (dss_has_feature(FEAT_MGR_LCD2))
2955 PIS(SYNC_LOST2);
80c39712
TV		 2956#undef PIS
2957
2958 printk("\n");
2959}
2960#endif
2961
2962/* Called from dss.c. Note that we don't touch clocks here,
2963 * but we presume they are on because we got an IRQ. However,
2964 * an irq handler may turn the clocks off, so we may not have
2965 * clock later in the function. */
affe360d 2966static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 2967{
2968 int i;
affe360d 2969 u32 irqstatus, irqenable;
80c39712
TV		 2970 u32 handledirqs = 0;
2971 u32 unhandled_errors;
2972 struct omap_dispc_isr_data *isr_data;
2973 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2974
2975 spin_lock(&dispc.irq_lock);
2976
2977 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 2978 irqenable = dispc_read_reg(DISPC_IRQENABLE);
2979
2980 /* IRQ is not for us */
2981 if (!(irqstatus & irqenable)) {
2982 spin_unlock(&dispc.irq_lock);
2983 return IRQ_NONE;
2984 }
80c39712 2985
dfc0fd8d
TV		 2986#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2987 spin_lock(&dispc.irq_stats_lock);
2988 dispc.irq_stats.irq_count++;
2989 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2990 spin_unlock(&dispc.irq_stats_lock);
2991#endif
2992
80c39712
TV		 2993#ifdef DEBUG
2994 if (dss_debug)
2995 print_irq_status(irqstatus);
2996#endif
2997 /* Ack the interrupt. Do it here before clocks are possibly turned
2998 * off */
2999 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3000 /* flush posted write */
3001 dispc_read_reg(DISPC_IRQSTATUS);
3002
3003 /* make a copy and unlock, so that isrs can unregister
3004 * themselves */
3005 memcpy(registered_isr, dispc.registered_isr,
3006 sizeof(registered_isr));
3007
3008 spin_unlock(&dispc.irq_lock);
3009
3010 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3011 isr_data = &registered_isr[i];
3012
3013 if (!isr_data->isr)
3014 continue;
3015
3016 if (isr_data->mask & irqstatus) {
3017 isr_data->isr(isr_data->arg, irqstatus);
3018 handledirqs |= isr_data->mask;
3019 }
3020 }
3021
3022 spin_lock(&dispc.irq_lock);
3023
3024 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3025
3026 if (unhandled_errors) {
3027 dispc.error_irqs |= unhandled_errors;
3028
3029 dispc.irq_error_mask &= ~unhandled_errors;
3030 _omap_dispc_set_irqs();
3031
3032 schedule_work(&dispc.error_work);
3033 }
3034
3035 spin_unlock(&dispc.irq_lock);
affe360d 3036
3037 return IRQ_HANDLED;
80c39712
TV		 3038}
3039
3040static void dispc_error_worker(struct work_struct *work)
3041{
3042 int i;
3043 u32 errors;
3044 unsigned long flags;
3045
3046 spin_lock_irqsave(&dispc.irq_lock, flags);
3047 errors = dispc.error_irqs;
3048 dispc.error_irqs = 0;
3049 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3050
13eae1f9
DZ		 3051 dispc_runtime_get();
3052
80c39712
TV		 3053 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
3054 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
3055 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3056 struct omap_overlay *ovl;
3057 ovl = omap_dss_get_overlay(i);
3058
3059 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3060 continue;
3061
3062 if (ovl->id == 0) {
3063 dispc_enable_plane(ovl->id, 0);
3064 dispc_go(ovl->manager->id);
3065 mdelay(50);
3066 break;
3067 }
3068 }
3069 }
3070
3071 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3072 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3073 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3074 struct omap_overlay *ovl;
3075 ovl = omap_dss_get_overlay(i);
3076
3077 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3078 continue;
3079
3080 if (ovl->id == 1) {
3081 dispc_enable_plane(ovl->id, 0);
3082 dispc_go(ovl->manager->id);
3083 mdelay(50);
3084 break;
3085 }
3086 }
3087 }
3088
3089 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3090 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3091 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3092 struct omap_overlay *ovl;
3093 ovl = omap_dss_get_overlay(i);
3094
3095 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3096 continue;
3097
3098 if (ovl->id == 2) {
3099 dispc_enable_plane(ovl->id, 0);
3100 dispc_go(ovl->manager->id);
3101 mdelay(50);
3102 break;
3103 }
3104 }
3105 }
3106
3107 if (errors & DISPC_IRQ_SYNC_LOST) {
3108 struct omap_overlay_manager *manager = NULL;
3109 bool enable = false;
3110
3111 DSSERR("SYNC_LOST, disabling LCD\n");
3112
3113 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3114 struct omap_overlay_manager *mgr;
3115 mgr = omap_dss_get_overlay_manager(i);
3116
3117 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3118 manager = mgr;
3119 enable = mgr->device->state ==
3120 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3121 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3122 break;
3123 }
3124 }
3125
3126 if (manager) {
37ac60e4 3127 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3128 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3129 struct omap_overlay *ovl;
3130 ovl = omap_dss_get_overlay(i);
3131
3132 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3133 continue;
3134
3135 if (ovl->id != 0 && ovl->manager == manager)
3136 dispc_enable_plane(ovl->id, 0);
3137 }
3138
3139 dispc_go(manager->id);
3140 mdelay(50);
3141 if (enable)
37ac60e4 3142 dssdev->driver->enable(dssdev);
80c39712
TV		 3143 }
3144 }
3145
3146 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3147 struct omap_overlay_manager *manager = NULL;
3148 bool enable = false;
3149
3150 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3151
3152 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3153 struct omap_overlay_manager *mgr;
3154 mgr = omap_dss_get_overlay_manager(i);
3155
3156 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3157 manager = mgr;
3158 enable = mgr->device->state ==
3159 OMAP_DSS_DISPLAY_ACTIVE;
37ac60e4 3160 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3161 break;
3162 }
3163 }
3164
3165 if (manager) {
37ac60e4 3166 struct omap_dss_device *dssdev = manager->device;
80c39712
TV		 3167 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3168 struct omap_overlay *ovl;
3169 ovl = omap_dss_get_overlay(i);
3170
3171 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3172 continue;
3173
3174 if (ovl->id != 0 && ovl->manager == manager)
3175 dispc_enable_plane(ovl->id, 0);
3176 }
3177
3178 dispc_go(manager->id);
3179 mdelay(50);
3180 if (enable)
37ac60e4 3181 dssdev->driver->enable(dssdev);
80c39712
TV		 3182 }
3183 }
3184
2a205f34
SS		 3185 if (errors & DISPC_IRQ_SYNC_LOST2) {
3186 struct omap_overlay_manager *manager = NULL;
3187 bool enable = false;
3188
3189 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3190
3191 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3192 struct omap_overlay_manager *mgr;
3193 mgr = omap_dss_get_overlay_manager(i);
3194
3195 if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3196 manager = mgr;
3197 enable = mgr->device->state ==
3198 OMAP_DSS_DISPLAY_ACTIVE;
3199 mgr->device->driver->disable(mgr->device);
3200 break;
3201 }
3202 }
3203
3204 if (manager) {
3205 struct omap_dss_device *dssdev = manager->device;
3206 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3207 struct omap_overlay *ovl;
3208 ovl = omap_dss_get_overlay(i);
3209
3210 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3211 continue;
3212
3213 if (ovl->id != 0 && ovl->manager == manager)
3214 dispc_enable_plane(ovl->id, 0);
3215 }
3216
3217 dispc_go(manager->id);
3218 mdelay(50);
3219 if (enable)
3220 dssdev->driver->enable(dssdev);
3221 }
3222 }
3223
80c39712
TV		 3224 if (errors & DISPC_IRQ_OCP_ERR) {
3225 DSSERR("OCP_ERR\n");
3226 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3227 struct omap_overlay_manager *mgr;
3228 mgr = omap_dss_get_overlay_manager(i);
3229
3230 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
37ac60e4 3231 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3232 }
3233 }
3234
3235 spin_lock_irqsave(&dispc.irq_lock, flags);
3236 dispc.irq_error_mask |= errors;
3237 _omap_dispc_set_irqs();
3238 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3239
3240 dispc_runtime_put();
80c39712
TV		 3241}
3242
3243int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3244{
3245 void dispc_irq_wait_handler(void *data, u32 mask)
3246 {
3247 complete((struct completion *)data);
3248 }
3249
3250 int r;
3251 DECLARE_COMPLETION_ONSTACK(completion);
3252
3253 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3254 irqmask);
3255
3256 if (r)
3257 return r;
3258
3259 timeout = wait_for_completion_timeout(&completion, timeout);
3260
3261 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3262
3263 if (timeout == 0)
3264 return -ETIMEDOUT;
3265
3266 if (timeout == -ERESTARTSYS)
3267 return -ERESTARTSYS;
3268
3269 return 0;
3270}
3271
3272int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3273 unsigned long timeout)
3274{
3275 void dispc_irq_wait_handler(void *data, u32 mask)
3276 {
3277 complete((struct completion *)data);
3278 }
3279
3280 int r;
3281 DECLARE_COMPLETION_ONSTACK(completion);
3282
3283 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3284 irqmask);
3285
3286 if (r)
3287 return r;
3288
3289 timeout = wait_for_completion_interruptible_timeout(&completion,
3290 timeout);
3291
3292 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3293
3294 if (timeout == 0)
3295 return -ETIMEDOUT;
3296
3297 if (timeout == -ERESTARTSYS)
3298 return -ERESTARTSYS;
3299
3300 return 0;
3301}
3302
3303#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3304void dispc_fake_vsync_irq(void)
3305{
3306 u32 irqstatus = DISPC_IRQ_VSYNC;
3307 int i;
3308
ab83b14c 3309 WARN_ON(!in_interrupt());
80c39712
TV		 3310
3311 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3312 struct omap_dispc_isr_data *isr_data;
3313 isr_data = &dispc.registered_isr[i];
3314
3315 if (!isr_data->isr)
3316 continue;
3317
3318 if (isr_data->mask & irqstatus)
3319 isr_data->isr(isr_data->arg, irqstatus);
3320 }
80c39712
TV		 3321}
3322#endif
3323
3324static void _omap_dispc_initialize_irq(void)
3325{
3326 unsigned long flags;
3327
3328 spin_lock_irqsave(&dispc.irq_lock, flags);
3329
3330 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3331
3332 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3333 if (dss_has_feature(FEAT_MGR_LCD2))
3334 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
80c39712
TV		 3335
3336 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3337 * so clear it */
3338 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3339
3340 _omap_dispc_set_irqs();
3341
3342 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3343}
3344
3345void dispc_enable_sidle(void)
3346{
3347 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3348}
3349
3350void dispc_disable_sidle(void)
3351{
3352 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3353}
3354
3355static void _omap_dispc_initial_config(void)
3356{
3357 u32 l;
3358
0cf35df3
MR		 3359 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3360 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3361 l = dispc_read_reg(DISPC_DIVISOR);
3362 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3363 l = FLD_MOD(l, 1, 0, 0);
3364 l = FLD_MOD(l, 1, 23, 16);
3365 dispc_write_reg(DISPC_DIVISOR, l);
3366 }
3367
80c39712 3368 /* FUNCGATED */
6ced40bf
AT		 3369 if (dss_has_feature(FEAT_FUNCGATED))
3370 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712
TV		 3371
3372 /* L3 firewall setting: enable access to OCM RAM */
3373 /* XXX this should be somewhere in plat-omap */
3374 if (cpu_is_omap24xx())
3375 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3376
3377 _dispc_setup_color_conv_coef();
3378
3379 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3380
3381 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3382
3383 dispc_configure_burst_sizes();
80c39712
TV		 3384}
3385
060b6d9c
SG		 3386/* DISPC HW IP initialisation */
3387static int omap_dispchw_probe(struct platform_device *pdev)
3388{
3389 u32 rev;
affe360d 3390 int r = 0;
ea9da36a 3391 struct resource *dispc_mem;
4fbafaf3 3392 struct clk *clk;
ea9da36a 3393
060b6d9c
SG		 3394 dispc.pdev = pdev;
3395
4fbafaf3
TV		 3396 clk = clk_get(&pdev->dev, "fck");
3397 if (IS_ERR(clk)) {
3398 DSSERR("can't get fck\n");
3399 r = PTR_ERR(clk);
3400 goto err_get_clk;
3401 }
3402
3403 dispc.dss_clk = clk;
3404
060b6d9c
SG		 3405 spin_lock_init(&dispc.irq_lock);
3406
3407#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3408 spin_lock_init(&dispc.irq_stats_lock);
3409 dispc.irq_stats.last_reset = jiffies;
3410#endif
3411
3412 INIT_WORK(&dispc.error_work, dispc_error_worker);
3413
ea9da36a
SG		 3414 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3415 if (!dispc_mem) {
3416 DSSERR("can't get IORESOURCE_MEM DISPC\n");
affe360d 3417 r = -EINVAL;
4fbafaf3 3418 goto err_ioremap;
ea9da36a
SG		 3419 }
3420 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
060b6d9c
SG		 3421 if (!dispc.base) {
3422 DSSERR("can't ioremap DISPC\n");
affe360d 3423 r = -ENOMEM;
4fbafaf3 3424 goto err_ioremap;
affe360d 3425 }
3426 dispc.irq = platform_get_irq(dispc.pdev, 0);
3427 if (dispc.irq < 0) {
3428 DSSERR("platform_get_irq failed\n");
3429 r = -ENODEV;
4fbafaf3 3430 goto err_irq;
affe360d 3431 }
3432
3433 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3434 "OMAP DISPC", dispc.pdev);
3435 if (r < 0) {
3436 DSSERR("request_irq failed\n");
4fbafaf3 3437 goto err_irq;
060b6d9c
SG		 3438 }
3439
4fbafaf3
TV		 3440 pm_runtime_enable(&pdev->dev);
3441
3442 r = dispc_runtime_get();
3443 if (r)
3444 goto err_runtime_get;
060b6d9c
SG		 3445
3446 _omap_dispc_initial_config();
3447
3448 _omap_dispc_initialize_irq();
3449
060b6d9c 3450 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3451 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3452 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3453
4fbafaf3 3454 dispc_runtime_put();
060b6d9c
SG		 3455
3456 return 0;
4fbafaf3
TV		 3457
3458err_runtime_get:
3459 pm_runtime_disable(&pdev->dev);
3460 free_irq(dispc.irq, dispc.pdev);
3461err_irq:
affe360d 3462 iounmap(dispc.base);
4fbafaf3
TV		 3463err_ioremap:
3464 clk_put(dispc.dss_clk);
3465err_get_clk:
affe360d 3466 return r;
060b6d9c
SG		 3467}
3468
3469static int omap_dispchw_remove(struct platform_device *pdev)
3470{
4fbafaf3
TV		 3471 pm_runtime_disable(&pdev->dev);
3472
3473 clk_put(dispc.dss_clk);
3474
affe360d 3475 free_irq(dispc.irq, dispc.pdev);
060b6d9c
SG		 3476 iounmap(dispc.base);
3477 return 0;
3478}
3479
4fbafaf3
TV		 3480static int dispc_runtime_suspend(struct device *dev)
3481{
3482 dispc_save_context();
3483 clk_disable(dispc.dss_clk);
3484 dss_runtime_put();
3485
3486 return 0;
3487}
3488
3489static int dispc_runtime_resume(struct device *dev)
3490{
3491 int r;
3492
3493 r = dss_runtime_get();
3494 if (r < 0)
3495 return r;
3496
3497 clk_enable(dispc.dss_clk);
49ea86f3 3498 dispc_restore_context();
4fbafaf3
TV		 3499
3500 return 0;
3501}
3502
3503static const struct dev_pm_ops dispc_pm_ops = {
3504 .runtime_suspend = dispc_runtime_suspend,
3505 .runtime_resume = dispc_runtime_resume,
3506};
3507
060b6d9c
SG		 3508static struct platform_driver omap_dispchw_driver = {
3509 .probe = omap_dispchw_probe,
3510 .remove = omap_dispchw_remove,
3511 .driver = {
3512 .name = "omapdss_dispc",
3513 .owner = THIS_MODULE,
4fbafaf3 3514 .pm = &dispc_pm_ops,
060b6d9c
SG		 3515 },
3516};
3517
3518int dispc_init_platform_driver(void)
3519{
3520 return platform_driver_register(&omap_dispchw_driver);
3521}
3522
3523void dispc_uninit_platform_driver(void)
3524{
3525 return platform_driver_unregister(&omap_dispchw_driver);
3526}
Linux kernel - Deliverables
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