projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAPDSS: remove dispc_irq_handler declaration
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
33366d0e 39#include <linux/sizes.h>
80c39712 40
a0b38cc4 41#include <video/omapdss.h>
80c39712
TV		 42
43#include "dss.h"
a0acb557 44#include "dss_features.h"
9b372c2d 45#include "dispc.h"
80c39712
TV		 46
47/* DISPC */
8613b000 48#define DISPC_SZ_REGS SZ_4K
80c39712 49
80c39712
TV		 50#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
51 DISPC_IRQ_OCP_ERR | \
52 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
53 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
54 DISPC_IRQ_SYNC_LOST | \
55 DISPC_IRQ_SYNC_LOST_DIGIT)
56
57#define DISPC_MAX_NR_ISRS 8
58
59struct omap_dispc_isr_data {
60 omap_dispc_isr_t isr;
61 void *arg;
62 u32 mask;
63};
64
5ed8cf5b
TV		 65enum omap_burst_size {
66 BURST_SIZE_X2 = 0,
67 BURST_SIZE_X4 = 1,
68 BURST_SIZE_X8 = 2,
69};
70
80c39712
TV		 71#define REG_GET(idx, start, end) \
72 FLD_GET(dispc_read_reg(idx), start, end)
73
74#define REG_FLD_MOD(idx, val, start, end) \
75 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
76
dfc0fd8d
TV		 77struct dispc_irq_stats {
78 unsigned long last_reset;
79 unsigned irq_count;
80 unsigned irqs[32];
81};
82
dcbe765b
CM		 83struct dispc_features {
84 u8 sw_start;
85 u8 fp_start;
86 u8 bp_start;
87 u16 sw_max;
88 u16 vp_max;
89 u16 hp_max;
3e8a6ff2 90 int (*calc_scaling) (enum omap_plane plane,
dcbe765b
CM		 91 const struct omap_video_timings *mgr_timings,
92 u16 width, u16 height, u16 out_width, u16 out_height,
93 enum omap_color_mode color_mode, bool *five_taps,
94 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 95 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
3e8a6ff2 96 unsigned long (*calc_core_clk) (enum omap_plane plane,
8ba85306
AT		 97 u16 width, u16 height, u16 out_width, u16 out_height,
98 bool mem_to_mem);
42a6961c 99 u8 num_fifos;
66a0f9e4
TV		 100
101 /* swap GFX & WB fifos */
102 bool gfx_fifo_workaround:1;
dcbe765b
CM		 103};
104
42a6961c
TV		 105#define DISPC_MAX_NR_FIFOS 5
106
80c39712 107static struct {
060b6d9c 108 struct platform_device *pdev;
80c39712 109 void __iomem *base;
4fbafaf3
TV		 110
111 int ctx_loss_cnt;
112
affe360d 113 int irq;
4fbafaf3 114 struct clk *dss_clk;
80c39712 115
42a6961c
TV		 116 u32 fifo_size[DISPC_MAX_NR_FIFOS];
117 /* maps which plane is using a fifo. fifo-id -> plane-id */
118 int fifo_assignment[DISPC_MAX_NR_FIFOS];
80c39712
TV		 119
120 spinlock_t irq_lock;
121 u32 irq_error_mask;
122 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
123 u32 error_irqs;
124 struct work_struct error_work;
125
49ea86f3 126 bool ctx_valid;
80c39712 127 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d 128
dcbe765b
CM		 129 const struct dispc_features *feat;
130
dfc0fd8d
TV		 131#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
132 spinlock_t irq_stats_lock;
133 struct dispc_irq_stats irq_stats;
134#endif
80c39712
TV		 135} dispc;
136
0d66cbb5
AJ		 137enum omap_color_component {
138 /* used for all color formats for OMAP3 and earlier
139 * and for RGB and Y color component on OMAP4
140 */
141 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
142 /* used for UV component for
143 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
144 * color formats on OMAP4
145 */
146 DISPC_COLOR_COMPONENT_UV = 1 << 1,
147};
148
efa70b3b
CM		 149enum mgr_reg_fields {
150 DISPC_MGR_FLD_ENABLE,
151 DISPC_MGR_FLD_STNTFT,
152 DISPC_MGR_FLD_GO,
153 DISPC_MGR_FLD_TFTDATALINES,
154 DISPC_MGR_FLD_STALLMODE,
155 DISPC_MGR_FLD_TCKENABLE,
156 DISPC_MGR_FLD_TCKSELECTION,
157 DISPC_MGR_FLD_CPR,
158 DISPC_MGR_FLD_FIFOHANDCHECK,
159 /* used to maintain a count of the above fields */
160 DISPC_MGR_FLD_NUM,
161};
162
163static const struct {
164 const char *name;
165 u32 vsync_irq;
166 u32 framedone_irq;
167 u32 sync_lost_irq;
168 struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
169} mgr_desc[] = {
170 [OMAP_DSS_CHANNEL_LCD] = {
171 .name = "LCD",
172 .vsync_irq = DISPC_IRQ_VSYNC,
173 .framedone_irq = DISPC_IRQ_FRAMEDONE,
174 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
175 .reg_desc = {
176 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
177 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
178 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
179 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
180 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
181 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
182 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
183 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
184 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
185 },
186 },
187 [OMAP_DSS_CHANNEL_DIGIT] = {
188 .name = "DIGIT",
189 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
190 .framedone_irq = 0,
191 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
192 .reg_desc = {
193 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
194 [DISPC_MGR_FLD_STNTFT] = { },
195 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
196 [DISPC_MGR_FLD_TFTDATALINES] = { },
197 [DISPC_MGR_FLD_STALLMODE] = { },
198 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
199 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
200 [DISPC_MGR_FLD_CPR] = { },
201 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
202 },
203 },
204 [OMAP_DSS_CHANNEL_LCD2] = {
205 .name = "LCD2",
206 .vsync_irq = DISPC_IRQ_VSYNC2,
207 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
208 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
209 .reg_desc = {
210 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
211 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
212 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
213 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
214 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
215 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
216 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
217 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
218 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
219 },
220 },
e86d456a
CM		 221 [OMAP_DSS_CHANNEL_LCD3] = {
222 .name = "LCD3",
223 .vsync_irq = DISPC_IRQ_VSYNC3,
224 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
225 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
226 .reg_desc = {
227 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
228 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
229 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
230 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
231 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
232 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
233 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
234 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
235 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
236 },
237 },
efa70b3b
CM		 238};
239
6e5264b0
AT		 240struct color_conv_coef {
241 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
242 int full_range;
243};
244
80c39712 245static void _omap_dispc_set_irqs(void);
3e8a6ff2
AT		 246static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
247static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
80c39712 248
55978cc2 249static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 250{
55978cc2 251 __raw_writel(val, dispc.base + idx);
80c39712
TV		 252}
253
55978cc2 254static inline u32 dispc_read_reg(const u16 idx)
80c39712 255{
55978cc2 256 return __raw_readl(dispc.base + idx);
80c39712
TV		 257}
258
efa70b3b
CM		 259static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
260{
261 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
262 return REG_GET(rfld.reg, rfld.high, rfld.low);
263}
264
265static void mgr_fld_write(enum omap_channel channel,
266 enum mgr_reg_fields regfld, int val) {
267 const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
268 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
269}
270
80c39712 271#define SR(reg) \
55978cc2 272 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 273#define RR(reg) \
55978cc2 274 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 275
4fbafaf3 276static void dispc_save_context(void)
80c39712 277{
c6104b8e 278 int i, j;
80c39712 279
4fbafaf3
TV		 280 DSSDBG("dispc_save_context\n");
281
80c39712
TV		 282 SR(IRQENABLE);
283 SR(CONTROL);
284 SR(CONFIG);
80c39712 285 SR(LINE_NUMBER);
11354dd5
AT		 286 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
287 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 288 SR(GLOBAL_ALPHA);
2a205f34
SS		 289 if (dss_has_feature(FEAT_MGR_LCD2)) {
290 SR(CONTROL2);
2a205f34
SS		 291 SR(CONFIG2);
292 }
e86d456a
CM		 293 if (dss_has_feature(FEAT_MGR_LCD3)) {
294 SR(CONTROL3);
295 SR(CONFIG3);
296 }
80c39712 297
c6104b8e
AT		 298 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
299 SR(DEFAULT_COLOR(i));
300 SR(TRANS_COLOR(i));
301 SR(SIZE_MGR(i));
302 if (i == OMAP_DSS_CHANNEL_DIGIT)
303 continue;
304 SR(TIMING_H(i));
305 SR(TIMING_V(i));
306 SR(POL_FREQ(i));
307 SR(DIVISORo(i));
308
309 SR(DATA_CYCLE1(i));
310 SR(DATA_CYCLE2(i));
311 SR(DATA_CYCLE3(i));
312
332e9d70 313 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 314 SR(CPR_COEF_R(i));
315 SR(CPR_COEF_G(i));
316 SR(CPR_COEF_B(i));
332e9d70 317 }
2a205f34 318 }
80c39712 319
c6104b8e
AT		 320 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
321 SR(OVL_BA0(i));
322 SR(OVL_BA1(i));
323 SR(OVL_POSITION(i));
324 SR(OVL_SIZE(i));
325 SR(OVL_ATTRIBUTES(i));
326 SR(OVL_FIFO_THRESHOLD(i));
327 SR(OVL_ROW_INC(i));
328 SR(OVL_PIXEL_INC(i));
329 if (dss_has_feature(FEAT_PRELOAD))
330 SR(OVL_PRELOAD(i));
331 if (i == OMAP_DSS_GFX) {
332 SR(OVL_WINDOW_SKIP(i));
333 SR(OVL_TABLE_BA(i));
334 continue;
335 }
336 SR(OVL_FIR(i));
337 SR(OVL_PICTURE_SIZE(i));
338 SR(OVL_ACCU0(i));
339 SR(OVL_ACCU1(i));
9b372c2d 340
c6104b8e
AT		 341 for (j = 0; j < 8; j++)
342 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 343
c6104b8e
AT		 344 for (j = 0; j < 8; j++)
345 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 346
c6104b8e
AT		 347 for (j = 0; j < 5; j++)
348 SR(OVL_CONV_COEF(i, j));
ab5ca071 349
c6104b8e
AT		 350 if (dss_has_feature(FEAT_FIR_COEF_V)) {
351 for (j = 0; j < 8; j++)
352 SR(OVL_FIR_COEF_V(i, j));
353 }
9b372c2d 354
c6104b8e
AT		 355 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
356 SR(OVL_BA0_UV(i));
357 SR(OVL_BA1_UV(i));
358 SR(OVL_FIR2(i));
359 SR(OVL_ACCU2_0(i));
360 SR(OVL_ACCU2_1(i));
ab5ca071 361
c6104b8e
AT		 362 for (j = 0; j < 8; j++)
363 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 364
c6104b8e
AT		 365 for (j = 0; j < 8; j++)
366 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 367
c6104b8e
AT		 368 for (j = 0; j < 8; j++)
369 SR(OVL_FIR_COEF_V2(i, j));
370 }
371 if (dss_has_feature(FEAT_ATTR2))
372 SR(OVL_ATTRIBUTES2(i));
ab5ca071 373 }
0cf35df3
MR		 374
375 if (dss_has_feature(FEAT_CORE_CLK_DIV))
376 SR(DIVISOR);
49ea86f3 377
00928eaf 378 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 379 dispc.ctx_valid = true;
380
381 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 382}
383
4fbafaf3 384static void dispc_restore_context(void)
80c39712 385{
c6104b8e 386 int i, j, ctx;
4fbafaf3
TV		 387
388 DSSDBG("dispc_restore_context\n");
389
49ea86f3
TV		 390 if (!dispc.ctx_valid)
391 return;
392
00928eaf 393 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
49ea86f3
TV		 394
395 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
396 return;
397
398 DSSDBG("ctx_loss_count: saved %d, current %d\n",
399 dispc.ctx_loss_cnt, ctx);
400
75c7d59d 401 /*RR(IRQENABLE);*/
80c39712
TV		 402 /*RR(CONTROL);*/
403 RR(CONFIG);
80c39712 404 RR(LINE_NUMBER);
11354dd5
AT		 405 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
406 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 407 RR(GLOBAL_ALPHA);
c6104b8e 408 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 409 RR(CONFIG2);
e86d456a
CM		 410 if (dss_has_feature(FEAT_MGR_LCD3))
411 RR(CONFIG3);
80c39712 412
c6104b8e
AT		 413 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
414 RR(DEFAULT_COLOR(i));
415 RR(TRANS_COLOR(i));
416 RR(SIZE_MGR(i));
417 if (i == OMAP_DSS_CHANNEL_DIGIT)
418 continue;
419 RR(TIMING_H(i));
420 RR(TIMING_V(i));
421 RR(POL_FREQ(i));
422 RR(DIVISORo(i));
423
424 RR(DATA_CYCLE1(i));
425 RR(DATA_CYCLE2(i));
426 RR(DATA_CYCLE3(i));
2a205f34 427
332e9d70 428 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 429 RR(CPR_COEF_R(i));
430 RR(CPR_COEF_G(i));
431 RR(CPR_COEF_B(i));
332e9d70 432 }
2a205f34 433 }
80c39712 434
c6104b8e
AT		 435 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
436 RR(OVL_BA0(i));
437 RR(OVL_BA1(i));
438 RR(OVL_POSITION(i));
439 RR(OVL_SIZE(i));
440 RR(OVL_ATTRIBUTES(i));
441 RR(OVL_FIFO_THRESHOLD(i));
442 RR(OVL_ROW_INC(i));
443 RR(OVL_PIXEL_INC(i));
444 if (dss_has_feature(FEAT_PRELOAD))
445 RR(OVL_PRELOAD(i));
446 if (i == OMAP_DSS_GFX) {
447 RR(OVL_WINDOW_SKIP(i));
448 RR(OVL_TABLE_BA(i));
449 continue;
450 }
451 RR(OVL_FIR(i));
452 RR(OVL_PICTURE_SIZE(i));
453 RR(OVL_ACCU0(i));
454 RR(OVL_ACCU1(i));
9b372c2d 455
c6104b8e
AT		 456 for (j = 0; j < 8; j++)
457 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 458
c6104b8e
AT		 459 for (j = 0; j < 8; j++)
460 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 461
c6104b8e
AT		 462 for (j = 0; j < 5; j++)
463 RR(OVL_CONV_COEF(i, j));
ab5ca071 464
c6104b8e
AT		 465 if (dss_has_feature(FEAT_FIR_COEF_V)) {
466 for (j = 0; j < 8; j++)
467 RR(OVL_FIR_COEF_V(i, j));
468 }
9b372c2d 469
c6104b8e
AT		 470 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
471 RR(OVL_BA0_UV(i));
472 RR(OVL_BA1_UV(i));
473 RR(OVL_FIR2(i));
474 RR(OVL_ACCU2_0(i));
475 RR(OVL_ACCU2_1(i));
ab5ca071 476
c6104b8e
AT		 477 for (j = 0; j < 8; j++)
478 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 479
c6104b8e
AT		 480 for (j = 0; j < 8; j++)
481 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 482
c6104b8e
AT		 483 for (j = 0; j < 8; j++)
484 RR(OVL_FIR_COEF_V2(i, j));
485 }
486 if (dss_has_feature(FEAT_ATTR2))
487 RR(OVL_ATTRIBUTES2(i));
ab5ca071 488 }
80c39712 489
0cf35df3
MR		 490 if (dss_has_feature(FEAT_CORE_CLK_DIV))
491 RR(DIVISOR);
492
80c39712
TV		 493 /* enable last, because LCD & DIGIT enable are here */
494 RR(CONTROL);
2a205f34
SS		 495 if (dss_has_feature(FEAT_MGR_LCD2))
496 RR(CONTROL2);
e86d456a
CM		 497 if (dss_has_feature(FEAT_MGR_LCD3))
498 RR(CONTROL3);
75c7d59d
VS		 499 /* clear spurious SYNC_LOST_DIGIT interrupts */
500 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
501
502 /*
503 * enable last so IRQs won't trigger before
504 * the context is fully restored
505 */
506 RR(IRQENABLE);
49ea86f3
TV		 507
508 DSSDBG("context restored\n");
80c39712
TV		 509}
510
511#undef SR
512#undef RR
513
4fbafaf3
TV		 514int dispc_runtime_get(void)
515{
516 int r;
517
518 DSSDBG("dispc_runtime_get\n");
519
520 r = pm_runtime_get_sync(&dispc.pdev->dev);
521 WARN_ON(r < 0);
522 return r < 0 ? r : 0;
523}
524
525void dispc_runtime_put(void)
526{
527 int r;
528
529 DSSDBG("dispc_runtime_put\n");
530
0eaf9f52 531 r = pm_runtime_put_sync(&dispc.pdev->dev);
5be3aebd 532 WARN_ON(r < 0 && r != -ENOSYS);
80c39712
TV		 533}
534
3dcec4d6
TV		 535u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
536{
efa70b3b 537 return mgr_desc[channel].vsync_irq;
3dcec4d6
TV		 538}
539
7d1365c9
TV		 540u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
541{
efa70b3b 542 return mgr_desc[channel].framedone_irq;
7d1365c9
TV		 543}
544
cb699200
TV		 545u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
546{
547 return mgr_desc[channel].sync_lost_irq;
548}
549
0b23e5b8
AT		 550u32 dispc_wb_get_framedone_irq(void)
551{
552 return DISPC_IRQ_FRAMEDONEWB;
553}
554
26d9dd0d 555bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712 556{
efa70b3b 557 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
80c39712
TV		 558}
559
26d9dd0d 560void dispc_mgr_go(enum omap_channel channel)
80c39712 561{
2a205f34 562 bool enable_bit, go_bit;
80c39712 563
80c39712 564 /* if the channel is not enabled, we don't need GO */
efa70b3b 565 enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
2a205f34
SS		 566
567 if (!enable_bit)
e6d80f95 568 return;
80c39712 569
efa70b3b 570 go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
2a205f34
SS		 571
572 if (go_bit) {
80c39712 573 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 574 return;
80c39712
TV		 575 }
576
efa70b3b 577 DSSDBG("GO %s\n", mgr_desc[channel].name);
80c39712 578
efa70b3b 579 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
80c39712
TV		 580}
581
0b23e5b8
AT		 582bool dispc_wb_go_busy(void)
583{
584 return REG_GET(DISPC_CONTROL2, 6, 6) == 1;
585}
586
587void dispc_wb_go(void)
588{
589 enum omap_plane plane = OMAP_DSS_WB;
590 bool enable, go;
591
592 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
593
594 if (!enable)
595 return;
596
597 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1;
598 if (go) {
599 DSSERR("GO bit not down for WB\n");
600 return;
601 }
602
603 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6);
604}
605
f0e5caab 606static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 607{
9b372c2d 608 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 609}
610
f0e5caab 611static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 612{
9b372c2d 613 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 614}
615
f0e5caab 616static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 617{
9b372c2d 618 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 619}
620
f0e5caab 621static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 622{
623 BUG_ON(plane == OMAP_DSS_GFX);
624
625 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
626}
627
f0e5caab
TV		 628static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
629 u32 value)
ab5ca071
AJ		 630{
631 BUG_ON(plane == OMAP_DSS_GFX);
632
633 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
634}
635
f0e5caab 636static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 637{
638 BUG_ON(plane == OMAP_DSS_GFX);
639
640 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
641}
642
debd9074
CM		 643static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
644 int fir_vinc, int five_taps,
645 enum omap_color_component color_comp)
80c39712 646{
debd9074 647 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 648 int i;
649
debd9074
CM		 650 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
651 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 652
653 for (i = 0; i < 8; i++) {
654 u32 h, hv;
655
debd9074
CM		 656 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
657 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
658 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
659 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
660 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
661 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
662 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
663 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 664
0d66cbb5 665 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 666 dispc_ovl_write_firh_reg(plane, i, h);
667 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 668 } else {
f0e5caab
TV		 669 dispc_ovl_write_firh2_reg(plane, i, h);
670 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 671 }
672
80c39712
TV		 673 }
674
66be8f6c
GI		 675 if (five_taps) {
676 for (i = 0; i < 8; i++) {
677 u32 v;
debd9074
CM		 678 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
679 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 680 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 681 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 682 else
f0e5caab 683 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 684 }
80c39712
TV		 685 }
686}
687
80c39712 688
6e5264b0
AT		 689static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
690 const struct color_conv_coef *ct)
691{
80c39712
TV		 692#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
693
6e5264b0
AT		 694 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
695 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
696 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
697 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
698 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
80c39712 699
6e5264b0 700 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
80c39712
TV		 701
702#undef CVAL
80c39712
TV		 703}
704
6e5264b0
AT		 705static void dispc_setup_color_conv_coef(void)
706{
707 int i;
708 int num_ovl = dss_feat_get_num_ovls();
709 int num_wb = dss_feat_get_num_wbs();
710 const struct color_conv_coef ctbl_bt601_5_ovl = {
711 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
712 };
713 const struct color_conv_coef ctbl_bt601_5_wb = {
714 66, 112, -38, 129, -94, -74, 25, -18, 112, 0,
715 };
716
717 for (i = 1; i < num_ovl; i++)
718 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
719
720 for (; i < num_wb; i++)
721 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_wb);
722}
80c39712 723
f0e5caab 724static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 725{
9b372c2d 726 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 727}
728
f0e5caab 729static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 730{
9b372c2d 731 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 732}
733
f0e5caab 734static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 735{
736 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
737}
738
f0e5caab 739static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 740{
741 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
742}
743
d79db853
AT		 744static void dispc_ovl_set_pos(enum omap_plane plane,
745 enum omap_overlay_caps caps, int x, int y)
80c39712 746{
d79db853
AT		 747 u32 val;
748
749 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
750 return;
751
752 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 753
754 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 755}
756
78b687fc
AT		 757static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
758 int height)
80c39712 759{
80c39712 760 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 761
36d87d95 762 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
9b372c2d
AT		 763 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
764 else
765 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 766}
767
78b687fc
AT		 768static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
769 int height)
80c39712
TV		 770{
771 u32 val;
80c39712
TV		 772
773 BUG_ON(plane == OMAP_DSS_GFX);
774
775 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d 776
36d87d95
AT		 777 if (plane == OMAP_DSS_WB)
778 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
779 else
780 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 781}
782
5b54ed3e
AT		 783static void dispc_ovl_set_zorder(enum omap_plane plane,
784 enum omap_overlay_caps caps, u8 zorder)
54128701 785{
5b54ed3e 786 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
54128701
AT		 787 return;
788
789 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
790}
791
792static void dispc_ovl_enable_zorder_planes(void)
793{
794 int i;
795
796 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
797 return;
798
799 for (i = 0; i < dss_feat_get_num_ovls(); i++)
800 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
801}
802
5b54ed3e
AT		 803static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
804 enum omap_overlay_caps caps, bool enable)
fd28a390 805{
5b54ed3e 806 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 807 return;
808
9b372c2d 809 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 810}
811
5b54ed3e
AT		 812static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
813 enum omap_overlay_caps caps, u8 global_alpha)
80c39712 814{
b8c095b4 815 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6
TV		 816 int shift;
817
5b54ed3e 818 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 819 return;
a0acb557 820
fe3cc9d6
TV		 821 shift = shifts[plane];
822 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 823}
824
f0e5caab 825static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 826{
9b372c2d 827 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 828}
829
f0e5caab 830static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 831{
9b372c2d 832 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 833}
834
f0e5caab 835static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 836 enum omap_color_mode color_mode)
837{
838 u32 m = 0;
f20e4220
AJ		 839 if (plane != OMAP_DSS_GFX) {
840 switch (color_mode) {
841 case OMAP_DSS_COLOR_NV12:
842 m = 0x0; break;
08f3267e 843 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 844 m = 0x1; break;
845 case OMAP_DSS_COLOR_RGBA16:
846 m = 0x2; break;
08f3267e 847 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 848 m = 0x4; break;
849 case OMAP_DSS_COLOR_ARGB16:
850 m = 0x5; break;
851 case OMAP_DSS_COLOR_RGB16:
852 m = 0x6; break;
853 case OMAP_DSS_COLOR_ARGB16_1555:
854 m = 0x7; break;
855 case OMAP_DSS_COLOR_RGB24U:
856 m = 0x8; break;
857 case OMAP_DSS_COLOR_RGB24P:
858 m = 0x9; break;
859 case OMAP_DSS_COLOR_YUV2:
860 m = 0xa; break;
861 case OMAP_DSS_COLOR_UYVY:
862 m = 0xb; break;
863 case OMAP_DSS_COLOR_ARGB32:
864 m = 0xc; break;
865 case OMAP_DSS_COLOR_RGBA32:
866 m = 0xd; break;
867 case OMAP_DSS_COLOR_RGBX32:
868 m = 0xe; break;
869 case OMAP_DSS_COLOR_XRGB16_1555:
870 m = 0xf; break;
871 default:
c6eee968 872 BUG(); return;
f20e4220
AJ		 873 }
874 } else {
875 switch (color_mode) {
876 case OMAP_DSS_COLOR_CLUT1:
877 m = 0x0; break;
878 case OMAP_DSS_COLOR_CLUT2:
879 m = 0x1; break;
880 case OMAP_DSS_COLOR_CLUT4:
881 m = 0x2; break;
882 case OMAP_DSS_COLOR_CLUT8:
883 m = 0x3; break;
884 case OMAP_DSS_COLOR_RGB12U:
885 m = 0x4; break;
886 case OMAP_DSS_COLOR_ARGB16:
887 m = 0x5; break;
888 case OMAP_DSS_COLOR_RGB16:
889 m = 0x6; break;
890 case OMAP_DSS_COLOR_ARGB16_1555:
891 m = 0x7; break;
892 case OMAP_DSS_COLOR_RGB24U:
893 m = 0x8; break;
894 case OMAP_DSS_COLOR_RGB24P:
895 m = 0x9; break;
08f3267e 896 case OMAP_DSS_COLOR_RGBX16:
f20e4220 897 m = 0xa; break;
08f3267e 898 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 899 m = 0xb; break;
900 case OMAP_DSS_COLOR_ARGB32:
901 m = 0xc; break;
902 case OMAP_DSS_COLOR_RGBA32:
903 m = 0xd; break;
904 case OMAP_DSS_COLOR_RGBX32:
905 m = 0xe; break;
906 case OMAP_DSS_COLOR_XRGB16_1555:
907 m = 0xf; break;
908 default:
c6eee968 909 BUG(); return;
f20e4220 910 }
80c39712
TV		 911 }
912
9b372c2d 913 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 914}
915
65e006ff
CM		 916static void dispc_ovl_configure_burst_type(enum omap_plane plane,
917 enum omap_dss_rotation_type rotation_type)
918{
919 if (dss_has_feature(FEAT_BURST_2D) == 0)
920 return;
921
922 if (rotation_type == OMAP_DSS_ROT_TILER)
923 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
924 else
925 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
926}
927
f427984e 928void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 929{
930 int shift;
931 u32 val;
2a205f34 932 int chan = 0, chan2 = 0;
80c39712
TV		 933
934 switch (plane) {
935 case OMAP_DSS_GFX:
936 shift = 8;
937 break;
938 case OMAP_DSS_VIDEO1:
939 case OMAP_DSS_VIDEO2:
b8c095b4 940 case OMAP_DSS_VIDEO3:
80c39712
TV		 941 shift = 16;
942 break;
943 default:
944 BUG();
945 return;
946 }
947
9b372c2d 948 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 949 if (dss_has_feature(FEAT_MGR_LCD2)) {
950 switch (channel) {
951 case OMAP_DSS_CHANNEL_LCD:
952 chan = 0;
953 chan2 = 0;
954 break;
955 case OMAP_DSS_CHANNEL_DIGIT:
956 chan = 1;
957 chan2 = 0;
958 break;
959 case OMAP_DSS_CHANNEL_LCD2:
960 chan = 0;
961 chan2 = 1;
962 break;
e86d456a
CM		 963 case OMAP_DSS_CHANNEL_LCD3:
964 if (dss_has_feature(FEAT_MGR_LCD3)) {
965 chan = 0;
966 chan2 = 2;
967 } else {
968 BUG();
969 return;
970 }
971 break;
2a205f34
SS		 972 default:
973 BUG();
c6eee968 974 return;
2a205f34
SS		 975 }
976
977 val = FLD_MOD(val, chan, shift, shift);
978 val = FLD_MOD(val, chan2, 31, 30);
979 } else {
980 val = FLD_MOD(val, channel, shift, shift);
981 }
9b372c2d 982 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 983}
984
2cc5d1af
TV		 985static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
986{
987 int shift;
988 u32 val;
989 enum omap_channel channel;
990
991 switch (plane) {
992 case OMAP_DSS_GFX:
993 shift = 8;
994 break;
995 case OMAP_DSS_VIDEO1:
996 case OMAP_DSS_VIDEO2:
997 case OMAP_DSS_VIDEO3:
998 shift = 16;
999 break;
1000 default:
1001 BUG();
c6eee968 1002 return 0;
2cc5d1af
TV		 1003 }
1004
1005 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1006
e86d456a
CM		 1007 if (dss_has_feature(FEAT_MGR_LCD3)) {
1008 if (FLD_GET(val, 31, 30) == 0)
1009 channel = FLD_GET(val, shift, shift);
1010 else if (FLD_GET(val, 31, 30) == 1)
1011 channel = OMAP_DSS_CHANNEL_LCD2;
1012 else
1013 channel = OMAP_DSS_CHANNEL_LCD3;
1014 } else if (dss_has_feature(FEAT_MGR_LCD2)) {
2cc5d1af
TV		 1015 if (FLD_GET(val, 31, 30) == 0)
1016 channel = FLD_GET(val, shift, shift);
1017 else
1018 channel = OMAP_DSS_CHANNEL_LCD2;
1019 } else {
1020 channel = FLD_GET(val, shift, shift);
1021 }
1022
1023 return channel;
1024}
1025
d9ac773c
AT		 1026void dispc_wb_set_channel_in(enum dss_writeback_channel channel)
1027{
1028 enum omap_plane plane = OMAP_DSS_WB;
1029
1030 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), channel, 18, 16);
1031}
1032
f0e5caab 1033static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 1034 enum omap_burst_size burst_size)
1035{
8bbe09ee 1036 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
80c39712 1037 int shift;
80c39712 1038
fe3cc9d6 1039 shift = shifts[plane];
5ed8cf5b 1040 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 1041}
1042
5ed8cf5b
TV		 1043static void dispc_configure_burst_sizes(void)
1044{
1045 int i;
1046 const int burst_size = BURST_SIZE_X8;
1047
1048 /* Configure burst size always to maximum size */
1049 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 1050 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 1051}
1052
83fa2f2e 1053static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 1054{
1055 unsigned unit = dss_feat_get_burst_size_unit();
1056 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1057 return unit * 8;
1058}
1059
d3862610
M		 1060void dispc_enable_gamma_table(bool enable)
1061{
1062 /*
1063 * This is partially implemented to support only disabling of
1064 * the gamma table.
1065 */
1066 if (enable) {
1067 DSSWARN("Gamma table enabling for TV not yet supported");
1068 return;
1069 }
1070
1071 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1072}
1073
c64dca40 1074static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2 1075{
efa70b3b 1076 if (channel == OMAP_DSS_CHANNEL_DIGIT)
3c07cae2
TV		 1077 return;
1078
efa70b3b 1079 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
3c07cae2
TV		 1080}
1081
c64dca40 1082static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
a8f3fcd1 1083 const struct omap_dss_cpr_coefs *coefs)
3c07cae2
TV		 1084{
1085 u32 coef_r, coef_g, coef_b;
1086
dd88b7a6 1087 if (!dss_mgr_is_lcd(channel))
3c07cae2
TV		 1088 return;
1089
1090 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1091 FLD_VAL(coefs->rb, 9, 0);
1092 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1093 FLD_VAL(coefs->gb, 9, 0);
1094 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1095 FLD_VAL(coefs->bb, 9, 0);
1096
1097 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1098 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1099 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1100}
1101
f0e5caab 1102static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 1103{
1104 u32 val;
1105
1106 BUG_ON(plane == OMAP_DSS_GFX);
1107
9b372c2d 1108 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1109 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 1110 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 1111}
1112
d79db853
AT		 1113static void dispc_ovl_enable_replication(enum omap_plane plane,
1114 enum omap_overlay_caps caps, bool enable)
80c39712 1115{
b8c095b4 1116 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 1117 int shift;
80c39712 1118
d79db853
AT		 1119 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1120 return;
1121
fe3cc9d6
TV		 1122 shift = shifts[plane];
1123 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 1124}
1125
8f366162 1126static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 1127 u16 height)
80c39712
TV		 1128{
1129 u32 val;
80c39712 1130
80c39712 1131 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 1132 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 1133}
1134
42a6961c 1135static void dispc_init_fifos(void)
80c39712 1136{
80c39712 1137 u32 size;
42a6961c 1138 int fifo;
a0acb557 1139 u8 start, end;
5ed8cf5b
TV		 1140 u32 unit;
1141
1142 unit = dss_feat_get_buffer_size_unit();
80c39712 1143
a0acb557 1144 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 1145
42a6961c
TV		 1146 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1147 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
5ed8cf5b 1148 size *= unit;
42a6961c
TV		 1149 dispc.fifo_size[fifo] = size;
1150
1151 /*
1152 * By default fifos are mapped directly to overlays, fifo 0 to
1153 * ovl 0, fifo 1 to ovl 1, etc.
1154 */
1155 dispc.fifo_assignment[fifo] = fifo;
80c39712 1156 }
66a0f9e4
TV		 1157
1158 /*
1159 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1160 * causes problems with certain use cases, like using the tiler in 2D
1161 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1162 * giving GFX plane a larger fifo. WB but should work fine with a
1163 * smaller fifo.
1164 */
1165 if (dispc.feat->gfx_fifo_workaround) {
1166 u32 v;
1167
1168 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1169
1170 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1171 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1172 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1173 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1174
1175 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1176
1177 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1178 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1179 }
80c39712
TV		 1180}
1181
83fa2f2e 1182static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712 1183{
42a6961c
TV		 1184 int fifo;
1185 u32 size = 0;
1186
1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1188 if (dispc.fifo_assignment[fifo] == plane)
1189 size += dispc.fifo_size[fifo];
1190 }
1191
1192 return size;
80c39712
TV		 1193}
1194
6f04e1bf 1195void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1196{
a0acb557 1197 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1198 u32 unit;
1199
1200 unit = dss_feat_get_buffer_size_unit();
1201
1202 WARN_ON(low % unit != 0);
1203 WARN_ON(high % unit != 0);
1204
1205 low /= unit;
1206 high /= unit;
a0acb557 1207
9b372c2d
AT		 1208 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1209 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1210
3cb5d966 1211 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1212 plane,
9b372c2d 1213 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1214 lo_start, lo_end) * unit,
9b372c2d 1215 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1216 hi_start, hi_end) * unit,
1217 low * unit, high * unit);
80c39712 1218
9b372c2d 1219 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1220 FLD_VAL(high, hi_start, hi_end) |
1221 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1222}
1223
1224void dispc_enable_fifomerge(bool enable)
1225{
e6b0f884
TV		 1226 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1227 WARN_ON(enable);
1228 return;
1229 }
1230
80c39712
TV		 1231 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1232 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1233}
1234
83fa2f2e 1235void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
3568f2a4
TV		 1236 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1237 bool manual_update)
83fa2f2e
TV		 1238{
1239 /*
1240 * All sizes are in bytes. Both the buffer and burst are made of
1241 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1242 */
1243
1244 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1245 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1246 int i;
83fa2f2e
TV		 1247
1248 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1249 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1250
e0e405b9
TV		 1251 if (use_fifomerge) {
1252 total_fifo_size = 0;
1253 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1254 total_fifo_size += dispc_ovl_get_fifo_size(i);
1255 } else {
1256 total_fifo_size = ovl_fifo_size;
1257 }
1258
1259 /*
1260 * We use the same low threshold for both fifomerge and non-fifomerge
1261 * cases, but for fifomerge we calculate the high threshold using the
1262 * combined fifo size
1263 */
1264
3568f2a4 1265 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
e0e405b9
TV		 1266 *fifo_low = ovl_fifo_size - burst_size * 2;
1267 *fifo_high = total_fifo_size - burst_size;
8bbe09ee
AT		 1268 } else if (plane == OMAP_DSS_WB) {
1269 /*
1270 * Most optimal configuration for writeback is to push out data
1271 * to the interconnect the moment writeback pushes enough pixels
1272 * in the FIFO to form a burst
1273 */
1274 *fifo_low = 0;
1275 *fifo_high = burst_size;
e0e405b9
TV		 1276 } else {
1277 *fifo_low = ovl_fifo_size - burst_size;
1278 *fifo_high = total_fifo_size - buf_unit;
1279 }
83fa2f2e
TV		 1280}
1281
f0e5caab 1282static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1283 int hinc, int vinc,
1284 enum omap_color_component color_comp)
80c39712
TV		 1285{
1286 u32 val;
80c39712 1287
0d66cbb5
AJ		 1288 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1289 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1290
0d66cbb5
AJ		 1291 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1292 &hinc_start, &hinc_end);
1293 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1294 &vinc_start, &vinc_end);
1295 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1296 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1297
0d66cbb5
AJ		 1298 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1299 } else {
1300 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1301 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1302 }
80c39712
TV		 1303}
1304
f0e5caab 1305static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1306{
1307 u32 val;
87a7484b 1308 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1309
87a7484b
AT		 1310 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1311 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1312
1313 val = FLD_VAL(vaccu, vert_start, vert_end) |
1314 FLD_VAL(haccu, hor_start, hor_end);
1315
9b372c2d 1316 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1317}
1318
f0e5caab 1319static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1320{
1321 u32 val;
87a7484b 1322 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1323
87a7484b
AT		 1324 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1325 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1326
1327 val = FLD_VAL(vaccu, vert_start, vert_end) |
1328 FLD_VAL(haccu, hor_start, hor_end);
1329
9b372c2d 1330 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1331}
1332
f0e5caab
TV		 1333static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1334 int vaccu)
ab5ca071
AJ		 1335{
1336 u32 val;
1337
1338 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1339 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1340}
1341
f0e5caab
TV		 1342static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1343 int vaccu)
ab5ca071
AJ		 1344{
1345 u32 val;
1346
1347 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1348 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1349}
80c39712 1350
f0e5caab 1351static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1352 u16 orig_width, u16 orig_height,
1353 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1354 bool five_taps, u8 rotation,
1355 enum omap_color_component color_comp)
80c39712 1356{
0d66cbb5 1357 int fir_hinc, fir_vinc;
80c39712 1358
ed14a3ce
AJ		 1359 fir_hinc = 1024 * orig_width / out_width;
1360 fir_vinc = 1024 * orig_height / out_height;
80c39712 1361
debd9074
CM		 1362 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1363 color_comp);
f0e5caab 1364 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1365}
1366
05dd0f53
CM		 1367static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1368 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1369 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1370{
1371 int h_accu2_0, h_accu2_1;
1372 int v_accu2_0, v_accu2_1;
1373 int chroma_hinc, chroma_vinc;
1374 int idx;
1375
1376 struct accu {
1377 s8 h0_m, h0_n;
1378 s8 h1_m, h1_n;
1379 s8 v0_m, v0_n;
1380 s8 v1_m, v1_n;
1381 };
1382
1383 const struct accu *accu_table;
1384 const struct accu *accu_val;
1385
1386 static const struct accu accu_nv12[4] = {
1387 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1388 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1389 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1390 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1391 };
1392
1393 static const struct accu accu_nv12_ilace[4] = {
1394 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1395 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1396 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1397 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1398 };
1399
1400 static const struct accu accu_yuv[4] = {
1401 { 0, 1, 0, 1, 0, 1, 0, 1 },
1402 { 0, 1, 0, 1, 0, 1, 0, 1 },
1403 { -1, 1, 0, 1, 0, 1, 0, 1 },
1404 { 0, 1, 0, 1, -1, 1, 0, 1 },
1405 };
1406
1407 switch (rotation) {
1408 case OMAP_DSS_ROT_0:
1409 idx = 0;
1410 break;
1411 case OMAP_DSS_ROT_90:
1412 idx = 1;
1413 break;
1414 case OMAP_DSS_ROT_180:
1415 idx = 2;
1416 break;
1417 case OMAP_DSS_ROT_270:
1418 idx = 3;
1419 break;
1420 default:
1421 BUG();
c6eee968 1422 return;
05dd0f53
CM		 1423 }
1424
1425 switch (color_mode) {
1426 case OMAP_DSS_COLOR_NV12:
1427 if (ilace)
1428 accu_table = accu_nv12_ilace;
1429 else
1430 accu_table = accu_nv12;
1431 break;
1432 case OMAP_DSS_COLOR_YUV2:
1433 case OMAP_DSS_COLOR_UYVY:
1434 accu_table = accu_yuv;
1435 break;
1436 default:
1437 BUG();
c6eee968 1438 return;
05dd0f53
CM		 1439 }
1440
1441 accu_val = &accu_table[idx];
1442
1443 chroma_hinc = 1024 * orig_width / out_width;
1444 chroma_vinc = 1024 * orig_height / out_height;
1445
1446 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1447 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1448 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1449 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1450
1451 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1452 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1453}
1454
f0e5caab 1455static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1456 u16 orig_width, u16 orig_height,
1457 u16 out_width, u16 out_height,
1458 bool ilace, bool five_taps,
1459 bool fieldmode, enum omap_color_mode color_mode,
1460 u8 rotation)
1461{
1462 int accu0 = 0;
1463 int accu1 = 0;
1464 u32 l;
80c39712 1465
f0e5caab 1466 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1467 out_width, out_height, five_taps,
1468 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1469 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1470
87a7484b
AT		 1471 /* RESIZEENABLE and VERTICALTAPS */
1472 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1473 l |= (orig_width != out_width) ? (1 << 5) : 0;
1474 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1475 l |= five_taps ? (1 << 21) : 0;
80c39712 1476
87a7484b
AT		 1477 /* VRESIZECONF and HRESIZECONF */
1478 if (dss_has_feature(FEAT_RESIZECONF)) {
1479 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1480 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1481 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1482 }
80c39712 1483
87a7484b
AT		 1484 /* LINEBUFFERSPLIT */
1485 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1486 l &= ~(0x1 << 22);
1487 l |= five_taps ? (1 << 22) : 0;
1488 }
80c39712 1489
9b372c2d 1490 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1491
1492 /*
1493 * field 0 = even field = bottom field
1494 * field 1 = odd field = top field
1495 */
1496 if (ilace && !fieldmode) {
1497 accu1 = 0;
0d66cbb5 1498 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1499 if (accu0 >= 1024/2) {
1500 accu1 = 1024/2;
1501 accu0 -= accu1;
1502 }
1503 }
1504
f0e5caab
TV		 1505 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1506 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1507}
1508
f0e5caab 1509static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1510 u16 orig_width, u16 orig_height,
1511 u16 out_width, u16 out_height,
1512 bool ilace, bool five_taps,
1513 bool fieldmode, enum omap_color_mode color_mode,
1514 u8 rotation)
1515{
1516 int scale_x = out_width != orig_width;
1517 int scale_y = out_height != orig_height;
f92afae2 1518 bool chroma_upscale = plane != OMAP_DSS_WB ? true : false;
0d66cbb5
AJ		 1519
1520 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1521 return;
1522 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1523 color_mode != OMAP_DSS_COLOR_UYVY &&
1524 color_mode != OMAP_DSS_COLOR_NV12)) {
1525 /* reset chroma resampling for RGB formats */
2a5561b1
AT		 1526 if (plane != OMAP_DSS_WB)
1527 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
0d66cbb5
AJ		 1528 return;
1529 }
36377357
TV		 1530
1531 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1532 out_height, ilace, color_mode, rotation);
1533
0d66cbb5
AJ		 1534 switch (color_mode) {
1535 case OMAP_DSS_COLOR_NV12:
20fbb50b
AT		 1536 if (chroma_upscale) {
1537 /* UV is subsampled by 2 horizontally and vertically */
1538 orig_height >>= 1;
1539 orig_width >>= 1;
1540 } else {
1541 /* UV is downsampled by 2 horizontally and vertically */
1542 orig_height <<= 1;
1543 orig_width <<= 1;
1544 }
1545
0d66cbb5
AJ		 1546 break;
1547 case OMAP_DSS_COLOR_YUV2:
1548 case OMAP_DSS_COLOR_UYVY:
20fbb50b 1549 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
0d66cbb5 1550 if (rotation == OMAP_DSS_ROT_0 ||
20fbb50b
AT		 1551 rotation == OMAP_DSS_ROT_180) {
1552 if (chroma_upscale)
1553 /* UV is subsampled by 2 horizontally */
1554 orig_width >>= 1;
1555 else
1556 /* UV is downsampled by 2 horizontally */
1557 orig_width <<= 1;
1558 }
1559
0d66cbb5
AJ		 1560 /* must use FIR for YUV422 if rotated */
1561 if (rotation != OMAP_DSS_ROT_0)
1562 scale_x = scale_y = true;
20fbb50b 1563
0d66cbb5
AJ		 1564 break;
1565 default:
1566 BUG();
c6eee968 1567 return;
0d66cbb5
AJ		 1568 }
1569
1570 if (out_width != orig_width)
1571 scale_x = true;
1572 if (out_height != orig_height)
1573 scale_y = true;
1574
f0e5caab 1575 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1576 out_width, out_height, five_taps,
1577 rotation, DISPC_COLOR_COMPONENT_UV);
1578
2a5561b1
AT		 1579 if (plane != OMAP_DSS_WB)
1580 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1581 (scale_x || scale_y) ? 1 : 0, 8, 8);
1582
0d66cbb5
AJ		 1583 /* set H scaling */
1584 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1585 /* set V scaling */
1586 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
0d66cbb5
AJ		 1587}
1588
f0e5caab 1589static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1590 u16 orig_width, u16 orig_height,
1591 u16 out_width, u16 out_height,
1592 bool ilace, bool five_taps,
1593 bool fieldmode, enum omap_color_mode color_mode,
1594 u8 rotation)
1595{
1596 BUG_ON(plane == OMAP_DSS_GFX);
1597
f0e5caab 1598 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1599 orig_width, orig_height,
1600 out_width, out_height,
1601 ilace, five_taps,
1602 fieldmode, color_mode,
1603 rotation);
1604
f0e5caab 1605 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1606 orig_width, orig_height,
1607 out_width, out_height,
1608 ilace, five_taps,
1609 fieldmode, color_mode,
1610 rotation);
1611}
1612
f0e5caab 1613static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1614 bool mirroring, enum omap_color_mode color_mode)
1615{
87a7484b
AT		 1616 bool row_repeat = false;
1617 int vidrot = 0;
1618
80c39712
TV		 1619 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1621
1622 if (mirroring) {
1623 switch (rotation) {
1624 case OMAP_DSS_ROT_0:
1625 vidrot = 2;
1626 break;
1627 case OMAP_DSS_ROT_90:
1628 vidrot = 1;
1629 break;
1630 case OMAP_DSS_ROT_180:
1631 vidrot = 0;
1632 break;
1633 case OMAP_DSS_ROT_270:
1634 vidrot = 3;
1635 break;
1636 }
1637 } else {
1638 switch (rotation) {
1639 case OMAP_DSS_ROT_0:
1640 vidrot = 0;
1641 break;
1642 case OMAP_DSS_ROT_90:
1643 vidrot = 1;
1644 break;
1645 case OMAP_DSS_ROT_180:
1646 vidrot = 2;
1647 break;
1648 case OMAP_DSS_ROT_270:
1649 vidrot = 3;
1650 break;
1651 }
1652 }
1653
80c39712 1654 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1655 row_repeat = true;
80c39712 1656 else
87a7484b 1657 row_repeat = false;
80c39712 1658 }
87a7484b 1659
9b372c2d 1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1661 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1662 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1663 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1664}
1665
1666static int color_mode_to_bpp(enum omap_color_mode color_mode)
1667{
1668 switch (color_mode) {
1669 case OMAP_DSS_COLOR_CLUT1:
1670 return 1;
1671 case OMAP_DSS_COLOR_CLUT2:
1672 return 2;
1673 case OMAP_DSS_COLOR_CLUT4:
1674 return 4;
1675 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1676 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1677 return 8;
1678 case OMAP_DSS_COLOR_RGB12U:
1679 case OMAP_DSS_COLOR_RGB16:
1680 case OMAP_DSS_COLOR_ARGB16:
1681 case OMAP_DSS_COLOR_YUV2:
1682 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1683 case OMAP_DSS_COLOR_RGBA16:
1684 case OMAP_DSS_COLOR_RGBX16:
1685 case OMAP_DSS_COLOR_ARGB16_1555:
1686 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1687 return 16;
1688 case OMAP_DSS_COLOR_RGB24P:
1689 return 24;
1690 case OMAP_DSS_COLOR_RGB24U:
1691 case OMAP_DSS_COLOR_ARGB32:
1692 case OMAP_DSS_COLOR_RGBA32:
1693 case OMAP_DSS_COLOR_RGBX32:
1694 return 32;
1695 default:
1696 BUG();
c6eee968 1697 return 0;
80c39712
TV		 1698 }
1699}
1700
1701static s32 pixinc(int pixels, u8 ps)
1702{
1703 if (pixels == 1)
1704 return 1;
1705 else if (pixels > 1)
1706 return 1 + (pixels - 1) * ps;
1707 else if (pixels < 0)
1708 return 1 - (-pixels + 1) * ps;
1709 else
1710 BUG();
c6eee968 1711 return 0;
80c39712
TV		 1712}
1713
1714static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1715 u16 screen_width,
1716 u16 width, u16 height,
1717 enum omap_color_mode color_mode, bool fieldmode,
1718 unsigned int field_offset,
1719 unsigned *offset0, unsigned *offset1,
aed74b55 1720 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1721{
1722 u8 ps;
1723
1724 /* FIXME CLUT formats */
1725 switch (color_mode) {
1726 case OMAP_DSS_COLOR_CLUT1:
1727 case OMAP_DSS_COLOR_CLUT2:
1728 case OMAP_DSS_COLOR_CLUT4:
1729 case OMAP_DSS_COLOR_CLUT8:
1730 BUG();
1731 return;
1732 case OMAP_DSS_COLOR_YUV2:
1733 case OMAP_DSS_COLOR_UYVY:
1734 ps = 4;
1735 break;
1736 default:
1737 ps = color_mode_to_bpp(color_mode) / 8;
1738 break;
1739 }
1740
1741 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1742 width, height);
1743
1744 /*
1745 * field 0 = even field = bottom field
1746 * field 1 = odd field = top field
1747 */
1748 switch (rotation + mirror * 4) {
1749 case OMAP_DSS_ROT_0:
1750 case OMAP_DSS_ROT_180:
1751 /*
1752 * If the pixel format is YUV or UYVY divide the width
1753 * of the image by 2 for 0 and 180 degree rotation.
1754 */
1755 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1756 color_mode == OMAP_DSS_COLOR_UYVY)
1757 width = width >> 1;
1758 case OMAP_DSS_ROT_90:
1759 case OMAP_DSS_ROT_270:
1760 *offset1 = 0;
1761 if (field_offset)
1762 *offset0 = field_offset * screen_width * ps;
1763 else
1764 *offset0 = 0;
1765
aed74b55
CM		 1766 *row_inc = pixinc(1 +
1767 (y_predecim * screen_width - x_predecim * width) +
1768 (fieldmode ? screen_width : 0), ps);
1769 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1770 break;
1771
1772 case OMAP_DSS_ROT_0 + 4:
1773 case OMAP_DSS_ROT_180 + 4:
1774 /* If the pixel format is YUV or UYVY divide the width
1775 * of the image by 2 for 0 degree and 180 degree
1776 */
1777 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1778 color_mode == OMAP_DSS_COLOR_UYVY)
1779 width = width >> 1;
1780 case OMAP_DSS_ROT_90 + 4:
1781 case OMAP_DSS_ROT_270 + 4:
1782 *offset1 = 0;
1783 if (field_offset)
1784 *offset0 = field_offset * screen_width * ps;
1785 else
1786 *offset0 = 0;
aed74b55
CM		 1787 *row_inc = pixinc(1 -
1788 (y_predecim * screen_width + x_predecim * width) -
1789 (fieldmode ? screen_width : 0), ps);
1790 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1791 break;
1792
1793 default:
1794 BUG();
c6eee968 1795 return;
80c39712
TV		 1796 }
1797}
1798
1799static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1800 u16 screen_width,
1801 u16 width, u16 height,
1802 enum omap_color_mode color_mode, bool fieldmode,
1803 unsigned int field_offset,
1804 unsigned *offset0, unsigned *offset1,
aed74b55 1805 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1806{
1807 u8 ps;
1808 u16 fbw, fbh;
1809
1810 /* FIXME CLUT formats */
1811 switch (color_mode) {
1812 case OMAP_DSS_COLOR_CLUT1:
1813 case OMAP_DSS_COLOR_CLUT2:
1814 case OMAP_DSS_COLOR_CLUT4:
1815 case OMAP_DSS_COLOR_CLUT8:
1816 BUG();
1817 return;
1818 default:
1819 ps = color_mode_to_bpp(color_mode) / 8;
1820 break;
1821 }
1822
1823 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1824 width, height);
1825
1826 /* width & height are overlay sizes, convert to fb sizes */
1827
1828 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1829 fbw = width;
1830 fbh = height;
1831 } else {
1832 fbw = height;
1833 fbh = width;
1834 }
1835
1836 /*
1837 * field 0 = even field = bottom field
1838 * field 1 = odd field = top field
1839 */
1840 switch (rotation + mirror * 4) {
1841 case OMAP_DSS_ROT_0:
1842 *offset1 = 0;
1843 if (field_offset)
1844 *offset0 = *offset1 + field_offset * screen_width * ps;
1845 else
1846 *offset0 = *offset1;
aed74b55
CM		 1847 *row_inc = pixinc(1 +
1848 (y_predecim * screen_width - fbw * x_predecim) +
1849 (fieldmode ? screen_width : 0), ps);
1850 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1851 color_mode == OMAP_DSS_COLOR_UYVY)
1852 *pix_inc = pixinc(x_predecim, 2 * ps);
1853 else
1854 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1855 break;
1856 case OMAP_DSS_ROT_90:
1857 *offset1 = screen_width * (fbh - 1) * ps;
1858 if (field_offset)
1859 *offset0 = *offset1 + field_offset * ps;
1860 else
1861 *offset0 = *offset1;
aed74b55
CM		 1862 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1863 y_predecim + (fieldmode ? 1 : 0), ps);
1864 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1865 break;
1866 case OMAP_DSS_ROT_180:
1867 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1868 if (field_offset)
1869 *offset0 = *offset1 - field_offset * screen_width * ps;
1870 else
1871 *offset0 = *offset1;
1872 *row_inc = pixinc(-1 -
aed74b55
CM		 1873 (y_predecim * screen_width - fbw * x_predecim) -
1874 (fieldmode ? screen_width : 0), ps);
1875 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1876 color_mode == OMAP_DSS_COLOR_UYVY)
1877 *pix_inc = pixinc(-x_predecim, 2 * ps);
1878 else
1879 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1880 break;
1881 case OMAP_DSS_ROT_270:
1882 *offset1 = (fbw - 1) * ps;
1883 if (field_offset)
1884 *offset0 = *offset1 - field_offset * ps;
1885 else
1886 *offset0 = *offset1;
aed74b55
CM		 1887 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1888 y_predecim - (fieldmode ? 1 : 0), ps);
1889 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1890 break;
1891
1892 /* mirroring */
1893 case OMAP_DSS_ROT_0 + 4:
1894 *offset1 = (fbw - 1) * ps;
1895 if (field_offset)
1896 *offset0 = *offset1 + field_offset * screen_width * ps;
1897 else
1898 *offset0 = *offset1;
aed74b55 1899 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1900 (fieldmode ? screen_width : 0),
1901 ps);
aed74b55
CM		 1902 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1903 color_mode == OMAP_DSS_COLOR_UYVY)
1904 *pix_inc = pixinc(-x_predecim, 2 * ps);
1905 else
1906 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1907 break;
1908
1909 case OMAP_DSS_ROT_90 + 4:
1910 *offset1 = 0;
1911 if (field_offset)
1912 *offset0 = *offset1 + field_offset * ps;
1913 else
1914 *offset0 = *offset1;
aed74b55
CM		 1915 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1916 y_predecim + (fieldmode ? 1 : 0),
80c39712 1917 ps);
aed74b55 1918 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1919 break;
1920
1921 case OMAP_DSS_ROT_180 + 4:
1922 *offset1 = screen_width * (fbh - 1) * ps;
1923 if (field_offset)
1924 *offset0 = *offset1 - field_offset * screen_width * ps;
1925 else
1926 *offset0 = *offset1;
aed74b55 1927 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1928 (fieldmode ? screen_width : 0),
1929 ps);
aed74b55
CM		 1930 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1931 color_mode == OMAP_DSS_COLOR_UYVY)
1932 *pix_inc = pixinc(x_predecim, 2 * ps);
1933 else
1934 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1935 break;
1936
1937 case OMAP_DSS_ROT_270 + 4:
1938 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1939 if (field_offset)
1940 *offset0 = *offset1 - field_offset * ps;
1941 else
1942 *offset0 = *offset1;
aed74b55
CM		 1943 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1944 y_predecim - (fieldmode ? 1 : 0),
80c39712 1945 ps);
aed74b55 1946 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1947 break;
1948
1949 default:
1950 BUG();
c6eee968 1951 return;
80c39712
TV		 1952 }
1953}
1954
65e006ff
CM		 1955static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1956 enum omap_color_mode color_mode, bool fieldmode,
1957 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1958 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1959{
1960 u8 ps;
1961
1962 switch (color_mode) {
1963 case OMAP_DSS_COLOR_CLUT1:
1964 case OMAP_DSS_COLOR_CLUT2:
1965 case OMAP_DSS_COLOR_CLUT4:
1966 case OMAP_DSS_COLOR_CLUT8:
1967 BUG();
1968 return;
1969 default:
1970 ps = color_mode_to_bpp(color_mode) / 8;
1971 break;
1972 }
1973
1974 DSSDBG("scrw %d, width %d\n", screen_width, width);
1975
1976 /*
1977 * field 0 = even field = bottom field
1978 * field 1 = odd field = top field
1979 */
1980 *offset1 = 0;
1981 if (field_offset)
1982 *offset0 = *offset1 + field_offset * screen_width * ps;
1983 else
1984 *offset0 = *offset1;
1985 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1986 (fieldmode ? screen_width : 0), ps);
1987 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1988 color_mode == OMAP_DSS_COLOR_UYVY)
1989 *pix_inc = pixinc(x_predecim, 2 * ps);
1990 else
1991 *pix_inc = pixinc(x_predecim, ps);
1992}
1993
7faa9233
CM		 1994/*
1995 * This function is used to avoid synclosts in OMAP3, because of some
1996 * undocumented horizontal position and timing related limitations.
1997 */
3e8a6ff2 1998static int check_horiz_timing_omap3(enum omap_plane plane,
81ab95b7 1999 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 2000 u16 width, u16 height, u16 out_width, u16 out_height)
2001{
2002 int DS = DIV_ROUND_UP(height, out_height);
3e8a6ff2 2003 unsigned long nonactive;
7faa9233
CM		 2004 static const u8 limits[3] = { 8, 10, 20 };
2005 u64 val, blank;
3e8a6ff2
AT		 2006 unsigned long pclk = dispc_plane_pclk_rate(plane);
2007 unsigned long lclk = dispc_plane_lclk_rate(plane);
7faa9233
CM		 2008 int i;
2009
81ab95b7 2010 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 2011
2012 i = 0;
2013 if (out_height < height)
2014 i++;
2015 if (out_width < width)
2016 i++;
81ab95b7 2017 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 2018 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2019 if (blank <= limits[i])
2020 return -EINVAL;
2021
2022 /*
2023 * Pixel data should be prepared before visible display point starts.
2024 * So, atleast DS-2 lines must have already been fetched by DISPC
2025 * during nonactive - pos_x period.
2026 */
2027 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2028 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2029 val, max(0, DS - 2) * width);
2030 if (val < max(0, DS - 2) * width)
2031 return -EINVAL;
2032
2033 /*
2034 * All lines need to be refilled during the nonactive period of which
2035 * only one line can be loaded during the active period. So, atleast
2036 * DS - 1 lines should be loaded during nonactive period.
2037 */
2038 val = div_u64((u64)nonactive * lclk, pclk);
2039 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2040 val, max(0, DS - 1) * width);
2041 if (val < max(0, DS - 1) * width)
2042 return -EINVAL;
2043
2044 return 0;
2045}
2046
3e8a6ff2 2047static unsigned long calc_core_clk_five_taps(enum omap_plane plane,
81ab95b7
AT		 2048 const struct omap_video_timings *mgr_timings, u16 width,
2049 u16 height, u16 out_width, u16 out_height,
ff1b2cde 2050 enum omap_color_mode color_mode)
80c39712 2051{
8b53d991 2052 u32 core_clk = 0;
3e8a6ff2
AT		 2053 u64 tmp;
2054 unsigned long pclk = dispc_plane_pclk_rate(plane);
80c39712 2055
7282f1b7
CM		 2056 if (height <= out_height && width <= out_width)
2057 return (unsigned long) pclk;
2058
80c39712 2059 if (height > out_height) {
81ab95b7 2060 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 2061
2062 tmp = pclk * height * out_width;
2063 do_div(tmp, 2 * out_height * ppl);
8b53d991 2064 core_clk = tmp;
80c39712 2065
2d9c5597
VS		 2066 if (height > 2 * out_height) {
2067 if (ppl == out_width)
2068 return 0;
2069
80c39712
TV		 2070 tmp = pclk * (height - 2 * out_height) * out_width;
2071 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 2072 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2073 }
2074 }
2075
2076 if (width > out_width) {
2077 tmp = pclk * width;
2078 do_div(tmp, out_width);
8b53d991 2079 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 2080
2081 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 2082 core_clk <<= 1;
80c39712
TV		 2083 }
2084
8b53d991 2085 return core_clk;
80c39712
TV		 2086}
2087
3e8a6ff2 2088static unsigned long calc_core_clk_24xx(enum omap_plane plane, u16 width,
8ba85306 2089 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2090{
3e8a6ff2 2091 unsigned long pclk = dispc_plane_pclk_rate(plane);
dcbe765b
CM		 2092
2093 if (height > out_height && width > out_width)
2094 return pclk * 4;
2095 else
2096 return pclk * 2;
2097}
2098
3e8a6ff2 2099static unsigned long calc_core_clk_34xx(enum omap_plane plane, u16 width,
8ba85306 2100 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
80c39712
TV		 2101{
2102 unsigned int hf, vf;
3e8a6ff2 2103 unsigned long pclk = dispc_plane_pclk_rate(plane);
80c39712
TV		 2104
2105 /*
2106 * FIXME how to determine the 'A' factor
2107 * for the no downscaling case ?
2108 */
2109
2110 if (width > 3 * out_width)
2111 hf = 4;
2112 else if (width > 2 * out_width)
2113 hf = 3;
2114 else if (width > out_width)
2115 hf = 2;
2116 else
2117 hf = 1;
80c39712
TV		 2118 if (height > out_height)
2119 vf = 2;
2120 else
2121 vf = 1;
2122
dcbe765b
CM		 2123 return pclk * vf * hf;
2124}
2125
3e8a6ff2 2126static unsigned long calc_core_clk_44xx(enum omap_plane plane, u16 width,
8ba85306 2127 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
dcbe765b 2128{
8ba85306
AT		 2129 unsigned long pclk;
2130
2131 /*
2132 * If the overlay/writeback is in mem to mem mode, there are no
2133 * downscaling limitations with respect to pixel clock, return 1 as
2134 * required core clock to represent that we have sufficient enough
2135 * core clock to do maximum downscaling
2136 */
2137 if (mem_to_mem)
2138 return 1;
2139
2140 pclk = dispc_plane_pclk_rate(plane);
dcbe765b
CM		 2141
2142 if (width > out_width)
2143 return DIV_ROUND_UP(pclk, out_width) * width;
2144 else
2145 return pclk;
2146}
2147
3e8a6ff2 2148static int dispc_ovl_calc_scaling_24xx(enum omap_plane plane,
dcbe765b
CM		 2149 const struct omap_video_timings *mgr_timings,
2150 u16 width, u16 height, u16 out_width, u16 out_height,
2151 enum omap_color_mode color_mode, bool *five_taps,
2152 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2153 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2154{
2155 int error;
2156 u16 in_width, in_height;
2157 int min_factor = min(*decim_x, *decim_y);
2158 const int maxsinglelinewidth =
2159 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2160
dcbe765b
CM		 2161 *five_taps = false;
2162
2163 do {
2164 in_height = DIV_ROUND_UP(height, *decim_y);
2165 in_width = DIV_ROUND_UP(width, *decim_x);
3e8a6ff2 2166 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
8ba85306 2167 in_height, out_width, out_height, mem_to_mem);
dcbe765b
CM		 2168 error = (in_width > maxsinglelinewidth || !*core_clk ||
2169 *core_clk > dispc_core_clk_rate());
2170 if (error) {
2171 if (*decim_x == *decim_y) {
2172 *decim_x = min_factor;
2173 ++*decim_y;
2174 } else {
2175 swap(*decim_x, *decim_y);
2176 if (*decim_x < *decim_y)
2177 ++*decim_x;
2178 }
2179 }
2180 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2181
2182 if (in_width > maxsinglelinewidth) {
2183 DSSERR("Cannot scale max input width exceeded");
2184 return -EINVAL;
2185 }
2186 return 0;
2187}
2188
3e8a6ff2 2189static int dispc_ovl_calc_scaling_34xx(enum omap_plane plane,
dcbe765b
CM		 2190 const struct omap_video_timings *mgr_timings,
2191 u16 width, u16 height, u16 out_width, u16 out_height,
2192 enum omap_color_mode color_mode, bool *five_taps,
2193 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2194 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2195{
2196 int error;
2197 u16 in_width, in_height;
2198 int min_factor = min(*decim_x, *decim_y);
2199 const int maxsinglelinewidth =
2200 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2201
2202 do {
2203 in_height = DIV_ROUND_UP(height, *decim_y);
2204 in_width = DIV_ROUND_UP(width, *decim_x);
3e8a6ff2 2205 *core_clk = calc_core_clk_five_taps(plane, mgr_timings,
dcbe765b
CM		 2206 in_width, in_height, out_width, out_height, color_mode);
2207
3e8a6ff2
AT		 2208 error = check_horiz_timing_omap3(plane, mgr_timings,
2209 pos_x, in_width, in_height, out_width,
2210 out_height);
dcbe765b
CM		 2211
2212 if (in_width > maxsinglelinewidth)
2213 if (in_height > out_height &&
2214 in_height < out_height * 2)
2215 *five_taps = false;
2216 if (!*five_taps)
3e8a6ff2 2217 *core_clk = dispc.feat->calc_core_clk(plane, in_width,
8ba85306
AT		 2218 in_height, out_width, out_height,
2219 mem_to_mem);
dcbe765b
CM		 2220
2221 error = (error || in_width > maxsinglelinewidth * 2 ||
2222 (in_width > maxsinglelinewidth && *five_taps) ||
2223 !*core_clk || *core_clk > dispc_core_clk_rate());
2224 if (error) {
2225 if (*decim_x == *decim_y) {
2226 *decim_x = min_factor;
2227 ++*decim_y;
2228 } else {
2229 swap(*decim_x, *decim_y);
2230 if (*decim_x < *decim_y)
2231 ++*decim_x;
2232 }
2233 }
2234 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2235
3e8a6ff2 2236 if (check_horiz_timing_omap3(plane, mgr_timings, pos_x, width, height,
dcbe765b
CM		 2237 out_width, out_height)){
2238 DSSERR("horizontal timing too tight\n");
2239 return -EINVAL;
7282f1b7 2240 }
dcbe765b
CM		 2241
2242 if (in_width > (maxsinglelinewidth * 2)) {
2243 DSSERR("Cannot setup scaling");
2244 DSSERR("width exceeds maximum width possible");
2245 return -EINVAL;
2246 }
2247
2248 if (in_width > maxsinglelinewidth && *five_taps) {
2249 DSSERR("cannot setup scaling with five taps");
2250 return -EINVAL;
2251 }
2252 return 0;
2253}
2254
3e8a6ff2 2255static int dispc_ovl_calc_scaling_44xx(enum omap_plane plane,
dcbe765b
CM		 2256 const struct omap_video_timings *mgr_timings,
2257 u16 width, u16 height, u16 out_width, u16 out_height,
2258 enum omap_color_mode color_mode, bool *five_taps,
2259 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
8ba85306 2260 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
dcbe765b
CM		 2261{
2262 u16 in_width, in_width_max;
2263 int decim_x_min = *decim_x;
2264 u16 in_height = DIV_ROUND_UP(height, *decim_y);
2265 const int maxsinglelinewidth =
2266 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
3e8a6ff2 2267 unsigned long pclk = dispc_plane_pclk_rate(plane);
8ba85306 2268 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
3e8a6ff2 2269
8ba85306
AT		 2270 if (mem_to_mem)
2271 in_width_max = DIV_ROUND_UP(out_width, maxdownscale);
2272 else
2273 in_width_max = dispc_core_clk_rate() /
2274 DIV_ROUND_UP(pclk, out_width);
dcbe765b 2275
dcbe765b
CM		 2276 *decim_x = DIV_ROUND_UP(width, in_width_max);
2277
2278 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2279 if (*decim_x > *x_predecim)
2280 return -EINVAL;
2281
2282 do {
2283 in_width = DIV_ROUND_UP(width, *decim_x);
2284 } while (*decim_x <= *x_predecim &&
2285 in_width > maxsinglelinewidth && ++*decim_x);
2286
2287 if (in_width > maxsinglelinewidth) {
2288 DSSERR("Cannot scale width exceeds max line width");
2289 return -EINVAL;
2290 }
2291
3e8a6ff2 2292 *core_clk = dispc.feat->calc_core_clk(plane, in_width, in_height,
8ba85306 2293 out_width, out_height, mem_to_mem);
dcbe765b 2294 return 0;
80c39712
TV		 2295}
2296
79ad75f2 2297static int dispc_ovl_calc_scaling(enum omap_plane plane,
3e8a6ff2 2298 enum omap_overlay_caps caps,
81ab95b7
AT		 2299 const struct omap_video_timings *mgr_timings,
2300 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 2301 enum omap_color_mode color_mode, bool *five_taps,
d557a9cf 2302 int *x_predecim, int *y_predecim, u16 pos_x,
8ba85306 2303 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
79ad75f2 2304{
0373cac6 2305 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
aed74b55 2306 const int max_decim_limit = 16;
8b53d991 2307 unsigned long core_clk = 0;
dcbe765b 2308 int decim_x, decim_y, ret;
79ad75f2 2309
f95cb5eb
TV		 2310 if (width == out_width && height == out_height)
2311 return 0;
2312
5b54ed3e 2313 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
f95cb5eb 2314 return -EINVAL;
79ad75f2 2315
aed74b55 2316 *x_predecim = max_decim_limit;
d557a9cf
CM		 2317 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2318 dss_has_feature(FEAT_BURST_2D)) ? 2 : max_decim_limit;
aed74b55
CM		 2319
2320 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2321 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2322 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2323 color_mode == OMAP_DSS_COLOR_CLUT8) {
2324 *x_predecim = 1;
2325 *y_predecim = 1;
2326 *five_taps = false;
2327 return 0;
2328 }
2329
2330 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2331 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2332
aed74b55 2333 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 2334 return -EINVAL;
2335
aed74b55 2336 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 2337 return -EINVAL;
2338
3e8a6ff2
AT		 2339 ret = dispc.feat->calc_scaling(plane, mgr_timings, width, height,
2340 out_width, out_height, color_mode, five_taps,
8ba85306
AT		 2341 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2342 mem_to_mem);
dcbe765b
CM		 2343 if (ret)
2344 return ret;
79ad75f2 2345
8b53d991
CM		 2346 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2347 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 2348
8b53d991 2349 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 2350 DSSERR("failed to set up scaling, "
8b53d991
CM		 2351 "required core clk rate = %lu Hz, "
2352 "current core clk rate = %lu Hz\n",
2353 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 2354 return -EINVAL;
2355 }
2356
aed74b55
CM		 2357 *x_predecim = decim_x;
2358 *y_predecim = decim_y;
79ad75f2
AT		 2359 return 0;
2360}
2361
84a880fd 2362static int dispc_ovl_setup_common(enum omap_plane plane,
3e8a6ff2
AT		 2363 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2364 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2365 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2366 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2367 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
8ba85306
AT		 2368 bool replication, const struct omap_video_timings *mgr_timings,
2369 bool mem_to_mem)
80c39712 2370{
7282f1b7 2371 bool five_taps = true;
80c39712 2372 bool fieldmode = 0;
79ad75f2 2373 int r, cconv = 0;
80c39712
TV		 2374 unsigned offset0, offset1;
2375 s32 row_inc;
2376 s32 pix_inc;
84a880fd 2377 u16 frame_height = height;
80c39712 2378 unsigned int field_offset = 0;
84a880fd
AT		 2379 u16 in_height = height;
2380 u16 in_width = width;
aed74b55 2381 int x_predecim = 1, y_predecim = 1;
8050cbe4 2382 bool ilace = mgr_timings->interlace;
e6d80f95 2383
84a880fd 2384 if (paddr == 0)
80c39712
TV		 2385 return -EINVAL;
2386
84a880fd
AT		 2387 out_width = out_width == 0 ? width : out_width;
2388 out_height = out_height == 0 ? height : out_height;
cf073668 2389
84a880fd 2390 if (ilace && height == out_height)
80c39712
TV		 2391 fieldmode = 1;
2392
2393 if (ilace) {
2394 if (fieldmode)
aed74b55 2395 in_height /= 2;
8eeb7019 2396 pos_y /= 2;
aed74b55 2397 out_height /= 2;
80c39712
TV		 2398
2399 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
84a880fd
AT		 2400 "out_height %d\n", in_height, pos_y,
2401 out_height);
80c39712
TV		 2402 }
2403
84a880fd 2404 if (!dss_feat_color_mode_supported(plane, color_mode))
8dad2ab6
AT		 2405 return -EINVAL;
2406
3e8a6ff2 2407 r = dispc_ovl_calc_scaling(plane, caps, mgr_timings, in_width,
84a880fd
AT		 2408 in_height, out_width, out_height, color_mode,
2409 &five_taps, &x_predecim, &y_predecim, pos_x,
8ba85306 2410 rotation_type, mem_to_mem);
79ad75f2
AT		 2411 if (r)
2412 return r;
80c39712 2413
aed74b55
CM		 2414 in_width = DIV_ROUND_UP(in_width, x_predecim);
2415 in_height = DIV_ROUND_UP(in_height, y_predecim);
2416
84a880fd
AT		 2417 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2418 color_mode == OMAP_DSS_COLOR_UYVY ||
2419 color_mode == OMAP_DSS_COLOR_NV12)
79ad75f2 2420 cconv = 1;
80c39712
TV		 2421
2422 if (ilace && !fieldmode) {
2423 /*
2424 * when downscaling the bottom field may have to start several
2425 * source lines below the top field. Unfortunately ACCUI
2426 * registers will only hold the fractional part of the offset
2427 * so the integer part must be added to the base address of the
2428 * bottom field.
2429 */
aed74b55 2430 if (!in_height || in_height == out_height)
80c39712
TV		 2431 field_offset = 0;
2432 else
aed74b55 2433 field_offset = in_height / out_height / 2;
80c39712
TV		 2434 }
2435
2436 /* Fields are independent but interleaved in memory. */
2437 if (fieldmode)
2438 field_offset = 1;
2439
c6eee968
TV		 2440 offset0 = 0;
2441 offset1 = 0;
2442 row_inc = 0;
2443 pix_inc = 0;
2444
84a880fd
AT		 2445 if (rotation_type == OMAP_DSS_ROT_TILER)
2446 calc_tiler_rotation_offset(screen_width, in_width,
2447 color_mode, fieldmode, field_offset,
65e006ff
CM		 2448 &offset0, &offset1, &row_inc, &pix_inc,
2449 x_predecim, y_predecim);
84a880fd
AT		 2450 else if (rotation_type == OMAP_DSS_ROT_DMA)
2451 calc_dma_rotation_offset(rotation, mirror,
2452 screen_width, in_width, frame_height,
2453 color_mode, fieldmode, field_offset,
aed74b55
CM		 2454 &offset0, &offset1, &row_inc, &pix_inc,
2455 x_predecim, y_predecim);
80c39712 2456 else
84a880fd
AT		 2457 calc_vrfb_rotation_offset(rotation, mirror,
2458 screen_width, in_width, frame_height,
2459 color_mode, fieldmode, field_offset,
aed74b55
CM		 2460 &offset0, &offset1, &row_inc, &pix_inc,
2461 x_predecim, y_predecim);
80c39712
TV		 2462
2463 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2464 offset0, offset1, row_inc, pix_inc);
2465
84a880fd 2466 dispc_ovl_set_color_mode(plane, color_mode);
80c39712 2467
84a880fd 2468 dispc_ovl_configure_burst_type(plane, rotation_type);
65e006ff 2469
84a880fd
AT		 2470 dispc_ovl_set_ba0(plane, paddr + offset0);
2471 dispc_ovl_set_ba1(plane, paddr + offset1);
80c39712 2472
84a880fd
AT		 2473 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2474 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2475 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
0d66cbb5
AJ		 2476 }
2477
f0e5caab
TV		 2478 dispc_ovl_set_row_inc(plane, row_inc);
2479 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2480
84a880fd 2481 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
aed74b55 2482 in_height, out_width, out_height);
80c39712 2483
84a880fd 2484 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
80c39712 2485
78b687fc 2486 dispc_ovl_set_input_size(plane, in_width, in_height);
80c39712 2487
5b54ed3e 2488 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2489 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2490 out_height, ilace, five_taps, fieldmode,
84a880fd 2491 color_mode, rotation);
78b687fc 2492 dispc_ovl_set_output_size(plane, out_width, out_height);
f0e5caab 2493 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2494 }
2495
84a880fd 2496 dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
80c39712 2497
84a880fd
AT		 2498 dispc_ovl_set_zorder(plane, caps, zorder);
2499 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2500 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
80c39712 2501
d79db853 2502 dispc_ovl_enable_replication(plane, caps, replication);
c3d92529 2503
80c39712
TV		 2504 return 0;
2505}
2506
84a880fd 2507int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
8ba85306
AT		 2508 bool replication, const struct omap_video_timings *mgr_timings,
2509 bool mem_to_mem)
84a880fd
AT		 2510{
2511 int r;
16bf20c7 2512 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
84a880fd
AT		 2513 enum omap_channel channel;
2514
2515 channel = dispc_ovl_get_channel_out(plane);
2516
2517 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2518 "%dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2519 plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
2520 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2521 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2522
16bf20c7 2523 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
3e8a6ff2
AT		 2524 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2525 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2526 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
8ba85306 2527 oi->rotation_type, replication, mgr_timings, mem_to_mem);
84a880fd
AT		 2528
2529 return r;
2530}
2531
749feffa 2532int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
9e4a0fc7 2533 bool mem_to_mem, const struct omap_video_timings *mgr_timings)
749feffa
AT		 2534{
2535 int r;
9e4a0fc7 2536 u32 l;
749feffa
AT		 2537 enum omap_plane plane = OMAP_DSS_WB;
2538 const int pos_x = 0, pos_y = 0;
2539 const u8 zorder = 0, global_alpha = 0;
2540 const bool replication = false;
9e4a0fc7 2541 bool truncation;
749feffa
AT		 2542 int in_width = mgr_timings->x_res;
2543 int in_height = mgr_timings->y_res;
2544 enum omap_overlay_caps caps =
2545 OMAP_DSS_OVL_CAP_SCALE | OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA;
2546
2547 DSSDBG("dispc_wb_setup, pa %x, pa_uv %x, %d,%d -> %dx%d, cmode %x, "
2548 "rot %d, mir %d\n", wi->paddr, wi->p_uv_addr, in_width,
2549 in_height, wi->width, wi->height, wi->color_mode, wi->rotation,
2550 wi->mirror);
2551
2552 r = dispc_ovl_setup_common(plane, caps, wi->paddr, wi->p_uv_addr,
2553 wi->buf_width, pos_x, pos_y, in_width, in_height, wi->width,
2554 wi->height, wi->color_mode, wi->rotation, wi->mirror, zorder,
2555 wi->pre_mult_alpha, global_alpha, wi->rotation_type,
9e4a0fc7
AT		 2556 replication, mgr_timings, mem_to_mem);
2557
2558 switch (wi->color_mode) {
2559 case OMAP_DSS_COLOR_RGB16:
2560 case OMAP_DSS_COLOR_RGB24P:
2561 case OMAP_DSS_COLOR_ARGB16:
2562 case OMAP_DSS_COLOR_RGBA16:
2563 case OMAP_DSS_COLOR_RGB12U:
2564 case OMAP_DSS_COLOR_ARGB16_1555:
2565 case OMAP_DSS_COLOR_XRGB16_1555:
2566 case OMAP_DSS_COLOR_RGBX16:
2567 truncation = true;
2568 break;
2569 default:
2570 truncation = false;
2571 break;
2572 }
2573
2574 /* setup extra DISPC_WB_ATTRIBUTES */
2575 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2576 l = FLD_MOD(l, truncation, 10, 10); /* TRUNCATIONENABLE */
2577 l = FLD_MOD(l, mem_to_mem, 19, 19); /* WRITEBACKMODE */
2578 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
749feffa
AT		 2579
2580 return r;
2581}
2582
f0e5caab 2583int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2584{
e6d80f95
TV		 2585 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2586
9b372c2d 2587 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2588
2589 return 0;
80c39712
TV		 2590}
2591
b1112249 2592static void dispc_mgr_disable_isr(void *data, u32 mask)
80c39712
TV		 2593{
2594 struct completion *compl = data;
2595 complete(compl);
2596}
2597
65398511 2598static void _enable_mgr_out(enum omap_channel channel, bool enable)
80c39712 2599{
efa70b3b
CM		 2600 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2601 /* flush posted write */
2602 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
80c39712
TV		 2603}
2604
65398511
TV		 2605bool dispc_mgr_is_enabled(enum omap_channel channel)
2606{
2607 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2608}
2609
b1112249 2610static void dispc_mgr_enable_lcd_out(enum omap_channel channel)
80c39712 2611{
b1112249
TV		 2612 _enable_mgr_out(channel, true);
2613}
2614
2615static void dispc_mgr_disable_lcd_out(enum omap_channel channel)
2616{
2617 DECLARE_COMPLETION_ONSTACK(framedone_compl);
80c39712 2618 int r;
2a205f34 2619 u32 irq;
80c39712 2620
b1112249
TV		 2621 if (dispc_mgr_is_enabled(channel) == false)
2622 return;
2a205f34 2623
b1112249
TV		 2624 /*
2625 * When we disable LCD output, we need to wait for FRAMEDONE to know
2626 * that DISPC has finished with the LCD output.
2627 */
80c39712 2628
b1112249 2629 irq = dispc_mgr_get_framedone_irq(channel);
80c39712 2630
b1112249
TV		 2631 r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
2632 irq);
2633 if (r)
2634 DSSERR("failed to register FRAMEDONE isr\n");
80c39712 2635
b1112249
TV		 2636 _enable_mgr_out(channel, false);
2637
2638 /* if we couldn't register for framedone, just sleep and exit */
2639 if (r) {
2640 msleep(100);
2641 return;
80c39712
TV		 2642 }
2643
b1112249
TV		 2644 if (!wait_for_completion_timeout(&framedone_compl,
2645 msecs_to_jiffies(100)))
2646 DSSERR("timeout waiting for FRAME DONE\n");
80c39712 2647
b1112249
TV		 2648 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
2649 irq);
2650 if (r)
2651 DSSERR("failed to unregister FRAMEDONE isr\n");
2652}
80c39712 2653
b1112249
TV		 2654static void dispc_digit_out_enable_isr(void *data, u32 mask)
2655{
2656 struct completion *compl = data;
80c39712 2657
b1112249
TV		 2658 /* ignore any sync lost interrupts */
2659 if (mask & (DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD))
2660 complete(compl);
2661}
2662
2663static void dispc_mgr_enable_digit_out(void)
2664{
2665 DECLARE_COMPLETION_ONSTACK(vsync_compl);
2666 int r;
2667 u32 irq_mask;
2668
2669 if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == true)
2670 return;
2671
2672 /*
2673 * Digit output produces some sync lost interrupts during the first
2674 * frame when enabling. Those need to be ignored, so we register for the
2675 * sync lost irq to prevent the error handler from triggering.
2676 */
2677
2678 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT) |
2679 dispc_mgr_get_sync_lost_irq(OMAP_DSS_CHANNEL_DIGIT);
2680
2681 r = omap_dispc_register_isr(dispc_digit_out_enable_isr, &vsync_compl,
2682 irq_mask);
2683 if (r) {
2684 DSSERR("failed to register %x isr\n", irq_mask);
2685 return;
80c39712 2686 }
b1112249
TV		 2687
2688 _enable_mgr_out(OMAP_DSS_CHANNEL_DIGIT, true);
2689
2690 /* wait for the first evsync */
2691 if (!wait_for_completion_timeout(&vsync_compl, msecs_to_jiffies(100)))
2692 DSSERR("timeout waiting for digit out to start\n");
2693
2694 r = omap_dispc_unregister_isr(dispc_digit_out_enable_isr, &vsync_compl,
2695 irq_mask);
2696 if (r)
2697 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2698}
2699
b1112249 2700static void dispc_mgr_disable_digit_out(void)
80c39712 2701{
b1112249 2702 DECLARE_COMPLETION_ONSTACK(framedone_compl);
e82b090b
TV		 2703 enum dss_hdmi_venc_clk_source_select src;
2704 int r, i;
2705 u32 irq_mask;
2706 int num_irqs;
80c39712 2707
b1112249 2708 if (dispc_mgr_is_enabled(OMAP_DSS_CHANNEL_DIGIT) == false)
80c39712 2709 return;
80c39712 2710
e82b090b
TV		 2711 src = dss_get_hdmi_venc_clk_source();
2712
b1112249
TV		 2713 /*
2714 * When we disable the digit output, we need to wait for FRAMEDONE to
2715 * know that DISPC has finished with the output. For analog tv out we'll
2716 * use vsync, as omap2/3 don't have framedone for TV.
2717 */
80c39712 2718
b1112249 2719 if (src == DSS_HDMI_M_PCLK) {
e82b090b
TV		 2720 irq_mask = DISPC_IRQ_FRAMEDONETV;
2721 num_irqs = 1;
2722 } else {
b1112249
TV		 2723 irq_mask = dispc_mgr_get_vsync_irq(OMAP_DSS_CHANNEL_DIGIT);
2724 /*
2725 * We need to wait for both even and odd vsyncs. Note that this
2726 * is not totally reliable, as we could get a vsync interrupt
2727 * before we disable the output, which leads to timeout in the
2728 * wait_for_completion.
2729 */
e82b090b
TV		 2730 num_irqs = 2;
2731 }
2732
b1112249 2733 r = omap_dispc_register_isr(dispc_mgr_disable_isr, &framedone_compl,
e82b090b 2734 irq_mask);
80c39712 2735 if (r)
e82b090b 2736 DSSERR("failed to register %x isr\n", irq_mask);
80c39712 2737
b1112249
TV		 2738 _enable_mgr_out(OMAP_DSS_CHANNEL_DIGIT, false);
2739
2740 /* if we couldn't register the irq, just sleep and exit */
2741 if (r) {
2742 msleep(100);
2743 return;
2744 }
80c39712 2745
e82b090b 2746 for (i = 0; i < num_irqs; ++i) {
b1112249 2747 if (!wait_for_completion_timeout(&framedone_compl,
e82b090b 2748 msecs_to_jiffies(100)))
b1112249 2749 DSSERR("timeout waiting for digit out to stop\n");
e82b090b 2750 }
80c39712 2751
b1112249 2752 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr, &framedone_compl,
e82b090b 2753 irq_mask);
80c39712 2754 if (r)
e82b090b 2755 DSSERR("failed to unregister %x isr\n", irq_mask);
b1112249 2756}
80c39712 2757
b1112249
TV		 2758void dispc_mgr_enable(enum omap_channel channel)
2759{
2760 if (dss_mgr_is_lcd(channel))
2761 dispc_mgr_enable_lcd_out(channel);
2762 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2763 dispc_mgr_enable_digit_out();
2764 else
2765 WARN_ON(1);
80c39712
TV		 2766}
2767
b1112249 2768void dispc_mgr_disable(enum omap_channel channel)
a2faee84 2769{
dd88b7a6 2770 if (dss_mgr_is_lcd(channel))
b1112249 2771 dispc_mgr_disable_lcd_out(channel);
a2faee84 2772 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
b1112249 2773 dispc_mgr_disable_digit_out();
a2faee84 2774 else
b1112249 2775 WARN_ON(1);
a2faee84
TV		 2776}
2777
0b23e5b8
AT		 2778void dispc_wb_enable(bool enable)
2779{
2780 enum omap_plane plane = OMAP_DSS_WB;
2781 struct completion frame_done_completion;
2782 bool is_on;
2783 int r;
2784 u32 irq;
2785
2786 is_on = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2787 irq = DISPC_IRQ_FRAMEDONEWB;
2788
2789 if (!enable && is_on) {
2790 init_completion(&frame_done_completion);
2791
b1112249 2792 r = omap_dispc_register_isr(dispc_mgr_disable_isr,
0b23e5b8
AT		 2793 &frame_done_completion, irq);
2794 if (r)
2795 DSSERR("failed to register FRAMEDONEWB isr\n");
2796 }
2797
2798 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2799
2800 if (!enable && is_on) {
2801 if (!wait_for_completion_timeout(&frame_done_completion,
2802 msecs_to_jiffies(100)))
2803 DSSERR("timeout waiting for FRAMEDONEWB\n");
2804
b1112249 2805 r = omap_dispc_unregister_isr(dispc_mgr_disable_isr,
0b23e5b8
AT		 2806 &frame_done_completion, irq);
2807 if (r)
2808 DSSERR("failed to unregister FRAMEDONEWB isr\n");
2809 }
2810}
2811
2812bool dispc_wb_is_enabled(void)
2813{
2814 enum omap_plane plane = OMAP_DSS_WB;
2815
2816 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2817}
2818
fb2cec1f 2819static void dispc_lcd_enable_signal_polarity(bool act_high)
80c39712 2820{
6ced40bf
AT		 2821 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2822 return;
2823
80c39712 2824 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2825}
2826
2827void dispc_lcd_enable_signal(bool enable)
2828{
6ced40bf
AT		 2829 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2830 return;
2831
80c39712 2832 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2833}
2834
2835void dispc_pck_free_enable(bool enable)
2836{
6ced40bf
AT		 2837 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2838 return;
2839
80c39712 2840 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2841}
2842
fb2cec1f 2843static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2844{
efa70b3b 2845 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
80c39712
TV		 2846}
2847
2848
fb2cec1f 2849static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
80c39712 2850{
d21f43bc 2851 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
80c39712
TV		 2852}
2853
2854void dispc_set_loadmode(enum omap_dss_load_mode mode)
2855{
80c39712 2856 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2857}
2858
2859
c64dca40 2860static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2861{
8613b000 2862 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2863}
2864
c64dca40 2865static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2866 enum omap_dss_trans_key_type type,
2867 u32 trans_key)
2868{
efa70b3b 2869 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
80c39712 2870
8613b000 2871 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2872}
2873
c64dca40 2874static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2875{
efa70b3b 2876 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
80c39712 2877}
11354dd5 2878
c64dca40
TV		 2879static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2880 bool enable)
80c39712 2881{
11354dd5 2882 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2883 return;
2884
80c39712
TV		 2885 if (ch == OMAP_DSS_CHANNEL_LCD)
2886 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2887 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2888 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2889}
11354dd5 2890
c64dca40 2891void dispc_mgr_setup(enum omap_channel channel,
a8f3fcd1 2892 const struct omap_overlay_manager_info *info)
c64dca40
TV		 2893{
2894 dispc_mgr_set_default_color(channel, info->default_color);
2895 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2896 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2897 dispc_mgr_enable_alpha_fixed_zorder(channel,
2898 info->partial_alpha_enabled);
2899 if (dss_has_feature(FEAT_CPR)) {
2900 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2901 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2902 }
2903}
80c39712 2904
fb2cec1f 2905static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2906{
2907 int code;
2908
2909 switch (data_lines) {
2910 case 12:
2911 code = 0;
2912 break;
2913 case 16:
2914 code = 1;
2915 break;
2916 case 18:
2917 code = 2;
2918 break;
2919 case 24:
2920 code = 3;
2921 break;
2922 default:
2923 BUG();
2924 return;
2925 }
2926
efa70b3b 2927 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
80c39712
TV		 2928}
2929
fb2cec1f 2930static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2931{
2932 u32 l;
569969d6 2933 int gpout0, gpout1;
80c39712
TV		 2934
2935 switch (mode) {
569969d6
AT		 2936 case DSS_IO_PAD_MODE_RESET:
2937 gpout0 = 0;
2938 gpout1 = 0;
80c39712 2939 break;
569969d6
AT		 2940 case DSS_IO_PAD_MODE_RFBI:
2941 gpout0 = 1;
80c39712
TV		 2942 gpout1 = 0;
2943 break;
569969d6
AT		 2944 case DSS_IO_PAD_MODE_BYPASS:
2945 gpout0 = 1;
80c39712
TV		 2946 gpout1 = 1;
2947 break;
80c39712
TV		 2948 default:
2949 BUG();
2950 return;
2951 }
2952
569969d6
AT		 2953 l = dispc_read_reg(DISPC_CONTROL);
2954 l = FLD_MOD(l, gpout0, 15, 15);
2955 l = FLD_MOD(l, gpout1, 16, 16);
2956 dispc_write_reg(DISPC_CONTROL, l);
2957}
2958
fb2cec1f 2959static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
569969d6 2960{
efa70b3b 2961 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
80c39712
TV		 2962}
2963
fb2cec1f
TV		 2964void dispc_mgr_set_lcd_config(enum omap_channel channel,
2965 const struct dss_lcd_mgr_config *config)
2966{
2967 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2968
2969 dispc_mgr_enable_stallmode(channel, config->stallmode);
2970 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2971
2972 dispc_mgr_set_clock_div(channel, &config->clock_info);
2973
2974 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2975
2976 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2977
2978 dispc_mgr_set_lcd_type_tft(channel);
2979}
2980
8f366162
AT		 2981static bool _dispc_mgr_size_ok(u16 width, u16 height)
2982{
2983 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2984 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2985}
2986
80c39712
TV		 2987static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2988 int vsw, int vfp, int vbp)
2989{
dcbe765b
CM		 2990 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2991 hfp < 1 || hfp > dispc.feat->hp_max ||
2992 hbp < 1 || hbp > dispc.feat->hp_max ||
2993 vsw < 1 || vsw > dispc.feat->sw_max ||
2994 vfp < 0 || vfp > dispc.feat->vp_max ||
2995 vbp < 0 || vbp > dispc.feat->vp_max)
2996 return false;
80c39712
TV		 2997 return true;
2998}
2999
8f366162 3000bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 3001 const struct omap_video_timings *timings)
80c39712 3002{
8f366162
AT		 3003 bool timings_ok;
3004
3005 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
3006
dd88b7a6 3007 if (dss_mgr_is_lcd(channel))
8f366162
AT		 3008 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
3009 timings->hfp, timings->hbp,
3010 timings->vsw, timings->vfp,
3011 timings->vbp);
3012
3013 return timings_ok;
80c39712
TV		 3014}
3015
26d9dd0d 3016static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
655e2941
AT		 3017 int hfp, int hbp, int vsw, int vfp, int vbp,
3018 enum omap_dss_signal_level vsync_level,
3019 enum omap_dss_signal_level hsync_level,
3020 enum omap_dss_signal_edge data_pclk_edge,
3021 enum omap_dss_signal_level de_level,
3022 enum omap_dss_signal_edge sync_pclk_edge)
3023
80c39712 3024{
655e2941
AT		 3025 u32 timing_h, timing_v, l;
3026 bool onoff, rf, ipc;
80c39712 3027
dcbe765b
CM		 3028 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3029 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3030 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3031 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3032 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3033 FLD_VAL(vbp, dispc.feat->bp_start, 20);
80c39712 3034
64ba4f74
SS		 3035 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3036 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
655e2941
AT		 3037
3038 switch (data_pclk_edge) {
3039 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3040 ipc = false;
3041 break;
3042 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3043 ipc = true;
3044 break;
3045 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
3046 default:
3047 BUG();
3048 }
3049
3050 switch (sync_pclk_edge) {
3051 case OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES:
3052 onoff = false;
3053 rf = false;
3054 break;
3055 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3056 onoff = true;
3057 rf = false;
3058 break;
3059 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3060 onoff = true;
3061 rf = true;
3062 break;
3063 default:
3064 BUG();
3065 };
3066
3067 l = dispc_read_reg(DISPC_POL_FREQ(channel));
3068 l |= FLD_VAL(onoff, 17, 17);
3069 l |= FLD_VAL(rf, 16, 16);
3070 l |= FLD_VAL(de_level, 15, 15);
3071 l |= FLD_VAL(ipc, 14, 14);
3072 l |= FLD_VAL(hsync_level, 13, 13);
3073 l |= FLD_VAL(vsync_level, 12, 12);
3074 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 3075}
3076
3077/* change name to mode? */
c51d921a 3078void dispc_mgr_set_timings(enum omap_channel channel,
a8f3fcd1 3079 const struct omap_video_timings *timings)
80c39712
TV		 3080{
3081 unsigned xtot, ytot;
3082 unsigned long ht, vt;
2aefad49 3083 struct omap_video_timings t = *timings;
80c39712 3084
2aefad49 3085 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
80c39712 3086
2aefad49 3087 if (!dispc_mgr_timings_ok(channel, &t)) {
8f366162 3088 BUG();
c6eee968
TV		 3089 return;
3090 }
80c39712 3091
dd88b7a6 3092 if (dss_mgr_is_lcd(channel)) {
2aefad49 3093 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
655e2941
AT		 3094 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3095 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
80c39712 3096
2aefad49
AT		 3097 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3098 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
80c39712 3099
c51d921a
AT		 3100 ht = (timings->pixel_clock * 1000) / xtot;
3101 vt = (timings->pixel_clock * 1000) / xtot / ytot;
3102
3103 DSSDBG("pck %u\n", timings->pixel_clock);
3104 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2aefad49 3105 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
655e2941
AT		 3106 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3107 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3108 t.de_level, t.sync_pclk_edge);
80c39712 3109
c51d921a 3110 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2aefad49 3111 } else {
23c8f88e 3112 if (t.interlace == true)
2aefad49 3113 t.y_res /= 2;
c51d921a 3114 }
8f366162 3115
2aefad49 3116 dispc_mgr_set_size(channel, t.x_res, t.y_res);
80c39712
TV		 3117}
3118
26d9dd0d 3119static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 3120 u16 pck_div)
80c39712
TV		 3121{
3122 BUG_ON(lck_div < 1);
9eaaf207 3123 BUG_ON(pck_div < 1);
80c39712 3124
ce7fa5eb 3125 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 3126 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 3127}
3128
26d9dd0d 3129static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 3130 int *pck_div)
80c39712
TV		 3131{
3132 u32 l;
ce7fa5eb 3133 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3134 *lck_div = FLD_GET(l, 23, 16);
3135 *pck_div = FLD_GET(l, 7, 0);
3136}
3137
3138unsigned long dispc_fclk_rate(void)
3139{
a72b64b9 3140 struct platform_device *dsidev;
80c39712
TV		 3141 unsigned long r = 0;
3142
66534e8e 3143 switch (dss_get_dispc_clk_source()) {
89a35e51 3144 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 3145 r = clk_get_rate(dispc.dss_clk);
66534e8e 3146 break;
89a35e51 3147 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3148 dsidev = dsi_get_dsidev_from_id(0);
3149 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 3150 break;
5a8b572d
AT		 3151 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3152 dsidev = dsi_get_dsidev_from_id(1);
3153 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3154 break;
66534e8e
TA		 3155 default:
3156 BUG();
c6eee968 3157 return 0;
66534e8e
TA		 3158 }
3159
80c39712
TV		 3160 return r;
3161}
3162
26d9dd0d 3163unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 3164{
a72b64b9 3165 struct platform_device *dsidev;
80c39712
TV		 3166 int lcd;
3167 unsigned long r;
3168 u32 l;
3169
ce7fa5eb 3170 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 3171
3172 lcd = FLD_GET(l, 23, 16);
3173
ea75159e 3174 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 3175 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 3176 r = clk_get_rate(dispc.dss_clk);
ea75159e 3177 break;
89a35e51 3178 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 3179 dsidev = dsi_get_dsidev_from_id(0);
3180 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 3181 break;
5a8b572d
AT		 3182 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3183 dsidev = dsi_get_dsidev_from_id(1);
3184 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
3185 break;
ea75159e
TA		 3186 default:
3187 BUG();
c6eee968 3188 return 0;
ea75159e 3189 }
80c39712
TV		 3190
3191 return r / lcd;
3192}
3193
26d9dd0d 3194unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 3195{
80c39712 3196 unsigned long r;
80c39712 3197
dd88b7a6 3198 if (dss_mgr_is_lcd(channel)) {
c3dc6a7a
AT		 3199 int pcd;
3200 u32 l;
80c39712 3201
c3dc6a7a 3202 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 3203
c3dc6a7a 3204 pcd = FLD_GET(l, 7, 0);
80c39712 3205
c3dc6a7a
AT		 3206 r = dispc_mgr_lclk_rate(channel);
3207
3208 return r / pcd;
3209 } else {
3fa03ba8 3210 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 3211
3fa03ba8
AT		 3212 source = dss_get_hdmi_venc_clk_source();
3213
3214 switch (source) {
3215 case DSS_VENC_TV_CLK:
c3dc6a7a 3216 return venc_get_pixel_clock();
3fa03ba8 3217 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 3218 return hdmi_get_pixel_clock();
3219 default:
3220 BUG();
c6eee968 3221 return 0;
c3dc6a7a
AT		 3222 }
3223 }
80c39712
TV		 3224}
3225
8b53d991
CM		 3226unsigned long dispc_core_clk_rate(void)
3227{
3228 int lcd;
3229 unsigned long fclk = dispc_fclk_rate();
3230
3231 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3232 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
3233 else
3234 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
3235
3236 return fclk / lcd;
3237}
3238
3e8a6ff2
AT		 3239static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3240{
3241 enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3242
3243 return dispc_mgr_pclk_rate(channel);
3244}
3245
3246static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3247{
3248 enum omap_channel channel = dispc_ovl_get_channel_out(plane);
3249
3250 if (dss_mgr_is_lcd(channel))
3251 return dispc_mgr_lclk_rate(channel);
3252 else
3253 return dispc_fclk_rate();
3254
3255}
6f1891fc 3256static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
80c39712
TV		 3257{
3258 int lcd, pcd;
6f1891fc
CM		 3259 enum omap_dss_clk_source lcd_clk_src;
3260
3261 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3262
3263 lcd_clk_src = dss_get_lcd_clk_source(channel);
3264
3265 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3266 dss_get_generic_clk_source_name(lcd_clk_src),
3267 dss_feat_get_clk_source_name(lcd_clk_src));
3268
3269 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3270
3271 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3272 dispc_mgr_lclk_rate(channel), lcd);
3273 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3274 dispc_mgr_pclk_rate(channel), pcd);
3275}
3276
3277void dispc_dump_clocks(struct seq_file *s)
3278{
3279 int lcd;
0cf35df3 3280 u32 l;
89a35e51 3281 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
80c39712 3282
4fbafaf3
TV		 3283 if (dispc_runtime_get())
3284 return;
80c39712 3285
80c39712
TV		 3286 seq_printf(s, "- DISPC -\n");
3287
067a57e4
AT		 3288 seq_printf(s, "dispc fclk source = %s (%s)\n",
3289 dss_get_generic_clk_source_name(dispc_clk_src),
3290 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 3291
3292 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 3293
0cf35df3
MR		 3294 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3295 seq_printf(s, "- DISPC-CORE-CLK -\n");
3296 l = dispc_read_reg(DISPC_DIVISOR);
3297 lcd = FLD_GET(l, 23, 16);
3298
3299 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3300 (dispc_fclk_rate()/lcd), lcd);
3301 }
2a205f34 3302
6f1891fc 3303 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
ea75159e 3304
6f1891fc
CM		 3305 if (dss_has_feature(FEAT_MGR_LCD2))
3306 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3307 if (dss_has_feature(FEAT_MGR_LCD3))
3308 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
4fbafaf3
TV		 3309
3310 dispc_runtime_put();
80c39712
TV		 3311}
3312
dfc0fd8d
TV		 3313#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3314void dispc_dump_irqs(struct seq_file *s)
3315{
3316 unsigned long flags;
3317 struct dispc_irq_stats stats;
3318
3319 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
3320
3321 stats = dispc.irq_stats;
3322 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
3323 dispc.irq_stats.last_reset = jiffies;
3324
3325 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
3326
3327 seq_printf(s, "period %u ms\n",
3328 jiffies_to_msecs(jiffies - stats.last_reset));
3329
3330 seq_printf(s, "irqs %d\n", stats.irq_count);
3331#define PIS(x) \
3332 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
3333
3334 PIS(FRAMEDONE);
3335 PIS(VSYNC);
3336 PIS(EVSYNC_EVEN);
3337 PIS(EVSYNC_ODD);
3338 PIS(ACBIAS_COUNT_STAT);
3339 PIS(PROG_LINE_NUM);
3340 PIS(GFX_FIFO_UNDERFLOW);
3341 PIS(GFX_END_WIN);
3342 PIS(PAL_GAMMA_MASK);
3343 PIS(OCP_ERR);
3344 PIS(VID1_FIFO_UNDERFLOW);
3345 PIS(VID1_END_WIN);
3346 PIS(VID2_FIFO_UNDERFLOW);
3347 PIS(VID2_END_WIN);
b8c095b4
AT		 3348 if (dss_feat_get_num_ovls() > 3) {
3349 PIS(VID3_FIFO_UNDERFLOW);
3350 PIS(VID3_END_WIN);
3351 }
dfc0fd8d
TV		 3352 PIS(SYNC_LOST);
3353 PIS(SYNC_LOST_DIGIT);
3354 PIS(WAKEUP);
2a205f34
SS		 3355 if (dss_has_feature(FEAT_MGR_LCD2)) {
3356 PIS(FRAMEDONE2);
3357 PIS(VSYNC2);
3358 PIS(ACBIAS_COUNT_STAT2);
3359 PIS(SYNC_LOST2);
3360 }
6f1891fc
CM		 3361 if (dss_has_feature(FEAT_MGR_LCD3)) {
3362 PIS(FRAMEDONE3);
3363 PIS(VSYNC3);
3364 PIS(ACBIAS_COUNT_STAT3);
3365 PIS(SYNC_LOST3);
3366 }
dfc0fd8d
TV		 3367#undef PIS
3368}
dfc0fd8d
TV		 3369#endif
3370
e40402cf 3371static void dispc_dump_regs(struct seq_file *s)
80c39712 3372{
4dd2da15
AT		 3373 int i, j;
3374 const char *mgr_names[] = {
3375 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3376 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3377 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
6f1891fc 3378 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
4dd2da15
AT		 3379 };
3380 const char *ovl_names[] = {
3381 [OMAP_DSS_GFX] = "GFX",
3382 [OMAP_DSS_VIDEO1] = "VID1",
3383 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 3384 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 3385 };
3386 const char **p_names;
3387
9b372c2d 3388#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 3389
4fbafaf3
TV		 3390 if (dispc_runtime_get())
3391 return;
80c39712 3392
5010be80 3393 /* DISPC common registers */
80c39712
TV		 3394 DUMPREG(DISPC_REVISION);
3395 DUMPREG(DISPC_SYSCONFIG);
3396 DUMPREG(DISPC_SYSSTATUS);
3397 DUMPREG(DISPC_IRQSTATUS);
3398 DUMPREG(DISPC_IRQENABLE);
3399 DUMPREG(DISPC_CONTROL);
3400 DUMPREG(DISPC_CONFIG);
3401 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 3402 DUMPREG(DISPC_LINE_STATUS);
3403 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 3404 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3405 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 3406 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 3407 if (dss_has_feature(FEAT_MGR_LCD2)) {
3408 DUMPREG(DISPC_CONTROL2);
3409 DUMPREG(DISPC_CONFIG2);
5010be80 3410 }
6f1891fc
CM		 3411 if (dss_has_feature(FEAT_MGR_LCD3)) {
3412 DUMPREG(DISPC_CONTROL3);
3413 DUMPREG(DISPC_CONFIG3);
3414 }
5010be80
AT		 3415
3416#undef DUMPREG
3417
3418#define DISPC_REG(i, name) name(i)
4dd2da15 3419#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
311d5ce8 3420 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
5010be80
AT		 3421 dispc_read_reg(DISPC_REG(i, r)))
3422
4dd2da15 3423 p_names = mgr_names;
5010be80 3424
4dd2da15
AT		 3425 /* DISPC channel specific registers */
3426 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3427 DUMPREG(i, DISPC_DEFAULT_COLOR);
3428 DUMPREG(i, DISPC_TRANS_COLOR);
3429 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 3430
4dd2da15
AT		 3431 if (i == OMAP_DSS_CHANNEL_DIGIT)
3432 continue;
5010be80 3433
4dd2da15
AT		 3434 DUMPREG(i, DISPC_DEFAULT_COLOR);
3435 DUMPREG(i, DISPC_TRANS_COLOR);
3436 DUMPREG(i, DISPC_TIMING_H);
3437 DUMPREG(i, DISPC_TIMING_V);
3438 DUMPREG(i, DISPC_POL_FREQ);
3439 DUMPREG(i, DISPC_DIVISORo);
3440 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 3441
4dd2da15
AT		 3442 DUMPREG(i, DISPC_DATA_CYCLE1);
3443 DUMPREG(i, DISPC_DATA_CYCLE2);
3444 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 3445
332e9d70 3446 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 3447 DUMPREG(i, DISPC_CPR_COEF_R);
3448 DUMPREG(i, DISPC_CPR_COEF_G);
3449 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 3450 }
2a205f34 3451 }
80c39712 3452
4dd2da15
AT		 3453 p_names = ovl_names;
3454
3455 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3456 DUMPREG(i, DISPC_OVL_BA0);
3457 DUMPREG(i, DISPC_OVL_BA1);
3458 DUMPREG(i, DISPC_OVL_POSITION);
3459 DUMPREG(i, DISPC_OVL_SIZE);
3460 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3461 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3462 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3463 DUMPREG(i, DISPC_OVL_ROW_INC);
3464 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3465 if (dss_has_feature(FEAT_PRELOAD))
3466 DUMPREG(i, DISPC_OVL_PRELOAD);
3467
3468 if (i == OMAP_DSS_GFX) {
3469 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3470 DUMPREG(i, DISPC_OVL_TABLE_BA);
3471 continue;
3472 }
3473
3474 DUMPREG(i, DISPC_OVL_FIR);
3475 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3476 DUMPREG(i, DISPC_OVL_ACCU0);
3477 DUMPREG(i, DISPC_OVL_ACCU1);
3478 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3479 DUMPREG(i, DISPC_OVL_BA0_UV);
3480 DUMPREG(i, DISPC_OVL_BA1_UV);
3481 DUMPREG(i, DISPC_OVL_FIR2);
3482 DUMPREG(i, DISPC_OVL_ACCU2_0);
3483 DUMPREG(i, DISPC_OVL_ACCU2_1);
3484 }
3485 if (dss_has_feature(FEAT_ATTR2))
3486 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3487 if (dss_has_feature(FEAT_PRELOAD))
3488 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 3489 }
5010be80
AT		 3490
3491#undef DISPC_REG
3492#undef DUMPREG
3493
3494#define DISPC_REG(plane, name, i) name(plane, i)
3495#define DUMPREG(plane, name, i) \
4dd2da15 3496 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
311d5ce8 3497 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
5010be80
AT		 3498 dispc_read_reg(DISPC_REG(plane, name, i)))
3499
4dd2da15 3500 /* Video pipeline coefficient registers */
332e9d70 3501
4dd2da15
AT		 3502 /* start from OMAP_DSS_VIDEO1 */
3503 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3504 for (j = 0; j < 8; j++)
3505 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 3506
4dd2da15
AT		 3507 for (j = 0; j < 8; j++)
3508 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 3509
4dd2da15
AT		 3510 for (j = 0; j < 5; j++)
3511 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 3512
4dd2da15
AT		 3513 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3514 for (j = 0; j < 8; j++)
3515 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3516 }
3517
3518 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3519 for (j = 0; j < 8; j++)
3520 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3521
3522 for (j = 0; j < 8; j++)
3523 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3524
3525 for (j = 0; j < 8; j++)
3526 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3527 }
332e9d70 3528 }
80c39712 3529
4fbafaf3 3530 dispc_runtime_put();
5010be80
AT		 3531
3532#undef DISPC_REG
80c39712
TV		 3533#undef DUMPREG
3534}
3535
80c39712 3536/* with fck as input clock rate, find dispc dividers that produce req_pck */
6d523e7b 3537void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
80c39712
TV		 3538 struct dispc_clock_info *cinfo)
3539{
9eaaf207 3540 u16 pcd_min, pcd_max;
80c39712
TV		 3541 unsigned long best_pck;
3542 u16 best_ld, cur_ld;
3543 u16 best_pd, cur_pd;
3544
9eaaf207
TV		 3545 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3546 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3547
80c39712
TV		 3548 best_pck = 0;
3549 best_ld = 0;
3550 best_pd = 0;
3551
3552 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3553 unsigned long lck = fck / cur_ld;
3554
9eaaf207 3555 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 3556 unsigned long pck = lck / cur_pd;
3557 long old_delta = abs(best_pck - req_pck);
3558 long new_delta = abs(pck - req_pck);
3559
3560 if (best_pck == 0 || new_delta < old_delta) {
3561 best_pck = pck;
3562 best_ld = cur_ld;
3563 best_pd = cur_pd;
3564
3565 if (pck == req_pck)
3566 goto found;
3567 }
3568
3569 if (pck < req_pck)
3570 break;
3571 }
3572
3573 if (lck / pcd_min < req_pck)
3574 break;
3575 }
3576
3577found:
3578 cinfo->lck_div = best_ld;
3579 cinfo->pck_div = best_pd;
3580 cinfo->lck = fck / cinfo->lck_div;
3581 cinfo->pck = cinfo->lck / cinfo->pck_div;
3582}
3583
3584/* calculate clock rates using dividers in cinfo */
3585int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3586 struct dispc_clock_info *cinfo)
3587{
3588 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3589 return -EINVAL;
9eaaf207 3590 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3591 return -EINVAL;
3592
3593 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3594 cinfo->pck = cinfo->lck / cinfo->pck_div;
3595
3596 return 0;
3597}
3598
f0d08f89 3599void dispc_mgr_set_clock_div(enum omap_channel channel,
a8f3fcd1 3600 const struct dispc_clock_info *cinfo)
80c39712
TV		 3601{
3602 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3603 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3604
26d9dd0d 3605 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3606}
3607
26d9dd0d 3608int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3609 struct dispc_clock_info *cinfo)
80c39712
TV		 3610{
3611 unsigned long fck;
3612
3613 fck = dispc_fclk_rate();
3614
ce7fa5eb
MR		 3615 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3616 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3617
3618 cinfo->lck = fck / cinfo->lck_div;
3619 cinfo->pck = cinfo->lck / cinfo->pck_div;
3620
3621 return 0;
3622}
3623
3624/* dispc.irq_lock has to be locked by the caller */
3625static void _omap_dispc_set_irqs(void)
3626{
3627 u32 mask;
3628 u32 old_mask;
3629 int i;
3630 struct omap_dispc_isr_data *isr_data;
3631
3632 mask = dispc.irq_error_mask;
3633
3634 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3635 isr_data = &dispc.registered_isr[i];
3636
3637 if (isr_data->isr == NULL)
3638 continue;
3639
3640 mask |= isr_data->mask;
3641 }
3642
80c39712
TV		 3643 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3644 /* clear the irqstatus for newly enabled irqs */
3645 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3646
3647 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3648}
3649
3650int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3651{
3652 int i;
3653 int ret;
3654 unsigned long flags;
3655 struct omap_dispc_isr_data *isr_data;
3656
3657 if (isr == NULL)
3658 return -EINVAL;
3659
3660 spin_lock_irqsave(&dispc.irq_lock, flags);
3661
3662 /* check for duplicate entry */
3663 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3664 isr_data = &dispc.registered_isr[i];
3665 if (isr_data->isr == isr && isr_data->arg == arg &&
3666 isr_data->mask == mask) {
3667 ret = -EINVAL;
3668 goto err;
3669 }
3670 }
3671
3672 isr_data = NULL;
3673 ret = -EBUSY;
3674
3675 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3676 isr_data = &dispc.registered_isr[i];
3677
3678 if (isr_data->isr != NULL)
3679 continue;
3680
3681 isr_data->isr = isr;
3682 isr_data->arg = arg;
3683 isr_data->mask = mask;
3684 ret = 0;
3685
3686 break;
3687 }
3688
b9cb0984
TV		 3689 if (ret)
3690 goto err;
3691
80c39712
TV		 3692 _omap_dispc_set_irqs();
3693
3694 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3695
3696 return 0;
3697err:
3698 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3699
3700 return ret;
3701}
3702EXPORT_SYMBOL(omap_dispc_register_isr);
3703
3704int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3705{
3706 int i;
3707 unsigned long flags;
3708 int ret = -EINVAL;
3709 struct omap_dispc_isr_data *isr_data;
3710
3711 spin_lock_irqsave(&dispc.irq_lock, flags);
3712
3713 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3714 isr_data = &dispc.registered_isr[i];
3715 if (isr_data->isr != isr || isr_data->arg != arg ||
3716 isr_data->mask != mask)
3717 continue;
3718
3719 /* found the correct isr */
3720
3721 isr_data->isr = NULL;
3722 isr_data->arg = NULL;
3723 isr_data->mask = 0;
3724
3725 ret = 0;
3726 break;
3727 }
3728
3729 if (ret == 0)
3730 _omap_dispc_set_irqs();
3731
3732 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3733
3734 return ret;
3735}
3736EXPORT_SYMBOL(omap_dispc_unregister_isr);
3737
80c39712
TV		 3738static void print_irq_status(u32 status)
3739{
3740 if ((status & dispc.irq_error_mask) == 0)
3741 return;
3742
f30be7d3
CM		 3743#define PIS(x) (status & DISPC_IRQ_##x) ? (#x " ") : ""
3744
3745 pr_debug("DISPC IRQ: 0x%x: %s%s%s%s%s%s%s%s%s\n",
3746 status,
3747 PIS(OCP_ERR),
3748 PIS(GFX_FIFO_UNDERFLOW),
3749 PIS(VID1_FIFO_UNDERFLOW),
3750 PIS(VID2_FIFO_UNDERFLOW),
3751 dss_feat_get_num_ovls() > 3 ? PIS(VID3_FIFO_UNDERFLOW) : "",
3752 PIS(SYNC_LOST),
3753 PIS(SYNC_LOST_DIGIT),
3754 dss_has_feature(FEAT_MGR_LCD2) ? PIS(SYNC_LOST2) : "",
3755 dss_has_feature(FEAT_MGR_LCD3) ? PIS(SYNC_LOST3) : "");
80c39712 3756#undef PIS
80c39712 3757}
80c39712
TV		 3758
3759/* Called from dss.c. Note that we don't touch clocks here,
3760 * but we presume they are on because we got an IRQ. However,
3761 * an irq handler may turn the clocks off, so we may not have
3762 * clock later in the function. */
affe360d 3763static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3764{
3765 int i;
affe360d 3766 u32 irqstatus, irqenable;
80c39712
TV		 3767 u32 handledirqs = 0;
3768 u32 unhandled_errors;
3769 struct omap_dispc_isr_data *isr_data;
3770 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3771
3772 spin_lock(&dispc.irq_lock);
3773
3774 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3775 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3776
3777 /* IRQ is not for us */
3778 if (!(irqstatus & irqenable)) {
3779 spin_unlock(&dispc.irq_lock);
3780 return IRQ_NONE;
3781 }
80c39712 3782
dfc0fd8d
TV		 3783#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3784 spin_lock(&dispc.irq_stats_lock);
3785 dispc.irq_stats.irq_count++;
3786 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3787 spin_unlock(&dispc.irq_stats_lock);
3788#endif
3789
28bcd199
CM		 3790 print_irq_status(irqstatus);
3791
80c39712
TV		 3792 /* Ack the interrupt. Do it here before clocks are possibly turned
3793 * off */
3794 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3795 /* flush posted write */
3796 dispc_read_reg(DISPC_IRQSTATUS);
3797
3798 /* make a copy and unlock, so that isrs can unregister
3799 * themselves */
3800 memcpy(registered_isr, dispc.registered_isr,
3801 sizeof(registered_isr));
3802
3803 spin_unlock(&dispc.irq_lock);
3804
3805 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3806 isr_data = &registered_isr[i];
3807
3808 if (!isr_data->isr)
3809 continue;
3810
3811 if (isr_data->mask & irqstatus) {
3812 isr_data->isr(isr_data->arg, irqstatus);
3813 handledirqs |= isr_data->mask;
3814 }
3815 }
3816
3817 spin_lock(&dispc.irq_lock);
3818
3819 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3820
3821 if (unhandled_errors) {
3822 dispc.error_irqs |= unhandled_errors;
3823
3824 dispc.irq_error_mask &= ~unhandled_errors;
3825 _omap_dispc_set_irqs();
3826
3827 schedule_work(&dispc.error_work);
3828 }
3829
3830 spin_unlock(&dispc.irq_lock);
affe360d 3831
3832 return IRQ_HANDLED;
80c39712
TV		 3833}
3834
3835static void dispc_error_worker(struct work_struct *work)
3836{
3837 int i;
3838 u32 errors;
3839 unsigned long flags;
fe3cc9d6
TV		 3840 static const unsigned fifo_underflow_bits[] = {
3841 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3842 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3843 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3844 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3845 };
3846
80c39712
TV		 3847 spin_lock_irqsave(&dispc.irq_lock, flags);
3848 errors = dispc.error_irqs;
3849 dispc.error_irqs = 0;
3850 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3851
13eae1f9
DZ		 3852 dispc_runtime_get();
3853
fe3cc9d6
TV		 3854 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3855 struct omap_overlay *ovl;
3856 unsigned bit;
80c39712 3857
fe3cc9d6
TV		 3858 ovl = omap_dss_get_overlay(i);
3859 bit = fifo_underflow_bits[i];
80c39712 3860
fe3cc9d6
TV		 3861 if (bit & errors) {
3862 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3863 ovl->name);
f0e5caab 3864 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3865 dispc_mgr_go(ovl->manager->id);
d7ad718d 3866 msleep(50);
80c39712
TV		 3867 }
3868 }
3869
fe3cc9d6
TV		 3870 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3871 struct omap_overlay_manager *mgr;
3872 unsigned bit;
80c39712 3873
fe3cc9d6 3874 mgr = omap_dss_get_overlay_manager(i);
efa70b3b 3875 bit = mgr_desc[i].sync_lost_irq;
80c39712 3876
fe3cc9d6 3877 if (bit & errors) {
794bc4ee 3878 struct omap_dss_device *dssdev = mgr->get_device(mgr);
fe3cc9d6 3879 bool enable;
80c39712 3880
fe3cc9d6
TV		 3881 DSSERR("SYNC_LOST on channel %s, restarting the output "
3882 "with video overlays disabled\n",
3883 mgr->name);
2a205f34 3884
fe3cc9d6
TV		 3885 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3886 dssdev->driver->disable(dssdev);
2a205f34 3887
2a205f34
SS		 3888 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3889 struct omap_overlay *ovl;
3890 ovl = omap_dss_get_overlay(i);
3891
fe3cc9d6
TV		 3892 if (ovl->id != OMAP_DSS_GFX &&
3893 ovl->manager == mgr)
f0e5caab 3894 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3895 }
3896
26d9dd0d 3897 dispc_mgr_go(mgr->id);
d7ad718d 3898 msleep(50);
fe3cc9d6 3899
2a205f34
SS		 3900 if (enable)
3901 dssdev->driver->enable(dssdev);
3902 }
3903 }
3904
80c39712
TV		 3905 if (errors & DISPC_IRQ_OCP_ERR) {
3906 DSSERR("OCP_ERR\n");
3907 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3908 struct omap_overlay_manager *mgr;
794bc4ee
AT		 3909 struct omap_dss_device *dssdev;
3910
80c39712 3911 mgr = omap_dss_get_overlay_manager(i);
794bc4ee
AT		 3912 dssdev = mgr->get_device(mgr);
3913
3914 if (dssdev && dssdev->driver)
3915 dssdev->driver->disable(dssdev);
80c39712
TV		 3916 }
3917 }
3918
3919 spin_lock_irqsave(&dispc.irq_lock, flags);
3920 dispc.irq_error_mask |= errors;
3921 _omap_dispc_set_irqs();
3922 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3923
3924 dispc_runtime_put();
80c39712
TV		 3925}
3926
3927int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3928{
3929 void dispc_irq_wait_handler(void *data, u32 mask)
3930 {
3931 complete((struct completion *)data);
3932 }
3933
3934 int r;
3935 DECLARE_COMPLETION_ONSTACK(completion);
3936
3937 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3938 irqmask);
3939
3940 if (r)
3941 return r;
3942
3943 timeout = wait_for_completion_timeout(&completion, timeout);
3944
3945 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3946
3947 if (timeout == 0)
3948 return -ETIMEDOUT;
3949
3950 if (timeout == -ERESTARTSYS)
3951 return -ERESTARTSYS;
3952
3953 return 0;
3954}
3955
3956int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3957 unsigned long timeout)
3958{
3959 void dispc_irq_wait_handler(void *data, u32 mask)
3960 {
3961 complete((struct completion *)data);
3962 }
3963
3964 int r;
3965 DECLARE_COMPLETION_ONSTACK(completion);
3966
3967 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3968 irqmask);
3969
3970 if (r)
3971 return r;
3972
3973 timeout = wait_for_completion_interruptible_timeout(&completion,
3974 timeout);
3975
3976 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3977
3978 if (timeout == 0)
3979 return -ETIMEDOUT;
3980
3981 if (timeout == -ERESTARTSYS)
3982 return -ERESTARTSYS;
3983
3984 return 0;
3985}
3986
80c39712
TV		 3987static void _omap_dispc_initialize_irq(void)
3988{
3989 unsigned long flags;
3990
3991 spin_lock_irqsave(&dispc.irq_lock, flags);
3992
3993 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3994
3995 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3996 if (dss_has_feature(FEAT_MGR_LCD2))
3997 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
e86d456a
CM		 3998 if (dss_has_feature(FEAT_MGR_LCD3))
3999 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
b8c095b4
AT		 4000 if (dss_feat_get_num_ovls() > 3)
4001 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 4002
4003 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
4004 * so clear it */
4005 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
4006
4007 _omap_dispc_set_irqs();
4008
4009 spin_unlock_irqrestore(&dispc.irq_lock, flags);
4010}
4011
4012void dispc_enable_sidle(void)
4013{
4014 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
4015}
4016
4017void dispc_disable_sidle(void)
4018{
4019 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
4020}
4021
4022static void _omap_dispc_initial_config(void)
4023{
4024 u32 l;
4025
0cf35df3
MR		 4026 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
4027 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
4028 l = dispc_read_reg(DISPC_DIVISOR);
4029 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
4030 l = FLD_MOD(l, 1, 0, 0);
4031 l = FLD_MOD(l, 1, 23, 16);
4032 dispc_write_reg(DISPC_DIVISOR, l);
4033 }
4034
80c39712 4035 /* FUNCGATED */
6ced40bf
AT		 4036 if (dss_has_feature(FEAT_FUNCGATED))
4037 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 4038
6e5264b0 4039 dispc_setup_color_conv_coef();
80c39712
TV		 4040
4041 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
4042
42a6961c 4043 dispc_init_fifos();
5ed8cf5b
TV		 4044
4045 dispc_configure_burst_sizes();
54128701
AT		 4046
4047 dispc_ovl_enable_zorder_planes();
80c39712
TV		 4048}
4049
dcbe765b
CM		 4050static const struct dispc_features omap24xx_dispc_feats __initconst = {
4051 .sw_start = 5,
4052 .fp_start = 15,
4053 .bp_start = 27,
4054 .sw_max = 64,
4055 .vp_max = 255,
4056 .hp_max = 256,
4057 .calc_scaling = dispc_ovl_calc_scaling_24xx,
4058 .calc_core_clk = calc_core_clk_24xx,
42a6961c 4059 .num_fifos = 3,
dcbe765b
CM		 4060};
4061
4062static const struct dispc_features omap34xx_rev1_0_dispc_feats __initconst = {
4063 .sw_start = 5,
4064 .fp_start = 15,
4065 .bp_start = 27,
4066 .sw_max = 64,
4067 .vp_max = 255,
4068 .hp_max = 256,
4069 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4070 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4071 .num_fifos = 3,
dcbe765b
CM		 4072};
4073
4074static const struct dispc_features omap34xx_rev3_0_dispc_feats __initconst = {
4075 .sw_start = 7,
4076 .fp_start = 19,
4077 .bp_start = 31,
4078 .sw_max = 256,
4079 .vp_max = 4095,
4080 .hp_max = 4096,
4081 .calc_scaling = dispc_ovl_calc_scaling_34xx,
4082 .calc_core_clk = calc_core_clk_34xx,
42a6961c 4083 .num_fifos = 3,
dcbe765b
CM		 4084};
4085
4086static const struct dispc_features omap44xx_dispc_feats __initconst = {
4087 .sw_start = 7,
4088 .fp_start = 19,
4089 .bp_start = 31,
4090 .sw_max = 256,
4091 .vp_max = 4095,
4092 .hp_max = 4096,
4093 .calc_scaling = dispc_ovl_calc_scaling_44xx,
4094 .calc_core_clk = calc_core_clk_44xx,
42a6961c 4095 .num_fifos = 5,
66a0f9e4 4096 .gfx_fifo_workaround = true,
dcbe765b
CM		 4097};
4098
84b47623 4099static int __init dispc_init_features(struct platform_device *pdev)
dcbe765b
CM		 4100{
4101 const struct dispc_features *src;
4102 struct dispc_features *dst;
4103
84b47623 4104 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
dcbe765b 4105 if (!dst) {
84b47623 4106 dev_err(&pdev->dev, "Failed to allocate DISPC Features\n");
dcbe765b
CM		 4107 return -ENOMEM;
4108 }
4109
b2c7d54f 4110 switch (omapdss_get_version()) {
84b47623 4111 case OMAPDSS_VER_OMAP24xx:
dcbe765b 4112 src = &omap24xx_dispc_feats;
84b47623
TV		 4113 break;
4114
4115 case OMAPDSS_VER_OMAP34xx_ES1:
4116 src = &omap34xx_rev1_0_dispc_feats;
4117 break;
4118
4119 case OMAPDSS_VER_OMAP34xx_ES3:
4120 case OMAPDSS_VER_OMAP3630:
4121 case OMAPDSS_VER_AM35xx:
4122 src = &omap34xx_rev3_0_dispc_feats;
4123 break;
4124
4125 case OMAPDSS_VER_OMAP4430_ES1:
4126 case OMAPDSS_VER_OMAP4430_ES2:
4127 case OMAPDSS_VER_OMAP4:
dcbe765b 4128 src = &omap44xx_dispc_feats;
84b47623
TV		 4129 break;
4130
4131 case OMAPDSS_VER_OMAP5:
23362832 4132 src = &omap44xx_dispc_feats;
84b47623
TV		 4133 break;
4134
4135 default:
dcbe765b
CM		 4136 return -ENODEV;
4137 }
4138
4139 memcpy(dst, src, sizeof(*dst));
4140 dispc.feat = dst;
4141
4142 return 0;
4143}
4144
060b6d9c 4145/* DISPC HW IP initialisation */
6e7e8f06 4146static int __init omap_dispchw_probe(struct platform_device *pdev)
060b6d9c
SG		 4147{
4148 u32 rev;
affe360d 4149 int r = 0;
ea9da36a 4150 struct resource *dispc_mem;
4fbafaf3 4151 struct clk *clk;
ea9da36a 4152
060b6d9c
SG		 4153 dispc.pdev = pdev;
4154
84b47623 4155 r = dispc_init_features(dispc.pdev);
dcbe765b
CM		 4156 if (r)
4157 return r;
4158
060b6d9c
SG		 4159 spin_lock_init(&dispc.irq_lock);
4160
4161#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4162 spin_lock_init(&dispc.irq_stats_lock);
4163 dispc.irq_stats.last_reset = jiffies;
4164#endif
4165
4166 INIT_WORK(&dispc.error_work, dispc_error_worker);
4167
ea9da36a
SG		 4168 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
4169 if (!dispc_mem) {
4170 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 4171 return -EINVAL;
ea9da36a 4172 }
cd3b3449 4173
6e2a14d2
JL		 4174 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
4175 resource_size(dispc_mem));
060b6d9c
SG		 4176 if (!dispc.base) {
4177 DSSERR("can't ioremap DISPC\n");
cd3b3449 4178 return -ENOMEM;
affe360d 4179 }
cd3b3449 4180
affe360d 4181 dispc.irq = platform_get_irq(dispc.pdev, 0);
4182 if (dispc.irq < 0) {
4183 DSSERR("platform_get_irq failed\n");
cd3b3449 4184 return -ENODEV;
affe360d 4185 }
4186
6e2a14d2
JL		 4187 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
4188 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 4189 if (r < 0) {
4190 DSSERR("request_irq failed\n");
cd3b3449
TV		 4191 return r;
4192 }
4193
4194 clk = clk_get(&pdev->dev, "fck");
4195 if (IS_ERR(clk)) {
4196 DSSERR("can't get fck\n");
4197 r = PTR_ERR(clk);
4198 return r;
060b6d9c
SG		 4199 }
4200
cd3b3449
TV		 4201 dispc.dss_clk = clk;
4202
4fbafaf3
TV		 4203 pm_runtime_enable(&pdev->dev);
4204
4205 r = dispc_runtime_get();
4206 if (r)
4207 goto err_runtime_get;
060b6d9c
SG		 4208
4209 _omap_dispc_initial_config();
4210
4211 _omap_dispc_initialize_irq();
4212
060b6d9c 4213 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 4214 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 4215 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4216
4fbafaf3 4217 dispc_runtime_put();
060b6d9c 4218
e40402cf
TV		 4219 dss_debugfs_create_file("dispc", dispc_dump_regs);
4220
4221#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4222 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
4223#endif
060b6d9c 4224 return 0;
4fbafaf3
TV		 4225
4226err_runtime_get:
4227 pm_runtime_disable(&pdev->dev);
4fbafaf3 4228 clk_put(dispc.dss_clk);
affe360d 4229 return r;
060b6d9c
SG		 4230}
4231
6e7e8f06 4232static int __exit omap_dispchw_remove(struct platform_device *pdev)
060b6d9c 4233{
4fbafaf3
TV		 4234 pm_runtime_disable(&pdev->dev);
4235
4236 clk_put(dispc.dss_clk);
4237
060b6d9c
SG		 4238 return 0;
4239}
4240
4fbafaf3
TV		 4241static int dispc_runtime_suspend(struct device *dev)
4242{
4243 dispc_save_context();
4fbafaf3
TV		 4244
4245 return 0;
4246}
4247
4248static int dispc_runtime_resume(struct device *dev)
4249{
49ea86f3 4250 dispc_restore_context();
4fbafaf3
TV		 4251
4252 return 0;
4253}
4254
4255static const struct dev_pm_ops dispc_pm_ops = {
4256 .runtime_suspend = dispc_runtime_suspend,
4257 .runtime_resume = dispc_runtime_resume,
4258};
4259
060b6d9c 4260static struct platform_driver omap_dispchw_driver = {
6e7e8f06 4261 .remove = __exit_p(omap_dispchw_remove),
060b6d9c
SG		 4262 .driver = {
4263 .name = "omapdss_dispc",
4264 .owner = THIS_MODULE,
4fbafaf3 4265 .pm = &dispc_pm_ops,
060b6d9c
SG		 4266 },
4267};
4268
6e7e8f06 4269int __init dispc_init_platform_driver(void)
060b6d9c 4270{
11436e1d 4271 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
060b6d9c
SG		 4272}
4273
6e7e8f06 4274void __exit dispc_uninit_platform_driver(void)
060b6d9c 4275{
04c742c3 4276 platform_driver_unregister(&omap_dispchw_driver);
060b6d9c 4277}
Linux kernel - Deliverables
This page took 0.530786 seconds and 5 git commands to generate.