projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
OMAPDSS: DSI: use dsi_get_dsidev_id(dsidev) instead of dsidev->id
[deliverable/linux.git] / drivers / video / omap2 / dss / dispc.c
CommitLineData
80c39712
TV		 1/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
a8a35931 28#include <linux/export.h>
80c39712
TV		 29#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
ab83b14c 35#include <linux/hardirq.h>
affe360d 36#include <linux/interrupt.h>
24e6289c 37#include <linux/platform_device.h>
4fbafaf3 38#include <linux/pm_runtime.h>
80c39712 39
80c39712
TV		 40#include <plat/clock.h>
41
a0b38cc4 42#include <video/omapdss.h>
80c39712
TV		 43
44#include "dss.h"
a0acb557 45#include "dss_features.h"
9b372c2d 46#include "dispc.h"
80c39712
TV		 47
48/* DISPC */
8613b000 49#define DISPC_SZ_REGS SZ_4K
80c39712 50
80c39712
TV		 51#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
5ed8cf5b
TV		 66enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
80c39712
TV		 72#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
dfc0fd8d
TV		 78struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
80c39712 84static struct {
060b6d9c 85 struct platform_device *pdev;
80c39712 86 void __iomem *base;
4fbafaf3
TV		 87
88 int ctx_loss_cnt;
89
affe360d 90 int irq;
4fbafaf3 91 struct clk *dss_clk;
80c39712 92
e13a138b 93 u32 fifo_size[MAX_DSS_OVERLAYS];
80c39712
TV		 94
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
49ea86f3 101 bool ctx_valid;
80c39712 102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
dfc0fd8d
TV		 103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
80c39712
TV		 108} dispc;
109
0d66cbb5
AJ		 110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
80c39712
TV		 122static void _omap_dispc_set_irqs(void);
123
55978cc2 124static inline void dispc_write_reg(const u16 idx, u32 val)
80c39712 125{
55978cc2 126 __raw_writel(val, dispc.base + idx);
80c39712
TV		 127}
128
55978cc2 129static inline u32 dispc_read_reg(const u16 idx)
80c39712 130{
55978cc2 131 return __raw_readl(dispc.base + idx);
80c39712
TV		 132}
133
49ea86f3
TV		 134static int dispc_get_ctx_loss_count(void)
135{
136 struct device *dev = &dispc.pdev->dev;
137 struct omap_display_platform_data *pdata = dev->platform_data;
138 struct omap_dss_board_info *board_data = pdata->board_data;
139 int cnt;
140
141 if (!board_data->get_context_loss_count)
142 return -ENOENT;
143
144 cnt = board_data->get_context_loss_count(dev);
145
146 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
147
148 return cnt;
149}
150
80c39712 151#define SR(reg) \
55978cc2 152 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
80c39712 153#define RR(reg) \
55978cc2 154 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
80c39712 155
4fbafaf3 156static void dispc_save_context(void)
80c39712 157{
c6104b8e 158 int i, j;
80c39712 159
4fbafaf3
TV		 160 DSSDBG("dispc_save_context\n");
161
80c39712
TV		 162 SR(IRQENABLE);
163 SR(CONTROL);
164 SR(CONFIG);
80c39712 165 SR(LINE_NUMBER);
11354dd5
AT		 166 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
167 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 168 SR(GLOBAL_ALPHA);
2a205f34
SS		 169 if (dss_has_feature(FEAT_MGR_LCD2)) {
170 SR(CONTROL2);
2a205f34
SS		 171 SR(CONFIG2);
172 }
80c39712 173
c6104b8e
AT		 174 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
175 SR(DEFAULT_COLOR(i));
176 SR(TRANS_COLOR(i));
177 SR(SIZE_MGR(i));
178 if (i == OMAP_DSS_CHANNEL_DIGIT)
179 continue;
180 SR(TIMING_H(i));
181 SR(TIMING_V(i));
182 SR(POL_FREQ(i));
183 SR(DIVISORo(i));
184
185 SR(DATA_CYCLE1(i));
186 SR(DATA_CYCLE2(i));
187 SR(DATA_CYCLE3(i));
188
332e9d70 189 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 190 SR(CPR_COEF_R(i));
191 SR(CPR_COEF_G(i));
192 SR(CPR_COEF_B(i));
332e9d70 193 }
2a205f34 194 }
80c39712 195
c6104b8e
AT		 196 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
197 SR(OVL_BA0(i));
198 SR(OVL_BA1(i));
199 SR(OVL_POSITION(i));
200 SR(OVL_SIZE(i));
201 SR(OVL_ATTRIBUTES(i));
202 SR(OVL_FIFO_THRESHOLD(i));
203 SR(OVL_ROW_INC(i));
204 SR(OVL_PIXEL_INC(i));
205 if (dss_has_feature(FEAT_PRELOAD))
206 SR(OVL_PRELOAD(i));
207 if (i == OMAP_DSS_GFX) {
208 SR(OVL_WINDOW_SKIP(i));
209 SR(OVL_TABLE_BA(i));
210 continue;
211 }
212 SR(OVL_FIR(i));
213 SR(OVL_PICTURE_SIZE(i));
214 SR(OVL_ACCU0(i));
215 SR(OVL_ACCU1(i));
9b372c2d 216
c6104b8e
AT		 217 for (j = 0; j < 8; j++)
218 SR(OVL_FIR_COEF_H(i, j));
ab5ca071 219
c6104b8e
AT		 220 for (j = 0; j < 8; j++)
221 SR(OVL_FIR_COEF_HV(i, j));
ab5ca071 222
c6104b8e
AT		 223 for (j = 0; j < 5; j++)
224 SR(OVL_CONV_COEF(i, j));
ab5ca071 225
c6104b8e
AT		 226 if (dss_has_feature(FEAT_FIR_COEF_V)) {
227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V(i, j));
229 }
9b372c2d 230
c6104b8e
AT		 231 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
232 SR(OVL_BA0_UV(i));
233 SR(OVL_BA1_UV(i));
234 SR(OVL_FIR2(i));
235 SR(OVL_ACCU2_0(i));
236 SR(OVL_ACCU2_1(i));
ab5ca071 237
c6104b8e
AT		 238 for (j = 0; j < 8; j++)
239 SR(OVL_FIR_COEF_H2(i, j));
ab5ca071 240
c6104b8e
AT		 241 for (j = 0; j < 8; j++)
242 SR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 243
c6104b8e
AT		 244 for (j = 0; j < 8; j++)
245 SR(OVL_FIR_COEF_V2(i, j));
246 }
247 if (dss_has_feature(FEAT_ATTR2))
248 SR(OVL_ATTRIBUTES2(i));
ab5ca071 249 }
0cf35df3
MR		 250
251 if (dss_has_feature(FEAT_CORE_CLK_DIV))
252 SR(DIVISOR);
49ea86f3
TV		 253
254 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
255 dispc.ctx_valid = true;
256
257 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
80c39712
TV		 258}
259
4fbafaf3 260static void dispc_restore_context(void)
80c39712 261{
c6104b8e 262 int i, j, ctx;
4fbafaf3
TV		 263
264 DSSDBG("dispc_restore_context\n");
265
49ea86f3
TV		 266 if (!dispc.ctx_valid)
267 return;
268
269 ctx = dispc_get_ctx_loss_count();
270
271 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
272 return;
273
274 DSSDBG("ctx_loss_count: saved %d, current %d\n",
275 dispc.ctx_loss_cnt, ctx);
276
75c7d59d 277 /*RR(IRQENABLE);*/
80c39712
TV		 278 /*RR(CONTROL);*/
279 RR(CONFIG);
80c39712 280 RR(LINE_NUMBER);
11354dd5
AT		 281 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
282 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 283 RR(GLOBAL_ALPHA);
c6104b8e 284 if (dss_has_feature(FEAT_MGR_LCD2))
2a205f34 285 RR(CONFIG2);
80c39712 286
c6104b8e
AT		 287 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
288 RR(DEFAULT_COLOR(i));
289 RR(TRANS_COLOR(i));
290 RR(SIZE_MGR(i));
291 if (i == OMAP_DSS_CHANNEL_DIGIT)
292 continue;
293 RR(TIMING_H(i));
294 RR(TIMING_V(i));
295 RR(POL_FREQ(i));
296 RR(DIVISORo(i));
297
298 RR(DATA_CYCLE1(i));
299 RR(DATA_CYCLE2(i));
300 RR(DATA_CYCLE3(i));
2a205f34 301
332e9d70 302 if (dss_has_feature(FEAT_CPR)) {
c6104b8e
AT		 303 RR(CPR_COEF_R(i));
304 RR(CPR_COEF_G(i));
305 RR(CPR_COEF_B(i));
332e9d70 306 }
2a205f34 307 }
80c39712 308
c6104b8e
AT		 309 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
310 RR(OVL_BA0(i));
311 RR(OVL_BA1(i));
312 RR(OVL_POSITION(i));
313 RR(OVL_SIZE(i));
314 RR(OVL_ATTRIBUTES(i));
315 RR(OVL_FIFO_THRESHOLD(i));
316 RR(OVL_ROW_INC(i));
317 RR(OVL_PIXEL_INC(i));
318 if (dss_has_feature(FEAT_PRELOAD))
319 RR(OVL_PRELOAD(i));
320 if (i == OMAP_DSS_GFX) {
321 RR(OVL_WINDOW_SKIP(i));
322 RR(OVL_TABLE_BA(i));
323 continue;
324 }
325 RR(OVL_FIR(i));
326 RR(OVL_PICTURE_SIZE(i));
327 RR(OVL_ACCU0(i));
328 RR(OVL_ACCU1(i));
9b372c2d 329
c6104b8e
AT		 330 for (j = 0; j < 8; j++)
331 RR(OVL_FIR_COEF_H(i, j));
ab5ca071 332
c6104b8e
AT		 333 for (j = 0; j < 8; j++)
334 RR(OVL_FIR_COEF_HV(i, j));
ab5ca071 335
c6104b8e
AT		 336 for (j = 0; j < 5; j++)
337 RR(OVL_CONV_COEF(i, j));
ab5ca071 338
c6104b8e
AT		 339 if (dss_has_feature(FEAT_FIR_COEF_V)) {
340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V(i, j));
342 }
9b372c2d 343
c6104b8e
AT		 344 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
345 RR(OVL_BA0_UV(i));
346 RR(OVL_BA1_UV(i));
347 RR(OVL_FIR2(i));
348 RR(OVL_ACCU2_0(i));
349 RR(OVL_ACCU2_1(i));
ab5ca071 350
c6104b8e
AT		 351 for (j = 0; j < 8; j++)
352 RR(OVL_FIR_COEF_H2(i, j));
ab5ca071 353
c6104b8e
AT		 354 for (j = 0; j < 8; j++)
355 RR(OVL_FIR_COEF_HV2(i, j));
ab5ca071 356
c6104b8e
AT		 357 for (j = 0; j < 8; j++)
358 RR(OVL_FIR_COEF_V2(i, j));
359 }
360 if (dss_has_feature(FEAT_ATTR2))
361 RR(OVL_ATTRIBUTES2(i));
ab5ca071 362 }
80c39712 363
0cf35df3
MR		 364 if (dss_has_feature(FEAT_CORE_CLK_DIV))
365 RR(DIVISOR);
366
80c39712
TV		 367 /* enable last, because LCD & DIGIT enable are here */
368 RR(CONTROL);
2a205f34
SS		 369 if (dss_has_feature(FEAT_MGR_LCD2))
370 RR(CONTROL2);
75c7d59d
VS		 371 /* clear spurious SYNC_LOST_DIGIT interrupts */
372 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
373
374 /*
375 * enable last so IRQs won't trigger before
376 * the context is fully restored
377 */
378 RR(IRQENABLE);
49ea86f3
TV		 379
380 DSSDBG("context restored\n");
80c39712
TV		 381}
382
383#undef SR
384#undef RR
385
4fbafaf3
TV		 386int dispc_runtime_get(void)
387{
388 int r;
389
390 DSSDBG("dispc_runtime_get\n");
391
392 r = pm_runtime_get_sync(&dispc.pdev->dev);
393 WARN_ON(r < 0);
394 return r < 0 ? r : 0;
395}
396
397void dispc_runtime_put(void)
398{
399 int r;
400
401 DSSDBG("dispc_runtime_put\n");
402
0eaf9f52 403 r = pm_runtime_put_sync(&dispc.pdev->dev);
4fbafaf3 404 WARN_ON(r < 0);
80c39712
TV		 405}
406
dac57a05
AT		 407static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
408{
409 if (channel == OMAP_DSS_CHANNEL_LCD ||
410 channel == OMAP_DSS_CHANNEL_LCD2)
411 return true;
412 else
413 return false;
414}
4fbafaf3 415
3dcec4d6
TV		 416u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
417{
418 switch (channel) {
419 case OMAP_DSS_CHANNEL_LCD:
420 return DISPC_IRQ_VSYNC;
421 case OMAP_DSS_CHANNEL_LCD2:
422 return DISPC_IRQ_VSYNC2;
423 case OMAP_DSS_CHANNEL_DIGIT:
424 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
425 default:
426 BUG();
427 }
428}
429
7d1365c9
TV		 430u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
431{
432 switch (channel) {
433 case OMAP_DSS_CHANNEL_LCD:
434 return DISPC_IRQ_FRAMEDONE;
435 case OMAP_DSS_CHANNEL_LCD2:
436 return DISPC_IRQ_FRAMEDONE2;
437 case OMAP_DSS_CHANNEL_DIGIT:
438 return 0;
439 default:
440 BUG();
441 }
442}
443
26d9dd0d 444bool dispc_mgr_go_busy(enum omap_channel channel)
80c39712
TV		 445{
446 int bit;
447
dac57a05 448 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 449 bit = 5; /* GOLCD */
450 else
451 bit = 6; /* GODIGIT */
452
2a205f34
SS		 453 if (channel == OMAP_DSS_CHANNEL_LCD2)
454 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
455 else
456 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
80c39712
TV		 457}
458
26d9dd0d 459void dispc_mgr_go(enum omap_channel channel)
80c39712
TV		 460{
461 int bit;
2a205f34 462 bool enable_bit, go_bit;
80c39712 463
dac57a05 464 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 465 bit = 0; /* LCDENABLE */
466 else
467 bit = 1; /* DIGITALENABLE */
468
469 /* if the channel is not enabled, we don't need GO */
2a205f34
SS		 470 if (channel == OMAP_DSS_CHANNEL_LCD2)
471 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
472 else
473 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
474
475 if (!enable_bit)
e6d80f95 476 return;
80c39712 477
dac57a05 478 if (dispc_mgr_is_lcd(channel))
80c39712
TV		 479 bit = 5; /* GOLCD */
480 else
481 bit = 6; /* GODIGIT */
482
2a205f34
SS		 483 if (channel == OMAP_DSS_CHANNEL_LCD2)
484 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
485 else
486 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
487
488 if (go_bit) {
80c39712 489 DSSERR("GO bit not down for channel %d\n", channel);
e6d80f95 490 return;
80c39712
TV		 491 }
492
2a205f34
SS		 493 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
494 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
80c39712 495
2a205f34
SS		 496 if (channel == OMAP_DSS_CHANNEL_LCD2)
497 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
498 else
499 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
80c39712
TV		 500}
501
f0e5caab 502static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
80c39712 503{
9b372c2d 504 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
80c39712
TV		 505}
506
f0e5caab 507static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 508{
9b372c2d 509 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
80c39712
TV		 510}
511
f0e5caab 512static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
80c39712 513{
9b372c2d 514 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
80c39712
TV		 515}
516
f0e5caab 517static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 518{
519 BUG_ON(plane == OMAP_DSS_GFX);
520
521 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
522}
523
f0e5caab
TV		 524static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
525 u32 value)
ab5ca071
AJ		 526{
527 BUG_ON(plane == OMAP_DSS_GFX);
528
529 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
530}
531
f0e5caab 532static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
ab5ca071
AJ		 533{
534 BUG_ON(plane == OMAP_DSS_GFX);
535
536 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
537}
538
debd9074
CM		 539static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
540 int fir_vinc, int five_taps,
541 enum omap_color_component color_comp)
80c39712 542{
debd9074 543 const struct dispc_coef *h_coef, *v_coef;
80c39712
TV		 544 int i;
545
debd9074
CM		 546 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
547 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
80c39712
TV		 548
549 for (i = 0; i < 8; i++) {
550 u32 h, hv;
551
debd9074
CM		 552 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
553 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
554 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
555 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
556 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
557 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
558 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
559 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
80c39712 560
0d66cbb5 561 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
f0e5caab
TV		 562 dispc_ovl_write_firh_reg(plane, i, h);
563 dispc_ovl_write_firhv_reg(plane, i, hv);
0d66cbb5 564 } else {
f0e5caab
TV		 565 dispc_ovl_write_firh2_reg(plane, i, h);
566 dispc_ovl_write_firhv2_reg(plane, i, hv);
0d66cbb5
AJ		 567 }
568
80c39712
TV		 569 }
570
66be8f6c
GI		 571 if (five_taps) {
572 for (i = 0; i < 8; i++) {
573 u32 v;
debd9074
CM		 574 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
575 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
0d66cbb5 576 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
f0e5caab 577 dispc_ovl_write_firv_reg(plane, i, v);
0d66cbb5 578 else
f0e5caab 579 dispc_ovl_write_firv2_reg(plane, i, v);
66be8f6c 580 }
80c39712
TV		 581 }
582}
583
584static void _dispc_setup_color_conv_coef(void)
585{
ac01c29e 586 int i;
80c39712
TV		 587 const struct color_conv_coef {
588 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
589 int full_range;
590 } ctbl_bt601_5 = {
591 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
592 };
593
594 const struct color_conv_coef *ct;
595
596#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
597
598 ct = &ctbl_bt601_5;
599
ac01c29e
AT		 600 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
601 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
602 CVAL(ct->rcr, ct->ry));
603 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
604 CVAL(ct->gy, ct->rcb));
605 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
606 CVAL(ct->gcb, ct->gcr));
607 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
608 CVAL(ct->bcr, ct->by));
609 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
610 CVAL(0, ct->bcb));
611
612 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
613 11, 11);
614 }
80c39712
TV		 615
616#undef CVAL
80c39712
TV		 617}
618
619
f0e5caab 620static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
80c39712 621{
9b372c2d 622 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
80c39712
TV		 623}
624
f0e5caab 625static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
80c39712 626{
9b372c2d 627 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
80c39712
TV		 628}
629
f0e5caab 630static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 631{
632 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
633}
634
f0e5caab 635static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
ab5ca071
AJ		 636{
637 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
638}
639
f0e5caab 640static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
80c39712 641{
80c39712 642 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
9b372c2d
AT		 643
644 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
80c39712
TV		 645}
646
f0e5caab 647static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
80c39712 648{
80c39712 649 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 650
651 if (plane == OMAP_DSS_GFX)
652 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
653 else
654 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
80c39712
TV		 655}
656
f0e5caab 657static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
80c39712
TV		 658{
659 u32 val;
80c39712
TV		 660
661 BUG_ON(plane == OMAP_DSS_GFX);
662
663 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
9b372c2d
AT		 664
665 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
80c39712
TV		 666}
667
54128701
AT		 668static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
669{
670 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
671
672 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
673 return;
674
675 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
676}
677
678static void dispc_ovl_enable_zorder_planes(void)
679{
680 int i;
681
682 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
683 return;
684
685 for (i = 0; i < dss_feat_get_num_ovls(); i++)
686 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
687}
688
f0e5caab 689static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
fd28a390 690{
f6dc8150 691 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fd28a390 692
f6dc8150 693 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
fd28a390
R		 694 return;
695
9b372c2d 696 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
fd28a390
R		 697}
698
f0e5caab 699static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
80c39712 700{
b8c095b4 701 static const unsigned shifts[] = { 0, 8, 16, 24, };
fe3cc9d6 702 int shift;
f6dc8150 703 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
fe3cc9d6 704
f6dc8150 705 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
fd28a390 706 return;
a0acb557 707
fe3cc9d6
TV		 708 shift = shifts[plane];
709 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
80c39712
TV		 710}
711
f0e5caab 712static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
80c39712 713{
9b372c2d 714 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
80c39712
TV		 715}
716
f0e5caab 717static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
80c39712 718{
9b372c2d 719 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
80c39712
TV		 720}
721
f0e5caab 722static void dispc_ovl_set_color_mode(enum omap_plane plane,
80c39712
TV		 723 enum omap_color_mode color_mode)
724{
725 u32 m = 0;
f20e4220
AJ		 726 if (plane != OMAP_DSS_GFX) {
727 switch (color_mode) {
728 case OMAP_DSS_COLOR_NV12:
729 m = 0x0; break;
08f3267e 730 case OMAP_DSS_COLOR_RGBX16:
f20e4220
AJ		 731 m = 0x1; break;
732 case OMAP_DSS_COLOR_RGBA16:
733 m = 0x2; break;
08f3267e 734 case OMAP_DSS_COLOR_RGB12U:
f20e4220
AJ		 735 m = 0x4; break;
736 case OMAP_DSS_COLOR_ARGB16:
737 m = 0x5; break;
738 case OMAP_DSS_COLOR_RGB16:
739 m = 0x6; break;
740 case OMAP_DSS_COLOR_ARGB16_1555:
741 m = 0x7; break;
742 case OMAP_DSS_COLOR_RGB24U:
743 m = 0x8; break;
744 case OMAP_DSS_COLOR_RGB24P:
745 m = 0x9; break;
746 case OMAP_DSS_COLOR_YUV2:
747 m = 0xa; break;
748 case OMAP_DSS_COLOR_UYVY:
749 m = 0xb; break;
750 case OMAP_DSS_COLOR_ARGB32:
751 m = 0xc; break;
752 case OMAP_DSS_COLOR_RGBA32:
753 m = 0xd; break;
754 case OMAP_DSS_COLOR_RGBX32:
755 m = 0xe; break;
756 case OMAP_DSS_COLOR_XRGB16_1555:
757 m = 0xf; break;
758 default:
759 BUG(); break;
760 }
761 } else {
762 switch (color_mode) {
763 case OMAP_DSS_COLOR_CLUT1:
764 m = 0x0; break;
765 case OMAP_DSS_COLOR_CLUT2:
766 m = 0x1; break;
767 case OMAP_DSS_COLOR_CLUT4:
768 m = 0x2; break;
769 case OMAP_DSS_COLOR_CLUT8:
770 m = 0x3; break;
771 case OMAP_DSS_COLOR_RGB12U:
772 m = 0x4; break;
773 case OMAP_DSS_COLOR_ARGB16:
774 m = 0x5; break;
775 case OMAP_DSS_COLOR_RGB16:
776 m = 0x6; break;
777 case OMAP_DSS_COLOR_ARGB16_1555:
778 m = 0x7; break;
779 case OMAP_DSS_COLOR_RGB24U:
780 m = 0x8; break;
781 case OMAP_DSS_COLOR_RGB24P:
782 m = 0x9; break;
08f3267e 783 case OMAP_DSS_COLOR_RGBX16:
f20e4220 784 m = 0xa; break;
08f3267e 785 case OMAP_DSS_COLOR_RGBA16:
f20e4220
AJ		 786 m = 0xb; break;
787 case OMAP_DSS_COLOR_ARGB32:
788 m = 0xc; break;
789 case OMAP_DSS_COLOR_RGBA32:
790 m = 0xd; break;
791 case OMAP_DSS_COLOR_RGBX32:
792 m = 0xe; break;
793 case OMAP_DSS_COLOR_XRGB16_1555:
794 m = 0xf; break;
795 default:
796 BUG(); break;
797 }
80c39712
TV		 798 }
799
9b372c2d 800 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
80c39712
TV		 801}
802
f427984e 803void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
80c39712
TV		 804{
805 int shift;
806 u32 val;
2a205f34 807 int chan = 0, chan2 = 0;
80c39712
TV		 808
809 switch (plane) {
810 case OMAP_DSS_GFX:
811 shift = 8;
812 break;
813 case OMAP_DSS_VIDEO1:
814 case OMAP_DSS_VIDEO2:
b8c095b4 815 case OMAP_DSS_VIDEO3:
80c39712
TV		 816 shift = 16;
817 break;
818 default:
819 BUG();
820 return;
821 }
822
9b372c2d 823 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
2a205f34
SS		 824 if (dss_has_feature(FEAT_MGR_LCD2)) {
825 switch (channel) {
826 case OMAP_DSS_CHANNEL_LCD:
827 chan = 0;
828 chan2 = 0;
829 break;
830 case OMAP_DSS_CHANNEL_DIGIT:
831 chan = 1;
832 chan2 = 0;
833 break;
834 case OMAP_DSS_CHANNEL_LCD2:
835 chan = 0;
836 chan2 = 1;
837 break;
838 default:
839 BUG();
840 }
841
842 val = FLD_MOD(val, chan, shift, shift);
843 val = FLD_MOD(val, chan2, 31, 30);
844 } else {
845 val = FLD_MOD(val, channel, shift, shift);
846 }
9b372c2d 847 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 848}
849
2cc5d1af
TV		 850static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
851{
852 int shift;
853 u32 val;
854 enum omap_channel channel;
855
856 switch (plane) {
857 case OMAP_DSS_GFX:
858 shift = 8;
859 break;
860 case OMAP_DSS_VIDEO1:
861 case OMAP_DSS_VIDEO2:
862 case OMAP_DSS_VIDEO3:
863 shift = 16;
864 break;
865 default:
866 BUG();
867 }
868
869 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
870
871 if (dss_has_feature(FEAT_MGR_LCD2)) {
872 if (FLD_GET(val, 31, 30) == 0)
873 channel = FLD_GET(val, shift, shift);
874 else
875 channel = OMAP_DSS_CHANNEL_LCD2;
876 } else {
877 channel = FLD_GET(val, shift, shift);
878 }
879
880 return channel;
881}
882
f0e5caab 883static void dispc_ovl_set_burst_size(enum omap_plane plane,
80c39712
TV		 884 enum omap_burst_size burst_size)
885{
b8c095b4 886 static const unsigned shifts[] = { 6, 14, 14, 14, };
80c39712 887 int shift;
80c39712 888
fe3cc9d6 889 shift = shifts[plane];
5ed8cf5b 890 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
80c39712
TV		 891}
892
5ed8cf5b
TV		 893static void dispc_configure_burst_sizes(void)
894{
895 int i;
896 const int burst_size = BURST_SIZE_X8;
897
898 /* Configure burst size always to maximum size */
899 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
f0e5caab 900 dispc_ovl_set_burst_size(i, burst_size);
5ed8cf5b
TV		 901}
902
83fa2f2e 903static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
5ed8cf5b
TV		 904{
905 unsigned unit = dss_feat_get_burst_size_unit();
906 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
907 return unit * 8;
908}
909
d3862610
M		 910void dispc_enable_gamma_table(bool enable)
911{
912 /*
913 * This is partially implemented to support only disabling of
914 * the gamma table.
915 */
916 if (enable) {
917 DSSWARN("Gamma table enabling for TV not yet supported");
918 return;
919 }
920
921 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
922}
923
c64dca40 924static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
3c07cae2
TV		 925{
926 u16 reg;
927
928 if (channel == OMAP_DSS_CHANNEL_LCD)
929 reg = DISPC_CONFIG;
930 else if (channel == OMAP_DSS_CHANNEL_LCD2)
931 reg = DISPC_CONFIG2;
932 else
933 return;
934
935 REG_FLD_MOD(reg, enable, 15, 15);
936}
937
c64dca40 938static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
3c07cae2
TV		 939 struct omap_dss_cpr_coefs *coefs)
940{
941 u32 coef_r, coef_g, coef_b;
942
dac57a05 943 if (!dispc_mgr_is_lcd(channel))
3c07cae2
TV		 944 return;
945
946 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
947 FLD_VAL(coefs->rb, 9, 0);
948 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
949 FLD_VAL(coefs->gb, 9, 0);
950 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
951 FLD_VAL(coefs->bb, 9, 0);
952
953 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
954 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
955 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
956}
957
f0e5caab 958static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
80c39712
TV		 959{
960 u32 val;
961
962 BUG_ON(plane == OMAP_DSS_GFX);
963
9b372c2d 964 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 965 val = FLD_MOD(val, enable, 9, 9);
9b372c2d 966 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
80c39712
TV		 967}
968
c3d92529 969static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
80c39712 970{
b8c095b4 971 static const unsigned shifts[] = { 5, 10, 10, 10 };
fe3cc9d6 972 int shift;
80c39712 973
fe3cc9d6
TV		 974 shift = shifts[plane];
975 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
80c39712
TV		 976}
977
8f366162 978static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
e5c09e06 979 u16 height)
80c39712
TV		 980{
981 u32 val;
80c39712 982
80c39712 983 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
8f366162 984 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
80c39712
TV		 985}
986
987static void dispc_read_plane_fifo_sizes(void)
988{
80c39712
TV		 989 u32 size;
990 int plane;
a0acb557 991 u8 start, end;
5ed8cf5b
TV		 992 u32 unit;
993
994 unit = dss_feat_get_buffer_size_unit();
80c39712 995
a0acb557 996 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
80c39712 997
e13a138b 998 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
5ed8cf5b
TV		 999 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1000 size *= unit;
80c39712
TV		 1001 dispc.fifo_size[plane] = size;
1002 }
80c39712
TV		 1003}
1004
83fa2f2e 1005static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
80c39712
TV		 1006{
1007 return dispc.fifo_size[plane];
1008}
1009
6f04e1bf 1010void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
80c39712 1011{
a0acb557 1012 u8 hi_start, hi_end, lo_start, lo_end;
5ed8cf5b
TV		 1013 u32 unit;
1014
1015 unit = dss_feat_get_buffer_size_unit();
1016
1017 WARN_ON(low % unit != 0);
1018 WARN_ON(high % unit != 0);
1019
1020 low /= unit;
1021 high /= unit;
a0acb557 1022
9b372c2d
AT		 1023 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1024 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1025
3cb5d966 1026 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
80c39712 1027 plane,
9b372c2d 1028 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966 1029 lo_start, lo_end) * unit,
9b372c2d 1030 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
3cb5d966
TV		 1031 hi_start, hi_end) * unit,
1032 low * unit, high * unit);
80c39712 1033
9b372c2d 1034 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
a0acb557
AT		 1035 FLD_VAL(high, hi_start, hi_end) |
1036 FLD_VAL(low, lo_start, lo_end));
80c39712
TV		 1037}
1038
1039void dispc_enable_fifomerge(bool enable)
1040{
e6b0f884
TV		 1041 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1042 WARN_ON(enable);
1043 return;
1044 }
1045
80c39712
TV		 1046 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1047 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
80c39712
TV		 1048}
1049
83fa2f2e
TV		 1050void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1051 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge)
1052{
1053 /*
1054 * All sizes are in bytes. Both the buffer and burst are made of
1055 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1056 */
1057
1058 unsigned buf_unit = dss_feat_get_buffer_size_unit();
e0e405b9
TV		 1059 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1060 int i;
83fa2f2e
TV		 1061
1062 burst_size = dispc_ovl_get_burst_size(plane);
e0e405b9 1063 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
83fa2f2e 1064
e0e405b9
TV		 1065 if (use_fifomerge) {
1066 total_fifo_size = 0;
1067 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1068 total_fifo_size += dispc_ovl_get_fifo_size(i);
1069 } else {
1070 total_fifo_size = ovl_fifo_size;
1071 }
1072
1073 /*
1074 * We use the same low threshold for both fifomerge and non-fifomerge
1075 * cases, but for fifomerge we calculate the high threshold using the
1076 * combined fifo size
1077 */
1078
1079 if (dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1080 *fifo_low = ovl_fifo_size - burst_size * 2;
1081 *fifo_high = total_fifo_size - burst_size;
1082 } else {
1083 *fifo_low = ovl_fifo_size - burst_size;
1084 *fifo_high = total_fifo_size - buf_unit;
1085 }
83fa2f2e
TV		 1086}
1087
f0e5caab 1088static void dispc_ovl_set_fir(enum omap_plane plane,
0d66cbb5
AJ		 1089 int hinc, int vinc,
1090 enum omap_color_component color_comp)
80c39712
TV		 1091{
1092 u32 val;
80c39712 1093
0d66cbb5
AJ		 1094 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1095 u8 hinc_start, hinc_end, vinc_start, vinc_end;
a0acb557 1096
0d66cbb5
AJ		 1097 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1098 &hinc_start, &hinc_end);
1099 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1100 &vinc_start, &vinc_end);
1101 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1102 FLD_VAL(hinc, hinc_start, hinc_end);
a0acb557 1103
0d66cbb5
AJ		 1104 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1105 } else {
1106 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1107 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1108 }
80c39712
TV		 1109}
1110
f0e5caab 1111static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1112{
1113 u32 val;
87a7484b 1114 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1115
87a7484b
AT		 1116 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1117 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1118
1119 val = FLD_VAL(vaccu, vert_start, vert_end) |
1120 FLD_VAL(haccu, hor_start, hor_end);
1121
9b372c2d 1122 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
80c39712
TV		 1123}
1124
f0e5caab 1125static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
80c39712
TV		 1126{
1127 u32 val;
87a7484b 1128 u8 hor_start, hor_end, vert_start, vert_end;
80c39712 1129
87a7484b
AT		 1130 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1131 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1132
1133 val = FLD_VAL(vaccu, vert_start, vert_end) |
1134 FLD_VAL(haccu, hor_start, hor_end);
1135
9b372c2d 1136 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
80c39712
TV		 1137}
1138
f0e5caab
TV		 1139static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1140 int vaccu)
ab5ca071
AJ		 1141{
1142 u32 val;
1143
1144 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1145 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1146}
1147
f0e5caab
TV		 1148static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1149 int vaccu)
ab5ca071
AJ		 1150{
1151 u32 val;
1152
1153 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1154 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1155}
80c39712 1156
f0e5caab 1157static void dispc_ovl_set_scale_param(enum omap_plane plane,
80c39712
TV		 1158 u16 orig_width, u16 orig_height,
1159 u16 out_width, u16 out_height,
0d66cbb5
AJ		 1160 bool five_taps, u8 rotation,
1161 enum omap_color_component color_comp)
80c39712 1162{
0d66cbb5 1163 int fir_hinc, fir_vinc;
80c39712 1164
ed14a3ce
AJ		 1165 fir_hinc = 1024 * orig_width / out_width;
1166 fir_vinc = 1024 * orig_height / out_height;
80c39712 1167
debd9074
CM		 1168 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1169 color_comp);
f0e5caab 1170 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
0d66cbb5
AJ		 1171}
1172
f0e5caab 1173static void dispc_ovl_set_scaling_common(enum omap_plane plane,
0d66cbb5
AJ		 1174 u16 orig_width, u16 orig_height,
1175 u16 out_width, u16 out_height,
1176 bool ilace, bool five_taps,
1177 bool fieldmode, enum omap_color_mode color_mode,
1178 u8 rotation)
1179{
1180 int accu0 = 0;
1181 int accu1 = 0;
1182 u32 l;
80c39712 1183
f0e5caab 1184 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1185 out_width, out_height, five_taps,
1186 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
9b372c2d 1187 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
80c39712 1188
87a7484b
AT		 1189 /* RESIZEENABLE and VERTICALTAPS */
1190 l &= ~((0x3 << 5) | (0x1 << 21));
ed14a3ce
AJ		 1191 l |= (orig_width != out_width) ? (1 << 5) : 0;
1192 l |= (orig_height != out_height) ? (1 << 6) : 0;
87a7484b 1193 l |= five_taps ? (1 << 21) : 0;
80c39712 1194
87a7484b
AT		 1195 /* VRESIZECONF and HRESIZECONF */
1196 if (dss_has_feature(FEAT_RESIZECONF)) {
1197 l &= ~(0x3 << 7);
0d66cbb5
AJ		 1198 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1199 l |= (orig_height <= out_height) ? 0 : (1 << 8);
87a7484b 1200 }
80c39712 1201
87a7484b
AT		 1202 /* LINEBUFFERSPLIT */
1203 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1204 l &= ~(0x1 << 22);
1205 l |= five_taps ? (1 << 22) : 0;
1206 }
80c39712 1207
9b372c2d 1208 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
80c39712
TV		 1209
1210 /*
1211 * field 0 = even field = bottom field
1212 * field 1 = odd field = top field
1213 */
1214 if (ilace && !fieldmode) {
1215 accu1 = 0;
0d66cbb5 1216 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
80c39712
TV		 1217 if (accu0 >= 1024/2) {
1218 accu1 = 1024/2;
1219 accu0 -= accu1;
1220 }
1221 }
1222
f0e5caab
TV		 1223 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1224 dispc_ovl_set_vid_accu1(plane, 0, accu1);
80c39712
TV		 1225}
1226
f0e5caab 1227static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
0d66cbb5
AJ		 1228 u16 orig_width, u16 orig_height,
1229 u16 out_width, u16 out_height,
1230 bool ilace, bool five_taps,
1231 bool fieldmode, enum omap_color_mode color_mode,
1232 u8 rotation)
1233{
1234 int scale_x = out_width != orig_width;
1235 int scale_y = out_height != orig_height;
1236
1237 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1238 return;
1239 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1240 color_mode != OMAP_DSS_COLOR_UYVY &&
1241 color_mode != OMAP_DSS_COLOR_NV12)) {
1242 /* reset chroma resampling for RGB formats */
1243 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1244 return;
1245 }
1246 switch (color_mode) {
1247 case OMAP_DSS_COLOR_NV12:
1248 /* UV is subsampled by 2 vertically*/
1249 orig_height >>= 1;
1250 /* UV is subsampled by 2 horz.*/
1251 orig_width >>= 1;
1252 break;
1253 case OMAP_DSS_COLOR_YUV2:
1254 case OMAP_DSS_COLOR_UYVY:
1255 /*For YUV422 with 90/270 rotation,
1256 *we don't upsample chroma
1257 */
1258 if (rotation == OMAP_DSS_ROT_0 ||
1259 rotation == OMAP_DSS_ROT_180)
1260 /* UV is subsampled by 2 hrz*/
1261 orig_width >>= 1;
1262 /* must use FIR for YUV422 if rotated */
1263 if (rotation != OMAP_DSS_ROT_0)
1264 scale_x = scale_y = true;
1265 break;
1266 default:
1267 BUG();
1268 }
1269
1270 if (out_width != orig_width)
1271 scale_x = true;
1272 if (out_height != orig_height)
1273 scale_y = true;
1274
f0e5caab 1275 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
0d66cbb5
AJ		 1276 out_width, out_height, five_taps,
1277 rotation, DISPC_COLOR_COMPONENT_UV);
1278
1279 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1280 (scale_x || scale_y) ? 1 : 0, 8, 8);
1281 /* set H scaling */
1282 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1283 /* set V scaling */
1284 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1285
f0e5caab
TV		 1286 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1287 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
0d66cbb5
AJ		 1288}
1289
f0e5caab 1290static void dispc_ovl_set_scaling(enum omap_plane plane,
0d66cbb5
AJ		 1291 u16 orig_width, u16 orig_height,
1292 u16 out_width, u16 out_height,
1293 bool ilace, bool five_taps,
1294 bool fieldmode, enum omap_color_mode color_mode,
1295 u8 rotation)
1296{
1297 BUG_ON(plane == OMAP_DSS_GFX);
1298
f0e5caab 1299 dispc_ovl_set_scaling_common(plane,
0d66cbb5
AJ		 1300 orig_width, orig_height,
1301 out_width, out_height,
1302 ilace, five_taps,
1303 fieldmode, color_mode,
1304 rotation);
1305
f0e5caab 1306 dispc_ovl_set_scaling_uv(plane,
0d66cbb5
AJ		 1307 orig_width, orig_height,
1308 out_width, out_height,
1309 ilace, five_taps,
1310 fieldmode, color_mode,
1311 rotation);
1312}
1313
f0e5caab 1314static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
80c39712
TV		 1315 bool mirroring, enum omap_color_mode color_mode)
1316{
87a7484b
AT		 1317 bool row_repeat = false;
1318 int vidrot = 0;
1319
80c39712
TV		 1320 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1321 color_mode == OMAP_DSS_COLOR_UYVY) {
80c39712
TV		 1322
1323 if (mirroring) {
1324 switch (rotation) {
1325 case OMAP_DSS_ROT_0:
1326 vidrot = 2;
1327 break;
1328 case OMAP_DSS_ROT_90:
1329 vidrot = 1;
1330 break;
1331 case OMAP_DSS_ROT_180:
1332 vidrot = 0;
1333 break;
1334 case OMAP_DSS_ROT_270:
1335 vidrot = 3;
1336 break;
1337 }
1338 } else {
1339 switch (rotation) {
1340 case OMAP_DSS_ROT_0:
1341 vidrot = 0;
1342 break;
1343 case OMAP_DSS_ROT_90:
1344 vidrot = 1;
1345 break;
1346 case OMAP_DSS_ROT_180:
1347 vidrot = 2;
1348 break;
1349 case OMAP_DSS_ROT_270:
1350 vidrot = 3;
1351 break;
1352 }
1353 }
1354
80c39712 1355 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
87a7484b 1356 row_repeat = true;
80c39712 1357 else
87a7484b 1358 row_repeat = false;
80c39712 1359 }
87a7484b 1360
9b372c2d 1361 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
87a7484b 1362 if (dss_has_feature(FEAT_ROWREPEATENABLE))
9b372c2d
AT		 1363 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1364 row_repeat ? 1 : 0, 18, 18);
80c39712
TV		 1365}
1366
1367static int color_mode_to_bpp(enum omap_color_mode color_mode)
1368{
1369 switch (color_mode) {
1370 case OMAP_DSS_COLOR_CLUT1:
1371 return 1;
1372 case OMAP_DSS_COLOR_CLUT2:
1373 return 2;
1374 case OMAP_DSS_COLOR_CLUT4:
1375 return 4;
1376 case OMAP_DSS_COLOR_CLUT8:
f20e4220 1377 case OMAP_DSS_COLOR_NV12:
80c39712
TV		 1378 return 8;
1379 case OMAP_DSS_COLOR_RGB12U:
1380 case OMAP_DSS_COLOR_RGB16:
1381 case OMAP_DSS_COLOR_ARGB16:
1382 case OMAP_DSS_COLOR_YUV2:
1383 case OMAP_DSS_COLOR_UYVY:
f20e4220
AJ		 1384 case OMAP_DSS_COLOR_RGBA16:
1385 case OMAP_DSS_COLOR_RGBX16:
1386 case OMAP_DSS_COLOR_ARGB16_1555:
1387 case OMAP_DSS_COLOR_XRGB16_1555:
80c39712
TV		 1388 return 16;
1389 case OMAP_DSS_COLOR_RGB24P:
1390 return 24;
1391 case OMAP_DSS_COLOR_RGB24U:
1392 case OMAP_DSS_COLOR_ARGB32:
1393 case OMAP_DSS_COLOR_RGBA32:
1394 case OMAP_DSS_COLOR_RGBX32:
1395 return 32;
1396 default:
1397 BUG();
1398 }
1399}
1400
1401static s32 pixinc(int pixels, u8 ps)
1402{
1403 if (pixels == 1)
1404 return 1;
1405 else if (pixels > 1)
1406 return 1 + (pixels - 1) * ps;
1407 else if (pixels < 0)
1408 return 1 - (-pixels + 1) * ps;
1409 else
1410 BUG();
1411}
1412
1413static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1414 u16 screen_width,
1415 u16 width, u16 height,
1416 enum omap_color_mode color_mode, bool fieldmode,
1417 unsigned int field_offset,
1418 unsigned *offset0, unsigned *offset1,
aed74b55 1419 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1420{
1421 u8 ps;
1422
1423 /* FIXME CLUT formats */
1424 switch (color_mode) {
1425 case OMAP_DSS_COLOR_CLUT1:
1426 case OMAP_DSS_COLOR_CLUT2:
1427 case OMAP_DSS_COLOR_CLUT4:
1428 case OMAP_DSS_COLOR_CLUT8:
1429 BUG();
1430 return;
1431 case OMAP_DSS_COLOR_YUV2:
1432 case OMAP_DSS_COLOR_UYVY:
1433 ps = 4;
1434 break;
1435 default:
1436 ps = color_mode_to_bpp(color_mode) / 8;
1437 break;
1438 }
1439
1440 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1441 width, height);
1442
1443 /*
1444 * field 0 = even field = bottom field
1445 * field 1 = odd field = top field
1446 */
1447 switch (rotation + mirror * 4) {
1448 case OMAP_DSS_ROT_0:
1449 case OMAP_DSS_ROT_180:
1450 /*
1451 * If the pixel format is YUV or UYVY divide the width
1452 * of the image by 2 for 0 and 180 degree rotation.
1453 */
1454 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1455 color_mode == OMAP_DSS_COLOR_UYVY)
1456 width = width >> 1;
1457 case OMAP_DSS_ROT_90:
1458 case OMAP_DSS_ROT_270:
1459 *offset1 = 0;
1460 if (field_offset)
1461 *offset0 = field_offset * screen_width * ps;
1462 else
1463 *offset0 = 0;
1464
aed74b55
CM		 1465 *row_inc = pixinc(1 +
1466 (y_predecim * screen_width - x_predecim * width) +
1467 (fieldmode ? screen_width : 0), ps);
1468 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1469 break;
1470
1471 case OMAP_DSS_ROT_0 + 4:
1472 case OMAP_DSS_ROT_180 + 4:
1473 /* If the pixel format is YUV or UYVY divide the width
1474 * of the image by 2 for 0 degree and 180 degree
1475 */
1476 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1477 color_mode == OMAP_DSS_COLOR_UYVY)
1478 width = width >> 1;
1479 case OMAP_DSS_ROT_90 + 4:
1480 case OMAP_DSS_ROT_270 + 4:
1481 *offset1 = 0;
1482 if (field_offset)
1483 *offset0 = field_offset * screen_width * ps;
1484 else
1485 *offset0 = 0;
aed74b55
CM		 1486 *row_inc = pixinc(1 -
1487 (y_predecim * screen_width + x_predecim * width) -
1488 (fieldmode ? screen_width : 0), ps);
1489 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1490 break;
1491
1492 default:
1493 BUG();
1494 }
1495}
1496
1497static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1498 u16 screen_width,
1499 u16 width, u16 height,
1500 enum omap_color_mode color_mode, bool fieldmode,
1501 unsigned int field_offset,
1502 unsigned *offset0, unsigned *offset1,
aed74b55 1503 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
80c39712
TV		 1504{
1505 u8 ps;
1506 u16 fbw, fbh;
1507
1508 /* FIXME CLUT formats */
1509 switch (color_mode) {
1510 case OMAP_DSS_COLOR_CLUT1:
1511 case OMAP_DSS_COLOR_CLUT2:
1512 case OMAP_DSS_COLOR_CLUT4:
1513 case OMAP_DSS_COLOR_CLUT8:
1514 BUG();
1515 return;
1516 default:
1517 ps = color_mode_to_bpp(color_mode) / 8;
1518 break;
1519 }
1520
1521 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1522 width, height);
1523
1524 /* width & height are overlay sizes, convert to fb sizes */
1525
1526 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1527 fbw = width;
1528 fbh = height;
1529 } else {
1530 fbw = height;
1531 fbh = width;
1532 }
1533
1534 /*
1535 * field 0 = even field = bottom field
1536 * field 1 = odd field = top field
1537 */
1538 switch (rotation + mirror * 4) {
1539 case OMAP_DSS_ROT_0:
1540 *offset1 = 0;
1541 if (field_offset)
1542 *offset0 = *offset1 + field_offset * screen_width * ps;
1543 else
1544 *offset0 = *offset1;
aed74b55
CM		 1545 *row_inc = pixinc(1 +
1546 (y_predecim * screen_width - fbw * x_predecim) +
1547 (fieldmode ? screen_width : 0), ps);
1548 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1549 color_mode == OMAP_DSS_COLOR_UYVY)
1550 *pix_inc = pixinc(x_predecim, 2 * ps);
1551 else
1552 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1553 break;
1554 case OMAP_DSS_ROT_90:
1555 *offset1 = screen_width * (fbh - 1) * ps;
1556 if (field_offset)
1557 *offset0 = *offset1 + field_offset * ps;
1558 else
1559 *offset0 = *offset1;
aed74b55
CM		 1560 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1561 y_predecim + (fieldmode ? 1 : 0), ps);
1562 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1563 break;
1564 case OMAP_DSS_ROT_180:
1565 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1566 if (field_offset)
1567 *offset0 = *offset1 - field_offset * screen_width * ps;
1568 else
1569 *offset0 = *offset1;
1570 *row_inc = pixinc(-1 -
aed74b55
CM		 1571 (y_predecim * screen_width - fbw * x_predecim) -
1572 (fieldmode ? screen_width : 0), ps);
1573 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1574 color_mode == OMAP_DSS_COLOR_UYVY)
1575 *pix_inc = pixinc(-x_predecim, 2 * ps);
1576 else
1577 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1578 break;
1579 case OMAP_DSS_ROT_270:
1580 *offset1 = (fbw - 1) * ps;
1581 if (field_offset)
1582 *offset0 = *offset1 - field_offset * ps;
1583 else
1584 *offset0 = *offset1;
aed74b55
CM		 1585 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1586 y_predecim - (fieldmode ? 1 : 0), ps);
1587 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1588 break;
1589
1590 /* mirroring */
1591 case OMAP_DSS_ROT_0 + 4:
1592 *offset1 = (fbw - 1) * ps;
1593 if (field_offset)
1594 *offset0 = *offset1 + field_offset * screen_width * ps;
1595 else
1596 *offset0 = *offset1;
aed74b55 1597 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
80c39712
TV		 1598 (fieldmode ? screen_width : 0),
1599 ps);
aed74b55
CM		 1600 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1601 color_mode == OMAP_DSS_COLOR_UYVY)
1602 *pix_inc = pixinc(-x_predecim, 2 * ps);
1603 else
1604 *pix_inc = pixinc(-x_predecim, ps);
80c39712
TV		 1605 break;
1606
1607 case OMAP_DSS_ROT_90 + 4:
1608 *offset1 = 0;
1609 if (field_offset)
1610 *offset0 = *offset1 + field_offset * ps;
1611 else
1612 *offset0 = *offset1;
aed74b55
CM		 1613 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1614 y_predecim + (fieldmode ? 1 : 0),
80c39712 1615 ps);
aed74b55 1616 *pix_inc = pixinc(x_predecim * screen_width, ps);
80c39712
TV		 1617 break;
1618
1619 case OMAP_DSS_ROT_180 + 4:
1620 *offset1 = screen_width * (fbh - 1) * ps;
1621 if (field_offset)
1622 *offset0 = *offset1 - field_offset * screen_width * ps;
1623 else
1624 *offset0 = *offset1;
aed74b55 1625 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
80c39712
TV		 1626 (fieldmode ? screen_width : 0),
1627 ps);
aed74b55
CM		 1628 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1629 color_mode == OMAP_DSS_COLOR_UYVY)
1630 *pix_inc = pixinc(x_predecim, 2 * ps);
1631 else
1632 *pix_inc = pixinc(x_predecim, ps);
80c39712
TV		 1633 break;
1634
1635 case OMAP_DSS_ROT_270 + 4:
1636 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1637 if (field_offset)
1638 *offset0 = *offset1 - field_offset * ps;
1639 else
1640 *offset0 = *offset1;
aed74b55
CM		 1641 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1642 y_predecim - (fieldmode ? 1 : 0),
80c39712 1643 ps);
aed74b55 1644 *pix_inc = pixinc(-x_predecim * screen_width, ps);
80c39712
TV		 1645 break;
1646
1647 default:
1648 BUG();
1649 }
1650}
1651
7faa9233
CM		 1652/*
1653 * This function is used to avoid synclosts in OMAP3, because of some
1654 * undocumented horizontal position and timing related limitations.
1655 */
81ab95b7
AT		 1656static int check_horiz_timing_omap3(enum omap_channel channel,
1657 const struct omap_video_timings *t, u16 pos_x,
7faa9233
CM		 1658 u16 width, u16 height, u16 out_width, u16 out_height)
1659{
1660 int DS = DIV_ROUND_UP(height, out_height);
7faa9233
CM		 1661 unsigned long nonactive, lclk, pclk;
1662 static const u8 limits[3] = { 8, 10, 20 };
1663 u64 val, blank;
1664 int i;
1665
81ab95b7 1666 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
7faa9233
CM		 1667 pclk = dispc_mgr_pclk_rate(channel);
1668 if (dispc_mgr_is_lcd(channel))
1669 lclk = dispc_mgr_lclk_rate(channel);
1670 else
1671 lclk = dispc_fclk_rate();
1672
1673 i = 0;
1674 if (out_height < height)
1675 i++;
1676 if (out_width < width)
1677 i++;
81ab95b7 1678 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
7faa9233
CM		 1679 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1680 if (blank <= limits[i])
1681 return -EINVAL;
1682
1683 /*
1684 * Pixel data should be prepared before visible display point starts.
1685 * So, atleast DS-2 lines must have already been fetched by DISPC
1686 * during nonactive - pos_x period.
1687 */
1688 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1689 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1690 val, max(0, DS - 2) * width);
1691 if (val < max(0, DS - 2) * width)
1692 return -EINVAL;
1693
1694 /*
1695 * All lines need to be refilled during the nonactive period of which
1696 * only one line can be loaded during the active period. So, atleast
1697 * DS - 1 lines should be loaded during nonactive period.
1698 */
1699 val = div_u64((u64)nonactive * lclk, pclk);
1700 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1701 val, max(0, DS - 1) * width);
1702 if (val < max(0, DS - 1) * width)
1703 return -EINVAL;
1704
1705 return 0;
1706}
1707
8b53d991 1708static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
81ab95b7
AT		 1709 const struct omap_video_timings *mgr_timings, u16 width,
1710 u16 height, u16 out_width, u16 out_height,
ff1b2cde 1711 enum omap_color_mode color_mode)
80c39712 1712{
8b53d991 1713 u32 core_clk = 0;
26d9dd0d 1714 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
80c39712 1715
7282f1b7
CM		 1716 if (height <= out_height && width <= out_width)
1717 return (unsigned long) pclk;
1718
80c39712 1719 if (height > out_height) {
81ab95b7 1720 unsigned int ppl = mgr_timings->x_res;
80c39712
TV		 1721
1722 tmp = pclk * height * out_width;
1723 do_div(tmp, 2 * out_height * ppl);
8b53d991 1724 core_clk = tmp;
80c39712 1725
2d9c5597
VS		 1726 if (height > 2 * out_height) {
1727 if (ppl == out_width)
1728 return 0;
1729
80c39712
TV		 1730 tmp = pclk * (height - 2 * out_height) * out_width;
1731 do_div(tmp, 2 * out_height * (ppl - out_width));
8b53d991 1732 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1733 }
1734 }
1735
1736 if (width > out_width) {
1737 tmp = pclk * width;
1738 do_div(tmp, out_width);
8b53d991 1739 core_clk = max_t(u32, core_clk, tmp);
80c39712
TV		 1740
1741 if (color_mode == OMAP_DSS_COLOR_RGB24U)
8b53d991 1742 core_clk <<= 1;
80c39712
TV		 1743 }
1744
8b53d991 1745 return core_clk;
80c39712
TV		 1746}
1747
8b53d991 1748static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
ff1b2cde 1749 u16 height, u16 out_width, u16 out_height)
80c39712
TV		 1750{
1751 unsigned int hf, vf;
79ee89cd 1752 unsigned long pclk = dispc_mgr_pclk_rate(channel);
80c39712
TV		 1753
1754 /*
1755 * FIXME how to determine the 'A' factor
1756 * for the no downscaling case ?
1757 */
1758
1759 if (width > 3 * out_width)
1760 hf = 4;
1761 else if (width > 2 * out_width)
1762 hf = 3;
1763 else if (width > out_width)
1764 hf = 2;
1765 else
1766 hf = 1;
1767
1768 if (height > out_height)
1769 vf = 2;
1770 else
1771 vf = 1;
1772
7282f1b7
CM		 1773 if (cpu_is_omap24xx()) {
1774 if (vf > 1 && hf > 1)
79ee89cd 1775 return pclk * 4;
7282f1b7 1776 else
79ee89cd 1777 return pclk * 2;
7282f1b7 1778 } else if (cpu_is_omap34xx()) {
79ee89cd 1779 return pclk * vf * hf;
7282f1b7 1780 } else {
79ee89cd
AT		 1781 if (hf > 1)
1782 return DIV_ROUND_UP(pclk, out_width) * width;
1783 else
1784 return pclk;
7282f1b7 1785 }
80c39712
TV		 1786}
1787
79ad75f2 1788static int dispc_ovl_calc_scaling(enum omap_plane plane,
81ab95b7
AT		 1789 enum omap_channel channel,
1790 const struct omap_video_timings *mgr_timings,
1791 u16 width, u16 height, u16 out_width, u16 out_height,
aed74b55 1792 enum omap_color_mode color_mode, bool *five_taps,
7faa9233 1793 int *x_predecim, int *y_predecim, u16 pos_x)
79ad75f2
AT		 1794{
1795 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
0373cac6 1796 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
7282f1b7
CM		 1797 const int maxsinglelinewidth =
1798 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
aed74b55 1799 const int max_decim_limit = 16;
8b53d991 1800 unsigned long core_clk = 0;
aed74b55
CM		 1801 int decim_x, decim_y, error, min_factor;
1802 u16 in_width, in_height, in_width_max = 0;
79ad75f2 1803
f95cb5eb
TV		 1804 if (width == out_width && height == out_height)
1805 return 0;
1806
1807 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1808 return -EINVAL;
79ad75f2 1809
aed74b55
CM		 1810 *x_predecim = max_decim_limit;
1811 *y_predecim = max_decim_limit;
1812
1813 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
1814 color_mode == OMAP_DSS_COLOR_CLUT2 ||
1815 color_mode == OMAP_DSS_COLOR_CLUT4 ||
1816 color_mode == OMAP_DSS_COLOR_CLUT8) {
1817 *x_predecim = 1;
1818 *y_predecim = 1;
1819 *five_taps = false;
1820 return 0;
1821 }
1822
1823 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
1824 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
1825
1826 min_factor = min(decim_x, decim_y);
1827
1828 if (decim_x > *x_predecim || out_width > width * 8)
79ad75f2
AT		 1829 return -EINVAL;
1830
aed74b55 1831 if (decim_y > *y_predecim || out_height > height * 8)
79ad75f2
AT		 1832 return -EINVAL;
1833
7282f1b7 1834 if (cpu_is_omap24xx()) {
7282f1b7 1835 *five_taps = false;
aed74b55
CM		 1836
1837 do {
1838 in_height = DIV_ROUND_UP(height, decim_y);
1839 in_width = DIV_ROUND_UP(width, decim_x);
8b53d991 1840 core_clk = calc_core_clk(channel, in_width, in_height,
aed74b55 1841 out_width, out_height);
8b53d991
CM		 1842 error = (in_width > maxsinglelinewidth || !core_clk ||
1843 core_clk > dispc_core_clk_rate());
aed74b55
CM		 1844 if (error) {
1845 if (decim_x == decim_y) {
1846 decim_x = min_factor;
1847 decim_y++;
1848 } else {
1849 swap(decim_x, decim_y);
1850 if (decim_x < decim_y)
1851 decim_x++;
1852 }
1853 }
1854 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
1855 error);
1856
1857 if (in_width > maxsinglelinewidth) {
1858 DSSERR("Cannot scale max input width exceeded");
1859 return -EINVAL;
1860 }
7282f1b7 1861 } else if (cpu_is_omap34xx()) {
aed74b55
CM		 1862
1863 do {
1864 in_height = DIV_ROUND_UP(height, decim_y);
1865 in_width = DIV_ROUND_UP(width, decim_x);
81ab95b7
AT		 1866 core_clk = calc_core_clk_five_taps(channel, mgr_timings,
1867 in_width, in_height, out_width, out_height,
1868 color_mode);
aed74b55 1869
81ab95b7
AT		 1870 error = check_horiz_timing_omap3(channel, mgr_timings,
1871 pos_x, in_width, in_height, out_width,
1872 out_height);
7faa9233 1873
aed74b55
CM		 1874 if (in_width > maxsinglelinewidth)
1875 if (in_height > out_height &&
1876 in_height < out_height * 2)
1877 *five_taps = false;
1878 if (!*five_taps)
8b53d991
CM		 1879 core_clk = calc_core_clk(channel, in_width,
1880 in_height, out_width, out_height);
7faa9233 1881 error = (error || in_width > maxsinglelinewidth * 2 ||
aed74b55 1882 (in_width > maxsinglelinewidth && *five_taps) ||
8b53d991 1883 !core_clk || core_clk > dispc_core_clk_rate());
aed74b55
CM		 1884 if (error) {
1885 if (decim_x == decim_y) {
1886 decim_x = min_factor;
1887 decim_y++;
1888 } else {
1889 swap(decim_x, decim_y);
1890 if (decim_x < decim_y)
1891 decim_x++;
1892 }
1893 }
1894 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
1895 && error);
1896
81ab95b7
AT		 1897 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
1898 height, out_width, out_height)){
7faa9233
CM		 1899 DSSERR("horizontal timing too tight\n");
1900 return -EINVAL;
1901 }
1902
aed74b55 1903 if (in_width > (maxsinglelinewidth * 2)) {
7282f1b7
CM		 1904 DSSERR("Cannot setup scaling");
1905 DSSERR("width exceeds maximum width possible");
1906 return -EINVAL;
1907 }
aed74b55
CM		 1908
1909 if (in_width > maxsinglelinewidth && *five_taps) {
1910 DSSERR("cannot setup scaling with five taps");
1911 return -EINVAL;
7282f1b7 1912 }
7282f1b7 1913 } else {
aed74b55
CM		 1914 int decim_x_min = decim_x;
1915 in_height = DIV_ROUND_UP(height, decim_y);
8b53d991 1916 in_width_max = dispc_core_clk_rate() /
aed74b55
CM		 1917 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
1918 out_width);
1919 decim_x = DIV_ROUND_UP(width, in_width_max);
1920
1921 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
1922 if (decim_x > *x_predecim)
1923 return -EINVAL;
1924
1925 do {
1926 in_width = DIV_ROUND_UP(width, decim_x);
1927 } while (decim_x <= *x_predecim &&
1928 in_width > maxsinglelinewidth && decim_x++);
1929
1930 if (in_width > maxsinglelinewidth) {
7282f1b7
CM		 1931 DSSERR("Cannot scale width exceeds max line width");
1932 return -EINVAL;
1933 }
aed74b55 1934
8b53d991
CM		 1935 core_clk = calc_core_clk(channel, in_width, in_height,
1936 out_width, out_height);
79ad75f2
AT		 1937 }
1938
8b53d991
CM		 1939 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
1940 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
79ad75f2 1941
8b53d991 1942 if (!core_clk || core_clk > dispc_core_clk_rate()) {
79ad75f2 1943 DSSERR("failed to set up scaling, "
8b53d991
CM		 1944 "required core clk rate = %lu Hz, "
1945 "current core clk rate = %lu Hz\n",
1946 core_clk, dispc_core_clk_rate());
79ad75f2
AT		 1947 return -EINVAL;
1948 }
1949
aed74b55
CM		 1950 *x_predecim = decim_x;
1951 *y_predecim = decim_y;
79ad75f2
AT		 1952 return 0;
1953}
1954
a4273b7c 1955int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
81ab95b7
AT		 1956 bool ilace, bool replication,
1957 const struct omap_video_timings *mgr_timings)
80c39712 1958{
79ad75f2 1959 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
7282f1b7 1960 bool five_taps = true;
80c39712 1961 bool fieldmode = 0;
79ad75f2 1962 int r, cconv = 0;
80c39712
TV		 1963 unsigned offset0, offset1;
1964 s32 row_inc;
1965 s32 pix_inc;
a4273b7c 1966 u16 frame_height = oi->height;
80c39712 1967 unsigned int field_offset = 0;
aed74b55
CM		 1968 u16 in_height = oi->height;
1969 u16 in_width = oi->width;
1970 u16 out_width, out_height;
2cc5d1af 1971 enum omap_channel channel;
aed74b55 1972 int x_predecim = 1, y_predecim = 1;
2cc5d1af
TV		 1973
1974 channel = dispc_ovl_get_channel_out(plane);
80c39712 1975
a4273b7c 1976 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
f38545da
TV		 1977 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
1978 plane, oi->paddr, oi->p_uv_addr,
c3d92529
AT		 1979 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1980 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
f38545da 1981 oi->mirror, ilace, channel, replication);
e6d80f95 1982
a4273b7c 1983 if (oi->paddr == 0)
80c39712
TV		 1984 return -EINVAL;
1985
aed74b55
CM		 1986 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
1987 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
cf073668 1988
aed74b55 1989 if (ilace && oi->height == out_height)
80c39712
TV		 1990 fieldmode = 1;
1991
1992 if (ilace) {
1993 if (fieldmode)
aed74b55 1994 in_height /= 2;
a4273b7c 1995 oi->pos_y /= 2;
aed74b55 1996 out_height /= 2;
80c39712
TV		 1997
1998 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1999 "out_height %d\n",
aed74b55 2000 in_height, oi->pos_y, out_height);
80c39712
TV		 2001 }
2002
a4273b7c 2003 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
8dad2ab6
AT		 2004 return -EINVAL;
2005
81ab95b7
AT		 2006 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2007 in_height, out_width, out_height, oi->color_mode,
2008 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
79ad75f2
AT		 2009 if (r)
2010 return r;
80c39712 2011
aed74b55
CM		 2012 in_width = DIV_ROUND_UP(in_width, x_predecim);
2013 in_height = DIV_ROUND_UP(in_height, y_predecim);
2014
79ad75f2
AT		 2015 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2016 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2017 oi->color_mode == OMAP_DSS_COLOR_NV12)
2018 cconv = 1;
80c39712
TV		 2019
2020 if (ilace && !fieldmode) {
2021 /*
2022 * when downscaling the bottom field may have to start several
2023 * source lines below the top field. Unfortunately ACCUI
2024 * registers will only hold the fractional part of the offset
2025 * so the integer part must be added to the base address of the
2026 * bottom field.
2027 */
aed74b55 2028 if (!in_height || in_height == out_height)
80c39712
TV		 2029 field_offset = 0;
2030 else
aed74b55 2031 field_offset = in_height / out_height / 2;
80c39712
TV		 2032 }
2033
2034 /* Fields are independent but interleaved in memory. */
2035 if (fieldmode)
2036 field_offset = 1;
2037
a4273b7c
AT		 2038 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
2039 calc_dma_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2040 oi->screen_width, in_width, frame_height,
a4273b7c 2041 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2042 &offset0, &offset1, &row_inc, &pix_inc,
2043 x_predecim, y_predecim);
80c39712 2044 else
a4273b7c 2045 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
aed74b55 2046 oi->screen_width, in_width, frame_height,
a4273b7c 2047 oi->color_mode, fieldmode, field_offset,
aed74b55
CM		 2048 &offset0, &offset1, &row_inc, &pix_inc,
2049 x_predecim, y_predecim);
80c39712
TV		 2050
2051 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2052 offset0, offset1, row_inc, pix_inc);
2053
a4273b7c 2054 dispc_ovl_set_color_mode(plane, oi->color_mode);
80c39712 2055
a4273b7c
AT		 2056 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2057 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
80c39712 2058
a4273b7c
AT		 2059 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2060 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2061 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
0d66cbb5
AJ		 2062 }
2063
2064
f0e5caab
TV		 2065 dispc_ovl_set_row_inc(plane, row_inc);
2066 dispc_ovl_set_pix_inc(plane, pix_inc);
80c39712 2067
aed74b55
CM		 2068 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2069 in_height, out_width, out_height);
80c39712 2070
a4273b7c 2071 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
80c39712 2072
aed74b55 2073 dispc_ovl_set_pic_size(plane, in_width, in_height);
80c39712 2074
79ad75f2 2075 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
aed74b55
CM		 2076 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2077 out_height, ilace, five_taps, fieldmode,
a4273b7c 2078 oi->color_mode, oi->rotation);
aed74b55 2079 dispc_ovl_set_vid_size(plane, out_width, out_height);
f0e5caab 2080 dispc_ovl_set_vid_color_conv(plane, cconv);
80c39712
TV		 2081 }
2082
a4273b7c
AT		 2083 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2084 oi->color_mode);
80c39712 2085
54128701 2086 dispc_ovl_set_zorder(plane, oi->zorder);
a4273b7c
AT		 2087 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2088 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
80c39712 2089
c3d92529 2090 dispc_ovl_enable_replication(plane, replication);
c3d92529 2091
80c39712
TV		 2092 return 0;
2093}
2094
f0e5caab 2095int dispc_ovl_enable(enum omap_plane plane, bool enable)
80c39712 2096{
e6d80f95
TV		 2097 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2098
9b372c2d 2099 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
e6d80f95
TV		 2100
2101 return 0;
80c39712
TV		 2102}
2103
2104static void dispc_disable_isr(void *data, u32 mask)
2105{
2106 struct completion *compl = data;
2107 complete(compl);
2108}
2109
2a205f34 2110static void _enable_lcd_out(enum omap_channel channel, bool enable)
80c39712 2111{
b6a44e77 2112 if (channel == OMAP_DSS_CHANNEL_LCD2) {
2a205f34 2113 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2114 /* flush posted write */
2115 dispc_read_reg(DISPC_CONTROL2);
2116 } else {
2a205f34 2117 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
b6a44e77
TV		 2118 dispc_read_reg(DISPC_CONTROL);
2119 }
80c39712
TV		 2120}
2121
26d9dd0d 2122static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
80c39712
TV		 2123{
2124 struct completion frame_done_completion;
2125 bool is_on;
2126 int r;
2a205f34 2127 u32 irq;
80c39712 2128
80c39712
TV		 2129 /* When we disable LCD output, we need to wait until frame is done.
2130 * Otherwise the DSS is still working, and turning off the clocks
2131 * prevents DSS from going to OFF mode */
2a205f34
SS		 2132 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2133 REG_GET(DISPC_CONTROL2, 0, 0) :
2134 REG_GET(DISPC_CONTROL, 0, 0);
2135
2136 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2137 DISPC_IRQ_FRAMEDONE;
80c39712
TV		 2138
2139 if (!enable && is_on) {
2140 init_completion(&frame_done_completion);
2141
2142 r = omap_dispc_register_isr(dispc_disable_isr,
2a205f34 2143 &frame_done_completion, irq);
80c39712
TV		 2144
2145 if (r)
2146 DSSERR("failed to register FRAMEDONE isr\n");
2147 }
2148
2a205f34 2149 _enable_lcd_out(channel, enable);
80c39712
TV		 2150
2151 if (!enable && is_on) {
2152 if (!wait_for_completion_timeout(&frame_done_completion,
2153 msecs_to_jiffies(100)))
2154 DSSERR("timeout waiting for FRAME DONE\n");
2155
2156 r = omap_dispc_unregister_isr(dispc_disable_isr,
2a205f34 2157 &frame_done_completion, irq);
80c39712
TV		 2158
2159 if (r)
2160 DSSERR("failed to unregister FRAMEDONE isr\n");
2161 }
80c39712
TV		 2162}
2163
2164static void _enable_digit_out(bool enable)
2165{
2166 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
b6a44e77
TV		 2167 /* flush posted write */
2168 dispc_read_reg(DISPC_CONTROL);
80c39712
TV		 2169}
2170
26d9dd0d 2171static void dispc_mgr_enable_digit_out(bool enable)
80c39712
TV		 2172{
2173 struct completion frame_done_completion;
e82b090b
TV		 2174 enum dss_hdmi_venc_clk_source_select src;
2175 int r, i;
2176 u32 irq_mask;
2177 int num_irqs;
80c39712 2178
e6d80f95 2179 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
80c39712 2180 return;
80c39712 2181
e82b090b
TV		 2182 src = dss_get_hdmi_venc_clk_source();
2183
80c39712
TV		 2184 if (enable) {
2185 unsigned long flags;
2186 /* When we enable digit output, we'll get an extra digit
2187 * sync lost interrupt, that we need to ignore */
2188 spin_lock_irqsave(&dispc.irq_lock, flags);
2189 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2190 _omap_dispc_set_irqs();
2191 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2192 }
2193
2194 /* When we disable digit output, we need to wait until fields are done.
2195 * Otherwise the DSS is still working, and turning off the clocks
2196 * prevents DSS from going to OFF mode. And when enabling, we need to
2197 * wait for the extra sync losts */
2198 init_completion(&frame_done_completion);
2199
e82b090b
TV		 2200 if (src == DSS_HDMI_M_PCLK && enable == false) {
2201 irq_mask = DISPC_IRQ_FRAMEDONETV;
2202 num_irqs = 1;
2203 } else {
2204 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2205 /* XXX I understand from TRM that we should only wait for the
2206 * current field to complete. But it seems we have to wait for
2207 * both fields */
2208 num_irqs = 2;
2209 }
2210
80c39712 2211 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
e82b090b 2212 irq_mask);
80c39712 2213 if (r)
e82b090b 2214 DSSERR("failed to register %x isr\n", irq_mask);
80c39712
TV		 2215
2216 _enable_digit_out(enable);
2217
e82b090b
TV		 2218 for (i = 0; i < num_irqs; ++i) {
2219 if (!wait_for_completion_timeout(&frame_done_completion,
2220 msecs_to_jiffies(100)))
2221 DSSERR("timeout waiting for digit out to %s\n",
2222 enable ? "start" : "stop");
2223 }
80c39712 2224
e82b090b
TV		 2225 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2226 irq_mask);
80c39712 2227 if (r)
e82b090b 2228 DSSERR("failed to unregister %x isr\n", irq_mask);
80c39712
TV		 2229
2230 if (enable) {
2231 unsigned long flags;
2232 spin_lock_irqsave(&dispc.irq_lock, flags);
e82b090b 2233 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
80c39712
TV		 2234 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2235 _omap_dispc_set_irqs();
2236 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2237 }
80c39712
TV		 2238}
2239
26d9dd0d 2240bool dispc_mgr_is_enabled(enum omap_channel channel)
a2faee84
TV		 2241{
2242 if (channel == OMAP_DSS_CHANNEL_LCD)
2243 return !!REG_GET(DISPC_CONTROL, 0, 0);
2244 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2245 return !!REG_GET(DISPC_CONTROL, 1, 1);
2a205f34
SS		 2246 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2247 return !!REG_GET(DISPC_CONTROL2, 0, 0);
a2faee84
TV		 2248 else
2249 BUG();
2250}
2251
26d9dd0d 2252void dispc_mgr_enable(enum omap_channel channel, bool enable)
a2faee84 2253{
dac57a05 2254 if (dispc_mgr_is_lcd(channel))
26d9dd0d 2255 dispc_mgr_enable_lcd_out(channel, enable);
a2faee84 2256 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
26d9dd0d 2257 dispc_mgr_enable_digit_out(enable);
a2faee84
TV		 2258 else
2259 BUG();
2260}
2261
80c39712
TV		 2262void dispc_lcd_enable_signal_polarity(bool act_high)
2263{
6ced40bf
AT		 2264 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2265 return;
2266
80c39712 2267 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
80c39712
TV		 2268}
2269
2270void dispc_lcd_enable_signal(bool enable)
2271{
6ced40bf
AT		 2272 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2273 return;
2274
80c39712 2275 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
80c39712
TV		 2276}
2277
2278void dispc_pck_free_enable(bool enable)
2279{
6ced40bf
AT		 2280 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2281 return;
2282
80c39712 2283 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
80c39712
TV		 2284}
2285
26d9dd0d 2286void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
80c39712 2287{
2a205f34
SS		 2288 if (channel == OMAP_DSS_CHANNEL_LCD2)
2289 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2290 else
2291 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
80c39712
TV		 2292}
2293
2294
26d9dd0d 2295void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
64ba4f74 2296 enum omap_lcd_display_type type)
80c39712
TV		 2297{
2298 int mode;
2299
2300 switch (type) {
2301 case OMAP_DSS_LCD_DISPLAY_STN:
2302 mode = 0;
2303 break;
2304
2305 case OMAP_DSS_LCD_DISPLAY_TFT:
2306 mode = 1;
2307 break;
2308
2309 default:
2310 BUG();
2311 return;
2312 }
2313
2a205f34
SS		 2314 if (channel == OMAP_DSS_CHANNEL_LCD2)
2315 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2316 else
2317 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
80c39712
TV		 2318}
2319
2320void dispc_set_loadmode(enum omap_dss_load_mode mode)
2321{
80c39712 2322 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
80c39712
TV		 2323}
2324
2325
c64dca40 2326static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
80c39712 2327{
8613b000 2328 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
80c39712
TV		 2329}
2330
c64dca40 2331static void dispc_mgr_set_trans_key(enum omap_channel ch,
80c39712
TV		 2332 enum omap_dss_trans_key_type type,
2333 u32 trans_key)
2334{
80c39712
TV		 2335 if (ch == OMAP_DSS_CHANNEL_LCD)
2336 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2a205f34 2337 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2338 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2a205f34
SS		 2339 else /* OMAP_DSS_CHANNEL_LCD2 */
2340 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
80c39712 2341
8613b000 2342 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
80c39712
TV		 2343}
2344
c64dca40 2345static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
80c39712 2346{
80c39712
TV		 2347 if (ch == OMAP_DSS_CHANNEL_LCD)
2348 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2a205f34 2349 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2350 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2a205f34
SS		 2351 else /* OMAP_DSS_CHANNEL_LCD2 */
2352 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
80c39712 2353}
11354dd5 2354
c64dca40
TV		 2355static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2356 bool enable)
80c39712 2357{
11354dd5 2358 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
80c39712
TV		 2359 return;
2360
80c39712
TV		 2361 if (ch == OMAP_DSS_CHANNEL_LCD)
2362 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2a205f34 2363 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
80c39712 2364 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
80c39712 2365}
11354dd5 2366
c64dca40
TV		 2367void dispc_mgr_setup(enum omap_channel channel,
2368 struct omap_overlay_manager_info *info)
2369{
2370 dispc_mgr_set_default_color(channel, info->default_color);
2371 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2372 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2373 dispc_mgr_enable_alpha_fixed_zorder(channel,
2374 info->partial_alpha_enabled);
2375 if (dss_has_feature(FEAT_CPR)) {
2376 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2377 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2378 }
2379}
80c39712 2380
26d9dd0d 2381void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
80c39712
TV		 2382{
2383 int code;
2384
2385 switch (data_lines) {
2386 case 12:
2387 code = 0;
2388 break;
2389 case 16:
2390 code = 1;
2391 break;
2392 case 18:
2393 code = 2;
2394 break;
2395 case 24:
2396 code = 3;
2397 break;
2398 default:
2399 BUG();
2400 return;
2401 }
2402
2a205f34
SS		 2403 if (channel == OMAP_DSS_CHANNEL_LCD2)
2404 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2405 else
2406 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
80c39712
TV		 2407}
2408
569969d6 2409void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
80c39712
TV		 2410{
2411 u32 l;
569969d6 2412 int gpout0, gpout1;
80c39712
TV		 2413
2414 switch (mode) {
569969d6
AT		 2415 case DSS_IO_PAD_MODE_RESET:
2416 gpout0 = 0;
2417 gpout1 = 0;
80c39712 2418 break;
569969d6
AT		 2419 case DSS_IO_PAD_MODE_RFBI:
2420 gpout0 = 1;
80c39712
TV		 2421 gpout1 = 0;
2422 break;
569969d6
AT		 2423 case DSS_IO_PAD_MODE_BYPASS:
2424 gpout0 = 1;
80c39712
TV		 2425 gpout1 = 1;
2426 break;
80c39712
TV		 2427 default:
2428 BUG();
2429 return;
2430 }
2431
569969d6
AT		 2432 l = dispc_read_reg(DISPC_CONTROL);
2433 l = FLD_MOD(l, gpout0, 15, 15);
2434 l = FLD_MOD(l, gpout1, 16, 16);
2435 dispc_write_reg(DISPC_CONTROL, l);
2436}
2437
2438void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2439{
2440 if (channel == OMAP_DSS_CHANNEL_LCD2)
2441 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2442 else
2443 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
80c39712
TV		 2444}
2445
8f366162
AT		 2446static bool _dispc_mgr_size_ok(u16 width, u16 height)
2447{
2448 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2449 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2450}
2451
80c39712
TV		 2452static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2453 int vsw, int vfp, int vbp)
2454{
2455 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2456 if (hsw < 1 || hsw > 64 ||
2457 hfp < 1 || hfp > 256 ||
2458 hbp < 1 || hbp > 256 ||
2459 vsw < 1 || vsw > 64 ||
2460 vfp < 0 || vfp > 255 ||
2461 vbp < 0 || vbp > 255)
2462 return false;
2463 } else {
2464 if (hsw < 1 || hsw > 256 ||
2465 hfp < 1 || hfp > 4096 ||
2466 hbp < 1 || hbp > 4096 ||
2467 vsw < 1 || vsw > 256 ||
2468 vfp < 0 || vfp > 4095 ||
2469 vbp < 0 || vbp > 4095)
2470 return false;
2471 }
2472
2473 return true;
2474}
2475
8f366162 2476bool dispc_mgr_timings_ok(enum omap_channel channel,
b917fa39 2477 const struct omap_video_timings *timings)
80c39712 2478{
8f366162
AT		 2479 bool timings_ok;
2480
2481 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2482
2483 if (dispc_mgr_is_lcd(channel))
2484 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2485 timings->hfp, timings->hbp,
2486 timings->vsw, timings->vfp,
2487 timings->vbp);
2488
2489 return timings_ok;
80c39712
TV		 2490}
2491
26d9dd0d 2492static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
64ba4f74 2493 int hfp, int hbp, int vsw, int vfp, int vbp)
80c39712
TV		 2494{
2495 u32 timing_h, timing_v;
2496
2497 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2498 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2499 FLD_VAL(hbp-1, 27, 20);
2500
2501 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2502 FLD_VAL(vbp, 27, 20);
2503 } else {
2504 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2505 FLD_VAL(hbp-1, 31, 20);
2506
2507 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2508 FLD_VAL(vbp, 31, 20);
2509 }
2510
64ba4f74
SS		 2511 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2512 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
80c39712
TV		 2513}
2514
2515/* change name to mode? */
c51d921a 2516void dispc_mgr_set_timings(enum omap_channel channel,
64ba4f74 2517 struct omap_video_timings *timings)
80c39712
TV		 2518{
2519 unsigned xtot, ytot;
2520 unsigned long ht, vt;
2521
c51d921a
AT		 2522 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2523 timings->y_res);
80c39712 2524
8f366162
AT		 2525 if (!dispc_mgr_timings_ok(channel, timings))
2526 BUG();
80c39712 2527
8f366162 2528 if (dispc_mgr_is_lcd(channel)) {
c51d921a
AT		 2529 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2530 timings->hbp, timings->vsw, timings->vfp,
2531 timings->vbp);
80c39712 2532
c51d921a
AT		 2533 xtot = timings->x_res + timings->hfp + timings->hsw +
2534 timings->hbp;
2535 ytot = timings->y_res + timings->vfp + timings->vsw +
2536 timings->vbp;
80c39712 2537
c51d921a
AT		 2538 ht = (timings->pixel_clock * 1000) / xtot;
2539 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2540
2541 DSSDBG("pck %u\n", timings->pixel_clock);
2542 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
80c39712
TV		 2543 timings->hsw, timings->hfp, timings->hbp,
2544 timings->vsw, timings->vfp, timings->vbp);
2545
c51d921a 2546 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
c51d921a 2547 }
8f366162
AT		 2548
2549 dispc_mgr_set_size(channel, timings->x_res, timings->y_res);
80c39712
TV		 2550}
2551
26d9dd0d 2552static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
ff1b2cde 2553 u16 pck_div)
80c39712
TV		 2554{
2555 BUG_ON(lck_div < 1);
9eaaf207 2556 BUG_ON(pck_div < 1);
80c39712 2557
ce7fa5eb 2558 dispc_write_reg(DISPC_DIVISORo(channel),
80c39712 2559 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
80c39712
TV		 2560}
2561
26d9dd0d 2562static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2a205f34 2563 int *pck_div)
80c39712
TV		 2564{
2565 u32 l;
ce7fa5eb 2566 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2567 *lck_div = FLD_GET(l, 23, 16);
2568 *pck_div = FLD_GET(l, 7, 0);
2569}
2570
2571unsigned long dispc_fclk_rate(void)
2572{
a72b64b9 2573 struct platform_device *dsidev;
80c39712
TV		 2574 unsigned long r = 0;
2575
66534e8e 2576 switch (dss_get_dispc_clk_source()) {
89a35e51 2577 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2578 r = clk_get_rate(dispc.dss_clk);
66534e8e 2579 break;
89a35e51 2580 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2581 dsidev = dsi_get_dsidev_from_id(0);
2582 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
66534e8e 2583 break;
5a8b572d
AT		 2584 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2585 dsidev = dsi_get_dsidev_from_id(1);
2586 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2587 break;
66534e8e
TA		 2588 default:
2589 BUG();
2590 }
2591
80c39712
TV		 2592 return r;
2593}
2594
26d9dd0d 2595unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
80c39712 2596{
a72b64b9 2597 struct platform_device *dsidev;
80c39712
TV		 2598 int lcd;
2599 unsigned long r;
2600 u32 l;
2601
ce7fa5eb 2602 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712
TV		 2603
2604 lcd = FLD_GET(l, 23, 16);
2605
ea75159e 2606 switch (dss_get_lcd_clk_source(channel)) {
89a35e51 2607 case OMAP_DSS_CLK_SRC_FCK:
4fbafaf3 2608 r = clk_get_rate(dispc.dss_clk);
ea75159e 2609 break;
89a35e51 2610 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
a72b64b9
AT		 2611 dsidev = dsi_get_dsidev_from_id(0);
2612 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
ea75159e 2613 break;
5a8b572d
AT		 2614 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2615 dsidev = dsi_get_dsidev_from_id(1);
2616 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2617 break;
ea75159e
TA		 2618 default:
2619 BUG();
2620 }
80c39712
TV		 2621
2622 return r / lcd;
2623}
2624
26d9dd0d 2625unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
80c39712 2626{
80c39712 2627 unsigned long r;
80c39712 2628
c3dc6a7a
AT		 2629 if (dispc_mgr_is_lcd(channel)) {
2630 int pcd;
2631 u32 l;
80c39712 2632
c3dc6a7a 2633 l = dispc_read_reg(DISPC_DIVISORo(channel));
80c39712 2634
c3dc6a7a 2635 pcd = FLD_GET(l, 7, 0);
80c39712 2636
c3dc6a7a
AT		 2637 r = dispc_mgr_lclk_rate(channel);
2638
2639 return r / pcd;
2640 } else {
3fa03ba8 2641 enum dss_hdmi_venc_clk_source_select source;
c3dc6a7a 2642
3fa03ba8
AT		 2643 source = dss_get_hdmi_venc_clk_source();
2644
2645 switch (source) {
2646 case DSS_VENC_TV_CLK:
c3dc6a7a 2647 return venc_get_pixel_clock();
3fa03ba8 2648 case DSS_HDMI_M_PCLK:
c3dc6a7a
AT		 2649 return hdmi_get_pixel_clock();
2650 default:
2651 BUG();
2652 }
2653 }
80c39712
TV		 2654}
2655
8b53d991
CM		 2656unsigned long dispc_core_clk_rate(void)
2657{
2658 int lcd;
2659 unsigned long fclk = dispc_fclk_rate();
2660
2661 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2662 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2663 else
2664 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2665
2666 return fclk / lcd;
2667}
2668
80c39712
TV		 2669void dispc_dump_clocks(struct seq_file *s)
2670{
2671 int lcd, pcd;
0cf35df3 2672 u32 l;
89a35e51
AT		 2673 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2674 enum omap_dss_clk_source lcd_clk_src;
80c39712 2675
4fbafaf3
TV		 2676 if (dispc_runtime_get())
2677 return;
80c39712 2678
80c39712
TV		 2679 seq_printf(s, "- DISPC -\n");
2680
067a57e4
AT		 2681 seq_printf(s, "dispc fclk source = %s (%s)\n",
2682 dss_get_generic_clk_source_name(dispc_clk_src),
2683 dss_feat_get_clk_source_name(dispc_clk_src));
80c39712
TV		 2684
2685 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2a205f34 2686
0cf35df3
MR		 2687 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2688 seq_printf(s, "- DISPC-CORE-CLK -\n");
2689 l = dispc_read_reg(DISPC_DIVISOR);
2690 lcd = FLD_GET(l, 23, 16);
2691
2692 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2693 (dispc_fclk_rate()/lcd), lcd);
2694 }
2a205f34
SS		 2695 seq_printf(s, "- LCD1 -\n");
2696
ea75159e
TA		 2697 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2698
2699 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2700 dss_get_generic_clk_source_name(lcd_clk_src),
2701 dss_feat_get_clk_source_name(lcd_clk_src));
2702
26d9dd0d 2703 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2a205f34 2704
ff1b2cde 2705 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2706 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
ff1b2cde 2707 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2708 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2a205f34
SS		 2709 if (dss_has_feature(FEAT_MGR_LCD2)) {
2710 seq_printf(s, "- LCD2 -\n");
2711
ea75159e
TA		 2712 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2713
2714 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2715 dss_get_generic_clk_source_name(lcd_clk_src),
2716 dss_feat_get_clk_source_name(lcd_clk_src));
2717
26d9dd0d 2718 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
80c39712 2719
2a205f34 2720 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
26d9dd0d 2721 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2a205f34 2722 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
26d9dd0d 2723 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2a205f34 2724 }
4fbafaf3
TV		 2725
2726 dispc_runtime_put();
80c39712
TV		 2727}
2728
dfc0fd8d
TV		 2729#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2730void dispc_dump_irqs(struct seq_file *s)
2731{
2732 unsigned long flags;
2733 struct dispc_irq_stats stats;
2734
2735 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2736
2737 stats = dispc.irq_stats;
2738 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2739 dispc.irq_stats.last_reset = jiffies;
2740
2741 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2742
2743 seq_printf(s, "period %u ms\n",
2744 jiffies_to_msecs(jiffies - stats.last_reset));
2745
2746 seq_printf(s, "irqs %d\n", stats.irq_count);
2747#define PIS(x) \
2748 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2749
2750 PIS(FRAMEDONE);
2751 PIS(VSYNC);
2752 PIS(EVSYNC_EVEN);
2753 PIS(EVSYNC_ODD);
2754 PIS(ACBIAS_COUNT_STAT);
2755 PIS(PROG_LINE_NUM);
2756 PIS(GFX_FIFO_UNDERFLOW);
2757 PIS(GFX_END_WIN);
2758 PIS(PAL_GAMMA_MASK);
2759 PIS(OCP_ERR);
2760 PIS(VID1_FIFO_UNDERFLOW);
2761 PIS(VID1_END_WIN);
2762 PIS(VID2_FIFO_UNDERFLOW);
2763 PIS(VID2_END_WIN);
b8c095b4
AT		 2764 if (dss_feat_get_num_ovls() > 3) {
2765 PIS(VID3_FIFO_UNDERFLOW);
2766 PIS(VID3_END_WIN);
2767 }
dfc0fd8d
TV		 2768 PIS(SYNC_LOST);
2769 PIS(SYNC_LOST_DIGIT);
2770 PIS(WAKEUP);
2a205f34
SS		 2771 if (dss_has_feature(FEAT_MGR_LCD2)) {
2772 PIS(FRAMEDONE2);
2773 PIS(VSYNC2);
2774 PIS(ACBIAS_COUNT_STAT2);
2775 PIS(SYNC_LOST2);
2776 }
dfc0fd8d
TV		 2777#undef PIS
2778}
dfc0fd8d
TV		 2779#endif
2780
80c39712
TV		 2781void dispc_dump_regs(struct seq_file *s)
2782{
4dd2da15
AT		 2783 int i, j;
2784 const char *mgr_names[] = {
2785 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2786 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2787 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2788 };
2789 const char *ovl_names[] = {
2790 [OMAP_DSS_GFX] = "GFX",
2791 [OMAP_DSS_VIDEO1] = "VID1",
2792 [OMAP_DSS_VIDEO2] = "VID2",
b8c095b4 2793 [OMAP_DSS_VIDEO3] = "VID3",
4dd2da15
AT		 2794 };
2795 const char **p_names;
2796
9b372c2d 2797#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
80c39712 2798
4fbafaf3
TV		 2799 if (dispc_runtime_get())
2800 return;
80c39712 2801
5010be80 2802 /* DISPC common registers */
80c39712
TV		 2803 DUMPREG(DISPC_REVISION);
2804 DUMPREG(DISPC_SYSCONFIG);
2805 DUMPREG(DISPC_SYSSTATUS);
2806 DUMPREG(DISPC_IRQSTATUS);
2807 DUMPREG(DISPC_IRQENABLE);
2808 DUMPREG(DISPC_CONTROL);
2809 DUMPREG(DISPC_CONFIG);
2810 DUMPREG(DISPC_CAPABLE);
80c39712
TV		 2811 DUMPREG(DISPC_LINE_STATUS);
2812 DUMPREG(DISPC_LINE_NUMBER);
11354dd5
AT		 2813 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2814 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
332e9d70 2815 DUMPREG(DISPC_GLOBAL_ALPHA);
2a205f34
SS		 2816 if (dss_has_feature(FEAT_MGR_LCD2)) {
2817 DUMPREG(DISPC_CONTROL2);
2818 DUMPREG(DISPC_CONFIG2);
5010be80
AT		 2819 }
2820
2821#undef DUMPREG
2822
2823#define DISPC_REG(i, name) name(i)
4dd2da15
AT		 2824#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2825 48 - strlen(#r) - strlen(p_names[i]), " ", \
5010be80
AT		 2826 dispc_read_reg(DISPC_REG(i, r)))
2827
4dd2da15 2828 p_names = mgr_names;
5010be80 2829
4dd2da15
AT		 2830 /* DISPC channel specific registers */
2831 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2832 DUMPREG(i, DISPC_DEFAULT_COLOR);
2833 DUMPREG(i, DISPC_TRANS_COLOR);
2834 DUMPREG(i, DISPC_SIZE_MGR);
80c39712 2835
4dd2da15
AT		 2836 if (i == OMAP_DSS_CHANNEL_DIGIT)
2837 continue;
5010be80 2838
4dd2da15
AT		 2839 DUMPREG(i, DISPC_DEFAULT_COLOR);
2840 DUMPREG(i, DISPC_TRANS_COLOR);
2841 DUMPREG(i, DISPC_TIMING_H);
2842 DUMPREG(i, DISPC_TIMING_V);
2843 DUMPREG(i, DISPC_POL_FREQ);
2844 DUMPREG(i, DISPC_DIVISORo);
2845 DUMPREG(i, DISPC_SIZE_MGR);
5010be80 2846
4dd2da15
AT		 2847 DUMPREG(i, DISPC_DATA_CYCLE1);
2848 DUMPREG(i, DISPC_DATA_CYCLE2);
2849 DUMPREG(i, DISPC_DATA_CYCLE3);
2a205f34 2850
332e9d70 2851 if (dss_has_feature(FEAT_CPR)) {
4dd2da15
AT		 2852 DUMPREG(i, DISPC_CPR_COEF_R);
2853 DUMPREG(i, DISPC_CPR_COEF_G);
2854 DUMPREG(i, DISPC_CPR_COEF_B);
332e9d70 2855 }
2a205f34 2856 }
80c39712 2857
4dd2da15
AT		 2858 p_names = ovl_names;
2859
2860 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2861 DUMPREG(i, DISPC_OVL_BA0);
2862 DUMPREG(i, DISPC_OVL_BA1);
2863 DUMPREG(i, DISPC_OVL_POSITION);
2864 DUMPREG(i, DISPC_OVL_SIZE);
2865 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2866 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2867 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2868 DUMPREG(i, DISPC_OVL_ROW_INC);
2869 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2870 if (dss_has_feature(FEAT_PRELOAD))
2871 DUMPREG(i, DISPC_OVL_PRELOAD);
2872
2873 if (i == OMAP_DSS_GFX) {
2874 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2875 DUMPREG(i, DISPC_OVL_TABLE_BA);
2876 continue;
2877 }
2878
2879 DUMPREG(i, DISPC_OVL_FIR);
2880 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2881 DUMPREG(i, DISPC_OVL_ACCU0);
2882 DUMPREG(i, DISPC_OVL_ACCU1);
2883 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2884 DUMPREG(i, DISPC_OVL_BA0_UV);
2885 DUMPREG(i, DISPC_OVL_BA1_UV);
2886 DUMPREG(i, DISPC_OVL_FIR2);
2887 DUMPREG(i, DISPC_OVL_ACCU2_0);
2888 DUMPREG(i, DISPC_OVL_ACCU2_1);
2889 }
2890 if (dss_has_feature(FEAT_ATTR2))
2891 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2892 if (dss_has_feature(FEAT_PRELOAD))
2893 DUMPREG(i, DISPC_OVL_PRELOAD);
ab5ca071 2894 }
5010be80
AT		 2895
2896#undef DISPC_REG
2897#undef DUMPREG
2898
2899#define DISPC_REG(plane, name, i) name(plane, i)
2900#define DUMPREG(plane, name, i) \
4dd2da15
AT		 2901 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2902 46 - strlen(#name) - strlen(p_names[plane]), " ", \
5010be80
AT		 2903 dispc_read_reg(DISPC_REG(plane, name, i)))
2904
4dd2da15 2905 /* Video pipeline coefficient registers */
332e9d70 2906
4dd2da15
AT		 2907 /* start from OMAP_DSS_VIDEO1 */
2908 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2909 for (j = 0; j < 8; j++)
2910 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
9b372c2d 2911
4dd2da15
AT		 2912 for (j = 0; j < 8; j++)
2913 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
5010be80 2914
4dd2da15
AT		 2915 for (j = 0; j < 5; j++)
2916 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
ab5ca071 2917
4dd2da15
AT		 2918 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2919 for (j = 0; j < 8; j++)
2920 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2921 }
2922
2923 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2924 for (j = 0; j < 8; j++)
2925 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2926
2927 for (j = 0; j < 8; j++)
2928 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2929
2930 for (j = 0; j < 8; j++)
2931 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2932 }
332e9d70 2933 }
80c39712 2934
4fbafaf3 2935 dispc_runtime_put();
5010be80
AT		 2936
2937#undef DISPC_REG
80c39712
TV		 2938#undef DUMPREG
2939}
2940
26d9dd0d
TV		 2941static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2942 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2943 u8 acb)
80c39712
TV		 2944{
2945 u32 l = 0;
2946
2947 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2948 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2949
2950 l |= FLD_VAL(onoff, 17, 17);
2951 l |= FLD_VAL(rf, 16, 16);
2952 l |= FLD_VAL(ieo, 15, 15);
2953 l |= FLD_VAL(ipc, 14, 14);
2954 l |= FLD_VAL(ihs, 13, 13);
2955 l |= FLD_VAL(ivs, 12, 12);
2956 l |= FLD_VAL(acbi, 11, 8);
2957 l |= FLD_VAL(acb, 7, 0);
2958
ff1b2cde 2959 dispc_write_reg(DISPC_POL_FREQ(channel), l);
80c39712
TV		 2960}
2961
26d9dd0d 2962void dispc_mgr_set_pol_freq(enum omap_channel channel,
ff1b2cde 2963 enum omap_panel_config config, u8 acbi, u8 acb)
80c39712 2964{
26d9dd0d 2965 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
80c39712
TV		 2966 (config & OMAP_DSS_LCD_RF) != 0,
2967 (config & OMAP_DSS_LCD_IEO) != 0,
2968 (config & OMAP_DSS_LCD_IPC) != 0,
2969 (config & OMAP_DSS_LCD_IHS) != 0,
2970 (config & OMAP_DSS_LCD_IVS) != 0,
2971 acbi, acb);
2972}
2973
2974/* with fck as input clock rate, find dispc dividers that produce req_pck */
2975void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2976 struct dispc_clock_info *cinfo)
2977{
9eaaf207 2978 u16 pcd_min, pcd_max;
80c39712
TV		 2979 unsigned long best_pck;
2980 u16 best_ld, cur_ld;
2981 u16 best_pd, cur_pd;
2982
9eaaf207
TV		 2983 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2984 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2985
2986 if (!is_tft)
2987 pcd_min = 3;
2988
80c39712
TV		 2989 best_pck = 0;
2990 best_ld = 0;
2991 best_pd = 0;
2992
2993 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2994 unsigned long lck = fck / cur_ld;
2995
9eaaf207 2996 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
80c39712
TV		 2997 unsigned long pck = lck / cur_pd;
2998 long old_delta = abs(best_pck - req_pck);
2999 long new_delta = abs(pck - req_pck);
3000
3001 if (best_pck == 0 || new_delta < old_delta) {
3002 best_pck = pck;
3003 best_ld = cur_ld;
3004 best_pd = cur_pd;
3005
3006 if (pck == req_pck)
3007 goto found;
3008 }
3009
3010 if (pck < req_pck)
3011 break;
3012 }
3013
3014 if (lck / pcd_min < req_pck)
3015 break;
3016 }
3017
3018found:
3019 cinfo->lck_div = best_ld;
3020 cinfo->pck_div = best_pd;
3021 cinfo->lck = fck / cinfo->lck_div;
3022 cinfo->pck = cinfo->lck / cinfo->pck_div;
3023}
3024
3025/* calculate clock rates using dividers in cinfo */
3026int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3027 struct dispc_clock_info *cinfo)
3028{
3029 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3030 return -EINVAL;
9eaaf207 3031 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
80c39712
TV		 3032 return -EINVAL;
3033
3034 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3035 cinfo->pck = cinfo->lck / cinfo->pck_div;
3036
3037 return 0;
3038}
3039
26d9dd0d 3040int dispc_mgr_set_clock_div(enum omap_channel channel,
ff1b2cde 3041 struct dispc_clock_info *cinfo)
80c39712
TV		 3042{
3043 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3044 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3045
26d9dd0d 3046 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
80c39712
TV		 3047
3048 return 0;
3049}
3050
26d9dd0d 3051int dispc_mgr_get_clock_div(enum omap_channel channel,
ff1b2cde 3052 struct dispc_clock_info *cinfo)
80c39712
TV		 3053{
3054 unsigned long fck;
3055
3056 fck = dispc_fclk_rate();
3057
ce7fa5eb
MR		 3058 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3059 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
80c39712
TV		 3060
3061 cinfo->lck = fck / cinfo->lck_div;
3062 cinfo->pck = cinfo->lck / cinfo->pck_div;
3063
3064 return 0;
3065}
3066
3067/* dispc.irq_lock has to be locked by the caller */
3068static void _omap_dispc_set_irqs(void)
3069{
3070 u32 mask;
3071 u32 old_mask;
3072 int i;
3073 struct omap_dispc_isr_data *isr_data;
3074
3075 mask = dispc.irq_error_mask;
3076
3077 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3078 isr_data = &dispc.registered_isr[i];
3079
3080 if (isr_data->isr == NULL)
3081 continue;
3082
3083 mask |= isr_data->mask;
3084 }
3085
80c39712
TV		 3086 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3087 /* clear the irqstatus for newly enabled irqs */
3088 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3089
3090 dispc_write_reg(DISPC_IRQENABLE, mask);
80c39712
TV		 3091}
3092
3093int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3094{
3095 int i;
3096 int ret;
3097 unsigned long flags;
3098 struct omap_dispc_isr_data *isr_data;
3099
3100 if (isr == NULL)
3101 return -EINVAL;
3102
3103 spin_lock_irqsave(&dispc.irq_lock, flags);
3104
3105 /* check for duplicate entry */
3106 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3107 isr_data = &dispc.registered_isr[i];
3108 if (isr_data->isr == isr && isr_data->arg == arg &&
3109 isr_data->mask == mask) {
3110 ret = -EINVAL;
3111 goto err;
3112 }
3113 }
3114
3115 isr_data = NULL;
3116 ret = -EBUSY;
3117
3118 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3119 isr_data = &dispc.registered_isr[i];
3120
3121 if (isr_data->isr != NULL)
3122 continue;
3123
3124 isr_data->isr = isr;
3125 isr_data->arg = arg;
3126 isr_data->mask = mask;
3127 ret = 0;
3128
3129 break;
3130 }
3131
b9cb0984
TV		 3132 if (ret)
3133 goto err;
3134
80c39712
TV		 3135 _omap_dispc_set_irqs();
3136
3137 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3138
3139 return 0;
3140err:
3141 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3142
3143 return ret;
3144}
3145EXPORT_SYMBOL(omap_dispc_register_isr);
3146
3147int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3148{
3149 int i;
3150 unsigned long flags;
3151 int ret = -EINVAL;
3152 struct omap_dispc_isr_data *isr_data;
3153
3154 spin_lock_irqsave(&dispc.irq_lock, flags);
3155
3156 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3157 isr_data = &dispc.registered_isr[i];
3158 if (isr_data->isr != isr || isr_data->arg != arg ||
3159 isr_data->mask != mask)
3160 continue;
3161
3162 /* found the correct isr */
3163
3164 isr_data->isr = NULL;
3165 isr_data->arg = NULL;
3166 isr_data->mask = 0;
3167
3168 ret = 0;
3169 break;
3170 }
3171
3172 if (ret == 0)
3173 _omap_dispc_set_irqs();
3174
3175 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3176
3177 return ret;
3178}
3179EXPORT_SYMBOL(omap_dispc_unregister_isr);
3180
3181#ifdef DEBUG
3182static void print_irq_status(u32 status)
3183{
3184 if ((status & dispc.irq_error_mask) == 0)
3185 return;
3186
3187 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3188
3189#define PIS(x) \
3190 if (status & DISPC_IRQ_##x) \
3191 printk(#x " ");
3192 PIS(GFX_FIFO_UNDERFLOW);
3193 PIS(OCP_ERR);
3194 PIS(VID1_FIFO_UNDERFLOW);
3195 PIS(VID2_FIFO_UNDERFLOW);
b8c095b4
AT		 3196 if (dss_feat_get_num_ovls() > 3)
3197 PIS(VID3_FIFO_UNDERFLOW);
80c39712
TV		 3198 PIS(SYNC_LOST);
3199 PIS(SYNC_LOST_DIGIT);
2a205f34
SS		 3200 if (dss_has_feature(FEAT_MGR_LCD2))
3201 PIS(SYNC_LOST2);
80c39712
TV		 3202#undef PIS
3203
3204 printk("\n");
3205}
3206#endif
3207
3208/* Called from dss.c. Note that we don't touch clocks here,
3209 * but we presume they are on because we got an IRQ. However,
3210 * an irq handler may turn the clocks off, so we may not have
3211 * clock later in the function. */
affe360d 3212static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
80c39712
TV		 3213{
3214 int i;
affe360d 3215 u32 irqstatus, irqenable;
80c39712
TV		 3216 u32 handledirqs = 0;
3217 u32 unhandled_errors;
3218 struct omap_dispc_isr_data *isr_data;
3219 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3220
3221 spin_lock(&dispc.irq_lock);
3222
3223 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
affe360d 3224 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3225
3226 /* IRQ is not for us */
3227 if (!(irqstatus & irqenable)) {
3228 spin_unlock(&dispc.irq_lock);
3229 return IRQ_NONE;
3230 }
80c39712 3231
dfc0fd8d
TV		 3232#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3233 spin_lock(&dispc.irq_stats_lock);
3234 dispc.irq_stats.irq_count++;
3235 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3236 spin_unlock(&dispc.irq_stats_lock);
3237#endif
3238
80c39712
TV		 3239#ifdef DEBUG
3240 if (dss_debug)
3241 print_irq_status(irqstatus);
3242#endif
3243 /* Ack the interrupt. Do it here before clocks are possibly turned
3244 * off */
3245 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3246 /* flush posted write */
3247 dispc_read_reg(DISPC_IRQSTATUS);
3248
3249 /* make a copy and unlock, so that isrs can unregister
3250 * themselves */
3251 memcpy(registered_isr, dispc.registered_isr,
3252 sizeof(registered_isr));
3253
3254 spin_unlock(&dispc.irq_lock);
3255
3256 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3257 isr_data = &registered_isr[i];
3258
3259 if (!isr_data->isr)
3260 continue;
3261
3262 if (isr_data->mask & irqstatus) {
3263 isr_data->isr(isr_data->arg, irqstatus);
3264 handledirqs |= isr_data->mask;
3265 }
3266 }
3267
3268 spin_lock(&dispc.irq_lock);
3269
3270 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3271
3272 if (unhandled_errors) {
3273 dispc.error_irqs |= unhandled_errors;
3274
3275 dispc.irq_error_mask &= ~unhandled_errors;
3276 _omap_dispc_set_irqs();
3277
3278 schedule_work(&dispc.error_work);
3279 }
3280
3281 spin_unlock(&dispc.irq_lock);
affe360d 3282
3283 return IRQ_HANDLED;
80c39712
TV		 3284}
3285
3286static void dispc_error_worker(struct work_struct *work)
3287{
3288 int i;
3289 u32 errors;
3290 unsigned long flags;
fe3cc9d6
TV		 3291 static const unsigned fifo_underflow_bits[] = {
3292 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3293 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3294 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
b8c095b4 3295 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
fe3cc9d6
TV		 3296 };
3297
3298 static const unsigned sync_lost_bits[] = {
3299 DISPC_IRQ_SYNC_LOST,
3300 DISPC_IRQ_SYNC_LOST_DIGIT,
3301 DISPC_IRQ_SYNC_LOST2,
3302 };
80c39712
TV		 3303
3304 spin_lock_irqsave(&dispc.irq_lock, flags);
3305 errors = dispc.error_irqs;
3306 dispc.error_irqs = 0;
3307 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3308
13eae1f9
DZ		 3309 dispc_runtime_get();
3310
fe3cc9d6
TV		 3311 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3312 struct omap_overlay *ovl;
3313 unsigned bit;
80c39712 3314
fe3cc9d6
TV		 3315 ovl = omap_dss_get_overlay(i);
3316 bit = fifo_underflow_bits[i];
80c39712 3317
fe3cc9d6
TV		 3318 if (bit & errors) {
3319 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3320 ovl->name);
f0e5caab 3321 dispc_ovl_enable(ovl->id, false);
26d9dd0d 3322 dispc_mgr_go(ovl->manager->id);
80c39712 3323 mdelay(50);
80c39712
TV		 3324 }
3325 }
3326
fe3cc9d6
TV		 3327 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3328 struct omap_overlay_manager *mgr;
3329 unsigned bit;
80c39712 3330
fe3cc9d6
TV		 3331 mgr = omap_dss_get_overlay_manager(i);
3332 bit = sync_lost_bits[i];
80c39712 3333
fe3cc9d6
TV		 3334 if (bit & errors) {
3335 struct omap_dss_device *dssdev = mgr->device;
3336 bool enable;
80c39712 3337
fe3cc9d6
TV		 3338 DSSERR("SYNC_LOST on channel %s, restarting the output "
3339 "with video overlays disabled\n",
3340 mgr->name);
2a205f34 3341
fe3cc9d6
TV		 3342 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3343 dssdev->driver->disable(dssdev);
2a205f34 3344
2a205f34
SS		 3345 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3346 struct omap_overlay *ovl;
3347 ovl = omap_dss_get_overlay(i);
3348
fe3cc9d6
TV		 3349 if (ovl->id != OMAP_DSS_GFX &&
3350 ovl->manager == mgr)
f0e5caab 3351 dispc_ovl_enable(ovl->id, false);
2a205f34
SS		 3352 }
3353
26d9dd0d 3354 dispc_mgr_go(mgr->id);
2a205f34 3355 mdelay(50);
fe3cc9d6 3356
2a205f34
SS		 3357 if (enable)
3358 dssdev->driver->enable(dssdev);
3359 }
3360 }
3361
80c39712
TV		 3362 if (errors & DISPC_IRQ_OCP_ERR) {
3363 DSSERR("OCP_ERR\n");
3364 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3365 struct omap_overlay_manager *mgr;
3366 mgr = omap_dss_get_overlay_manager(i);
00f17e45
RC		 3367 if (mgr->device && mgr->device->driver)
3368 mgr->device->driver->disable(mgr->device);
80c39712
TV		 3369 }
3370 }
3371
3372 spin_lock_irqsave(&dispc.irq_lock, flags);
3373 dispc.irq_error_mask |= errors;
3374 _omap_dispc_set_irqs();
3375 spin_unlock_irqrestore(&dispc.irq_lock, flags);
13eae1f9
DZ		 3376
3377 dispc_runtime_put();
80c39712
TV		 3378}
3379
3380int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3381{
3382 void dispc_irq_wait_handler(void *data, u32 mask)
3383 {
3384 complete((struct completion *)data);
3385 }
3386
3387 int r;
3388 DECLARE_COMPLETION_ONSTACK(completion);
3389
3390 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3391 irqmask);
3392
3393 if (r)
3394 return r;
3395
3396 timeout = wait_for_completion_timeout(&completion, timeout);
3397
3398 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3399
3400 if (timeout == 0)
3401 return -ETIMEDOUT;
3402
3403 if (timeout == -ERESTARTSYS)
3404 return -ERESTARTSYS;
3405
3406 return 0;
3407}
3408
3409int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3410 unsigned long timeout)
3411{
3412 void dispc_irq_wait_handler(void *data, u32 mask)
3413 {
3414 complete((struct completion *)data);
3415 }
3416
3417 int r;
3418 DECLARE_COMPLETION_ONSTACK(completion);
3419
3420 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3421 irqmask);
3422
3423 if (r)
3424 return r;
3425
3426 timeout = wait_for_completion_interruptible_timeout(&completion,
3427 timeout);
3428
3429 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3430
3431 if (timeout == 0)
3432 return -ETIMEDOUT;
3433
3434 if (timeout == -ERESTARTSYS)
3435 return -ERESTARTSYS;
3436
3437 return 0;
3438}
3439
80c39712
TV		 3440static void _omap_dispc_initialize_irq(void)
3441{
3442 unsigned long flags;
3443
3444 spin_lock_irqsave(&dispc.irq_lock, flags);
3445
3446 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3447
3448 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2a205f34
SS		 3449 if (dss_has_feature(FEAT_MGR_LCD2))
3450 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
b8c095b4
AT		 3451 if (dss_feat_get_num_ovls() > 3)
3452 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
80c39712
TV		 3453
3454 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3455 * so clear it */
3456 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3457
3458 _omap_dispc_set_irqs();
3459
3460 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3461}
3462
3463void dispc_enable_sidle(void)
3464{
3465 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3466}
3467
3468void dispc_disable_sidle(void)
3469{
3470 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3471}
3472
3473static void _omap_dispc_initial_config(void)
3474{
3475 u32 l;
3476
0cf35df3
MR		 3477 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3478 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3479 l = dispc_read_reg(DISPC_DIVISOR);
3480 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3481 l = FLD_MOD(l, 1, 0, 0);
3482 l = FLD_MOD(l, 1, 23, 16);
3483 dispc_write_reg(DISPC_DIVISOR, l);
3484 }
3485
80c39712 3486 /* FUNCGATED */
6ced40bf
AT		 3487 if (dss_has_feature(FEAT_FUNCGATED))
3488 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
80c39712 3489
80c39712
TV		 3490 _dispc_setup_color_conv_coef();
3491
3492 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3493
3494 dispc_read_plane_fifo_sizes();
5ed8cf5b
TV		 3495
3496 dispc_configure_burst_sizes();
54128701
AT		 3497
3498 dispc_ovl_enable_zorder_planes();
80c39712
TV		 3499}
3500
060b6d9c
SG		 3501/* DISPC HW IP initialisation */
3502static int omap_dispchw_probe(struct platform_device *pdev)
3503{
3504 u32 rev;
affe360d 3505 int r = 0;
ea9da36a 3506 struct resource *dispc_mem;
4fbafaf3 3507 struct clk *clk;
ea9da36a 3508
060b6d9c
SG		 3509 dispc.pdev = pdev;
3510
3511 spin_lock_init(&dispc.irq_lock);
3512
3513#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3514 spin_lock_init(&dispc.irq_stats_lock);
3515 dispc.irq_stats.last_reset = jiffies;
3516#endif
3517
3518 INIT_WORK(&dispc.error_work, dispc_error_worker);
3519
ea9da36a
SG		 3520 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3521 if (!dispc_mem) {
3522 DSSERR("can't get IORESOURCE_MEM DISPC\n");
cd3b3449 3523 return -EINVAL;
ea9da36a 3524 }
cd3b3449 3525
6e2a14d2
JL		 3526 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3527 resource_size(dispc_mem));
060b6d9c
SG		 3528 if (!dispc.base) {
3529 DSSERR("can't ioremap DISPC\n");
cd3b3449 3530 return -ENOMEM;
affe360d 3531 }
cd3b3449 3532
affe360d 3533 dispc.irq = platform_get_irq(dispc.pdev, 0);
3534 if (dispc.irq < 0) {
3535 DSSERR("platform_get_irq failed\n");
cd3b3449 3536 return -ENODEV;
affe360d 3537 }
3538
6e2a14d2
JL		 3539 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3540 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
affe360d 3541 if (r < 0) {
3542 DSSERR("request_irq failed\n");
cd3b3449
TV		 3543 return r;
3544 }
3545
3546 clk = clk_get(&pdev->dev, "fck");
3547 if (IS_ERR(clk)) {
3548 DSSERR("can't get fck\n");
3549 r = PTR_ERR(clk);
3550 return r;
060b6d9c
SG		 3551 }
3552
cd3b3449
TV		 3553 dispc.dss_clk = clk;
3554
4fbafaf3
TV		 3555 pm_runtime_enable(&pdev->dev);
3556
3557 r = dispc_runtime_get();
3558 if (r)
3559 goto err_runtime_get;
060b6d9c
SG		 3560
3561 _omap_dispc_initial_config();
3562
3563 _omap_dispc_initialize_irq();
3564
060b6d9c 3565 rev = dispc_read_reg(DISPC_REVISION);
a06b62f8 3566 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
060b6d9c
SG		 3567 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3568
4fbafaf3 3569 dispc_runtime_put();
060b6d9c
SG		 3570
3571 return 0;
4fbafaf3
TV		 3572
3573err_runtime_get:
3574 pm_runtime_disable(&pdev->dev);
4fbafaf3 3575 clk_put(dispc.dss_clk);
affe360d 3576 return r;
060b6d9c
SG		 3577}
3578
3579static int omap_dispchw_remove(struct platform_device *pdev)
3580{
4fbafaf3
TV		 3581 pm_runtime_disable(&pdev->dev);
3582
3583 clk_put(dispc.dss_clk);
3584
060b6d9c
SG		 3585 return 0;
3586}
3587
4fbafaf3
TV		 3588static int dispc_runtime_suspend(struct device *dev)
3589{
3590 dispc_save_context();
4fbafaf3
TV		 3591 dss_runtime_put();
3592
3593 return 0;
3594}
3595
3596static int dispc_runtime_resume(struct device *dev)
3597{
3598 int r;
3599
3600 r = dss_runtime_get();
3601 if (r < 0)
3602 return r;
3603
49ea86f3 3604 dispc_restore_context();
4fbafaf3
TV		 3605
3606 return 0;
3607}
3608
3609static const struct dev_pm_ops dispc_pm_ops = {
3610 .runtime_suspend = dispc_runtime_suspend,
3611 .runtime_resume = dispc_runtime_resume,
3612};
3613
060b6d9c
SG		 3614static struct platform_driver omap_dispchw_driver = {
3615 .probe = omap_dispchw_probe,
3616 .remove = omap_dispchw_remove,
3617 .driver = {
3618 .name = "omapdss_dispc",
3619 .owner = THIS_MODULE,
4fbafaf3 3620 .pm = &dispc_pm_ops,
060b6d9c
SG		 3621 },
3622};
3623
3624int dispc_init_platform_driver(void)
3625{
3626 return platform_driver_register(&omap_dispchw_driver);
3627}
3628
3629void dispc_uninit_platform_driver(void)
3630{
3631 return platform_driver_unregister(&omap_dispchw_driver);
3632}
Linux kernel - Deliverables
This page took 0.651887 seconds and 5 git commands to generate.