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OMAP2PLUS: DSS2: Use dss features to get clock source names of current OMAP
[deliverable/linux.git] / drivers / video / omap2 / dss / dsi.c
CommitLineData
3de7a1dc
TV		 1/*
2 * linux/drivers/video/omap2/dss/dsi.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#define DSS_SUBSYS_NAME "DSI"
21
22#include <linux/kernel.h>
23#include <linux/io.h>
24#include <linux/clk.h>
25#include <linux/device.h>
26#include <linux/err.h>
27#include <linux/interrupt.h>
28#include <linux/delay.h>
29#include <linux/mutex.h>
b9eb5d7d 30#include <linux/semaphore.h>
3de7a1dc
TV		 31#include <linux/seq_file.h>
32#include <linux/platform_device.h>
33#include <linux/regulator/consumer.h>
3de7a1dc 34#include <linux/wait.h>
18946f62 35#include <linux/workqueue.h>
3de7a1dc
TV		 36
37#include <plat/display.h>
38#include <plat/clock.h>
39
40#include "dss.h"
819d807c 41#include "dss_features.h"
3de7a1dc
TV		 42
43/*#define VERBOSE_IRQ*/
44#define DSI_CATCH_MISSING_TE
45
3de7a1dc
TV		 46struct dsi_reg { u16 idx; };
47
48#define DSI_REG(idx) ((const struct dsi_reg) { idx })
49
50#define DSI_SZ_REGS SZ_1K
51/* DSI Protocol Engine */
52
53#define DSI_REVISION DSI_REG(0x0000)
54#define DSI_SYSCONFIG DSI_REG(0x0010)
55#define DSI_SYSSTATUS DSI_REG(0x0014)
56#define DSI_IRQSTATUS DSI_REG(0x0018)
57#define DSI_IRQENABLE DSI_REG(0x001C)
58#define DSI_CTRL DSI_REG(0x0040)
59#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
60#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
61#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
62#define DSI_CLK_CTRL DSI_REG(0x0054)
63#define DSI_TIMING1 DSI_REG(0x0058)
64#define DSI_TIMING2 DSI_REG(0x005C)
65#define DSI_VM_TIMING1 DSI_REG(0x0060)
66#define DSI_VM_TIMING2 DSI_REG(0x0064)
67#define DSI_VM_TIMING3 DSI_REG(0x0068)
68#define DSI_CLK_TIMING DSI_REG(0x006C)
69#define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
70#define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
71#define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
72#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
73#define DSI_VM_TIMING4 DSI_REG(0x0080)
74#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
75#define DSI_VM_TIMING5 DSI_REG(0x0088)
76#define DSI_VM_TIMING6 DSI_REG(0x008C)
77#define DSI_VM_TIMING7 DSI_REG(0x0090)
78#define DSI_STOPCLK_TIMING DSI_REG(0x0094)
79#define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
80#define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
81#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
82#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
83#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
84#define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
85#define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
86
87/* DSIPHY_SCP */
88
89#define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
90#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
91#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
92#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
93
94/* DSI_PLL_CTRL_SCP */
95
96#define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
97#define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
98#define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
99#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
100#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
101
102#define REG_GET(idx, start, end) \
103 FLD_GET(dsi_read_reg(idx), start, end)
104
105#define REG_FLD_MOD(idx, val, start, end) \
106 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
107
108/* Global interrupts */
109#define DSI_IRQ_VC0 (1 << 0)
110#define DSI_IRQ_VC1 (1 << 1)
111#define DSI_IRQ_VC2 (1 << 2)
112#define DSI_IRQ_VC3 (1 << 3)
113#define DSI_IRQ_WAKEUP (1 << 4)
114#define DSI_IRQ_RESYNC (1 << 5)
115#define DSI_IRQ_PLL_LOCK (1 << 7)
116#define DSI_IRQ_PLL_UNLOCK (1 << 8)
117#define DSI_IRQ_PLL_RECALL (1 << 9)
118#define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
119#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
120#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
121#define DSI_IRQ_TE_TRIGGER (1 << 16)
122#define DSI_IRQ_ACK_TRIGGER (1 << 17)
123#define DSI_IRQ_SYNC_LOST (1 << 18)
124#define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
125#define DSI_IRQ_TA_TIMEOUT (1 << 20)
126#define DSI_IRQ_ERROR_MASK \
127 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
128 DSI_IRQ_TA_TIMEOUT)
129#define DSI_IRQ_CHANNEL_MASK 0xf
130
131/* Virtual channel interrupts */
132#define DSI_VC_IRQ_CS (1 << 0)
133#define DSI_VC_IRQ_ECC_CORR (1 << 1)
134#define DSI_VC_IRQ_PACKET_SENT (1 << 2)
135#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
136#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
137#define DSI_VC_IRQ_BTA (1 << 5)
138#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
139#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
140#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
141#define DSI_VC_IRQ_ERROR_MASK \
142 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
143 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
144 DSI_VC_IRQ_FIFO_TX_UDF)
145
146/* ComplexIO interrupts */
147#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
148#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
149#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
150#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
151#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
152#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
153#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
154#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
155#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
156#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
157#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
158#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
159#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
160#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
161#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
162#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
163#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
164#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
165#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
166#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
bbecb50b
TV		 167#define DSI_CIO_IRQ_ERROR_MASK \
168 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
169 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
170 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
171 DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
172 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
173 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
174 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
3de7a1dc
TV		 175
176#define DSI_DT_DCS_SHORT_WRITE_0 0x05
177#define DSI_DT_DCS_SHORT_WRITE_1 0x15
178#define DSI_DT_DCS_READ 0x06
179#define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
180#define DSI_DT_NULL_PACKET 0x09
181#define DSI_DT_DCS_LONG_WRITE 0x39
182
183#define DSI_DT_RX_ACK_WITH_ERR 0x02
184#define DSI_DT_RX_DCS_LONG_READ 0x1c
185#define DSI_DT_RX_SHORT_READ_1 0x21
186#define DSI_DT_RX_SHORT_READ_2 0x22
187
188#define FINT_MAX 2100000
189#define FINT_MIN 750000
190#define REGN_MAX (1 << 7)
191#define REGM_MAX ((1 << 11) - 1)
192#define REGM3_MAX (1 << 4)
193#define REGM4_MAX (1 << 4)
194#define LP_DIV_MAX ((1 << 13) - 1)
195
196enum fifo_size {
197 DSI_FIFO_SIZE_0 = 0,
198 DSI_FIFO_SIZE_32 = 1,
199 DSI_FIFO_SIZE_64 = 2,
200 DSI_FIFO_SIZE_96 = 3,
201 DSI_FIFO_SIZE_128 = 4,
202};
203
204enum dsi_vc_mode {
205 DSI_VC_MODE_L4 = 0,
206 DSI_VC_MODE_VP,
207};
208
209struct dsi_update_region {
3de7a1dc
TV		 210 u16 x, y, w, h;
211 struct omap_dss_device *device;
212};
213
dfc0fd8d
TV		 214struct dsi_irq_stats {
215 unsigned long last_reset;
216 unsigned irq_count;
217 unsigned dsi_irqs[32];
218 unsigned vc_irqs[4][32];
219 unsigned cio_irqs[32];
220};
221
3de7a1dc
TV		 222static struct
223{
c8aac01b 224 struct platform_device *pdev;
3de7a1dc 225 void __iomem *base;
affe360d 226 int irq;
3de7a1dc
TV		 227
228 struct dsi_clock_info current_cinfo;
229
230 struct regulator *vdds_dsi_reg;
231
232 struct {
233 enum dsi_vc_mode mode;
234 struct omap_dss_device *dssdev;
235 enum fifo_size fifo_size;
3de7a1dc
TV		 236 } vc[4];
237
238 struct mutex lock;
b9eb5d7d 239 struct semaphore bus_lock;
3de7a1dc
TV		 240
241 unsigned pll_locked;
242
243 struct completion bta_completion;
ab83b14c 244 void (*bta_callback)(void);
3de7a1dc 245
18946f62 246 int update_channel;
3de7a1dc 247 struct dsi_update_region update_region;
3de7a1dc 248
3de7a1dc 249 bool te_enabled;
3de7a1dc 250
0f16aa0a
TV		 251 struct workqueue_struct *workqueue;
252
18946f62
TV		 253 void (*framedone_callback)(int, void *);
254 void *framedone_data;
255
256 struct delayed_work framedone_timeout_work;
257
3de7a1dc
TV		 258#ifdef DSI_CATCH_MISSING_TE
259 struct timer_list te_timer;
260#endif
261
262 unsigned long cache_req_pck;
263 unsigned long cache_clk_freq;
264 struct dsi_clock_info cache_cinfo;
265
266 u32 errors;
267 spinlock_t errors_lock;
268#ifdef DEBUG
269 ktime_t perf_setup_time;
270 ktime_t perf_start_time;
3de7a1dc
TV		 271#endif
272 int debug_read;
273 int debug_write;
dfc0fd8d
TV		 274
275#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
276 spinlock_t irq_stats_lock;
277 struct dsi_irq_stats irq_stats;
278#endif
3de7a1dc
TV		 279} dsi;
280
281#ifdef DEBUG
282static unsigned int dsi_perf;
283module_param_named(dsi_perf, dsi_perf, bool, 0644);
284#endif
285
286static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
287{
288 __raw_writel(val, dsi.base + idx.idx);
289}
290
291static inline u32 dsi_read_reg(const struct dsi_reg idx)
292{
293 return __raw_readl(dsi.base + idx.idx);
294}
295
296
297void dsi_save_context(void)
298{
299}
300
301void dsi_restore_context(void)
302{
303}
304
305void dsi_bus_lock(void)
306{
b9eb5d7d 307 down(&dsi.bus_lock);
3de7a1dc
TV		 308}
309EXPORT_SYMBOL(dsi_bus_lock);
310
311void dsi_bus_unlock(void)
312{
b9eb5d7d 313 up(&dsi.bus_lock);
3de7a1dc
TV		 314}
315EXPORT_SYMBOL(dsi_bus_unlock);
316
4f765023
TV		 317static bool dsi_bus_is_locked(void)
318{
b9eb5d7d 319 return dsi.bus_lock.count == 0;
4f765023
TV		 320}
321
3de7a1dc
TV		 322static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
323 int value)
324{
325 int t = 100000;
326
327 while (REG_GET(idx, bitnum, bitnum) != value) {
328 if (--t == 0)
329 return !value;
330 }
331
332 return value;
333}
334
335#ifdef DEBUG
336static void dsi_perf_mark_setup(void)
337{
338 dsi.perf_setup_time = ktime_get();
339}
340
341static void dsi_perf_mark_start(void)
342{
343 dsi.perf_start_time = ktime_get();
344}
345
3de7a1dc
TV		 346static void dsi_perf_show(const char *name)
347{
348 ktime_t t, setup_time, trans_time;
349 u32 total_bytes;
350 u32 setup_us, trans_us, total_us;
351
352 if (!dsi_perf)
353 return;
354
3de7a1dc
TV		 355 t = ktime_get();
356
357 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
358 setup_us = (u32)ktime_to_us(setup_time);
359 if (setup_us == 0)
360 setup_us = 1;
361
362 trans_time = ktime_sub(t, dsi.perf_start_time);
363 trans_us = (u32)ktime_to_us(trans_time);
364 if (trans_us == 0)
365 trans_us = 1;
366
367 total_us = setup_us + trans_us;
368
18946f62
TV		 369 total_bytes = dsi.update_region.w *
370 dsi.update_region.h *
371 dsi.update_region.device->ctrl.pixel_size / 8;
3de7a1dc 372
1bbb275e
TV		 373 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
374 "%u bytes, %u kbytes/sec\n",
375 name,
376 setup_us,
377 trans_us,
378 total_us,
379 1000*1000 / total_us,
380 total_bytes,
381 total_bytes * 1000 / total_us);
3de7a1dc
TV		 382}
383#else
384#define dsi_perf_mark_setup()
385#define dsi_perf_mark_start()
3de7a1dc
TV		 386#define dsi_perf_show(x)
387#endif
388
389static void print_irq_status(u32 status)
390{
391#ifndef VERBOSE_IRQ
392 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
393 return;
394#endif
395 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
396
397#define PIS(x) \
398 if (status & DSI_IRQ_##x) \
399 printk(#x " ");
400#ifdef VERBOSE_IRQ
401 PIS(VC0);
402 PIS(VC1);
403 PIS(VC2);
404 PIS(VC3);
405#endif
406 PIS(WAKEUP);
407 PIS(RESYNC);
408 PIS(PLL_LOCK);
409 PIS(PLL_UNLOCK);
410 PIS(PLL_RECALL);
411 PIS(COMPLEXIO_ERR);
412 PIS(HS_TX_TIMEOUT);
413 PIS(LP_RX_TIMEOUT);
414 PIS(TE_TRIGGER);
415 PIS(ACK_TRIGGER);
416 PIS(SYNC_LOST);
417 PIS(LDO_POWER_GOOD);
418 PIS(TA_TIMEOUT);
419#undef PIS
420
421 printk("\n");
422}
423
424static void print_irq_status_vc(int channel, u32 status)
425{
426#ifndef VERBOSE_IRQ
427 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
428 return;
429#endif
430 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
431
432#define PIS(x) \
433 if (status & DSI_VC_IRQ_##x) \
434 printk(#x " ");
435 PIS(CS);
436 PIS(ECC_CORR);
437#ifdef VERBOSE_IRQ
438 PIS(PACKET_SENT);
439#endif
440 PIS(FIFO_TX_OVF);
441 PIS(FIFO_RX_OVF);
442 PIS(BTA);
443 PIS(ECC_NO_CORR);
444 PIS(FIFO_TX_UDF);
445 PIS(PP_BUSY_CHANGE);
446#undef PIS
447 printk("\n");
448}
449
450static void print_irq_status_cio(u32 status)
451{
452 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
453
454#define PIS(x) \
455 if (status & DSI_CIO_IRQ_##x) \
456 printk(#x " ");
457 PIS(ERRSYNCESC1);
458 PIS(ERRSYNCESC2);
459 PIS(ERRSYNCESC3);
460 PIS(ERRESC1);
461 PIS(ERRESC2);
462 PIS(ERRESC3);
463 PIS(ERRCONTROL1);
464 PIS(ERRCONTROL2);
465 PIS(ERRCONTROL3);
466 PIS(STATEULPS1);
467 PIS(STATEULPS2);
468 PIS(STATEULPS3);
469 PIS(ERRCONTENTIONLP0_1);
470 PIS(ERRCONTENTIONLP1_1);
471 PIS(ERRCONTENTIONLP0_2);
472 PIS(ERRCONTENTIONLP1_2);
473 PIS(ERRCONTENTIONLP0_3);
474 PIS(ERRCONTENTIONLP1_3);
475 PIS(ULPSACTIVENOT_ALL0);
476 PIS(ULPSACTIVENOT_ALL1);
477#undef PIS
478
479 printk("\n");
480}
481
482static int debug_irq;
483
484/* called from dss */
affe360d 485static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
3de7a1dc
TV		 486{
487 u32 irqstatus, vcstatus, ciostatus;
488 int i;
489
490 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
491
affe360d 492 /* IRQ is not for us */
493 if (!irqstatus)
494 return IRQ_NONE;
495
dfc0fd8d
TV		 496#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
497 spin_lock(&dsi.irq_stats_lock);
498 dsi.irq_stats.irq_count++;
499 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
500#endif
501
3de7a1dc
TV		 502 if (irqstatus & DSI_IRQ_ERROR_MASK) {
503 DSSERR("DSI error, irqstatus %x\n", irqstatus);
504 print_irq_status(irqstatus);
505 spin_lock(&dsi.errors_lock);
506 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
507 spin_unlock(&dsi.errors_lock);
508 } else if (debug_irq) {
509 print_irq_status(irqstatus);
510 }
511
512#ifdef DSI_CATCH_MISSING_TE
513 if (irqstatus & DSI_IRQ_TE_TRIGGER)
514 del_timer(&dsi.te_timer);
515#endif
516
517 for (i = 0; i < 4; ++i) {
518 if ((irqstatus & (1<<i)) == 0)
519 continue;
520
521 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
522
dfc0fd8d
TV		 523#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
524 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
525#endif
526
ab83b14c 527 if (vcstatus & DSI_VC_IRQ_BTA) {
3de7a1dc
TV		 528 complete(&dsi.bta_completion);
529
ab83b14c
TV		 530 if (dsi.bta_callback)
531 dsi.bta_callback();
532 }
533
3de7a1dc
TV		 534 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
535 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
536 i, vcstatus);
537 print_irq_status_vc(i, vcstatus);
538 } else if (debug_irq) {
539 print_irq_status_vc(i, vcstatus);
540 }
541
542 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
543 /* flush posted write */
544 dsi_read_reg(DSI_VC_IRQSTATUS(i));
545 }
546
547 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
548 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
549
dfc0fd8d
TV		 550#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
551 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
552#endif
553
3de7a1dc
TV		 554 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
555 /* flush posted write */
556 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
557
bbecb50b
TV		 558 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
559 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
560 print_irq_status_cio(ciostatus);
561 } else if (debug_irq) {
562 print_irq_status_cio(ciostatus);
563 }
3de7a1dc
TV		 564 }
565
566 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
567 /* flush posted write */
568 dsi_read_reg(DSI_IRQSTATUS);
dfc0fd8d
TV		 569
570#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
571 spin_unlock(&dsi.irq_stats_lock);
572#endif
affe360d 573 return IRQ_HANDLED;
3de7a1dc
TV		 574}
575
3de7a1dc
TV		 576static void _dsi_initialize_irq(void)
577{
578 u32 l;
579 int i;
580
581 /* disable all interrupts */
582 dsi_write_reg(DSI_IRQENABLE, 0);
583 for (i = 0; i < 4; ++i)
584 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
585 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
586
587 /* clear interrupt status */
588 l = dsi_read_reg(DSI_IRQSTATUS);
589 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
590
591 for (i = 0; i < 4; ++i) {
592 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
593 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
594 }
595
596 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
597 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
598
599 /* enable error irqs */
600 l = DSI_IRQ_ERROR_MASK;
601#ifdef DSI_CATCH_MISSING_TE
602 l |= DSI_IRQ_TE_TRIGGER;
603#endif
604 dsi_write_reg(DSI_IRQENABLE, l);
605
606 l = DSI_VC_IRQ_ERROR_MASK;
607 for (i = 0; i < 4; ++i)
608 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
609
bbecb50b
TV		 610 l = DSI_CIO_IRQ_ERROR_MASK;
611 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l);
3de7a1dc
TV		 612}
613
614static u32 dsi_get_errors(void)
615{
616 unsigned long flags;
617 u32 e;
618 spin_lock_irqsave(&dsi.errors_lock, flags);
619 e = dsi.errors;
620 dsi.errors = 0;
621 spin_unlock_irqrestore(&dsi.errors_lock, flags);
622 return e;
623}
624
625static void dsi_vc_enable_bta_irq(int channel)
626{
627 u32 l;
628
629 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
630
631 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
632 l |= DSI_VC_IRQ_BTA;
633 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
634}
635
636static void dsi_vc_disable_bta_irq(int channel)
637{
638 u32 l;
639
640 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
641 l &= ~DSI_VC_IRQ_BTA;
642 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
643}
644
645/* DSI func clock. this could also be DSI2_PLL_FCLK */
646static inline void enable_clocks(bool enable)
647{
648 if (enable)
6af9cd14 649 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
3de7a1dc 650 else
6af9cd14 651 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
3de7a1dc
TV		 652}
653
654/* source clock for DSI PLL. this could also be PCLKFREE */
655static inline void dsi_enable_pll_clock(bool enable)
656{
657 if (enable)
6af9cd14 658 dss_clk_enable(DSS_CLK_SYSCK);
3de7a1dc 659 else
6af9cd14 660 dss_clk_disable(DSS_CLK_SYSCK);
3de7a1dc
TV		 661
662 if (enable && dsi.pll_locked) {
663 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
664 DSSERR("cannot lock PLL when enabling clocks\n");
665 }
666}
667
668#ifdef DEBUG
669static void _dsi_print_reset_status(void)
670{
671 u32 l;
672
673 if (!dss_debug)
674 return;
675
676 /* A dummy read using the SCP interface to any DSIPHY register is
677 * required after DSIPHY reset to complete the reset of the DSI complex
678 * I/O. */
679 l = dsi_read_reg(DSI_DSIPHY_CFG5);
680
681 printk(KERN_DEBUG "DSI resets: ");
682
683 l = dsi_read_reg(DSI_PLL_STATUS);
684 printk("PLL (%d) ", FLD_GET(l, 0, 0));
685
686 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
687 printk("CIO (%d) ", FLD_GET(l, 29, 29));
688
689 l = dsi_read_reg(DSI_DSIPHY_CFG5);
690 printk("PHY (%x, %d, %d, %d)\n",
691 FLD_GET(l, 28, 26),
692 FLD_GET(l, 29, 29),
693 FLD_GET(l, 30, 30),
694 FLD_GET(l, 31, 31));
695}
696#else
697#define _dsi_print_reset_status()
698#endif
699
700static inline int dsi_if_enable(bool enable)
701{
702 DSSDBG("dsi_if_enable(%d)\n", enable);
703
704 enable = enable ? 1 : 0;
705 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
706
707 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
708 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
709 return -EIO;
710 }
711
712 return 0;
713}
714
715unsigned long dsi_get_dsi1_pll_rate(void)
716{
717 return dsi.current_cinfo.dsi1_pll_fclk;
718}
719
720static unsigned long dsi_get_dsi2_pll_rate(void)
721{
722 return dsi.current_cinfo.dsi2_pll_fclk;
723}
724
725static unsigned long dsi_get_txbyteclkhs(void)
726{
727 return dsi.current_cinfo.clkin4ddr / 16;
728}
729
730static unsigned long dsi_fclk_rate(void)
731{
732 unsigned long r;
733
88134fa1 734 if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
3de7a1dc 735 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
6af9cd14 736 r = dss_clk_get_rate(DSS_CLK_FCK);
3de7a1dc
TV		 737 } else {
738 /* DSI FCLK source is DSI2_PLL_FCLK */
739 r = dsi_get_dsi2_pll_rate();
740 }
741
742 return r;
743}
744
745static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
746{
747 unsigned long dsi_fclk;
748 unsigned lp_clk_div;
749 unsigned long lp_clk;
750
751 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
752
753 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
754 return -EINVAL;
755
756 dsi_fclk = dsi_fclk_rate();
757
758 lp_clk = dsi_fclk / 2 / lp_clk_div;
759
760 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
761 dsi.current_cinfo.lp_clk = lp_clk;
762 dsi.current_cinfo.lp_clk_div = lp_clk_div;
763
764 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
765
766 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
767 21, 21); /* LP_RX_SYNCHRO_ENABLE */
768
769 return 0;
770}
771
772
773enum dsi_pll_power_state {
774 DSI_PLL_POWER_OFF = 0x0,
775 DSI_PLL_POWER_ON_HSCLK = 0x1,
776 DSI_PLL_POWER_ON_ALL = 0x2,
777 DSI_PLL_POWER_ON_DIV = 0x3,
778};
779
780static int dsi_pll_power(enum dsi_pll_power_state state)
781{
782 int t = 0;
783
784 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
785
786 /* PLL_PWR_STATUS */
787 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
24be78b3 788 if (++t > 1000) {
3de7a1dc
TV		 789 DSSERR("Failed to set DSI PLL power mode to %d\n",
790 state);
791 return -ENODEV;
792 }
24be78b3 793 udelay(1);
3de7a1dc
TV		 794 }
795
796 return 0;
797}
798
799/* calculate clock rates using dividers in cinfo */
ff1b2cde
SS		 800static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
801 struct dsi_clock_info *cinfo)
3de7a1dc
TV		 802{
803 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
804 return -EINVAL;
805
806 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
807 return -EINVAL;
808
809 if (cinfo->regm3 > REGM3_MAX)
810 return -EINVAL;
811
812 if (cinfo->regm4 > REGM4_MAX)
813 return -EINVAL;
814
815 if (cinfo->use_dss2_fck) {
6af9cd14 816 cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
3de7a1dc
TV		 817 /* XXX it is unclear if highfreq should be used
818 * with DSS2_FCK source also */
819 cinfo->highfreq = 0;
820 } else {
ff1b2cde 821 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
3de7a1dc
TV		 822
823 if (cinfo->clkin < 32000000)
824 cinfo->highfreq = 0;
825 else
826 cinfo->highfreq = 1;
827 }
828
829 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
830
831 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
832 return -EINVAL;
833
834 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
835
836 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
837 return -EINVAL;
838
839 if (cinfo->regm3 > 0)
840 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
841 else
842 cinfo->dsi1_pll_fclk = 0;
843
844 if (cinfo->regm4 > 0)
845 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
846 else
847 cinfo->dsi2_pll_fclk = 0;
848
849 return 0;
850}
851
852int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
853 struct dsi_clock_info *dsi_cinfo,
854 struct dispc_clock_info *dispc_cinfo)
855{
856 struct dsi_clock_info cur, best;
857 struct dispc_clock_info best_dispc;
858 int min_fck_per_pck;
859 int match = 0;
819d807c 860 unsigned long dss_clk_fck2, max_dss_fck;
3de7a1dc 861
6af9cd14 862 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
3de7a1dc 863
819d807c
AT		 864 max_dss_fck = dss_feat_get_max_dss_fck();
865
3de7a1dc
TV		 866 if (req_pck == dsi.cache_req_pck &&
867 dsi.cache_cinfo.clkin == dss_clk_fck2) {
868 DSSDBG("DSI clock info found from cache\n");
869 *dsi_cinfo = dsi.cache_cinfo;
870 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
871 dispc_cinfo);
872 return 0;
873 }
874
875 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
876
877 if (min_fck_per_pck &&
819d807c 878 req_pck * min_fck_per_pck > max_dss_fck) {
3de7a1dc
TV		 879 DSSERR("Requested pixel clock not possible with the current "
880 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
881 "the constraint off.\n");
882 min_fck_per_pck = 0;
883 }
884
885 DSSDBG("dsi_pll_calc\n");
886
887retry:
888 memset(&best, 0, sizeof(best));
889 memset(&best_dispc, 0, sizeof(best_dispc));
890
891 memset(&cur, 0, sizeof(cur));
892 cur.clkin = dss_clk_fck2;
893 cur.use_dss2_fck = 1;
894 cur.highfreq = 0;
895
896 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
897 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
898 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
899 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
900 if (cur.highfreq == 0)
901 cur.fint = cur.clkin / cur.regn;
902 else
903 cur.fint = cur.clkin / (2 * cur.regn);
904
905 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
906 continue;
907
908 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
909 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
910 unsigned long a, b;
911
912 a = 2 * cur.regm * (cur.clkin/1000);
913 b = cur.regn * (cur.highfreq + 1);
914 cur.clkin4ddr = a / b * 1000;
915
916 if (cur.clkin4ddr > 1800 * 1000 * 1000)
917 break;
918
919 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
920 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
921 ++cur.regm3) {
922 struct dispc_clock_info cur_dispc;
923 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
924
925 /* this will narrow down the search a bit,
926 * but still give pixclocks below what was
927 * requested */
928 if (cur.dsi1_pll_fclk < req_pck)
929 break;
930
819d807c 931 if (cur.dsi1_pll_fclk > max_dss_fck)
3de7a1dc
TV		 932 continue;
933
934 if (min_fck_per_pck &&
935 cur.dsi1_pll_fclk <
936 req_pck * min_fck_per_pck)
937 continue;
938
939 match = 1;
940
941 dispc_find_clk_divs(is_tft, req_pck,
942 cur.dsi1_pll_fclk,
943 &cur_dispc);
944
945 if (abs(cur_dispc.pck - req_pck) <
946 abs(best_dispc.pck - req_pck)) {
947 best = cur;
948 best_dispc = cur_dispc;
949
950 if (cur_dispc.pck == req_pck)
951 goto found;
952 }
953 }
954 }
955 }
956found:
957 if (!match) {
958 if (min_fck_per_pck) {
959 DSSERR("Could not find suitable clock settings.\n"
960 "Turning FCK/PCK constraint off and"
961 "trying again.\n");
962 min_fck_per_pck = 0;
963 goto retry;
964 }
965
966 DSSERR("Could not find suitable clock settings.\n");
967
968 return -EINVAL;
969 }
970
971 /* DSI2_PLL_FCLK (regm4) is not used */
972 best.regm4 = 0;
973 best.dsi2_pll_fclk = 0;
974
975 if (dsi_cinfo)
976 *dsi_cinfo = best;
977 if (dispc_cinfo)
978 *dispc_cinfo = best_dispc;
979
980 dsi.cache_req_pck = req_pck;
981 dsi.cache_clk_freq = 0;
982 dsi.cache_cinfo = best;
983
984 return 0;
985}
986
987int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
988{
989 int r = 0;
990 u32 l;
991 int f;
992
993 DSSDBGF();
994
995 dsi.current_cinfo.fint = cinfo->fint;
996 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
997 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
998 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
999
1000 dsi.current_cinfo.regn = cinfo->regn;
1001 dsi.current_cinfo.regm = cinfo->regm;
1002 dsi.current_cinfo.regm3 = cinfo->regm3;
1003 dsi.current_cinfo.regm4 = cinfo->regm4;
1004
1005 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1006
1007 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1008 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
1009 cinfo->clkin,
1010 cinfo->highfreq);
1011
1012 /* DSIPHY == CLKIN4DDR */
1013 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1014 cinfo->regm,
1015 cinfo->regn,
1016 cinfo->clkin,
1017 cinfo->highfreq + 1,
1018 cinfo->clkin4ddr);
1019
1020 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1021 cinfo->clkin4ddr / 1000 / 1000 / 2);
1022
1023 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1024
067a57e4
AT		 1025 DSSDBG("regm3 = %d, %s (%s) = %lu\n", cinfo->regm3,
1026 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1027 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1028 cinfo->dsi1_pll_fclk);
1029 DSSDBG("regm4 = %d, %s (%s) = %lu\n", cinfo->regm4,
1030 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1031 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1032 cinfo->dsi2_pll_fclk);
3de7a1dc
TV		 1033
1034 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1035
1036 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1037 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1038 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1039 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1040 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1041 22, 19); /* DSI_CLOCK_DIV */
1042 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1043 26, 23); /* DSIPROTO_CLOCK_DIV */
1044 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1045
1046 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1047 if (cinfo->fint < 1000000)
1048 f = 0x3;
1049 else if (cinfo->fint < 1250000)
1050 f = 0x4;
1051 else if (cinfo->fint < 1500000)
1052 f = 0x5;
1053 else if (cinfo->fint < 1750000)
1054 f = 0x6;
1055 else
1056 f = 0x7;
1057
1058 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1059 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1060 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1061 11, 11); /* DSI_PLL_CLKSEL */
1062 l = FLD_MOD(l, cinfo->highfreq,
1063 12, 12); /* DSI_PLL_HIGHFREQ */
1064 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1065 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1066 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1067 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1068
1069 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1070
1071 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1072 DSSERR("dsi pll go bit not going down.\n");
1073 r = -EIO;
1074 goto err;
1075 }
1076
1077 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1078 DSSERR("cannot lock PLL\n");
1079 r = -EIO;
1080 goto err;
1081 }
1082
1083 dsi.pll_locked = 1;
1084
1085 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1086 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1087 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1088 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1089 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1090 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1091 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1092 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1093 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1094 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1095 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1096 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1097 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1098 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1099 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1100 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1101
1102 DSSDBG("PLL config done\n");
1103err:
1104 return r;
1105}
1106
1107int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1108 bool enable_hsdiv)
1109{
1110 int r = 0;
1111 enum dsi_pll_power_state pwstate;
1112
1113 DSSDBG("PLL init\n");
1114
1115 enable_clocks(1);
1116 dsi_enable_pll_clock(1);
1117
1118 r = regulator_enable(dsi.vdds_dsi_reg);
1119 if (r)
1120 goto err0;
1121
1122 /* XXX PLL does not come out of reset without this... */
1123 dispc_pck_free_enable(1);
1124
1125 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1126 DSSERR("PLL not coming out of reset.\n");
1127 r = -ENODEV;
481dfa0e 1128 dispc_pck_free_enable(0);
3de7a1dc
TV		 1129 goto err1;
1130 }
1131
1132 /* XXX ... but if left on, we get problems when planes do not
1133 * fill the whole display. No idea about this */
1134 dispc_pck_free_enable(0);
1135
1136 if (enable_hsclk && enable_hsdiv)
1137 pwstate = DSI_PLL_POWER_ON_ALL;
1138 else if (enable_hsclk)
1139 pwstate = DSI_PLL_POWER_ON_HSCLK;
1140 else if (enable_hsdiv)
1141 pwstate = DSI_PLL_POWER_ON_DIV;
1142 else
1143 pwstate = DSI_PLL_POWER_OFF;
1144
1145 r = dsi_pll_power(pwstate);
1146
1147 if (r)
1148 goto err1;
1149
1150 DSSDBG("PLL init done\n");
1151
1152 return 0;
1153err1:
1154 regulator_disable(dsi.vdds_dsi_reg);
1155err0:
1156 enable_clocks(0);
1157 dsi_enable_pll_clock(0);
1158 return r;
1159}
1160
1161void dsi_pll_uninit(void)
1162{
1163 enable_clocks(0);
1164 dsi_enable_pll_clock(0);
1165
1166 dsi.pll_locked = 0;
1167 dsi_pll_power(DSI_PLL_POWER_OFF);
1168 regulator_disable(dsi.vdds_dsi_reg);
1169 DSSDBG("PLL uninit done\n");
1170}
1171
1172void dsi_dump_clocks(struct seq_file *s)
1173{
1174 int clksel;
1175 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
067a57e4
AT		 1176 enum dss_clk_source dispc_clk_src, dsi_clk_src;
1177
1178 dispc_clk_src = dss_get_dispc_clk_source();
1179 dsi_clk_src = dss_get_dsi_clk_source();
3de7a1dc
TV		 1180
1181 enable_clocks(1);
1182
1183 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1184
1185 seq_printf(s, "- DSI PLL -\n");
1186
1187 seq_printf(s, "dsi pll source = %s\n",
1188 clksel == 0 ?
1189 "dss2_alwon_fclk" : "pclkfree");
1190
1191 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1192
1193 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1194 cinfo->clkin4ddr, cinfo->regm);
1195
067a57e4
AT		 1196 seq_printf(s, "%s (%s)\t%-16luregm3 %u\t(%s)\n",
1197 dss_get_generic_clk_source_name(dispc_clk_src),
1198 dss_feat_get_clk_source_name(dispc_clk_src),
3de7a1dc
TV		 1199 cinfo->dsi1_pll_fclk,
1200 cinfo->regm3,
067a57e4 1201 dispc_clk_src == DSS_CLK_SRC_FCK ?
63cf28ac 1202 "off" : "on");
3de7a1dc 1203
067a57e4
AT		 1204 seq_printf(s, "%s (%s)\t%-16luregm4 %u\t(%s)\n",
1205 dss_get_generic_clk_source_name(dsi_clk_src),
1206 dss_feat_get_clk_source_name(dsi_clk_src),
3de7a1dc
TV		 1207 cinfo->dsi2_pll_fclk,
1208 cinfo->regm4,
067a57e4 1209 dsi_clk_src == DSS_CLK_SRC_FCK ?
63cf28ac 1210 "off" : "on");
3de7a1dc
TV		 1211
1212 seq_printf(s, "- DSI -\n");
1213
067a57e4
AT		 1214 seq_printf(s, "dsi fclk source = %s (%s)\n",
1215 dss_get_generic_clk_source_name(dsi_clk_src),
1216 dss_feat_get_clk_source_name(dsi_clk_src));
3de7a1dc
TV		 1217
1218 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1219
1220 seq_printf(s, "DDR_CLK\t\t%lu\n",
1221 cinfo->clkin4ddr / 4);
1222
1223 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1224
1225 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1226
1227 seq_printf(s, "VP_CLK\t\t%lu\n"
1228 "VP_PCLK\t\t%lu\n",
ff1b2cde
SS		 1229 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1230 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
3de7a1dc
TV		 1231
1232 enable_clocks(0);
1233}
1234
dfc0fd8d
TV		 1235#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1236void dsi_dump_irqs(struct seq_file *s)
1237{
1238 unsigned long flags;
1239 struct dsi_irq_stats stats;
1240
1241 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1242
1243 stats = dsi.irq_stats;
1244 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1245 dsi.irq_stats.last_reset = jiffies;
1246
1247 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1248
1249 seq_printf(s, "period %u ms\n",
1250 jiffies_to_msecs(jiffies - stats.last_reset));
1251
1252 seq_printf(s, "irqs %d\n", stats.irq_count);
1253#define PIS(x) \
1254 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1255
1256 seq_printf(s, "-- DSI interrupts --\n");
1257 PIS(VC0);
1258 PIS(VC1);
1259 PIS(VC2);
1260 PIS(VC3);
1261 PIS(WAKEUP);
1262 PIS(RESYNC);
1263 PIS(PLL_LOCK);
1264 PIS(PLL_UNLOCK);
1265 PIS(PLL_RECALL);
1266 PIS(COMPLEXIO_ERR);
1267 PIS(HS_TX_TIMEOUT);
1268 PIS(LP_RX_TIMEOUT);
1269 PIS(TE_TRIGGER);
1270 PIS(ACK_TRIGGER);
1271 PIS(SYNC_LOST);
1272 PIS(LDO_POWER_GOOD);
1273 PIS(TA_TIMEOUT);
1274#undef PIS
1275
1276#define PIS(x) \
1277 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1278 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1279 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1280 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1281 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1282
1283 seq_printf(s, "-- VC interrupts --\n");
1284 PIS(CS);
1285 PIS(ECC_CORR);
1286 PIS(PACKET_SENT);
1287 PIS(FIFO_TX_OVF);
1288 PIS(FIFO_RX_OVF);
1289 PIS(BTA);
1290 PIS(ECC_NO_CORR);
1291 PIS(FIFO_TX_UDF);
1292 PIS(PP_BUSY_CHANGE);
1293#undef PIS
1294
1295#define PIS(x) \
1296 seq_printf(s, "%-20s %10d\n", #x, \
1297 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1298
1299 seq_printf(s, "-- CIO interrupts --\n");
1300 PIS(ERRSYNCESC1);
1301 PIS(ERRSYNCESC2);
1302 PIS(ERRSYNCESC3);
1303 PIS(ERRESC1);
1304 PIS(ERRESC2);
1305 PIS(ERRESC3);
1306 PIS(ERRCONTROL1);
1307 PIS(ERRCONTROL2);
1308 PIS(ERRCONTROL3);
1309 PIS(STATEULPS1);
1310 PIS(STATEULPS2);
1311 PIS(STATEULPS3);
1312 PIS(ERRCONTENTIONLP0_1);
1313 PIS(ERRCONTENTIONLP1_1);
1314 PIS(ERRCONTENTIONLP0_2);
1315 PIS(ERRCONTENTIONLP1_2);
1316 PIS(ERRCONTENTIONLP0_3);
1317 PIS(ERRCONTENTIONLP1_3);
1318 PIS(ULPSACTIVENOT_ALL0);
1319 PIS(ULPSACTIVENOT_ALL1);
1320#undef PIS
1321}
1322#endif
1323
3de7a1dc
TV		 1324void dsi_dump_regs(struct seq_file *s)
1325{
1326#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1327
6af9cd14 1328 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
3de7a1dc
TV		 1329
1330 DUMPREG(DSI_REVISION);
1331 DUMPREG(DSI_SYSCONFIG);
1332 DUMPREG(DSI_SYSSTATUS);
1333 DUMPREG(DSI_IRQSTATUS);
1334 DUMPREG(DSI_IRQENABLE);
1335 DUMPREG(DSI_CTRL);
1336 DUMPREG(DSI_COMPLEXIO_CFG1);
1337 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1338 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1339 DUMPREG(DSI_CLK_CTRL);
1340 DUMPREG(DSI_TIMING1);
1341 DUMPREG(DSI_TIMING2);
1342 DUMPREG(DSI_VM_TIMING1);
1343 DUMPREG(DSI_VM_TIMING2);
1344 DUMPREG(DSI_VM_TIMING3);
1345 DUMPREG(DSI_CLK_TIMING);
1346 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1347 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1348 DUMPREG(DSI_COMPLEXIO_CFG2);
1349 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1350 DUMPREG(DSI_VM_TIMING4);
1351 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1352 DUMPREG(DSI_VM_TIMING5);
1353 DUMPREG(DSI_VM_TIMING6);
1354 DUMPREG(DSI_VM_TIMING7);
1355 DUMPREG(DSI_STOPCLK_TIMING);
1356
1357 DUMPREG(DSI_VC_CTRL(0));
1358 DUMPREG(DSI_VC_TE(0));
1359 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1360 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1361 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1362 DUMPREG(DSI_VC_IRQSTATUS(0));
1363 DUMPREG(DSI_VC_IRQENABLE(0));
1364
1365 DUMPREG(DSI_VC_CTRL(1));
1366 DUMPREG(DSI_VC_TE(1));
1367 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1368 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1369 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1370 DUMPREG(DSI_VC_IRQSTATUS(1));
1371 DUMPREG(DSI_VC_IRQENABLE(1));
1372
1373 DUMPREG(DSI_VC_CTRL(2));
1374 DUMPREG(DSI_VC_TE(2));
1375 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1376 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1377 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1378 DUMPREG(DSI_VC_IRQSTATUS(2));
1379 DUMPREG(DSI_VC_IRQENABLE(2));
1380
1381 DUMPREG(DSI_VC_CTRL(3));
1382 DUMPREG(DSI_VC_TE(3));
1383 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1384 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1385 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1386 DUMPREG(DSI_VC_IRQSTATUS(3));
1387 DUMPREG(DSI_VC_IRQENABLE(3));
1388
1389 DUMPREG(DSI_DSIPHY_CFG0);
1390 DUMPREG(DSI_DSIPHY_CFG1);
1391 DUMPREG(DSI_DSIPHY_CFG2);
1392 DUMPREG(DSI_DSIPHY_CFG5);
1393
1394 DUMPREG(DSI_PLL_CONTROL);
1395 DUMPREG(DSI_PLL_STATUS);
1396 DUMPREG(DSI_PLL_GO);
1397 DUMPREG(DSI_PLL_CONFIGURATION1);
1398 DUMPREG(DSI_PLL_CONFIGURATION2);
1399
6af9cd14 1400 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
3de7a1dc
TV		 1401#undef DUMPREG
1402}
1403
1404enum dsi_complexio_power_state {
1405 DSI_COMPLEXIO_POWER_OFF = 0x0,
1406 DSI_COMPLEXIO_POWER_ON = 0x1,
1407 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1408};
1409
1410static int dsi_complexio_power(enum dsi_complexio_power_state state)
1411{
1412 int t = 0;
1413
1414 /* PWR_CMD */
1415 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1416
1417 /* PWR_STATUS */
1418 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
24be78b3 1419 if (++t > 1000) {
3de7a1dc
TV		 1420 DSSERR("failed to set complexio power state to "
1421 "%d\n", state);
1422 return -ENODEV;
1423 }
24be78b3 1424 udelay(1);
3de7a1dc
TV		 1425 }
1426
1427 return 0;
1428}
1429
1430static void dsi_complexio_config(struct omap_dss_device *dssdev)
1431{
1432 u32 r;
1433
1434 int clk_lane = dssdev->phy.dsi.clk_lane;
1435 int data1_lane = dssdev->phy.dsi.data1_lane;
1436 int data2_lane = dssdev->phy.dsi.data2_lane;
1437 int clk_pol = dssdev->phy.dsi.clk_pol;
1438 int data1_pol = dssdev->phy.dsi.data1_pol;
1439 int data2_pol = dssdev->phy.dsi.data2_pol;
1440
1441 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1442 r = FLD_MOD(r, clk_lane, 2, 0);
1443 r = FLD_MOD(r, clk_pol, 3, 3);
1444 r = FLD_MOD(r, data1_lane, 6, 4);
1445 r = FLD_MOD(r, data1_pol, 7, 7);
1446 r = FLD_MOD(r, data2_lane, 10, 8);
1447 r = FLD_MOD(r, data2_pol, 11, 11);
1448 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1449
1450 /* The configuration of the DSI complex I/O (number of data lanes,
1451 position, differential order) should not be changed while
1452 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1453 the hardware to take into account a new configuration of the complex
1454 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1455 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1456 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1457 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1458 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1459 DSI complex I/O configuration is unknown. */
1460
1461 /*
1462 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1463 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1464 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1465 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1466 */
1467}
1468
1469static inline unsigned ns2ddr(unsigned ns)
1470{
1471 /* convert time in ns to ddr ticks, rounding up */
1472 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1473 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1474}
1475
1476static inline unsigned ddr2ns(unsigned ddr)
1477{
1478 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1479 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1480}
1481
1482static void dsi_complexio_timings(void)
1483{
1484 u32 r;
1485 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1486 u32 tlpx_half, tclk_trail, tclk_zero;
1487 u32 tclk_prepare;
1488
1489 /* calculate timings */
1490
1491 /* 1 * DDR_CLK = 2 * UI */
1492
1493 /* min 40ns + 4*UI max 85ns + 6*UI */
1494 ths_prepare = ns2ddr(70) + 2;
1495
1496 /* min 145ns + 10*UI */
1497 ths_prepare_ths_zero = ns2ddr(175) + 2;
1498
1499 /* min max(8*UI, 60ns+4*UI) */
1500 ths_trail = ns2ddr(60) + 5;
1501
1502 /* min 100ns */
1503 ths_exit = ns2ddr(145);
1504
1505 /* tlpx min 50n */
1506 tlpx_half = ns2ddr(25);
1507
1508 /* min 60ns */
1509 tclk_trail = ns2ddr(60) + 2;
1510
1511 /* min 38ns, max 95ns */
1512 tclk_prepare = ns2ddr(65);
1513
1514 /* min tclk-prepare + tclk-zero = 300ns */
1515 tclk_zero = ns2ddr(260);
1516
1517 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1518 ths_prepare, ddr2ns(ths_prepare),
1519 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1520 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1521 ths_trail, ddr2ns(ths_trail),
1522 ths_exit, ddr2ns(ths_exit));
1523
1524 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1525 "tclk_zero %u (%uns)\n",
1526 tlpx_half, ddr2ns(tlpx_half),
1527 tclk_trail, ddr2ns(tclk_trail),
1528 tclk_zero, ddr2ns(tclk_zero));
1529 DSSDBG("tclk_prepare %u (%uns)\n",
1530 tclk_prepare, ddr2ns(tclk_prepare));
1531
1532 /* program timings */
1533
1534 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1535 r = FLD_MOD(r, ths_prepare, 31, 24);
1536 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1537 r = FLD_MOD(r, ths_trail, 15, 8);
1538 r = FLD_MOD(r, ths_exit, 7, 0);
1539 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1540
1541 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1542 r = FLD_MOD(r, tlpx_half, 22, 16);
1543 r = FLD_MOD(r, tclk_trail, 15, 8);
1544 r = FLD_MOD(r, tclk_zero, 7, 0);
1545 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1546
1547 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1548 r = FLD_MOD(r, tclk_prepare, 7, 0);
1549 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1550}
1551
1552
1553static int dsi_complexio_init(struct omap_dss_device *dssdev)
1554{
1555 int r = 0;
1556
1557 DSSDBG("dsi_complexio_init\n");
1558
1559 /* CIO_CLK_ICG, enable L3 clk to CIO */
1560 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1561
1562 /* A dummy read using the SCP interface to any DSIPHY register is
1563 * required after DSIPHY reset to complete the reset of the DSI complex
1564 * I/O. */
1565 dsi_read_reg(DSI_DSIPHY_CFG5);
1566
1567 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1568 DSSERR("ComplexIO PHY not coming out of reset.\n");
1569 r = -ENODEV;
1570 goto err;
1571 }
1572
1573 dsi_complexio_config(dssdev);
1574
1575 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1576
1577 if (r)
1578 goto err;
1579
1580 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1581 DSSERR("ComplexIO not coming out of reset.\n");
1582 r = -ENODEV;
1583 goto err;
1584 }
1585
1586 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1587 DSSERR("ComplexIO LDO power down.\n");
1588 r = -ENODEV;
1589 goto err;
1590 }
1591
1592 dsi_complexio_timings();
1593
1594 /*
1595 The configuration of the DSI complex I/O (number of data lanes,
1596 position, differential order) should not be changed while
1597 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1598 hardware to recognize a new configuration of the complex I/O (done
1599 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1600 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1601 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1602 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1603 bit to 1. If the sequence is not followed, the DSi complex I/O
1604 configuration is undetermined.
1605 */
1606 dsi_if_enable(1);
1607 dsi_if_enable(0);
1608 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1609 dsi_if_enable(1);
1610 dsi_if_enable(0);
1611
1612 DSSDBG("CIO init done\n");
1613err:
1614 return r;
1615}
1616
1617static void dsi_complexio_uninit(void)
1618{
1619 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1620}
1621
1622static int _dsi_wait_reset(void)
1623{
24be78b3 1624 int t = 0;
3de7a1dc
TV		 1625
1626 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
24be78b3 1627 if (++t > 5) {
3de7a1dc
TV		 1628 DSSERR("soft reset failed\n");
1629 return -ENODEV;
1630 }
1631 udelay(1);
1632 }
1633
1634 return 0;
1635}
1636
1637static int _dsi_reset(void)
1638{
1639 /* Soft reset */
1640 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1641 return _dsi_wait_reset();
1642}
1643
3de7a1dc
TV		 1644static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1645 enum fifo_size size3, enum fifo_size size4)
1646{
1647 u32 r = 0;
1648 int add = 0;
1649 int i;
1650
1651 dsi.vc[0].fifo_size = size1;
1652 dsi.vc[1].fifo_size = size2;
1653 dsi.vc[2].fifo_size = size3;
1654 dsi.vc[3].fifo_size = size4;
1655
1656 for (i = 0; i < 4; i++) {
1657 u8 v;
1658 int size = dsi.vc[i].fifo_size;
1659
1660 if (add + size > 4) {
1661 DSSERR("Illegal FIFO configuration\n");
1662 BUG();
1663 }
1664
1665 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1666 r |= v << (8 * i);
1667 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1668 add += size;
1669 }
1670
1671 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1672}
1673
1674static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1675 enum fifo_size size3, enum fifo_size size4)
1676{
1677 u32 r = 0;
1678 int add = 0;
1679 int i;
1680
1681 dsi.vc[0].fifo_size = size1;
1682 dsi.vc[1].fifo_size = size2;
1683 dsi.vc[2].fifo_size = size3;
1684 dsi.vc[3].fifo_size = size4;
1685
1686 for (i = 0; i < 4; i++) {
1687 u8 v;
1688 int size = dsi.vc[i].fifo_size;
1689
1690 if (add + size > 4) {
1691 DSSERR("Illegal FIFO configuration\n");
1692 BUG();
1693 }
1694
1695 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1696 r |= v << (8 * i);
1697 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1698 add += size;
1699 }
1700
1701 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1702}
1703
1704static int dsi_force_tx_stop_mode_io(void)
1705{
1706 u32 r;
1707
1708 r = dsi_read_reg(DSI_TIMING1);
1709 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1710 dsi_write_reg(DSI_TIMING1, r);
1711
1712 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1713 DSSERR("TX_STOP bit not going down\n");
1714 return -EIO;
1715 }
1716
1717 return 0;
1718}
1719
3de7a1dc
TV		 1720static int dsi_vc_enable(int channel, bool enable)
1721{
446f7bff
TV		 1722 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1723 channel, enable);
3de7a1dc
TV		 1724
1725 enable = enable ? 1 : 0;
1726
1727 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1728
1729 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1730 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1731 return -EIO;
1732 }
1733
1734 return 0;
1735}
1736
1737static void dsi_vc_initial_config(int channel)
1738{
1739 u32 r;
1740
1741 DSSDBGF("%d", channel);
1742
1743 r = dsi_read_reg(DSI_VC_CTRL(channel));
1744
1745 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1746 DSSERR("VC(%d) busy when trying to configure it!\n",
1747 channel);
1748
1749 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1750 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1751 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1752 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1753 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1754 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1755 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1756
1757 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1758 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1759
1760 dsi_write_reg(DSI_VC_CTRL(channel), r);
1761
1762 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1763}
1764
9ecd9684 1765static int dsi_vc_config_l4(int channel)
3de7a1dc
TV		 1766{
1767 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
9ecd9684 1768 return 0;
3de7a1dc
TV		 1769
1770 DSSDBGF("%d", channel);
1771
1772 dsi_vc_enable(channel, 0);
1773
9ecd9684
TV		 1774 /* VC_BUSY */
1775 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
3de7a1dc 1776 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
9ecd9684
TV		 1777 return -EIO;
1778 }
3de7a1dc
TV		 1779
1780 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1781
1782 dsi_vc_enable(channel, 1);
1783
1784 dsi.vc[channel].mode = DSI_VC_MODE_L4;
9ecd9684
TV		 1785
1786 return 0;
3de7a1dc
TV		 1787}
1788
9ecd9684 1789static int dsi_vc_config_vp(int channel)
3de7a1dc
TV		 1790{
1791 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
9ecd9684 1792 return 0;
3de7a1dc
TV		 1793
1794 DSSDBGF("%d", channel);
1795
1796 dsi_vc_enable(channel, 0);
1797
9ecd9684
TV		 1798 /* VC_BUSY */
1799 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
3de7a1dc 1800 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
9ecd9684
TV		 1801 return -EIO;
1802 }
3de7a1dc
TV		 1803
1804 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1805
1806 dsi_vc_enable(channel, 1);
1807
1808 dsi.vc[channel].mode = DSI_VC_MODE_VP;
9ecd9684
TV		 1809
1810 return 0;
3de7a1dc
TV		 1811}
1812
1813
61140c9a 1814void omapdss_dsi_vc_enable_hs(int channel, bool enable)
3de7a1dc
TV		 1815{
1816 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1817
61140c9a
TV		 1818 WARN_ON(!dsi_bus_is_locked());
1819
3de7a1dc
TV		 1820 dsi_vc_enable(channel, 0);
1821 dsi_if_enable(0);
1822
1823 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1824
1825 dsi_vc_enable(channel, 1);
1826 dsi_if_enable(1);
1827
1828 dsi_force_tx_stop_mode_io();
1829}
61140c9a 1830EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
3de7a1dc
TV		 1831
1832static void dsi_vc_flush_long_data(int channel)
1833{
1834 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1835 u32 val;
1836 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1837 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1838 (val >> 0) & 0xff,
1839 (val >> 8) & 0xff,
1840 (val >> 16) & 0xff,
1841 (val >> 24) & 0xff);
1842 }
1843}
1844
1845static void dsi_show_rx_ack_with_err(u16 err)
1846{
1847 DSSERR("\tACK with ERROR (%#x):\n", err);
1848 if (err & (1 << 0))
1849 DSSERR("\t\tSoT Error\n");
1850 if (err & (1 << 1))
1851 DSSERR("\t\tSoT Sync Error\n");
1852 if (err & (1 << 2))
1853 DSSERR("\t\tEoT Sync Error\n");
1854 if (err & (1 << 3))
1855 DSSERR("\t\tEscape Mode Entry Command Error\n");
1856 if (err & (1 << 4))
1857 DSSERR("\t\tLP Transmit Sync Error\n");
1858 if (err & (1 << 5))
1859 DSSERR("\t\tHS Receive Timeout Error\n");
1860 if (err & (1 << 6))
1861 DSSERR("\t\tFalse Control Error\n");
1862 if (err & (1 << 7))
1863 DSSERR("\t\t(reserved7)\n");
1864 if (err & (1 << 8))
1865 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1866 if (err & (1 << 9))
1867 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1868 if (err & (1 << 10))
1869 DSSERR("\t\tChecksum Error\n");
1870 if (err & (1 << 11))
1871 DSSERR("\t\tData type not recognized\n");
1872 if (err & (1 << 12))
1873 DSSERR("\t\tInvalid VC ID\n");
1874 if (err & (1 << 13))
1875 DSSERR("\t\tInvalid Transmission Length\n");
1876 if (err & (1 << 14))
1877 DSSERR("\t\t(reserved14)\n");
1878 if (err & (1 << 15))
1879 DSSERR("\t\tDSI Protocol Violation\n");
1880}
1881
1882static u16 dsi_vc_flush_receive_data(int channel)
1883{
1884 /* RX_FIFO_NOT_EMPTY */
1885 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1886 u32 val;
1887 u8 dt;
1888 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
86a7867e 1889 DSSERR("\trawval %#08x\n", val);
3de7a1dc
TV		 1890 dt = FLD_GET(val, 5, 0);
1891 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1892 u16 err = FLD_GET(val, 23, 8);
1893 dsi_show_rx_ack_with_err(err);
1894 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
86a7867e 1895 DSSERR("\tDCS short response, 1 byte: %#x\n",
3de7a1dc
TV		 1896 FLD_GET(val, 23, 8));
1897 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
86a7867e 1898 DSSERR("\tDCS short response, 2 byte: %#x\n",
3de7a1dc
TV		 1899 FLD_GET(val, 23, 8));
1900 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
86a7867e 1901 DSSERR("\tDCS long response, len %d\n",
3de7a1dc
TV		 1902 FLD_GET(val, 23, 8));
1903 dsi_vc_flush_long_data(channel);
1904 } else {
1905 DSSERR("\tunknown datatype 0x%02x\n", dt);
1906 }
1907 }
1908 return 0;
1909}
1910
1911static int dsi_vc_send_bta(int channel)
1912{
446f7bff 1913 if (dsi.debug_write || dsi.debug_read)
3de7a1dc
TV		 1914 DSSDBG("dsi_vc_send_bta %d\n", channel);
1915
4f765023 1916 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 1917
1918 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1919 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1920 dsi_vc_flush_receive_data(channel);
1921 }
1922
1923 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1924
1925 return 0;
1926}
1927
1928int dsi_vc_send_bta_sync(int channel)
1929{
1930 int r = 0;
1931 u32 err;
1932
1933 INIT_COMPLETION(dsi.bta_completion);
1934
1935 dsi_vc_enable_bta_irq(channel);
1936
1937 r = dsi_vc_send_bta(channel);
1938 if (r)
1939 goto err;
1940
1941 if (wait_for_completion_timeout(&dsi.bta_completion,
1942 msecs_to_jiffies(500)) == 0) {
1943 DSSERR("Failed to receive BTA\n");
1944 r = -EIO;
1945 goto err;
1946 }
1947
1948 err = dsi_get_errors();
1949 if (err) {
1950 DSSERR("Error while sending BTA: %x\n", err);
1951 r = -EIO;
1952 goto err;
1953 }
1954err:
1955 dsi_vc_disable_bta_irq(channel);
1956
1957 return r;
1958}
1959EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1960
1961static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1962 u16 len, u8 ecc)
1963{
1964 u32 val;
1965 u8 data_id;
1966
4f765023 1967 WARN_ON(!dsi_bus_is_locked());
3de7a1dc 1968
dd8079d6 1969 data_id = data_type | channel << 6;
3de7a1dc
TV		 1970
1971 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1972 FLD_VAL(ecc, 31, 24);
1973
1974 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1975}
1976
1977static inline void dsi_vc_write_long_payload(int channel,
1978 u8 b1, u8 b2, u8 b3, u8 b4)
1979{
1980 u32 val;
1981
1982 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1983
1984/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1985 b1, b2, b3, b4, val); */
1986
1987 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1988}
1989
1990static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1991 u8 ecc)
1992{
1993 /*u32 val; */
1994 int i;
1995 u8 *p;
1996 int r = 0;
1997 u8 b1, b2, b3, b4;
1998
1999 if (dsi.debug_write)
2000 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2001
2002 /* len + header */
2003 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
2004 DSSERR("unable to send long packet: packet too long.\n");
2005 return -EINVAL;
2006 }
2007
2008 dsi_vc_config_l4(channel);
2009
2010 dsi_vc_write_long_header(channel, data_type, len, ecc);
2011
3de7a1dc
TV		 2012 p = data;
2013 for (i = 0; i < len >> 2; i++) {
2014 if (dsi.debug_write)
2015 DSSDBG("\tsending full packet %d\n", i);
3de7a1dc
TV		 2016
2017 b1 = *p++;
2018 b2 = *p++;
2019 b3 = *p++;
2020 b4 = *p++;
2021
2022 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2023 }
2024
2025 i = len % 4;
2026 if (i) {
2027 b1 = 0; b2 = 0; b3 = 0;
2028
2029 if (dsi.debug_write)
2030 DSSDBG("\tsending remainder bytes %d\n", i);
2031
2032 switch (i) {
2033 case 3:
2034 b1 = *p++;
2035 b2 = *p++;
2036 b3 = *p++;
2037 break;
2038 case 2:
2039 b1 = *p++;
2040 b2 = *p++;
2041 break;
2042 case 1:
2043 b1 = *p++;
2044 break;
2045 }
2046
2047 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2048 }
2049
2050 return r;
2051}
2052
2053static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2054{
2055 u32 r;
2056 u8 data_id;
2057
4f765023 2058 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 2059
2060 if (dsi.debug_write)
2061 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2062 channel,
2063 data_type, data & 0xff, (data >> 8) & 0xff);
2064
2065 dsi_vc_config_l4(channel);
2066
2067 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2068 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2069 return -EINVAL;
2070 }
2071
dd8079d6 2072 data_id = data_type | channel << 6;
3de7a1dc
TV		 2073
2074 r = (data_id << 0) | (data << 8) | (ecc << 24);
2075
2076 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2077
2078 return 0;
2079}
2080
2081int dsi_vc_send_null(int channel)
2082{
2083 u8 nullpkg[] = {0, 0, 0, 0};
397bb3c2 2084 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
3de7a1dc
TV		 2085}
2086EXPORT_SYMBOL(dsi_vc_send_null);
2087
2088int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2089{
2090 int r;
2091
2092 BUG_ON(len == 0);
2093
2094 if (len == 1) {
2095 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2096 data[0], 0);
2097 } else if (len == 2) {
2098 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2099 data[0] | (data[1] << 8), 0);
2100 } else {
2101 /* 0x39 = DCS Long Write */
2102 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2103 data, len, 0);
2104 }
2105
2106 return r;
2107}
2108EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2109
2110int dsi_vc_dcs_write(int channel, u8 *data, int len)
2111{
2112 int r;
2113
2114 r = dsi_vc_dcs_write_nosync(channel, data, len);
2115 if (r)
5d68e032 2116 goto err;
3de7a1dc
TV		 2117
2118 r = dsi_vc_send_bta_sync(channel);
5d68e032
TV		 2119 if (r)
2120 goto err;
3de7a1dc 2121
b63ac1e3
TV		 2122 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2123 DSSERR("rx fifo not empty after write, dumping data:\n");
2124 dsi_vc_flush_receive_data(channel);
2125 r = -EIO;
2126 goto err;
2127 }
2128
5d68e032
TV		 2129 return 0;
2130err:
2131 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2132 channel, data[0], len);
3de7a1dc
TV		 2133 return r;
2134}
2135EXPORT_SYMBOL(dsi_vc_dcs_write);
2136
828c48f8
TV		 2137int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2138{
2139 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2140}
2141EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2142
2143int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2144{
2145 u8 buf[2];
2146 buf[0] = dcs_cmd;
2147 buf[1] = param;
2148 return dsi_vc_dcs_write(channel, buf, 2);
2149}
2150EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2151
3de7a1dc
TV		 2152int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2153{
2154 u32 val;
2155 u8 dt;
2156 int r;
2157
2158 if (dsi.debug_read)
ff90a348 2159 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
3de7a1dc
TV		 2160
2161 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2162 if (r)
5d68e032 2163 goto err;
3de7a1dc
TV		 2164
2165 r = dsi_vc_send_bta_sync(channel);
2166 if (r)
5d68e032 2167 goto err;
3de7a1dc
TV		 2168
2169 /* RX_FIFO_NOT_EMPTY */
2170 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2171 DSSERR("RX fifo empty when trying to read.\n");
5d68e032
TV		 2172 r = -EIO;
2173 goto err;
3de7a1dc
TV		 2174 }
2175
2176 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2177 if (dsi.debug_read)
2178 DSSDBG("\theader: %08x\n", val);
2179 dt = FLD_GET(val, 5, 0);
2180 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2181 u16 err = FLD_GET(val, 23, 8);
2182 dsi_show_rx_ack_with_err(err);
5d68e032
TV		 2183 r = -EIO;
2184 goto err;
3de7a1dc
TV		 2185
2186 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2187 u8 data = FLD_GET(val, 15, 8);
2188 if (dsi.debug_read)
2189 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2190
5d68e032
TV		 2191 if (buflen < 1) {
2192 r = -EIO;
2193 goto err;
2194 }
3de7a1dc
TV		 2195
2196 buf[0] = data;
2197
2198 return 1;
2199 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2200 u16 data = FLD_GET(val, 23, 8);
2201 if (dsi.debug_read)
2202 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2203
5d68e032
TV		 2204 if (buflen < 2) {
2205 r = -EIO;
2206 goto err;
2207 }
3de7a1dc
TV		 2208
2209 buf[0] = data & 0xff;
2210 buf[1] = (data >> 8) & 0xff;
2211
2212 return 2;
2213 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2214 int w;
2215 int len = FLD_GET(val, 23, 8);
2216 if (dsi.debug_read)
2217 DSSDBG("\tDCS long response, len %d\n", len);
2218
5d68e032
TV		 2219 if (len > buflen) {
2220 r = -EIO;
2221 goto err;
2222 }
3de7a1dc
TV		 2223
2224 /* two byte checksum ends the packet, not included in len */
2225 for (w = 0; w < len + 2;) {
2226 int b;
2227 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2228 if (dsi.debug_read)
2229 DSSDBG("\t\t%02x %02x %02x %02x\n",
2230 (val >> 0) & 0xff,
2231 (val >> 8) & 0xff,
2232 (val >> 16) & 0xff,
2233 (val >> 24) & 0xff);
2234
2235 for (b = 0; b < 4; ++b) {
2236 if (w < len)
2237 buf[w] = (val >> (b * 8)) & 0xff;
2238 /* we discard the 2 byte checksum */
2239 ++w;
2240 }
2241 }
2242
2243 return len;
3de7a1dc
TV		 2244 } else {
2245 DSSERR("\tunknown datatype 0x%02x\n", dt);
5d68e032
TV		 2246 r = -EIO;
2247 goto err;
3de7a1dc 2248 }
5d68e032
TV		 2249
2250 BUG();
2251err:
2252 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2253 channel, dcs_cmd);
2254 return r;
2255
3de7a1dc
TV		 2256}
2257EXPORT_SYMBOL(dsi_vc_dcs_read);
2258
828c48f8
TV		 2259int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2260{
2261 int r;
2262
2263 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2264
2265 if (r < 0)
2266 return r;
2267
2268 if (r != 1)
2269 return -EIO;
2270
2271 return 0;
2272}
2273EXPORT_SYMBOL(dsi_vc_dcs_read_1);
3de7a1dc 2274
0c244f77 2275int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
53055aae 2276{
0c244f77 2277 u8 buf[2];
53055aae
TV		 2278 int r;
2279
0c244f77 2280 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
53055aae
TV		 2281
2282 if (r < 0)
2283 return r;
2284
2285 if (r != 2)
2286 return -EIO;
2287
0c244f77
TV		 2288 *data1 = buf[0];
2289 *data2 = buf[1];
2290
53055aae
TV		 2291 return 0;
2292}
2293EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2294
3de7a1dc
TV		 2295int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2296{
fa15c79b 2297 return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
3de7a1dc 2298 len, 0);
3de7a1dc
TV		 2299}
2300EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2301
4ffa3571 2302static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
3de7a1dc 2303{
3de7a1dc 2304 unsigned long fck;
4ffa3571
TV		 2305 unsigned long total_ticks;
2306 u32 r;
3de7a1dc 2307
4ffa3571 2308 BUG_ON(ticks > 0x1fff);
3de7a1dc 2309
4ffa3571 2310 /* ticks in DSI_FCK */
3de7a1dc 2311 fck = dsi_fclk_rate();
3de7a1dc
TV		 2312
2313 r = dsi_read_reg(DSI_TIMING2);
2314 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
4ffa3571
TV		 2315 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2316 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3de7a1dc
TV		 2317 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2318 dsi_write_reg(DSI_TIMING2, r);
2319
4ffa3571
TV		 2320 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2321
2322 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2323 total_ticks,
2324 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2325 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2326}
2327
4ffa3571 2328static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
3de7a1dc 2329{
3de7a1dc 2330 unsigned long fck;
4ffa3571
TV		 2331 unsigned long total_ticks;
2332 u32 r;
2333
2334 BUG_ON(ticks > 0x1fff);
3de7a1dc
TV		 2335
2336 /* ticks in DSI_FCK */
2337 fck = dsi_fclk_rate();
3de7a1dc
TV		 2338
2339 r = dsi_read_reg(DSI_TIMING1);
2340 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
4ffa3571
TV		 2341 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2342 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3de7a1dc
TV		 2343 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2344 dsi_write_reg(DSI_TIMING1, r);
2345
4ffa3571
TV		 2346 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2347
2348 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2349 total_ticks,
2350 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2351 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2352}
2353
4ffa3571 2354static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
3de7a1dc 2355{
3de7a1dc 2356 unsigned long fck;
4ffa3571
TV		 2357 unsigned long total_ticks;
2358 u32 r;
3de7a1dc 2359
4ffa3571 2360 BUG_ON(ticks > 0x1fff);
3de7a1dc 2361
4ffa3571 2362 /* ticks in DSI_FCK */
3de7a1dc 2363 fck = dsi_fclk_rate();
3de7a1dc
TV		 2364
2365 r = dsi_read_reg(DSI_TIMING1);
2366 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
4ffa3571
TV		 2367 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2368 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3de7a1dc
TV		 2369 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2370 dsi_write_reg(DSI_TIMING1, r);
2371
4ffa3571
TV		 2372 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2373
2374 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2375 total_ticks,
2376 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2377 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2378}
2379
4ffa3571 2380static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
3de7a1dc 2381{
3de7a1dc 2382 unsigned long fck;
4ffa3571
TV		 2383 unsigned long total_ticks;
2384 u32 r;
3de7a1dc 2385
4ffa3571 2386 BUG_ON(ticks > 0x1fff);
3de7a1dc 2387
4ffa3571 2388 /* ticks in TxByteClkHS */
3de7a1dc 2389 fck = dsi_get_txbyteclkhs();
3de7a1dc
TV		 2390
2391 r = dsi_read_reg(DSI_TIMING2);
2392 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
4ffa3571
TV		 2393 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2394 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3de7a1dc
TV		 2395 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2396 dsi_write_reg(DSI_TIMING2, r);
2397
4ffa3571
TV		 2398 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2399
2400 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2401 total_ticks,
2402 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2403 (total_ticks * 1000) / (fck / 1000 / 1000));
3de7a1dc
TV		 2404}
2405static int dsi_proto_config(struct omap_dss_device *dssdev)
2406{
2407 u32 r;
2408 int buswidth = 0;
2409
dd8079d6
TV		 2410 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2411 DSI_FIFO_SIZE_32,
2412 DSI_FIFO_SIZE_32,
2413 DSI_FIFO_SIZE_32);
3de7a1dc 2414
dd8079d6
TV		 2415 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2416 DSI_FIFO_SIZE_32,
2417 DSI_FIFO_SIZE_32,
2418 DSI_FIFO_SIZE_32);
3de7a1dc
TV		 2419
2420 /* XXX what values for the timeouts? */
4ffa3571
TV		 2421 dsi_set_stop_state_counter(0x1000, false, false);
2422 dsi_set_ta_timeout(0x1fff, true, true);
2423 dsi_set_lp_rx_timeout(0x1fff, true, true);
2424 dsi_set_hs_tx_timeout(0x1fff, true, true);
3de7a1dc
TV		 2425
2426 switch (dssdev->ctrl.pixel_size) {
2427 case 16:
2428 buswidth = 0;
2429 break;
2430 case 18:
2431 buswidth = 1;
2432 break;
2433 case 24:
2434 buswidth = 2;
2435 break;
2436 default:
2437 BUG();
2438 }
2439
2440 r = dsi_read_reg(DSI_CTRL);
2441 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2442 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2443 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2444 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2445 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2446 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2447 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2448 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2449 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2450 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2451 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2452
2453 dsi_write_reg(DSI_CTRL, r);
2454
2455 dsi_vc_initial_config(0);
dd8079d6
TV		 2456 dsi_vc_initial_config(1);
2457 dsi_vc_initial_config(2);
2458 dsi_vc_initial_config(3);
3de7a1dc
TV		 2459
2460 return 0;
2461}
2462
2463static void dsi_proto_timings(struct omap_dss_device *dssdev)
2464{
2465 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2466 unsigned tclk_pre, tclk_post;
2467 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2468 unsigned ths_trail, ths_exit;
2469 unsigned ddr_clk_pre, ddr_clk_post;
2470 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2471 unsigned ths_eot;
2472 u32 r;
2473
2474 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2475 ths_prepare = FLD_GET(r, 31, 24);
2476 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2477 ths_zero = ths_prepare_ths_zero - ths_prepare;
2478 ths_trail = FLD_GET(r, 15, 8);
2479 ths_exit = FLD_GET(r, 7, 0);
2480
2481 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2482 tlpx = FLD_GET(r, 22, 16) * 2;
2483 tclk_trail = FLD_GET(r, 15, 8);
2484 tclk_zero = FLD_GET(r, 7, 0);
2485
2486 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2487 tclk_prepare = FLD_GET(r, 7, 0);
2488
2489 /* min 8*UI */
2490 tclk_pre = 20;
2491 /* min 60ns + 52*UI */
2492 tclk_post = ns2ddr(60) + 26;
2493
2494 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2495 if (dssdev->phy.dsi.data1_lane != 0 &&
2496 dssdev->phy.dsi.data2_lane != 0)
2497 ths_eot = 2;
2498 else
2499 ths_eot = 4;
2500
2501 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2502 4);
2503 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2504
2505 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2506 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2507
2508 r = dsi_read_reg(DSI_CLK_TIMING);
2509 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2510 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2511 dsi_write_reg(DSI_CLK_TIMING, r);
2512
2513 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2514 ddr_clk_pre,
2515 ddr_clk_post);
2516
2517 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2518 DIV_ROUND_UP(ths_prepare, 4) +
2519 DIV_ROUND_UP(ths_zero + 3, 4);
2520
2521 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2522
2523 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2524 FLD_VAL(exit_hs_mode_lat, 15, 0);
2525 dsi_write_reg(DSI_VM_TIMING7, r);
2526
2527 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2528 enter_hs_mode_lat, exit_hs_mode_lat);
2529}
2530
2531
2532#define DSI_DECL_VARS \
2533 int __dsi_cb = 0; u32 __dsi_cv = 0;
2534
2535#define DSI_FLUSH(ch) \
2536 if (__dsi_cb > 0) { \
2537 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2538 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2539 __dsi_cb = __dsi_cv = 0; \
2540 }
2541
2542#define DSI_PUSH(ch, data) \
2543 do { \
2544 __dsi_cv |= (data) << (__dsi_cb * 8); \
2545 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2546 if (++__dsi_cb > 3) \
2547 DSI_FLUSH(ch); \
2548 } while (0)
2549
2550static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2551 int x, int y, int w, int h)
2552{
2553 /* Note: supports only 24bit colors in 32bit container */
2554 int first = 1;
2555 int fifo_stalls = 0;
2556 int max_dsi_packet_size;
2557 int max_data_per_packet;
2558 int max_pixels_per_packet;
2559 int pixels_left;
2560 int bytespp = dssdev->ctrl.pixel_size / 8;
2561 int scr_width;
2562 u32 __iomem *data;
2563 int start_offset;
2564 int horiz_inc;
2565 int current_x;
2566 struct omap_overlay *ovl;
2567
2568 debug_irq = 0;
2569
2570 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2571 x, y, w, h);
2572
2573 ovl = dssdev->manager->overlays[0];
2574
2575 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2576 return -EINVAL;
2577
2578 if (dssdev->ctrl.pixel_size != 24)
2579 return -EINVAL;
2580
2581 scr_width = ovl->info.screen_width;
2582 data = ovl->info.vaddr;
2583
2584 start_offset = scr_width * y + x;
2585 horiz_inc = scr_width - w;
2586 current_x = x;
2587
2588 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2589 * in fifo */
2590
2591 /* When using CPU, max long packet size is TX buffer size */
2592 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2593
2594 /* we seem to get better perf if we divide the tx fifo to half,
2595 and while the other half is being sent, we fill the other half
2596 max_dsi_packet_size /= 2; */
2597
2598 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2599
2600 max_pixels_per_packet = max_data_per_packet / bytespp;
2601
2602 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2603
2604 pixels_left = w * h;
2605
2606 DSSDBG("total pixels %d\n", pixels_left);
2607
2608 data += start_offset;
2609
2610 while (pixels_left > 0) {
2611 /* 0x2c = write_memory_start */
2612 /* 0x3c = write_memory_continue */
2613 u8 dcs_cmd = first ? 0x2c : 0x3c;
2614 int pixels;
2615 DSI_DECL_VARS;
2616 first = 0;
2617
2618#if 1
2619 /* using fifo not empty */
2620 /* TX_FIFO_NOT_EMPTY */
2621 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
3de7a1dc
TV		 2622 fifo_stalls++;
2623 if (fifo_stalls > 0xfffff) {
2624 DSSERR("fifo stalls overflow, pixels left %d\n",
2625 pixels_left);
2626 dsi_if_enable(0);
2627 return -EIO;
2628 }
24be78b3 2629 udelay(1);
3de7a1dc
TV		 2630 }
2631#elif 1
2632 /* using fifo emptiness */
2633 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2634 max_dsi_packet_size) {
2635 fifo_stalls++;
2636 if (fifo_stalls > 0xfffff) {
2637 DSSERR("fifo stalls overflow, pixels left %d\n",
2638 pixels_left);
2639 dsi_if_enable(0);
2640 return -EIO;
2641 }
2642 }
2643#else
2644 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2645 fifo_stalls++;
2646 if (fifo_stalls > 0xfffff) {
2647 DSSERR("fifo stalls overflow, pixels left %d\n",
2648 pixels_left);
2649 dsi_if_enable(0);
2650 return -EIO;
2651 }
2652 }
2653#endif
2654 pixels = min(max_pixels_per_packet, pixels_left);
2655
2656 pixels_left -= pixels;
2657
2658 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2659 1 + pixels * bytespp, 0);
2660
2661 DSI_PUSH(0, dcs_cmd);
2662
2663 while (pixels-- > 0) {
2664 u32 pix = __raw_readl(data++);
2665
2666 DSI_PUSH(0, (pix >> 16) & 0xff);
2667 DSI_PUSH(0, (pix >> 8) & 0xff);
2668 DSI_PUSH(0, (pix >> 0) & 0xff);
2669
2670 current_x++;
2671 if (current_x == x+w) {
2672 current_x = x;
2673 data += horiz_inc;
2674 }
2675 }
2676
2677 DSI_FLUSH(0);
2678 }
2679
2680 return 0;
2681}
2682
2683static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2684 u16 x, u16 y, u16 w, u16 h)
2685{
2686 unsigned bytespp;
2687 unsigned bytespl;
2688 unsigned bytespf;
2689 unsigned total_len;
2690 unsigned packet_payload;
2691 unsigned packet_len;
2692 u32 l;
0f16aa0a 2693 int r;
18946f62 2694 const unsigned channel = dsi.update_channel;
3de7a1dc
TV		 2695 /* line buffer is 1024 x 24bits */
2696 /* XXX: for some reason using full buffer size causes considerable TX
2697 * slowdown with update sizes that fill the whole buffer */
2698 const unsigned line_buf_size = 1023 * 3;
2699
446f7bff
TV		 2700 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2701 x, y, w, h);
3de7a1dc 2702
18946f62
TV		 2703 dsi_vc_config_vp(channel);
2704
3de7a1dc
TV		 2705 bytespp = dssdev->ctrl.pixel_size / 8;
2706 bytespl = w * bytespp;
2707 bytespf = bytespl * h;
2708
2709 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2710 * number of lines in a packet. See errata about VP_CLK_RATIO */
2711
2712 if (bytespf < line_buf_size)
2713 packet_payload = bytespf;
2714 else
2715 packet_payload = (line_buf_size) / bytespl * bytespl;
2716
2717 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2718 total_len = (bytespf / packet_payload) * packet_len;
2719
2720 if (bytespf % packet_payload)
2721 total_len += (bytespf % packet_payload) + 1;
2722
3de7a1dc
TV		 2723 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2724 dsi_write_reg(DSI_VC_TE(channel), l);
2725
2726 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2727
942a91a6 2728 if (dsi.te_enabled)
3de7a1dc
TV		 2729 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2730 else
2731 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2732 dsi_write_reg(DSI_VC_TE(channel), l);
2733
2734 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2735 * because DSS interrupts are not capable of waking up the CPU and the
2736 * framedone interrupt could be delayed for quite a long time. I think
2737 * the same goes for any DSS interrupts, but for some reason I have not
2738 * seen the problem anywhere else than here.
2739 */
2740 dispc_disable_sidle();
2741
18946f62
TV		 2742 dsi_perf_mark_start();
2743
0f16aa0a 2744 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
18946f62 2745 msecs_to_jiffies(250));
0f16aa0a 2746 BUG_ON(r == 0);
18946f62 2747
3de7a1dc
TV		 2748 dss_start_update(dssdev);
2749
942a91a6 2750 if (dsi.te_enabled) {
3de7a1dc
TV		 2751 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2752 * for TE is longer than the timer allows */
2753 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2754
2755 dsi_vc_send_bta(channel);
2756
2757#ifdef DSI_CATCH_MISSING_TE
2758 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2759#endif
2760 }
2761}
2762
2763#ifdef DSI_CATCH_MISSING_TE
2764static void dsi_te_timeout(unsigned long arg)
2765{
2766 DSSERR("TE not received for 250ms!\n");
2767}
2768#endif
2769
ab83b14c 2770static void dsi_handle_framedone(int error)
3de7a1dc 2771{
18946f62 2772 const int channel = dsi.update_channel;
18946f62 2773
ab83b14c 2774 cancel_delayed_work(&dsi.framedone_timeout_work);
3de7a1dc 2775
ab83b14c 2776 dsi_vc_disable_bta_irq(channel);
0f16aa0a 2777
3de7a1dc
TV		 2778 /* SIDLEMODE back to smart-idle */
2779 dispc_enable_sidle();
2780
ab83b14c
TV		 2781 dsi.bta_callback = NULL;
2782
942a91a6 2783 if (dsi.te_enabled) {
18946f62
TV		 2784 /* enable LP_RX_TO again after the TE */
2785 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3de7a1dc
TV		 2786 }
2787
18946f62
TV		 2788 /* RX_FIFO_NOT_EMPTY */
2789 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2790 DSSERR("Received error during frame transfer:\n");
2791 dsi_vc_flush_receive_data(channel);
ab83b14c
TV		 2792 if (!error)
2793 error = -EIO;
18946f62
TV		 2794 }
2795
ab83b14c
TV		 2796 dsi.framedone_callback(error, dsi.framedone_data);
2797
2798 if (!error)
2799 dsi_perf_show("DISPC");
18946f62 2800}
3de7a1dc 2801
ab83b14c 2802static void dsi_framedone_timeout_work_callback(struct work_struct *work)
18946f62 2803{
ab83b14c
TV		 2804 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
2805 * 250ms which would conflict with this timeout work. What should be
2806 * done is first cancel the transfer on the HW, and then cancel the
2807 * possibly scheduled framedone work. However, cancelling the transfer
2808 * on the HW is buggy, and would probably require resetting the whole
2809 * DSI */
18946f62 2810
ab83b14c 2811 DSSERR("Framedone not received for 250ms!\n");
3de7a1dc 2812
ab83b14c 2813 dsi_handle_framedone(-ETIMEDOUT);
3de7a1dc
TV		 2814}
2815
ab83b14c
TV		 2816static void dsi_framedone_bta_callback(void)
2817{
2818 dsi_handle_framedone(0);
2819
2820#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2821 dispc_fake_vsync_irq();
2822#endif
2823}
2824
2825static void dsi_framedone_irq_callback(void *data, u32 mask)
3de7a1dc 2826{
18946f62 2827 const int channel = dsi.update_channel;
ab83b14c 2828 int r;
3de7a1dc 2829
ab83b14c
TV		 2830 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2831 * turns itself off. However, DSI still has the pixels in its buffers,
2832 * and is sending the data.
2833 */
3de7a1dc 2834
942a91a6 2835 if (dsi.te_enabled) {
3de7a1dc
TV		 2836 /* enable LP_RX_TO again after the TE */
2837 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2838 }
2839
2840 /* Send BTA after the frame. We need this for the TE to work, as TE
2841 * trigger is only sent for BTAs without preceding packet. Thus we need
2842 * to BTA after the pixel packets so that next BTA will cause TE
2843 * trigger.
2844 *
2845 * This is not needed when TE is not in use, but we do it anyway to
2846 * make sure that the transfer has been completed. It would be more
2847 * optimal, but more complex, to wait only just before starting next
ab83b14c
TV		 2848 * transfer.
2849 *
2850 * Also, as there's no interrupt telling when the transfer has been
2851 * done and the channel could be reconfigured, the only way is to
2852 * busyloop until TE_SIZE is zero. With BTA we can do this
2853 * asynchronously.
2854 * */
3de7a1dc 2855
ab83b14c 2856 dsi.bta_callback = dsi_framedone_bta_callback;
3de7a1dc 2857
ab83b14c 2858 barrier();
3de7a1dc 2859
ab83b14c 2860 dsi_vc_enable_bta_irq(channel);
3de7a1dc 2861
ab83b14c
TV		 2862 r = dsi_vc_send_bta(channel);
2863 if (r) {
2864 DSSERR("BTA after framedone failed\n");
2865 dsi_handle_framedone(-EIO);
2866 }
18946f62 2867}
3de7a1dc 2868
18946f62 2869int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
26a8c250
TV		 2870 u16 *x, u16 *y, u16 *w, u16 *h,
2871 bool enlarge_update_area)
18946f62
TV		 2872{
2873 u16 dw, dh;
3de7a1dc 2874
18946f62 2875 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3de7a1dc 2876
18946f62
TV		 2877 if (*x > dw || *y > dh)
2878 return -EINVAL;
3de7a1dc 2879
18946f62
TV		 2880 if (*x + *w > dw)
2881 return -EINVAL;
3de7a1dc 2882
18946f62
TV		 2883 if (*y + *h > dh)
2884 return -EINVAL;
3de7a1dc 2885
18946f62
TV		 2886 if (*w == 1)
2887 return -EINVAL;
3de7a1dc 2888
18946f62
TV		 2889 if (*w == 0 || *h == 0)
2890 return -EINVAL;
3de7a1dc 2891
18946f62 2892 dsi_perf_mark_setup();
3de7a1dc 2893
18946f62 2894 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
26a8c250
TV		 2895 dss_setup_partial_planes(dssdev, x, y, w, h,
2896 enlarge_update_area);
64ba4f74 2897 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
18946f62 2898 }
3de7a1dc 2899
18946f62
TV		 2900 return 0;
2901}
2902EXPORT_SYMBOL(omap_dsi_prepare_update);
3de7a1dc 2903
18946f62
TV		 2904int omap_dsi_update(struct omap_dss_device *dssdev,
2905 int channel,
2906 u16 x, u16 y, u16 w, u16 h,
2907 void (*callback)(int, void *), void *data)
2908{
2909 dsi.update_channel = channel;
3de7a1dc 2910
a602771c
TV		 2911 /* OMAP DSS cannot send updates of odd widths.
2912 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
2913 * here to make sure we catch erroneous updates. Otherwise we'll only
2914 * see rather obscure HW error happening, as DSS halts. */
2915 BUG_ON(x % 2 == 1);
2916
18946f62
TV		 2917 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2918 dsi.framedone_callback = callback;
2919 dsi.framedone_data = data;
3de7a1dc 2920
18946f62
TV		 2921 dsi.update_region.x = x;
2922 dsi.update_region.y = y;
2923 dsi.update_region.w = w;
2924 dsi.update_region.h = h;
2925 dsi.update_region.device = dssdev;
3de7a1dc 2926
18946f62
TV		 2927 dsi_update_screen_dispc(dssdev, x, y, w, h);
2928 } else {
e9c31afc
AT		 2929 int r;
2930
2931 r = dsi_update_screen_l4(dssdev, x, y, w, h);
2932 if (r)
2933 return r;
2934
18946f62
TV		 2935 dsi_perf_show("L4");
2936 callback(0, data);
3de7a1dc
TV		 2937 }
2938
3de7a1dc
TV		 2939 return 0;
2940}
18946f62 2941EXPORT_SYMBOL(omap_dsi_update);
3de7a1dc
TV		 2942
2943/* Display funcs */
2944
2945static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2946{
2947 int r;
2948
2949 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
2950 DISPC_IRQ_FRAMEDONE);
2951 if (r) {
2952 DSSERR("can't get FRAMEDONE irq\n");
2953 return r;
2954 }
2955
64ba4f74
SS		 2956 dispc_set_lcd_display_type(dssdev->manager->id,
2957 OMAP_DSS_LCD_DISPLAY_TFT);
3de7a1dc 2958
64ba4f74
SS		 2959 dispc_set_parallel_interface_mode(dssdev->manager->id,
2960 OMAP_DSS_PARALLELMODE_DSI);
2961 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
3de7a1dc 2962
64ba4f74 2963 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
3de7a1dc
TV		 2964
2965 {
2966 struct omap_video_timings timings = {
2967 .hsw = 1,
2968 .hfp = 1,
2969 .hbp = 1,
2970 .vsw = 1,
2971 .vfp = 0,
2972 .vbp = 0,
2973 };
2974
64ba4f74 2975 dispc_set_lcd_timings(dssdev->manager->id, &timings);
3de7a1dc
TV		 2976 }
2977
2978 return 0;
2979}
2980
2981static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
2982{
2983 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
2984 DISPC_IRQ_FRAMEDONE);
2985}
2986
2987static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
2988{
2989 struct dsi_clock_info cinfo;
2990 int r;
2991
2992 /* we always use DSS2_FCK as input clock */
2993 cinfo.use_dss2_fck = true;
2994 cinfo.regn = dssdev->phy.dsi.div.regn;
2995 cinfo.regm = dssdev->phy.dsi.div.regm;
2996 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
2997 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
ff1b2cde 2998 r = dsi_calc_clock_rates(dssdev, &cinfo);
ebf0a3fe
VS		 2999 if (r) {
3000 DSSERR("Failed to calc dsi clocks\n");
3de7a1dc 3001 return r;
ebf0a3fe 3002 }
3de7a1dc
TV		 3003
3004 r = dsi_pll_set_clock_div(&cinfo);
3005 if (r) {
3006 DSSERR("Failed to set dsi clocks\n");
3007 return r;
3008 }
3009
3010 return 0;
3011}
3012
3013static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3014{
3015 struct dispc_clock_info dispc_cinfo;
3016 int r;
3017 unsigned long long fck;
3018
3019 fck = dsi_get_dsi1_pll_rate();
3020
3021 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3022 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3023
3024 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3025 if (r) {
3026 DSSERR("Failed to calc dispc clocks\n");
3027 return r;
3028 }
3029
ff1b2cde 3030 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3de7a1dc
TV		 3031 if (r) {
3032 DSSERR("Failed to set dispc clocks\n");
3033 return r;
3034 }
3035
3036 return 0;
3037}
3038
3039static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3040{
3041 int r;
3042
3043 _dsi_print_reset_status();
3044
3045 r = dsi_pll_init(dssdev, true, true);
3046 if (r)
3047 goto err0;
3048
3049 r = dsi_configure_dsi_clocks(dssdev);
3050 if (r)
3051 goto err1;
3052
88134fa1
AT		 3053 dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
3054 dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
3de7a1dc
TV		 3055
3056 DSSDBG("PLL OK\n");
3057
3058 r = dsi_configure_dispc_clocks(dssdev);
3059 if (r)
3060 goto err2;
3061
3062 r = dsi_complexio_init(dssdev);
3063 if (r)
3064 goto err2;
3065
3066 _dsi_print_reset_status();
3067
3068 dsi_proto_timings(dssdev);
3069 dsi_set_lp_clk_divisor(dssdev);
3070
3071 if (1)
3072 _dsi_print_reset_status();
3073
3074 r = dsi_proto_config(dssdev);
3075 if (r)
3076 goto err3;
3077
3078 /* enable interface */
3079 dsi_vc_enable(0, 1);
dd8079d6
TV		 3080 dsi_vc_enable(1, 1);
3081 dsi_vc_enable(2, 1);
3082 dsi_vc_enable(3, 1);
3de7a1dc
TV		 3083 dsi_if_enable(1);
3084 dsi_force_tx_stop_mode_io();
3085
3de7a1dc 3086 return 0;
3de7a1dc
TV		 3087err3:
3088 dsi_complexio_uninit();
3089err2:
88134fa1
AT		 3090 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
3091 dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
3de7a1dc
TV		 3092err1:
3093 dsi_pll_uninit();
3094err0:
3095 return r;
3096}
3097
3098static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3099{
d7370104
VS		 3100 /* disable interface */
3101 dsi_if_enable(0);
3102 dsi_vc_enable(0, 0);
3103 dsi_vc_enable(1, 0);
3104 dsi_vc_enable(2, 0);
3105 dsi_vc_enable(3, 0);
3106
88134fa1
AT		 3107 dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
3108 dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
3de7a1dc
TV		 3109 dsi_complexio_uninit();
3110 dsi_pll_uninit();
3111}
3112
3113static int dsi_core_init(void)
3114{
3115 /* Autoidle */
3116 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3117
3118 /* ENWAKEUP */
3119 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3120
3121 /* SIDLEMODE smart-idle */
3122 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3123
3124 _dsi_initialize_irq();
3125
3126 return 0;
3127}
3128
37ac60e4 3129int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3de7a1dc
TV		 3130{
3131 int r = 0;
3132
3133 DSSDBG("dsi_display_enable\n");
3134
37ac60e4
TV		 3135 WARN_ON(!dsi_bus_is_locked());
3136
3de7a1dc 3137 mutex_lock(&dsi.lock);
3de7a1dc
TV		 3138
3139 r = omap_dss_start_device(dssdev);
3140 if (r) {
3141 DSSERR("failed to start device\n");
3142 goto err0;
3143 }
3144
3de7a1dc
TV		 3145 enable_clocks(1);
3146 dsi_enable_pll_clock(1);
3147
3148 r = _dsi_reset();
3149 if (r)
37ac60e4 3150 goto err1;
3de7a1dc
TV		 3151
3152 dsi_core_init();
3153
3154 r = dsi_display_init_dispc(dssdev);
3155 if (r)
37ac60e4 3156 goto err1;
3de7a1dc
TV		 3157
3158 r = dsi_display_init_dsi(dssdev);
3159 if (r)
37ac60e4 3160 goto err2;
3de7a1dc 3161
3de7a1dc
TV		 3162 mutex_unlock(&dsi.lock);
3163
3164 return 0;
3165
3de7a1dc 3166err2:
37ac60e4
TV		 3167 dsi_display_uninit_dispc(dssdev);
3168err1:
3de7a1dc
TV		 3169 enable_clocks(0);
3170 dsi_enable_pll_clock(0);
3de7a1dc
TV		 3171 omap_dss_stop_device(dssdev);
3172err0:
3de7a1dc
TV		 3173 mutex_unlock(&dsi.lock);
3174 DSSDBG("dsi_display_enable FAILED\n");
3175 return r;
3176}
37ac60e4 3177EXPORT_SYMBOL(omapdss_dsi_display_enable);
3de7a1dc 3178
37ac60e4 3179void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
3de7a1dc
TV		 3180{
3181 DSSDBG("dsi_display_disable\n");
3182
37ac60e4 3183 WARN_ON(!dsi_bus_is_locked());
3de7a1dc
TV		 3184
3185 mutex_lock(&dsi.lock);
3de7a1dc
TV		 3186
3187 dsi_display_uninit_dispc(dssdev);
3188
3189 dsi_display_uninit_dsi(dssdev);
3190
3191 enable_clocks(0);
3192 dsi_enable_pll_clock(0);
3de7a1dc 3193
37ac60e4 3194 omap_dss_stop_device(dssdev);
3de7a1dc 3195
3de7a1dc 3196 mutex_unlock(&dsi.lock);
3de7a1dc 3197}
37ac60e4 3198EXPORT_SYMBOL(omapdss_dsi_display_disable);
3de7a1dc 3199
225b650d 3200int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3de7a1dc 3201{
3de7a1dc 3202 dsi.te_enabled = enable;
225b650d 3203 return 0;
3de7a1dc 3204}
225b650d 3205EXPORT_SYMBOL(omapdss_dsi_enable_te);
3de7a1dc 3206
3de7a1dc
TV		 3207void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3208 u32 fifo_size, enum omap_burst_size *burst_size,
3209 u32 *fifo_low, u32 *fifo_high)
3210{
3211 unsigned burst_size_bytes;
3212
3213 *burst_size = OMAP_DSS_BURST_16x32;
3214 burst_size_bytes = 16 * 32 / 8;
3215
3216 *fifo_high = fifo_size - burst_size_bytes;
36194b47 3217 *fifo_low = fifo_size - burst_size_bytes * 2;
3de7a1dc
TV		 3218}
3219
3220int dsi_init_display(struct omap_dss_device *dssdev)
3221{
3222 DSSDBG("DSI init\n");
3223
3de7a1dc
TV		 3224 /* XXX these should be figured out dynamically */
3225 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3226 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3227
3228 dsi.vc[0].dssdev = dssdev;
3229 dsi.vc[1].dssdev = dssdev;
3230
5f42f2ce
TV		 3231 if (dsi.vdds_dsi_reg == NULL) {
3232 struct regulator *vdds_dsi;
3233
3234 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
3235
3236 if (IS_ERR(vdds_dsi)) {
3237 DSSERR("can't get VDDS_DSI regulator\n");
3238 return PTR_ERR(vdds_dsi);
3239 }
3240
3241 dsi.vdds_dsi_reg = vdds_dsi;
3242 }
3243
3de7a1dc
TV		 3244 return 0;
3245}
3246
e406f907
TV		 3247void dsi_wait_dsi1_pll_active(void)
3248{
3249 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
067a57e4
AT		 3250 DSSERR("%s (%s) not active\n",
3251 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
3252 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
e406f907
TV		 3253}
3254
3255void dsi_wait_dsi2_pll_active(void)
3256{
3257 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
067a57e4
AT		 3258 DSSERR("%s (%s) not active\n",
3259 dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
3260 dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
e406f907
TV		 3261}
3262
c8aac01b 3263static int dsi_init(struct platform_device *pdev)
3de7a1dc
TV		 3264{
3265 u32 rev;
3266 int r;
ea9da36a 3267 struct resource *dsi_mem;
3de7a1dc
TV		 3268
3269 spin_lock_init(&dsi.errors_lock);
3270 dsi.errors = 0;
3271
dfc0fd8d
TV		 3272#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3273 spin_lock_init(&dsi.irq_stats_lock);
3274 dsi.irq_stats.last_reset = jiffies;
3275#endif
3276
3de7a1dc 3277 init_completion(&dsi.bta_completion);
3de7a1dc
TV		 3278
3279 mutex_init(&dsi.lock);
b9eb5d7d 3280 sema_init(&dsi.bus_lock, 1);
3de7a1dc 3281
0f16aa0a
TV		 3282 dsi.workqueue = create_singlethread_workqueue("dsi");
3283 if (dsi.workqueue == NULL)
3284 return -ENOMEM;
3285
18946f62
TV		 3286 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3287 dsi_framedone_timeout_work_callback);
3288
3de7a1dc
TV		 3289#ifdef DSI_CATCH_MISSING_TE
3290 init_timer(&dsi.te_timer);
3291 dsi.te_timer.function = dsi_te_timeout;
3292 dsi.te_timer.data = 0;
3293#endif
ea9da36a
SG		 3294 dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
3295 if (!dsi_mem) {
3296 DSSERR("can't get IORESOURCE_MEM DSI\n");
3297 r = -EINVAL;
3298 goto err1;
3299 }
3300 dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
3de7a1dc
TV		 3301 if (!dsi.base) {
3302 DSSERR("can't ioremap DSI\n");
3303 r = -ENOMEM;
3304 goto err1;
3305 }
affe360d 3306 dsi.irq = platform_get_irq(dsi.pdev, 0);
3307 if (dsi.irq < 0) {
3308 DSSERR("platform_get_irq failed\n");
3309 r = -ENODEV;
3310 goto err2;
3311 }
3312
3313 r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
3314 "OMAP DSI1", dsi.pdev);
3315 if (r < 0) {
3316 DSSERR("request_irq failed\n");
3317 goto err2;
3318 }
3de7a1dc 3319
3de7a1dc
TV		 3320 enable_clocks(1);
3321
3322 rev = dsi_read_reg(DSI_REVISION);
a06b62f8 3323 dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
3de7a1dc
TV		 3324 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3325
3326 enable_clocks(0);
3327
3de7a1dc 3328 return 0;
affe360d 3329err2:
3330 iounmap(dsi.base);
3de7a1dc 3331err1:
0f16aa0a 3332 destroy_workqueue(dsi.workqueue);
3de7a1dc
TV		 3333 return r;
3334}
3335
c8aac01b 3336static void dsi_exit(void)
3de7a1dc 3337{
c8aac01b
SG		 3338 if (dsi.vdds_dsi_reg != NULL) {
3339 regulator_put(dsi.vdds_dsi_reg);
3340 dsi.vdds_dsi_reg = NULL;
3341 }
3342
affe360d 3343 free_irq(dsi.irq, dsi.pdev);
3de7a1dc
TV		 3344 iounmap(dsi.base);
3345
0f16aa0a
TV		 3346 destroy_workqueue(dsi.workqueue);
3347
3de7a1dc
TV		 3348 DSSDBG("omap_dsi_exit\n");
3349}
3350
c8aac01b
SG		 3351/* DSI1 HW IP initialisation */
3352static int omap_dsi1hw_probe(struct platform_device *pdev)
3353{
3354 int r;
3355 dsi.pdev = pdev;
3356 r = dsi_init(pdev);
3357 if (r) {
3358 DSSERR("Failed to initialize DSI\n");
3359 goto err_dsi;
3360 }
3361err_dsi:
3362 return r;
3363}
3364
3365static int omap_dsi1hw_remove(struct platform_device *pdev)
3366{
3367 dsi_exit();
3368 return 0;
3369}
3370
3371static struct platform_driver omap_dsi1hw_driver = {
3372 .probe = omap_dsi1hw_probe,
3373 .remove = omap_dsi1hw_remove,
3374 .driver = {
3375 .name = "omapdss_dsi1",
3376 .owner = THIS_MODULE,
3377 },
3378};
3379
3380int dsi_init_platform_driver(void)
3381{
3382 return platform_driver_register(&omap_dsi1hw_driver);
3383}
3384
3385void dsi_uninit_platform_driver(void)
3386{
3387 return platform_driver_unregister(&omap_dsi1hw_driver);
3388}
Linux kernel - Deliverables
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