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3de7a1dc TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dsi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #define DSS_SUBSYS_NAME "DSI" | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/mutex.h> | |
355b200b | 30 | #include <linux/module.h> |
b9eb5d7d | 31 | #include <linux/semaphore.h> |
3de7a1dc TV |
32 | #include <linux/seq_file.h> |
33 | #include <linux/platform_device.h> | |
34 | #include <linux/regulator/consumer.h> | |
3de7a1dc | 35 | #include <linux/wait.h> |
18946f62 | 36 | #include <linux/workqueue.h> |
40885ab3 | 37 | #include <linux/sched.h> |
f1da39d9 | 38 | #include <linux/slab.h> |
5a8b572d | 39 | #include <linux/debugfs.h> |
4fbafaf3 | 40 | #include <linux/pm_runtime.h> |
3de7a1dc | 41 | |
a0b38cc4 | 42 | #include <video/omapdss.h> |
7a7c48f9 | 43 | #include <video/mipi_display.h> |
3de7a1dc TV |
44 | #include <plat/clock.h> |
45 | ||
46 | #include "dss.h" | |
819d807c | 47 | #include "dss_features.h" |
3de7a1dc TV |
48 | |
49 | /*#define VERBOSE_IRQ*/ | |
50 | #define DSI_CATCH_MISSING_TE | |
51 | ||
3de7a1dc TV |
52 | struct dsi_reg { u16 idx; }; |
53 | ||
54 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) | |
55 | ||
56 | #define DSI_SZ_REGS SZ_1K | |
57 | /* DSI Protocol Engine */ | |
58 | ||
59 | #define DSI_REVISION DSI_REG(0x0000) | |
60 | #define DSI_SYSCONFIG DSI_REG(0x0010) | |
61 | #define DSI_SYSSTATUS DSI_REG(0x0014) | |
62 | #define DSI_IRQSTATUS DSI_REG(0x0018) | |
63 | #define DSI_IRQENABLE DSI_REG(0x001C) | |
64 | #define DSI_CTRL DSI_REG(0x0040) | |
75d7247c | 65 | #define DSI_GNQ DSI_REG(0x0044) |
3de7a1dc TV |
66 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) |
67 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) | |
68 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) | |
69 | #define DSI_CLK_CTRL DSI_REG(0x0054) | |
70 | #define DSI_TIMING1 DSI_REG(0x0058) | |
71 | #define DSI_TIMING2 DSI_REG(0x005C) | |
72 | #define DSI_VM_TIMING1 DSI_REG(0x0060) | |
73 | #define DSI_VM_TIMING2 DSI_REG(0x0064) | |
74 | #define DSI_VM_TIMING3 DSI_REG(0x0068) | |
75 | #define DSI_CLK_TIMING DSI_REG(0x006C) | |
76 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) | |
77 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) | |
78 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) | |
79 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) | |
80 | #define DSI_VM_TIMING4 DSI_REG(0x0080) | |
81 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) | |
82 | #define DSI_VM_TIMING5 DSI_REG(0x0088) | |
83 | #define DSI_VM_TIMING6 DSI_REG(0x008C) | |
84 | #define DSI_VM_TIMING7 DSI_REG(0x0090) | |
85 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) | |
86 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) | |
87 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) | |
88 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) | |
89 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) | |
90 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) | |
91 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) | |
92 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) | |
93 | ||
94 | /* DSIPHY_SCP */ | |
95 | ||
96 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) | |
97 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) | |
98 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) | |
99 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) | |
0a0ee46b | 100 | #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) |
3de7a1dc TV |
101 | |
102 | /* DSI_PLL_CTRL_SCP */ | |
103 | ||
104 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) | |
105 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) | |
106 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) | |
107 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) | |
108 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) | |
109 | ||
a72b64b9 AT |
110 | #define REG_GET(dsidev, idx, start, end) \ |
111 | FLD_GET(dsi_read_reg(dsidev, idx), start, end) | |
3de7a1dc | 112 | |
a72b64b9 AT |
113 | #define REG_FLD_MOD(dsidev, idx, val, start, end) \ |
114 | dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end)) | |
3de7a1dc TV |
115 | |
116 | /* Global interrupts */ | |
117 | #define DSI_IRQ_VC0 (1 << 0) | |
118 | #define DSI_IRQ_VC1 (1 << 1) | |
119 | #define DSI_IRQ_VC2 (1 << 2) | |
120 | #define DSI_IRQ_VC3 (1 << 3) | |
121 | #define DSI_IRQ_WAKEUP (1 << 4) | |
122 | #define DSI_IRQ_RESYNC (1 << 5) | |
123 | #define DSI_IRQ_PLL_LOCK (1 << 7) | |
124 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) | |
125 | #define DSI_IRQ_PLL_RECALL (1 << 9) | |
126 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) | |
127 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) | |
128 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) | |
129 | #define DSI_IRQ_TE_TRIGGER (1 << 16) | |
130 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) | |
131 | #define DSI_IRQ_SYNC_LOST (1 << 18) | |
132 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) | |
133 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) | |
134 | #define DSI_IRQ_ERROR_MASK \ | |
135 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ | |
8af6ff01 | 136 | DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST) |
3de7a1dc TV |
137 | #define DSI_IRQ_CHANNEL_MASK 0xf |
138 | ||
139 | /* Virtual channel interrupts */ | |
140 | #define DSI_VC_IRQ_CS (1 << 0) | |
141 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) | |
142 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) | |
143 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) | |
144 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) | |
145 | #define DSI_VC_IRQ_BTA (1 << 5) | |
146 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) | |
147 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) | |
148 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) | |
149 | #define DSI_VC_IRQ_ERROR_MASK \ | |
150 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ | |
151 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ | |
152 | DSI_VC_IRQ_FIFO_TX_UDF) | |
153 | ||
154 | /* ComplexIO interrupts */ | |
155 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) | |
156 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) | |
157 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) | |
6705615e TV |
158 | #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) |
159 | #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) | |
3de7a1dc TV |
160 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) |
161 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) | |
162 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) | |
6705615e TV |
163 | #define DSI_CIO_IRQ_ERRESC4 (1 << 8) |
164 | #define DSI_CIO_IRQ_ERRESC5 (1 << 9) | |
3de7a1dc TV |
165 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) |
166 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) | |
167 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) | |
6705615e TV |
168 | #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) |
169 | #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) | |
3de7a1dc TV |
170 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) |
171 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) | |
172 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) | |
6705615e TV |
173 | #define DSI_CIO_IRQ_STATEULPS4 (1 << 18) |
174 | #define DSI_CIO_IRQ_STATEULPS5 (1 << 19) | |
3de7a1dc TV |
175 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) |
176 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) | |
177 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) | |
178 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) | |
179 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) | |
180 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) | |
6705615e TV |
181 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) |
182 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) | |
183 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) | |
184 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) | |
3de7a1dc TV |
185 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) |
186 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) | |
bbecb50b TV |
187 | #define DSI_CIO_IRQ_ERROR_MASK \ |
188 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ | |
6705615e TV |
189 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ |
190 | DSI_CIO_IRQ_ERRSYNCESC5 | \ | |
191 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ | |
192 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ | |
193 | DSI_CIO_IRQ_ERRESC5 | \ | |
194 | DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ | |
195 | DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ | |
196 | DSI_CIO_IRQ_ERRCONTROL5 | \ | |
bbecb50b TV |
197 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ |
198 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ | |
6705615e TV |
199 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ |
200 | DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ | |
201 | DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) | |
3de7a1dc | 202 | |
4ae2dddd TV |
203 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
204 | ||
205 | #define DSI_MAX_NR_ISRS 2 | |
739a7f46 TV |
206 | #define DSI_MAX_NR_LANES 5 |
207 | ||
208 | enum dsi_lane_function { | |
209 | DSI_LANE_UNUSED = 0, | |
210 | DSI_LANE_CLK, | |
211 | DSI_LANE_DATA1, | |
212 | DSI_LANE_DATA2, | |
213 | DSI_LANE_DATA3, | |
214 | DSI_LANE_DATA4, | |
215 | }; | |
216 | ||
217 | struct dsi_lane_config { | |
218 | enum dsi_lane_function function; | |
219 | u8 polarity; | |
220 | }; | |
4ae2dddd TV |
221 | |
222 | struct dsi_isr_data { | |
223 | omap_dsi_isr_t isr; | |
224 | void *arg; | |
225 | u32 mask; | |
226 | }; | |
227 | ||
3de7a1dc TV |
228 | enum fifo_size { |
229 | DSI_FIFO_SIZE_0 = 0, | |
230 | DSI_FIFO_SIZE_32 = 1, | |
231 | DSI_FIFO_SIZE_64 = 2, | |
232 | DSI_FIFO_SIZE_96 = 3, | |
233 | DSI_FIFO_SIZE_128 = 4, | |
234 | }; | |
235 | ||
d6049144 AT |
236 | enum dsi_vc_source { |
237 | DSI_VC_SOURCE_L4 = 0, | |
238 | DSI_VC_SOURCE_VP, | |
3de7a1dc TV |
239 | }; |
240 | ||
dfc0fd8d TV |
241 | struct dsi_irq_stats { |
242 | unsigned long last_reset; | |
243 | unsigned irq_count; | |
244 | unsigned dsi_irqs[32]; | |
245 | unsigned vc_irqs[4][32]; | |
246 | unsigned cio_irqs[32]; | |
247 | }; | |
248 | ||
4ae2dddd TV |
249 | struct dsi_isr_tables { |
250 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; | |
251 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; | |
252 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; | |
253 | }; | |
254 | ||
f1da39d9 | 255 | struct dsi_data { |
c8aac01b | 256 | struct platform_device *pdev; |
3de7a1dc | 257 | void __iomem *base; |
4fbafaf3 | 258 | |
11ee9606 TV |
259 | int module_id; |
260 | ||
affe360d | 261 | int irq; |
3de7a1dc | 262 | |
4fbafaf3 TV |
263 | struct clk *dss_clk; |
264 | struct clk *sys_clk; | |
265 | ||
3de7a1dc TV |
266 | struct dsi_clock_info current_cinfo; |
267 | ||
2a89dc15 | 268 | bool vdds_dsi_enabled; |
3de7a1dc TV |
269 | struct regulator *vdds_dsi_reg; |
270 | ||
271 | struct { | |
d6049144 | 272 | enum dsi_vc_source source; |
3de7a1dc TV |
273 | struct omap_dss_device *dssdev; |
274 | enum fifo_size fifo_size; | |
5ee3c144 | 275 | int vc_id; |
3de7a1dc TV |
276 | } vc[4]; |
277 | ||
278 | struct mutex lock; | |
b9eb5d7d | 279 | struct semaphore bus_lock; |
3de7a1dc TV |
280 | |
281 | unsigned pll_locked; | |
282 | ||
4ae2dddd TV |
283 | spinlock_t irq_lock; |
284 | struct dsi_isr_tables isr_tables; | |
285 | /* space for a copy used by the interrupt handler */ | |
286 | struct dsi_isr_tables isr_tables_copy; | |
287 | ||
18946f62 | 288 | int update_channel; |
5476e74a TV |
289 | #ifdef DEBUG |
290 | unsigned update_bytes; | |
291 | #endif | |
3de7a1dc | 292 | |
3de7a1dc | 293 | bool te_enabled; |
40885ab3 | 294 | bool ulps_enabled; |
3de7a1dc | 295 | |
18946f62 TV |
296 | void (*framedone_callback)(int, void *); |
297 | void *framedone_data; | |
298 | ||
299 | struct delayed_work framedone_timeout_work; | |
300 | ||
3de7a1dc TV |
301 | #ifdef DSI_CATCH_MISSING_TE |
302 | struct timer_list te_timer; | |
303 | #endif | |
304 | ||
305 | unsigned long cache_req_pck; | |
306 | unsigned long cache_clk_freq; | |
307 | struct dsi_clock_info cache_cinfo; | |
308 | ||
309 | u32 errors; | |
310 | spinlock_t errors_lock; | |
311 | #ifdef DEBUG | |
312 | ktime_t perf_setup_time; | |
313 | ktime_t perf_start_time; | |
3de7a1dc TV |
314 | #endif |
315 | int debug_read; | |
316 | int debug_write; | |
dfc0fd8d TV |
317 | |
318 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
319 | spinlock_t irq_stats_lock; | |
320 | struct dsi_irq_stats irq_stats; | |
321 | #endif | |
49641116 TA |
322 | /* DSI PLL Parameter Ranges */ |
323 | unsigned long regm_max, regn_max; | |
324 | unsigned long regm_dispc_max, regm_dsi_max; | |
325 | unsigned long fint_min, fint_max; | |
326 | unsigned long lpdiv_max; | |
24c1ae41 | 327 | |
d9820850 | 328 | unsigned num_lanes_supported; |
75d7247c | 329 | |
739a7f46 TV |
330 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; |
331 | unsigned num_lanes_used; | |
75d7247c | 332 | |
24c1ae41 | 333 | unsigned scp_clk_refcount; |
7d2572f8 AT |
334 | |
335 | struct dss_lcd_mgr_config mgr_config; | |
e67458a8 | 336 | struct omap_video_timings timings; |
02c3960b | 337 | enum omap_dss_dsi_pixel_format pix_fmt; |
f1da39d9 | 338 | }; |
3de7a1dc | 339 | |
2e868dbe AT |
340 | struct dsi_packet_sent_handler_data { |
341 | struct platform_device *dsidev; | |
342 | struct completion *completion; | |
343 | }; | |
344 | ||
a72b64b9 AT |
345 | static struct platform_device *dsi_pdev_map[MAX_NUM_DSI]; |
346 | ||
3de7a1dc | 347 | #ifdef DEBUG |
90ab5ee9 RR |
348 | static bool dsi_perf; |
349 | module_param(dsi_perf, bool, 0644); | |
3de7a1dc TV |
350 | #endif |
351 | ||
f1da39d9 AT |
352 | static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev) |
353 | { | |
354 | return dev_get_drvdata(&dsidev->dev); | |
355 | } | |
356 | ||
a72b64b9 AT |
357 | static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev) |
358 | { | |
359 | return dsi_pdev_map[dssdev->phy.dsi.module]; | |
360 | } | |
361 | ||
362 | struct platform_device *dsi_get_dsidev_from_id(int module) | |
363 | { | |
364 | return dsi_pdev_map[module]; | |
365 | } | |
366 | ||
367 | static inline void dsi_write_reg(struct platform_device *dsidev, | |
368 | const struct dsi_reg idx, u32 val) | |
3de7a1dc | 369 | { |
f1da39d9 AT |
370 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
371 | ||
372 | __raw_writel(val, dsi->base + idx.idx); | |
3de7a1dc TV |
373 | } |
374 | ||
a72b64b9 AT |
375 | static inline u32 dsi_read_reg(struct platform_device *dsidev, |
376 | const struct dsi_reg idx) | |
3de7a1dc | 377 | { |
f1da39d9 AT |
378 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
379 | ||
380 | return __raw_readl(dsi->base + idx.idx); | |
3de7a1dc TV |
381 | } |
382 | ||
1ffefe75 | 383 | void dsi_bus_lock(struct omap_dss_device *dssdev) |
3de7a1dc | 384 | { |
f1da39d9 AT |
385 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
386 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
387 | ||
388 | down(&dsi->bus_lock); | |
3de7a1dc TV |
389 | } |
390 | EXPORT_SYMBOL(dsi_bus_lock); | |
391 | ||
1ffefe75 | 392 | void dsi_bus_unlock(struct omap_dss_device *dssdev) |
3de7a1dc | 393 | { |
f1da39d9 AT |
394 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
395 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
396 | ||
397 | up(&dsi->bus_lock); | |
3de7a1dc TV |
398 | } |
399 | EXPORT_SYMBOL(dsi_bus_unlock); | |
400 | ||
a72b64b9 | 401 | static bool dsi_bus_is_locked(struct platform_device *dsidev) |
4f765023 | 402 | { |
f1da39d9 AT |
403 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
404 | ||
405 | return dsi->bus_lock.count == 0; | |
4f765023 TV |
406 | } |
407 | ||
f36a06e7 TV |
408 | static void dsi_completion_handler(void *data, u32 mask) |
409 | { | |
410 | complete((struct completion *)data); | |
411 | } | |
412 | ||
a72b64b9 AT |
413 | static inline int wait_for_bit_change(struct platform_device *dsidev, |
414 | const struct dsi_reg idx, int bitnum, int value) | |
3de7a1dc | 415 | { |
3b98409e TV |
416 | unsigned long timeout; |
417 | ktime_t wait; | |
418 | int t; | |
3de7a1dc | 419 | |
3b98409e TV |
420 | /* first busyloop to see if the bit changes right away */ |
421 | t = 100; | |
422 | while (t-- > 0) { | |
423 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) | |
424 | return value; | |
3de7a1dc TV |
425 | } |
426 | ||
3b98409e TV |
427 | /* then loop for 500ms, sleeping for 1ms in between */ |
428 | timeout = jiffies + msecs_to_jiffies(500); | |
429 | while (time_before(jiffies, timeout)) { | |
430 | if (REG_GET(dsidev, idx, bitnum, bitnum) == value) | |
431 | return value; | |
3de7a1dc | 432 | |
3b98409e TV |
433 | wait = ns_to_ktime(1000 * 1000); |
434 | set_current_state(TASK_UNINTERRUPTIBLE); | |
435 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
3de7a1dc TV |
436 | } |
437 | ||
3b98409e | 438 | return !value; |
3de7a1dc TV |
439 | } |
440 | ||
a3b3cc2b AT |
441 | u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) |
442 | { | |
443 | switch (fmt) { | |
444 | case OMAP_DSS_DSI_FMT_RGB888: | |
445 | case OMAP_DSS_DSI_FMT_RGB666: | |
446 | return 24; | |
447 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
448 | return 18; | |
449 | case OMAP_DSS_DSI_FMT_RGB565: | |
450 | return 16; | |
451 | default: | |
452 | BUG(); | |
c6eee968 | 453 | return 0; |
a3b3cc2b AT |
454 | } |
455 | } | |
456 | ||
3de7a1dc | 457 | #ifdef DEBUG |
a72b64b9 | 458 | static void dsi_perf_mark_setup(struct platform_device *dsidev) |
3de7a1dc | 459 | { |
f1da39d9 AT |
460 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
461 | dsi->perf_setup_time = ktime_get(); | |
3de7a1dc TV |
462 | } |
463 | ||
a72b64b9 | 464 | static void dsi_perf_mark_start(struct platform_device *dsidev) |
3de7a1dc | 465 | { |
f1da39d9 AT |
466 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
467 | dsi->perf_start_time = ktime_get(); | |
3de7a1dc TV |
468 | } |
469 | ||
a72b64b9 | 470 | static void dsi_perf_show(struct platform_device *dsidev, const char *name) |
3de7a1dc | 471 | { |
f1da39d9 | 472 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
473 | ktime_t t, setup_time, trans_time; |
474 | u32 total_bytes; | |
475 | u32 setup_us, trans_us, total_us; | |
476 | ||
477 | if (!dsi_perf) | |
478 | return; | |
479 | ||
3de7a1dc TV |
480 | t = ktime_get(); |
481 | ||
f1da39d9 | 482 | setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); |
3de7a1dc TV |
483 | setup_us = (u32)ktime_to_us(setup_time); |
484 | if (setup_us == 0) | |
485 | setup_us = 1; | |
486 | ||
f1da39d9 | 487 | trans_time = ktime_sub(t, dsi->perf_start_time); |
3de7a1dc TV |
488 | trans_us = (u32)ktime_to_us(trans_time); |
489 | if (trans_us == 0) | |
490 | trans_us = 1; | |
491 | ||
492 | total_us = setup_us + trans_us; | |
493 | ||
5476e74a | 494 | total_bytes = dsi->update_bytes; |
3de7a1dc | 495 | |
1bbb275e TV |
496 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
497 | "%u bytes, %u kbytes/sec\n", | |
498 | name, | |
499 | setup_us, | |
500 | trans_us, | |
501 | total_us, | |
502 | 1000*1000 / total_us, | |
503 | total_bytes, | |
504 | total_bytes * 1000 / total_us); | |
3de7a1dc TV |
505 | } |
506 | #else | |
4a9a5e39 TV |
507 | static inline void dsi_perf_mark_setup(struct platform_device *dsidev) |
508 | { | |
509 | } | |
510 | ||
511 | static inline void dsi_perf_mark_start(struct platform_device *dsidev) | |
512 | { | |
513 | } | |
514 | ||
515 | static inline void dsi_perf_show(struct platform_device *dsidev, | |
516 | const char *name) | |
517 | { | |
518 | } | |
3de7a1dc TV |
519 | #endif |
520 | ||
521 | static void print_irq_status(u32 status) | |
522 | { | |
d80d499e TV |
523 | if (status == 0) |
524 | return; | |
525 | ||
3de7a1dc TV |
526 | #ifndef VERBOSE_IRQ |
527 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) | |
528 | return; | |
529 | #endif | |
530 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); | |
531 | ||
532 | #define PIS(x) \ | |
533 | if (status & DSI_IRQ_##x) \ | |
534 | printk(#x " "); | |
535 | #ifdef VERBOSE_IRQ | |
536 | PIS(VC0); | |
537 | PIS(VC1); | |
538 | PIS(VC2); | |
539 | PIS(VC3); | |
540 | #endif | |
541 | PIS(WAKEUP); | |
542 | PIS(RESYNC); | |
543 | PIS(PLL_LOCK); | |
544 | PIS(PLL_UNLOCK); | |
545 | PIS(PLL_RECALL); | |
546 | PIS(COMPLEXIO_ERR); | |
547 | PIS(HS_TX_TIMEOUT); | |
548 | PIS(LP_RX_TIMEOUT); | |
549 | PIS(TE_TRIGGER); | |
550 | PIS(ACK_TRIGGER); | |
551 | PIS(SYNC_LOST); | |
552 | PIS(LDO_POWER_GOOD); | |
553 | PIS(TA_TIMEOUT); | |
554 | #undef PIS | |
555 | ||
556 | printk("\n"); | |
557 | } | |
558 | ||
559 | static void print_irq_status_vc(int channel, u32 status) | |
560 | { | |
d80d499e TV |
561 | if (status == 0) |
562 | return; | |
563 | ||
3de7a1dc TV |
564 | #ifndef VERBOSE_IRQ |
565 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) | |
566 | return; | |
567 | #endif | |
568 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); | |
569 | ||
570 | #define PIS(x) \ | |
571 | if (status & DSI_VC_IRQ_##x) \ | |
572 | printk(#x " "); | |
573 | PIS(CS); | |
574 | PIS(ECC_CORR); | |
575 | #ifdef VERBOSE_IRQ | |
576 | PIS(PACKET_SENT); | |
577 | #endif | |
578 | PIS(FIFO_TX_OVF); | |
579 | PIS(FIFO_RX_OVF); | |
580 | PIS(BTA); | |
581 | PIS(ECC_NO_CORR); | |
582 | PIS(FIFO_TX_UDF); | |
583 | PIS(PP_BUSY_CHANGE); | |
584 | #undef PIS | |
585 | printk("\n"); | |
586 | } | |
587 | ||
588 | static void print_irq_status_cio(u32 status) | |
589 | { | |
d80d499e TV |
590 | if (status == 0) |
591 | return; | |
592 | ||
3de7a1dc TV |
593 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
594 | ||
595 | #define PIS(x) \ | |
596 | if (status & DSI_CIO_IRQ_##x) \ | |
597 | printk(#x " "); | |
598 | PIS(ERRSYNCESC1); | |
599 | PIS(ERRSYNCESC2); | |
600 | PIS(ERRSYNCESC3); | |
601 | PIS(ERRESC1); | |
602 | PIS(ERRESC2); | |
603 | PIS(ERRESC3); | |
604 | PIS(ERRCONTROL1); | |
605 | PIS(ERRCONTROL2); | |
606 | PIS(ERRCONTROL3); | |
607 | PIS(STATEULPS1); | |
608 | PIS(STATEULPS2); | |
609 | PIS(STATEULPS3); | |
610 | PIS(ERRCONTENTIONLP0_1); | |
611 | PIS(ERRCONTENTIONLP1_1); | |
612 | PIS(ERRCONTENTIONLP0_2); | |
613 | PIS(ERRCONTENTIONLP1_2); | |
614 | PIS(ERRCONTENTIONLP0_3); | |
615 | PIS(ERRCONTENTIONLP1_3); | |
616 | PIS(ULPSACTIVENOT_ALL0); | |
617 | PIS(ULPSACTIVENOT_ALL1); | |
618 | #undef PIS | |
619 | ||
620 | printk("\n"); | |
621 | } | |
622 | ||
69b281a6 | 623 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
a72b64b9 AT |
624 | static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus, |
625 | u32 *vcstatus, u32 ciostatus) | |
3de7a1dc | 626 | { |
f1da39d9 | 627 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
628 | int i; |
629 | ||
f1da39d9 | 630 | spin_lock(&dsi->irq_stats_lock); |
69b281a6 | 631 | |
f1da39d9 AT |
632 | dsi->irq_stats.irq_count++; |
633 | dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); | |
69b281a6 TV |
634 | |
635 | for (i = 0; i < 4; ++i) | |
f1da39d9 | 636 | dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); |
69b281a6 | 637 | |
f1da39d9 | 638 | dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); |
69b281a6 | 639 | |
f1da39d9 | 640 | spin_unlock(&dsi->irq_stats_lock); |
69b281a6 TV |
641 | } |
642 | #else | |
a72b64b9 | 643 | #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus) |
dfc0fd8d TV |
644 | #endif |
645 | ||
69b281a6 TV |
646 | static int debug_irq; |
647 | ||
a72b64b9 AT |
648 | static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus, |
649 | u32 *vcstatus, u32 ciostatus) | |
69b281a6 | 650 | { |
f1da39d9 | 651 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
69b281a6 TV |
652 | int i; |
653 | ||
3de7a1dc TV |
654 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
655 | DSSERR("DSI error, irqstatus %x\n", irqstatus); | |
656 | print_irq_status(irqstatus); | |
f1da39d9 AT |
657 | spin_lock(&dsi->errors_lock); |
658 | dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; | |
659 | spin_unlock(&dsi->errors_lock); | |
3de7a1dc TV |
660 | } else if (debug_irq) { |
661 | print_irq_status(irqstatus); | |
662 | } | |
663 | ||
3de7a1dc | 664 | for (i = 0; i < 4; ++i) { |
69b281a6 TV |
665 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
666 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", | |
667 | i, vcstatus[i]); | |
668 | print_irq_status_vc(i, vcstatus[i]); | |
669 | } else if (debug_irq) { | |
670 | print_irq_status_vc(i, vcstatus[i]); | |
671 | } | |
672 | } | |
3de7a1dc | 673 | |
69b281a6 TV |
674 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
675 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); | |
676 | print_irq_status_cio(ciostatus); | |
677 | } else if (debug_irq) { | |
678 | print_irq_status_cio(ciostatus); | |
679 | } | |
680 | } | |
3de7a1dc | 681 | |
4ae2dddd TV |
682 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
683 | unsigned isr_array_size, u32 irqstatus) | |
684 | { | |
685 | struct dsi_isr_data *isr_data; | |
686 | int i; | |
687 | ||
688 | for (i = 0; i < isr_array_size; i++) { | |
689 | isr_data = &isr_array[i]; | |
690 | if (isr_data->isr && isr_data->mask & irqstatus) | |
691 | isr_data->isr(isr_data->arg, irqstatus); | |
692 | } | |
693 | } | |
694 | ||
695 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, | |
696 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
697 | { | |
698 | int i; | |
699 | ||
700 | dsi_call_isrs(isr_tables->isr_table, | |
701 | ARRAY_SIZE(isr_tables->isr_table), | |
702 | irqstatus); | |
703 | ||
704 | for (i = 0; i < 4; ++i) { | |
705 | if (vcstatus[i] == 0) | |
706 | continue; | |
707 | dsi_call_isrs(isr_tables->isr_table_vc[i], | |
708 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), | |
709 | vcstatus[i]); | |
710 | } | |
711 | ||
712 | if (ciostatus != 0) | |
713 | dsi_call_isrs(isr_tables->isr_table_cio, | |
714 | ARRAY_SIZE(isr_tables->isr_table_cio), | |
715 | ciostatus); | |
716 | } | |
717 | ||
69b281a6 TV |
718 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
719 | { | |
a72b64b9 | 720 | struct platform_device *dsidev; |
f1da39d9 | 721 | struct dsi_data *dsi; |
69b281a6 TV |
722 | u32 irqstatus, vcstatus[4], ciostatus; |
723 | int i; | |
dfc0fd8d | 724 | |
a72b64b9 | 725 | dsidev = (struct platform_device *) arg; |
f1da39d9 | 726 | dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 727 | |
f1da39d9 | 728 | spin_lock(&dsi->irq_lock); |
4ae2dddd | 729 | |
a72b64b9 | 730 | irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS); |
3de7a1dc | 731 | |
69b281a6 | 732 | /* IRQ is not for us */ |
4ae2dddd | 733 | if (!irqstatus) { |
f1da39d9 | 734 | spin_unlock(&dsi->irq_lock); |
69b281a6 | 735 | return IRQ_NONE; |
4ae2dddd | 736 | } |
ab83b14c | 737 | |
a72b64b9 | 738 | dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
69b281a6 | 739 | /* flush posted write */ |
a72b64b9 | 740 | dsi_read_reg(dsidev, DSI_IRQSTATUS); |
69b281a6 TV |
741 | |
742 | for (i = 0; i < 4; ++i) { | |
743 | if ((irqstatus & (1 << i)) == 0) { | |
744 | vcstatus[i] = 0; | |
745 | continue; | |
3de7a1dc TV |
746 | } |
747 | ||
a72b64b9 | 748 | vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
69b281a6 | 749 | |
a72b64b9 | 750 | dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]); |
3de7a1dc | 751 | /* flush posted write */ |
a72b64b9 | 752 | dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i)); |
3de7a1dc TV |
753 | } |
754 | ||
755 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { | |
a72b64b9 | 756 | ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
3de7a1dc | 757 | |
a72b64b9 | 758 | dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); |
3de7a1dc | 759 | /* flush posted write */ |
a72b64b9 | 760 | dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS); |
69b281a6 TV |
761 | } else { |
762 | ciostatus = 0; | |
763 | } | |
3de7a1dc | 764 | |
69b281a6 TV |
765 | #ifdef DSI_CATCH_MISSING_TE |
766 | if (irqstatus & DSI_IRQ_TE_TRIGGER) | |
f1da39d9 | 767 | del_timer(&dsi->te_timer); |
69b281a6 TV |
768 | #endif |
769 | ||
4ae2dddd TV |
770 | /* make a copy and unlock, so that isrs can unregister |
771 | * themselves */ | |
f1da39d9 AT |
772 | memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, |
773 | sizeof(dsi->isr_tables)); | |
4ae2dddd | 774 | |
f1da39d9 | 775 | spin_unlock(&dsi->irq_lock); |
4ae2dddd | 776 | |
f1da39d9 | 777 | dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); |
4ae2dddd | 778 | |
a72b64b9 | 779 | dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus); |
69b281a6 | 780 | |
a72b64b9 | 781 | dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus); |
dfc0fd8d | 782 | |
affe360d | 783 | return IRQ_HANDLED; |
3de7a1dc TV |
784 | } |
785 | ||
f1da39d9 | 786 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 AT |
787 | static void _omap_dsi_configure_irqs(struct platform_device *dsidev, |
788 | struct dsi_isr_data *isr_array, | |
4ae2dddd TV |
789 | unsigned isr_array_size, u32 default_mask, |
790 | const struct dsi_reg enable_reg, | |
791 | const struct dsi_reg status_reg) | |
3de7a1dc | 792 | { |
4ae2dddd TV |
793 | struct dsi_isr_data *isr_data; |
794 | u32 mask; | |
795 | u32 old_mask; | |
3de7a1dc TV |
796 | int i; |
797 | ||
4ae2dddd | 798 | mask = default_mask; |
3de7a1dc | 799 | |
4ae2dddd TV |
800 | for (i = 0; i < isr_array_size; i++) { |
801 | isr_data = &isr_array[i]; | |
3de7a1dc | 802 | |
4ae2dddd TV |
803 | if (isr_data->isr == NULL) |
804 | continue; | |
805 | ||
806 | mask |= isr_data->mask; | |
3de7a1dc TV |
807 | } |
808 | ||
a72b64b9 | 809 | old_mask = dsi_read_reg(dsidev, enable_reg); |
4ae2dddd | 810 | /* clear the irqstatus for newly enabled irqs */ |
a72b64b9 AT |
811 | dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask); |
812 | dsi_write_reg(dsidev, enable_reg, mask); | |
4ae2dddd TV |
813 | |
814 | /* flush posted writes */ | |
a72b64b9 AT |
815 | dsi_read_reg(dsidev, enable_reg); |
816 | dsi_read_reg(dsidev, status_reg); | |
4ae2dddd | 817 | } |
3de7a1dc | 818 | |
f1da39d9 | 819 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 820 | static void _omap_dsi_set_irqs(struct platform_device *dsidev) |
4ae2dddd | 821 | { |
f1da39d9 | 822 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd | 823 | u32 mask = DSI_IRQ_ERROR_MASK; |
3de7a1dc | 824 | #ifdef DSI_CATCH_MISSING_TE |
4ae2dddd | 825 | mask |= DSI_IRQ_TE_TRIGGER; |
3de7a1dc | 826 | #endif |
f1da39d9 AT |
827 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table, |
828 | ARRAY_SIZE(dsi->isr_tables.isr_table), mask, | |
4ae2dddd TV |
829 | DSI_IRQENABLE, DSI_IRQSTATUS); |
830 | } | |
3de7a1dc | 831 | |
f1da39d9 | 832 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 833 | static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc) |
4ae2dddd | 834 | { |
f1da39d9 AT |
835 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
836 | ||
837 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc], | |
838 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), | |
4ae2dddd TV |
839 | DSI_VC_IRQ_ERROR_MASK, |
840 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); | |
841 | } | |
842 | ||
f1da39d9 | 843 | /* dsi->irq_lock has to be locked by the caller */ |
a72b64b9 | 844 | static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev) |
4ae2dddd | 845 | { |
f1da39d9 AT |
846 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
847 | ||
848 | _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio, | |
849 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio), | |
4ae2dddd TV |
850 | DSI_CIO_IRQ_ERROR_MASK, |
851 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); | |
852 | } | |
853 | ||
a72b64b9 | 854 | static void _dsi_initialize_irq(struct platform_device *dsidev) |
4ae2dddd | 855 | { |
f1da39d9 | 856 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
857 | unsigned long flags; |
858 | int vc; | |
859 | ||
f1da39d9 | 860 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 861 | |
f1da39d9 | 862 | memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); |
4ae2dddd | 863 | |
a72b64b9 | 864 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 865 | for (vc = 0; vc < 4; ++vc) |
a72b64b9 AT |
866 | _omap_dsi_set_irqs_vc(dsidev, vc); |
867 | _omap_dsi_set_irqs_cio(dsidev); | |
4ae2dddd | 868 | |
f1da39d9 | 869 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd | 870 | } |
3de7a1dc | 871 | |
4ae2dddd TV |
872 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
873 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
874 | { | |
875 | struct dsi_isr_data *isr_data; | |
876 | int free_idx; | |
877 | int i; | |
878 | ||
879 | BUG_ON(isr == NULL); | |
880 | ||
881 | /* check for duplicate entry and find a free slot */ | |
882 | free_idx = -1; | |
883 | for (i = 0; i < isr_array_size; i++) { | |
884 | isr_data = &isr_array[i]; | |
885 | ||
886 | if (isr_data->isr == isr && isr_data->arg == arg && | |
887 | isr_data->mask == mask) { | |
888 | return -EINVAL; | |
889 | } | |
890 | ||
891 | if (isr_data->isr == NULL && free_idx == -1) | |
892 | free_idx = i; | |
893 | } | |
894 | ||
895 | if (free_idx == -1) | |
896 | return -EBUSY; | |
897 | ||
898 | isr_data = &isr_array[free_idx]; | |
899 | isr_data->isr = isr; | |
900 | isr_data->arg = arg; | |
901 | isr_data->mask = mask; | |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, | |
907 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
908 | { | |
909 | struct dsi_isr_data *isr_data; | |
910 | int i; | |
911 | ||
912 | for (i = 0; i < isr_array_size; i++) { | |
913 | isr_data = &isr_array[i]; | |
914 | if (isr_data->isr != isr || isr_data->arg != arg || | |
915 | isr_data->mask != mask) | |
916 | continue; | |
917 | ||
918 | isr_data->isr = NULL; | |
919 | isr_data->arg = NULL; | |
920 | isr_data->mask = 0; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
925 | return -EINVAL; | |
926 | } | |
927 | ||
a72b64b9 AT |
928 | static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr, |
929 | void *arg, u32 mask) | |
4ae2dddd | 930 | { |
f1da39d9 | 931 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
932 | unsigned long flags; |
933 | int r; | |
934 | ||
f1da39d9 | 935 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 936 | |
f1da39d9 AT |
937 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
938 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
939 | |
940 | if (r == 0) | |
a72b64b9 | 941 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 942 | |
f1da39d9 | 943 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
944 | |
945 | return r; | |
946 | } | |
947 | ||
a72b64b9 AT |
948 | static int dsi_unregister_isr(struct platform_device *dsidev, |
949 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 950 | { |
f1da39d9 | 951 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
952 | unsigned long flags; |
953 | int r; | |
954 | ||
f1da39d9 | 955 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 956 | |
f1da39d9 AT |
957 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, |
958 | ARRAY_SIZE(dsi->isr_tables.isr_table)); | |
4ae2dddd TV |
959 | |
960 | if (r == 0) | |
a72b64b9 | 961 | _omap_dsi_set_irqs(dsidev); |
4ae2dddd | 962 | |
f1da39d9 | 963 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
964 | |
965 | return r; | |
966 | } | |
967 | ||
a72b64b9 AT |
968 | static int dsi_register_isr_vc(struct platform_device *dsidev, int channel, |
969 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 970 | { |
f1da39d9 | 971 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
972 | unsigned long flags; |
973 | int r; | |
974 | ||
f1da39d9 | 975 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
976 | |
977 | r = _dsi_register_isr(isr, arg, mask, | |
f1da39d9 AT |
978 | dsi->isr_tables.isr_table_vc[channel], |
979 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
980 | |
981 | if (r == 0) | |
a72b64b9 | 982 | _omap_dsi_set_irqs_vc(dsidev, channel); |
4ae2dddd | 983 | |
f1da39d9 | 984 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
985 | |
986 | return r; | |
987 | } | |
988 | ||
a72b64b9 AT |
989 | static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel, |
990 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 991 | { |
f1da39d9 | 992 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
993 | unsigned long flags; |
994 | int r; | |
995 | ||
f1da39d9 | 996 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd TV |
997 | |
998 | r = _dsi_unregister_isr(isr, arg, mask, | |
f1da39d9 AT |
999 | dsi->isr_tables.isr_table_vc[channel], |
1000 | ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); | |
4ae2dddd TV |
1001 | |
1002 | if (r == 0) | |
a72b64b9 | 1003 | _omap_dsi_set_irqs_vc(dsidev, channel); |
4ae2dddd | 1004 | |
f1da39d9 | 1005 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1006 | |
1007 | return r; | |
1008 | } | |
1009 | ||
a72b64b9 AT |
1010 | static int dsi_register_isr_cio(struct platform_device *dsidev, |
1011 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1012 | { |
f1da39d9 | 1013 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1014 | unsigned long flags; |
1015 | int r; | |
1016 | ||
f1da39d9 | 1017 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1018 | |
f1da39d9 AT |
1019 | r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1020 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1021 | |
1022 | if (r == 0) | |
a72b64b9 | 1023 | _omap_dsi_set_irqs_cio(dsidev); |
4ae2dddd | 1024 | |
f1da39d9 | 1025 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1026 | |
1027 | return r; | |
1028 | } | |
1029 | ||
a72b64b9 AT |
1030 | static int dsi_unregister_isr_cio(struct platform_device *dsidev, |
1031 | omap_dsi_isr_t isr, void *arg, u32 mask) | |
4ae2dddd | 1032 | { |
f1da39d9 | 1033 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4ae2dddd TV |
1034 | unsigned long flags; |
1035 | int r; | |
1036 | ||
f1da39d9 | 1037 | spin_lock_irqsave(&dsi->irq_lock, flags); |
4ae2dddd | 1038 | |
f1da39d9 AT |
1039 | r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, |
1040 | ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); | |
4ae2dddd TV |
1041 | |
1042 | if (r == 0) | |
a72b64b9 | 1043 | _omap_dsi_set_irqs_cio(dsidev); |
4ae2dddd | 1044 | |
f1da39d9 | 1045 | spin_unlock_irqrestore(&dsi->irq_lock, flags); |
4ae2dddd TV |
1046 | |
1047 | return r; | |
3de7a1dc TV |
1048 | } |
1049 | ||
a72b64b9 | 1050 | static u32 dsi_get_errors(struct platform_device *dsidev) |
3de7a1dc | 1051 | { |
f1da39d9 | 1052 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1053 | unsigned long flags; |
1054 | u32 e; | |
f1da39d9 AT |
1055 | spin_lock_irqsave(&dsi->errors_lock, flags); |
1056 | e = dsi->errors; | |
1057 | dsi->errors = 0; | |
1058 | spin_unlock_irqrestore(&dsi->errors_lock, flags); | |
3de7a1dc TV |
1059 | return e; |
1060 | } | |
1061 | ||
4fbafaf3 | 1062 | int dsi_runtime_get(struct platform_device *dsidev) |
3de7a1dc | 1063 | { |
4fbafaf3 TV |
1064 | int r; |
1065 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1066 | ||
1067 | DSSDBG("dsi_runtime_get\n"); | |
1068 | ||
1069 | r = pm_runtime_get_sync(&dsi->pdev->dev); | |
1070 | WARN_ON(r < 0); | |
1071 | return r < 0 ? r : 0; | |
1072 | } | |
1073 | ||
1074 | void dsi_runtime_put(struct platform_device *dsidev) | |
1075 | { | |
1076 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
1077 | int r; | |
1078 | ||
1079 | DSSDBG("dsi_runtime_put\n"); | |
1080 | ||
0eaf9f52 | 1081 | r = pm_runtime_put_sync(&dsi->pdev->dev); |
5be3aebd | 1082 | WARN_ON(r < 0 && r != -ENOSYS); |
3de7a1dc TV |
1083 | } |
1084 | ||
1085 | /* source clock for DSI PLL. this could also be PCLKFREE */ | |
a72b64b9 AT |
1086 | static inline void dsi_enable_pll_clock(struct platform_device *dsidev, |
1087 | bool enable) | |
3de7a1dc | 1088 | { |
f1da39d9 AT |
1089 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1090 | ||
3de7a1dc | 1091 | if (enable) |
f11766d1 | 1092 | clk_prepare_enable(dsi->sys_clk); |
3de7a1dc | 1093 | else |
f11766d1 | 1094 | clk_disable_unprepare(dsi->sys_clk); |
3de7a1dc | 1095 | |
f1da39d9 | 1096 | if (enable && dsi->pll_locked) { |
a72b64b9 | 1097 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) |
3de7a1dc TV |
1098 | DSSERR("cannot lock PLL when enabling clocks\n"); |
1099 | } | |
1100 | } | |
1101 | ||
1102 | #ifdef DEBUG | |
a72b64b9 | 1103 | static void _dsi_print_reset_status(struct platform_device *dsidev) |
3de7a1dc TV |
1104 | { |
1105 | u32 l; | |
c335cbf9 | 1106 | int b0, b1, b2; |
3de7a1dc TV |
1107 | |
1108 | if (!dss_debug) | |
1109 | return; | |
1110 | ||
1111 | /* A dummy read using the SCP interface to any DSIPHY register is | |
1112 | * required after DSIPHY reset to complete the reset of the DSI complex | |
1113 | * I/O. */ | |
a72b64b9 | 1114 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
3de7a1dc TV |
1115 | |
1116 | printk(KERN_DEBUG "DSI resets: "); | |
1117 | ||
a72b64b9 | 1118 | l = dsi_read_reg(dsidev, DSI_PLL_STATUS); |
3de7a1dc TV |
1119 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); |
1120 | ||
a72b64b9 | 1121 | l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
3de7a1dc TV |
1122 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); |
1123 | ||
c335cbf9 TV |
1124 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) { |
1125 | b0 = 28; | |
1126 | b1 = 27; | |
1127 | b2 = 26; | |
1128 | } else { | |
1129 | b0 = 24; | |
1130 | b1 = 25; | |
1131 | b2 = 26; | |
1132 | } | |
1133 | ||
a72b64b9 | 1134 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
c335cbf9 TV |
1135 | printk("PHY (%x%x%x, %d, %d, %d)\n", |
1136 | FLD_GET(l, b0, b0), | |
1137 | FLD_GET(l, b1, b1), | |
1138 | FLD_GET(l, b2, b2), | |
3de7a1dc TV |
1139 | FLD_GET(l, 29, 29), |
1140 | FLD_GET(l, 30, 30), | |
1141 | FLD_GET(l, 31, 31)); | |
1142 | } | |
1143 | #else | |
a72b64b9 | 1144 | #define _dsi_print_reset_status(x) |
3de7a1dc TV |
1145 | #endif |
1146 | ||
a72b64b9 | 1147 | static inline int dsi_if_enable(struct platform_device *dsidev, bool enable) |
3de7a1dc TV |
1148 | { |
1149 | DSSDBG("dsi_if_enable(%d)\n", enable); | |
1150 | ||
1151 | enable = enable ? 1 : 0; | |
a72b64b9 | 1152 | REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ |
3de7a1dc | 1153 | |
a72b64b9 | 1154 | if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) { |
3de7a1dc TV |
1155 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); |
1156 | return -EIO; | |
1157 | } | |
1158 | ||
1159 | return 0; | |
1160 | } | |
1161 | ||
a72b64b9 | 1162 | unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev) |
3de7a1dc | 1163 | { |
f1da39d9 AT |
1164 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1165 | ||
1166 | return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk; | |
3de7a1dc TV |
1167 | } |
1168 | ||
a72b64b9 | 1169 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev) |
3de7a1dc | 1170 | { |
f1da39d9 AT |
1171 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1172 | ||
1173 | return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk; | |
3de7a1dc TV |
1174 | } |
1175 | ||
a72b64b9 | 1176 | static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev) |
3de7a1dc | 1177 | { |
f1da39d9 AT |
1178 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1179 | ||
1180 | return dsi->current_cinfo.clkin4ddr / 16; | |
3de7a1dc TV |
1181 | } |
1182 | ||
a72b64b9 | 1183 | static unsigned long dsi_fclk_rate(struct platform_device *dsidev) |
3de7a1dc TV |
1184 | { |
1185 | unsigned long r; | |
4fbafaf3 | 1186 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc | 1187 | |
11ee9606 | 1188 | if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) { |
1bb47835 | 1189 | /* DSI FCLK source is DSS_CLK_FCK */ |
4fbafaf3 | 1190 | r = clk_get_rate(dsi->dss_clk); |
3de7a1dc | 1191 | } else { |
1bb47835 | 1192 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
a72b64b9 | 1193 | r = dsi_get_pll_hsdiv_dsi_rate(dsidev); |
3de7a1dc TV |
1194 | } |
1195 | ||
1196 | return r; | |
1197 | } | |
1198 | ||
1199 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) | |
1200 | { | |
a72b64b9 | 1201 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 1202 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1203 | unsigned long dsi_fclk; |
1204 | unsigned lp_clk_div; | |
1205 | unsigned long lp_clk; | |
1206 | ||
c6940a3d | 1207 | lp_clk_div = dssdev->clocks.dsi.lp_clk_div; |
3de7a1dc | 1208 | |
f1da39d9 | 1209 | if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max) |
3de7a1dc TV |
1210 | return -EINVAL; |
1211 | ||
a72b64b9 | 1212 | dsi_fclk = dsi_fclk_rate(dsidev); |
3de7a1dc TV |
1213 | |
1214 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1215 | ||
1216 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); | |
f1da39d9 AT |
1217 | dsi->current_cinfo.lp_clk = lp_clk; |
1218 | dsi->current_cinfo.lp_clk_div = lp_clk_div; | |
3de7a1dc | 1219 | |
a72b64b9 AT |
1220 | /* LP_CLK_DIVISOR */ |
1221 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); | |
3de7a1dc | 1222 | |
a72b64b9 AT |
1223 | /* LP_RX_SYNCHRO_ENABLE */ |
1224 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); | |
3de7a1dc TV |
1225 | |
1226 | return 0; | |
1227 | } | |
1228 | ||
a72b64b9 | 1229 | static void dsi_enable_scp_clk(struct platform_device *dsidev) |
24c1ae41 | 1230 | { |
f1da39d9 AT |
1231 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1232 | ||
1233 | if (dsi->scp_clk_refcount++ == 0) | |
a72b64b9 | 1234 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 TV |
1235 | } |
1236 | ||
a72b64b9 | 1237 | static void dsi_disable_scp_clk(struct platform_device *dsidev) |
24c1ae41 | 1238 | { |
f1da39d9 AT |
1239 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1240 | ||
1241 | WARN_ON(dsi->scp_clk_refcount == 0); | |
1242 | if (--dsi->scp_clk_refcount == 0) | |
a72b64b9 | 1243 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ |
24c1ae41 | 1244 | } |
3de7a1dc TV |
1245 | |
1246 | enum dsi_pll_power_state { | |
1247 | DSI_PLL_POWER_OFF = 0x0, | |
1248 | DSI_PLL_POWER_ON_HSCLK = 0x1, | |
1249 | DSI_PLL_POWER_ON_ALL = 0x2, | |
1250 | DSI_PLL_POWER_ON_DIV = 0x3, | |
1251 | }; | |
1252 | ||
a72b64b9 AT |
1253 | static int dsi_pll_power(struct platform_device *dsidev, |
1254 | enum dsi_pll_power_state state) | |
3de7a1dc TV |
1255 | { |
1256 | int t = 0; | |
1257 | ||
c94dfe05 TV |
1258 | /* DSI-PLL power command 0x3 is not working */ |
1259 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && | |
1260 | state == DSI_PLL_POWER_ON_DIV) | |
1261 | state = DSI_PLL_POWER_ON_ALL; | |
1262 | ||
a72b64b9 AT |
1263 | /* PLL_PWR_CMD */ |
1264 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); | |
3de7a1dc TV |
1265 | |
1266 | /* PLL_PWR_STATUS */ | |
a72b64b9 | 1267 | while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) { |
24be78b3 | 1268 | if (++t > 1000) { |
3de7a1dc TV |
1269 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
1270 | state); | |
1271 | return -ENODEV; | |
1272 | } | |
24be78b3 | 1273 | udelay(1); |
3de7a1dc TV |
1274 | } |
1275 | ||
1276 | return 0; | |
1277 | } | |
1278 | ||
1279 | /* calculate clock rates using dividers in cinfo */ | |
b6e695ab | 1280 | static int dsi_calc_clock_rates(struct platform_device *dsidev, |
ff1b2cde | 1281 | struct dsi_clock_info *cinfo) |
3de7a1dc | 1282 | { |
f1da39d9 AT |
1283 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1284 | ||
1285 | if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max) | |
3de7a1dc TV |
1286 | return -EINVAL; |
1287 | ||
f1da39d9 | 1288 | if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max) |
3de7a1dc TV |
1289 | return -EINVAL; |
1290 | ||
f1da39d9 | 1291 | if (cinfo->regm_dispc > dsi->regm_dispc_max) |
3de7a1dc TV |
1292 | return -EINVAL; |
1293 | ||
f1da39d9 | 1294 | if (cinfo->regm_dsi > dsi->regm_dsi_max) |
3de7a1dc TV |
1295 | return -EINVAL; |
1296 | ||
b6e695ab TV |
1297 | cinfo->clkin = clk_get_rate(dsi->sys_clk); |
1298 | cinfo->fint = cinfo->clkin / cinfo->regn; | |
3de7a1dc | 1299 | |
f1da39d9 | 1300 | if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min) |
3de7a1dc TV |
1301 | return -EINVAL; |
1302 | ||
1303 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; | |
1304 | ||
1305 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) | |
1306 | return -EINVAL; | |
1307 | ||
1bb47835 AT |
1308 | if (cinfo->regm_dispc > 0) |
1309 | cinfo->dsi_pll_hsdiv_dispc_clk = | |
1310 | cinfo->clkin4ddr / cinfo->regm_dispc; | |
3de7a1dc | 1311 | else |
1bb47835 | 1312 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
3de7a1dc | 1313 | |
1bb47835 AT |
1314 | if (cinfo->regm_dsi > 0) |
1315 | cinfo->dsi_pll_hsdiv_dsi_clk = | |
1316 | cinfo->clkin4ddr / cinfo->regm_dsi; | |
3de7a1dc | 1317 | else |
1bb47835 | 1318 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
3de7a1dc TV |
1319 | |
1320 | return 0; | |
1321 | } | |
1322 | ||
6d523e7b | 1323 | int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, |
a72b64b9 | 1324 | unsigned long req_pck, struct dsi_clock_info *dsi_cinfo, |
3de7a1dc TV |
1325 | struct dispc_clock_info *dispc_cinfo) |
1326 | { | |
f1da39d9 | 1327 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1328 | struct dsi_clock_info cur, best; |
1329 | struct dispc_clock_info best_dispc; | |
1330 | int min_fck_per_pck; | |
1331 | int match = 0; | |
1bb47835 | 1332 | unsigned long dss_sys_clk, max_dss_fck; |
3de7a1dc | 1333 | |
4fbafaf3 | 1334 | dss_sys_clk = clk_get_rate(dsi->sys_clk); |
3de7a1dc | 1335 | |
31ef8237 | 1336 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
819d807c | 1337 | |
f1da39d9 AT |
1338 | if (req_pck == dsi->cache_req_pck && |
1339 | dsi->cache_cinfo.clkin == dss_sys_clk) { | |
3de7a1dc | 1340 | DSSDBG("DSI clock info found from cache\n"); |
f1da39d9 | 1341 | *dsi_cinfo = dsi->cache_cinfo; |
6d523e7b AT |
1342 | dispc_find_clk_divs(req_pck, dsi_cinfo->dsi_pll_hsdiv_dispc_clk, |
1343 | dispc_cinfo); | |
3de7a1dc TV |
1344 | return 0; |
1345 | } | |
1346 | ||
1347 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
1348 | ||
1349 | if (min_fck_per_pck && | |
819d807c | 1350 | req_pck * min_fck_per_pck > max_dss_fck) { |
3de7a1dc TV |
1351 | DSSERR("Requested pixel clock not possible with the current " |
1352 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " | |
1353 | "the constraint off.\n"); | |
1354 | min_fck_per_pck = 0; | |
1355 | } | |
1356 | ||
1357 | DSSDBG("dsi_pll_calc\n"); | |
1358 | ||
1359 | retry: | |
1360 | memset(&best, 0, sizeof(best)); | |
1361 | memset(&best_dispc, 0, sizeof(best_dispc)); | |
1362 | ||
1363 | memset(&cur, 0, sizeof(cur)); | |
1bb47835 | 1364 | cur.clkin = dss_sys_clk; |
3de7a1dc | 1365 | |
b6e695ab | 1366 | /* 0.75MHz < Fint = clkin / regn < 2.1MHz */ |
3de7a1dc | 1367 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ |
f1da39d9 | 1368 | for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) { |
b6e695ab | 1369 | cur.fint = cur.clkin / cur.regn; |
3de7a1dc | 1370 | |
f1da39d9 | 1371 | if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min) |
3de7a1dc TV |
1372 | continue; |
1373 | ||
b6e695ab | 1374 | /* DSIPHY(MHz) = (2 * regm / regn) * clkin */ |
f1da39d9 | 1375 | for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) { |
3de7a1dc TV |
1376 | unsigned long a, b; |
1377 | ||
1378 | a = 2 * cur.regm * (cur.clkin/1000); | |
b6e695ab | 1379 | b = cur.regn; |
3de7a1dc TV |
1380 | cur.clkin4ddr = a / b * 1000; |
1381 | ||
1382 | if (cur.clkin4ddr > 1800 * 1000 * 1000) | |
1383 | break; | |
1384 | ||
1bb47835 AT |
1385 | /* dsi_pll_hsdiv_dispc_clk(MHz) = |
1386 | * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ | |
f1da39d9 AT |
1387 | for (cur.regm_dispc = 1; cur.regm_dispc < |
1388 | dsi->regm_dispc_max; ++cur.regm_dispc) { | |
3de7a1dc | 1389 | struct dispc_clock_info cur_dispc; |
1bb47835 AT |
1390 | cur.dsi_pll_hsdiv_dispc_clk = |
1391 | cur.clkin4ddr / cur.regm_dispc; | |
3de7a1dc TV |
1392 | |
1393 | /* this will narrow down the search a bit, | |
1394 | * but still give pixclocks below what was | |
1395 | * requested */ | |
1bb47835 | 1396 | if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) |
3de7a1dc TV |
1397 | break; |
1398 | ||
1bb47835 | 1399 | if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) |
3de7a1dc TV |
1400 | continue; |
1401 | ||
1402 | if (min_fck_per_pck && | |
1bb47835 | 1403 | cur.dsi_pll_hsdiv_dispc_clk < |
3de7a1dc TV |
1404 | req_pck * min_fck_per_pck) |
1405 | continue; | |
1406 | ||
1407 | match = 1; | |
1408 | ||
6d523e7b | 1409 | dispc_find_clk_divs(req_pck, |
1bb47835 | 1410 | cur.dsi_pll_hsdiv_dispc_clk, |
3de7a1dc TV |
1411 | &cur_dispc); |
1412 | ||
1413 | if (abs(cur_dispc.pck - req_pck) < | |
1414 | abs(best_dispc.pck - req_pck)) { | |
1415 | best = cur; | |
1416 | best_dispc = cur_dispc; | |
1417 | ||
1418 | if (cur_dispc.pck == req_pck) | |
1419 | goto found; | |
1420 | } | |
1421 | } | |
1422 | } | |
1423 | } | |
1424 | found: | |
1425 | if (!match) { | |
1426 | if (min_fck_per_pck) { | |
1427 | DSSERR("Could not find suitable clock settings.\n" | |
1428 | "Turning FCK/PCK constraint off and" | |
1429 | "trying again.\n"); | |
1430 | min_fck_per_pck = 0; | |
1431 | goto retry; | |
1432 | } | |
1433 | ||
1434 | DSSERR("Could not find suitable clock settings.\n"); | |
1435 | ||
1436 | return -EINVAL; | |
1437 | } | |
1438 | ||
1bb47835 AT |
1439 | /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ |
1440 | best.regm_dsi = 0; | |
1441 | best.dsi_pll_hsdiv_dsi_clk = 0; | |
3de7a1dc TV |
1442 | |
1443 | if (dsi_cinfo) | |
1444 | *dsi_cinfo = best; | |
1445 | if (dispc_cinfo) | |
1446 | *dispc_cinfo = best_dispc; | |
1447 | ||
f1da39d9 AT |
1448 | dsi->cache_req_pck = req_pck; |
1449 | dsi->cache_clk_freq = 0; | |
1450 | dsi->cache_cinfo = best; | |
3de7a1dc TV |
1451 | |
1452 | return 0; | |
1453 | } | |
1454 | ||
a72b64b9 AT |
1455 | int dsi_pll_set_clock_div(struct platform_device *dsidev, |
1456 | struct dsi_clock_info *cinfo) | |
3de7a1dc | 1457 | { |
f1da39d9 | 1458 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1459 | int r = 0; |
1460 | u32 l; | |
9613c02b | 1461 | int f = 0; |
49641116 TA |
1462 | u8 regn_start, regn_end, regm_start, regm_end; |
1463 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; | |
3de7a1dc TV |
1464 | |
1465 | DSSDBGF(); | |
1466 | ||
b6e695ab | 1467 | dsi->current_cinfo.clkin = cinfo->clkin; |
f1da39d9 AT |
1468 | dsi->current_cinfo.fint = cinfo->fint; |
1469 | dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr; | |
1470 | dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk = | |
1bb47835 | 1471 | cinfo->dsi_pll_hsdiv_dispc_clk; |
f1da39d9 | 1472 | dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk = |
1bb47835 | 1473 | cinfo->dsi_pll_hsdiv_dsi_clk; |
3de7a1dc | 1474 | |
f1da39d9 AT |
1475 | dsi->current_cinfo.regn = cinfo->regn; |
1476 | dsi->current_cinfo.regm = cinfo->regm; | |
1477 | dsi->current_cinfo.regm_dispc = cinfo->regm_dispc; | |
1478 | dsi->current_cinfo.regm_dsi = cinfo->regm_dsi; | |
3de7a1dc TV |
1479 | |
1480 | DSSDBG("DSI Fint %ld\n", cinfo->fint); | |
1481 | ||
b6e695ab | 1482 | DSSDBG("clkin rate %ld\n", cinfo->clkin); |
3de7a1dc TV |
1483 | |
1484 | /* DSIPHY == CLKIN4DDR */ | |
b6e695ab | 1485 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n", |
3de7a1dc TV |
1486 | cinfo->regm, |
1487 | cinfo->regn, | |
1488 | cinfo->clkin, | |
3de7a1dc TV |
1489 | cinfo->clkin4ddr); |
1490 | ||
1491 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", | |
1492 | cinfo->clkin4ddr / 1000 / 1000 / 2); | |
1493 | ||
1494 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); | |
1495 | ||
1bb47835 | 1496 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
89a35e51 AT |
1497 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1498 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), | |
1bb47835 AT |
1499 | cinfo->dsi_pll_hsdiv_dispc_clk); |
1500 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, | |
89a35e51 AT |
1501 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
1502 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | |
1bb47835 | 1503 | cinfo->dsi_pll_hsdiv_dsi_clk); |
3de7a1dc | 1504 | |
49641116 TA |
1505 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
1506 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); | |
1507 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, | |
1508 | ®m_dispc_end); | |
1509 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, | |
1510 | ®m_dsi_end); | |
1511 | ||
a72b64b9 AT |
1512 | /* DSI_PLL_AUTOMODE = manual */ |
1513 | REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0); | |
3de7a1dc | 1514 | |
a72b64b9 | 1515 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1); |
3de7a1dc | 1516 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ |
49641116 TA |
1517 | /* DSI_PLL_REGN */ |
1518 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); | |
1519 | /* DSI_PLL_REGM */ | |
1520 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); | |
1521 | /* DSI_CLOCK_DIV */ | |
1bb47835 | 1522 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
49641116 TA |
1523 | regm_dispc_start, regm_dispc_end); |
1524 | /* DSIPROTO_CLOCK_DIV */ | |
1bb47835 | 1525 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
49641116 | 1526 | regm_dsi_start, regm_dsi_end); |
a72b64b9 | 1527 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l); |
3de7a1dc | 1528 | |
f1da39d9 | 1529 | BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max); |
9613c02b AT |
1530 | |
1531 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) { | |
1532 | f = cinfo->fint < 1000000 ? 0x3 : | |
1533 | cinfo->fint < 1250000 ? 0x4 : | |
1534 | cinfo->fint < 1500000 ? 0x5 : | |
1535 | cinfo->fint < 1750000 ? 0x6 : | |
1536 | 0x7; | |
1537 | } | |
3de7a1dc | 1538 | |
a72b64b9 | 1539 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
9613c02b AT |
1540 | |
1541 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) | |
1542 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ | |
3de7a1dc TV |
1543 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ |
1544 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ | |
1545 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ | |
a72b64b9 | 1546 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
3de7a1dc | 1547 | |
a72b64b9 | 1548 | REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ |
3de7a1dc | 1549 | |
a72b64b9 | 1550 | if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) { |
3de7a1dc TV |
1551 | DSSERR("dsi pll go bit not going down.\n"); |
1552 | r = -EIO; | |
1553 | goto err; | |
1554 | } | |
1555 | ||
a72b64b9 | 1556 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) { |
3de7a1dc TV |
1557 | DSSERR("cannot lock PLL\n"); |
1558 | r = -EIO; | |
1559 | goto err; | |
1560 | } | |
1561 | ||
f1da39d9 | 1562 | dsi->pll_locked = 1; |
3de7a1dc | 1563 | |
a72b64b9 | 1564 | l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2); |
3de7a1dc TV |
1565 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ |
1566 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ | |
1567 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ | |
1568 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ | |
1569 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ | |
1570 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ | |
1571 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ | |
1572 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ | |
1573 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ | |
1574 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ | |
1575 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ | |
1576 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ | |
1577 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ | |
1578 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ | |
a72b64b9 | 1579 | dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l); |
3de7a1dc TV |
1580 | |
1581 | DSSDBG("PLL config done\n"); | |
1582 | err: | |
1583 | return r; | |
1584 | } | |
1585 | ||
a72b64b9 AT |
1586 | int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk, |
1587 | bool enable_hsdiv) | |
3de7a1dc | 1588 | { |
f1da39d9 | 1589 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
1590 | int r = 0; |
1591 | enum dsi_pll_power_state pwstate; | |
1592 | ||
1593 | DSSDBG("PLL init\n"); | |
1594 | ||
f1da39d9 | 1595 | if (dsi->vdds_dsi_reg == NULL) { |
f2988ab9 TV |
1596 | struct regulator *vdds_dsi; |
1597 | ||
f1da39d9 | 1598 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
f2988ab9 TV |
1599 | |
1600 | if (IS_ERR(vdds_dsi)) { | |
1601 | DSSERR("can't get VDDS_DSI regulator\n"); | |
1602 | return PTR_ERR(vdds_dsi); | |
1603 | } | |
1604 | ||
f1da39d9 | 1605 | dsi->vdds_dsi_reg = vdds_dsi; |
f2988ab9 | 1606 | } |
f2988ab9 | 1607 | |
a72b64b9 | 1608 | dsi_enable_pll_clock(dsidev, 1); |
24c1ae41 TV |
1609 | /* |
1610 | * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. | |
1611 | */ | |
a72b64b9 | 1612 | dsi_enable_scp_clk(dsidev); |
3de7a1dc | 1613 | |
f1da39d9 AT |
1614 | if (!dsi->vdds_dsi_enabled) { |
1615 | r = regulator_enable(dsi->vdds_dsi_reg); | |
2a89dc15 TV |
1616 | if (r) |
1617 | goto err0; | |
f1da39d9 | 1618 | dsi->vdds_dsi_enabled = true; |
2a89dc15 | 1619 | } |
3de7a1dc TV |
1620 | |
1621 | /* XXX PLL does not come out of reset without this... */ | |
1622 | dispc_pck_free_enable(1); | |
1623 | ||
a72b64b9 | 1624 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) { |
3de7a1dc TV |
1625 | DSSERR("PLL not coming out of reset.\n"); |
1626 | r = -ENODEV; | |
481dfa0e | 1627 | dispc_pck_free_enable(0); |
3de7a1dc TV |
1628 | goto err1; |
1629 | } | |
1630 | ||
1631 | /* XXX ... but if left on, we get problems when planes do not | |
1632 | * fill the whole display. No idea about this */ | |
1633 | dispc_pck_free_enable(0); | |
1634 | ||
1635 | if (enable_hsclk && enable_hsdiv) | |
1636 | pwstate = DSI_PLL_POWER_ON_ALL; | |
1637 | else if (enable_hsclk) | |
1638 | pwstate = DSI_PLL_POWER_ON_HSCLK; | |
1639 | else if (enable_hsdiv) | |
1640 | pwstate = DSI_PLL_POWER_ON_DIV; | |
1641 | else | |
1642 | pwstate = DSI_PLL_POWER_OFF; | |
1643 | ||
a72b64b9 | 1644 | r = dsi_pll_power(dsidev, pwstate); |
3de7a1dc TV |
1645 | |
1646 | if (r) | |
1647 | goto err1; | |
1648 | ||
1649 | DSSDBG("PLL init done\n"); | |
1650 | ||
1651 | return 0; | |
1652 | err1: | |
f1da39d9 AT |
1653 | if (dsi->vdds_dsi_enabled) { |
1654 | regulator_disable(dsi->vdds_dsi_reg); | |
1655 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1656 | } |
3de7a1dc | 1657 | err0: |
a72b64b9 | 1658 | dsi_disable_scp_clk(dsidev); |
a72b64b9 | 1659 | dsi_enable_pll_clock(dsidev, 0); |
3de7a1dc TV |
1660 | return r; |
1661 | } | |
1662 | ||
a72b64b9 | 1663 | void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes) |
3de7a1dc | 1664 | { |
f1da39d9 AT |
1665 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1666 | ||
1667 | dsi->pll_locked = 0; | |
a72b64b9 | 1668 | dsi_pll_power(dsidev, DSI_PLL_POWER_OFF); |
2a89dc15 | 1669 | if (disconnect_lanes) { |
f1da39d9 AT |
1670 | WARN_ON(!dsi->vdds_dsi_enabled); |
1671 | regulator_disable(dsi->vdds_dsi_reg); | |
1672 | dsi->vdds_dsi_enabled = false; | |
2a89dc15 | 1673 | } |
24c1ae41 | 1674 | |
a72b64b9 | 1675 | dsi_disable_scp_clk(dsidev); |
a72b64b9 | 1676 | dsi_enable_pll_clock(dsidev, 0); |
24c1ae41 | 1677 | |
3de7a1dc TV |
1678 | DSSDBG("PLL uninit done\n"); |
1679 | } | |
1680 | ||
5a8b572d AT |
1681 | static void dsi_dump_dsidev_clocks(struct platform_device *dsidev, |
1682 | struct seq_file *s) | |
3de7a1dc | 1683 | { |
f1da39d9 AT |
1684 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
1685 | struct dsi_clock_info *cinfo = &dsi->current_cinfo; | |
89a35e51 | 1686 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
11ee9606 | 1687 | int dsi_module = dsi->module_id; |
067a57e4 AT |
1688 | |
1689 | dispc_clk_src = dss_get_dispc_clk_source(); | |
5a8b572d | 1690 | dsi_clk_src = dss_get_dsi_clk_source(dsi_module); |
3de7a1dc | 1691 | |
4fbafaf3 TV |
1692 | if (dsi_runtime_get(dsidev)) |
1693 | return; | |
3de7a1dc | 1694 | |
5a8b572d | 1695 | seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); |
3de7a1dc | 1696 | |
b6e695ab | 1697 | seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin); |
3de7a1dc TV |
1698 | |
1699 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); | |
1700 | ||
1701 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", | |
1702 | cinfo->clkin4ddr, cinfo->regm); | |
1703 | ||
84309f16 AT |
1704 | seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n", |
1705 | dss_feat_get_clk_source_name(dsi_module == 0 ? | |
1706 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC : | |
1707 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC), | |
1bb47835 AT |
1708 | cinfo->dsi_pll_hsdiv_dispc_clk, |
1709 | cinfo->regm_dispc, | |
89a35e51 | 1710 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1711 | "off" : "on"); |
3de7a1dc | 1712 | |
84309f16 AT |
1713 | seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n", |
1714 | dss_feat_get_clk_source_name(dsi_module == 0 ? | |
1715 | OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI : | |
1716 | OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI), | |
1bb47835 AT |
1717 | cinfo->dsi_pll_hsdiv_dsi_clk, |
1718 | cinfo->regm_dsi, | |
89a35e51 | 1719 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1720 | "off" : "on"); |
3de7a1dc | 1721 | |
5a8b572d | 1722 | seq_printf(s, "- DSI%d -\n", dsi_module + 1); |
3de7a1dc | 1723 | |
067a57e4 AT |
1724 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
1725 | dss_get_generic_clk_source_name(dsi_clk_src), | |
1726 | dss_feat_get_clk_source_name(dsi_clk_src)); | |
3de7a1dc | 1727 | |
a72b64b9 | 1728 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev)); |
3de7a1dc TV |
1729 | |
1730 | seq_printf(s, "DDR_CLK\t\t%lu\n", | |
1731 | cinfo->clkin4ddr / 4); | |
1732 | ||
a72b64b9 | 1733 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev)); |
3de7a1dc TV |
1734 | |
1735 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); | |
1736 | ||
4fbafaf3 | 1737 | dsi_runtime_put(dsidev); |
3de7a1dc TV |
1738 | } |
1739 | ||
5a8b572d AT |
1740 | void dsi_dump_clocks(struct seq_file *s) |
1741 | { | |
1742 | struct platform_device *dsidev; | |
1743 | int i; | |
1744 | ||
1745 | for (i = 0; i < MAX_NUM_DSI; i++) { | |
1746 | dsidev = dsi_get_dsidev_from_id(i); | |
1747 | if (dsidev) | |
1748 | dsi_dump_dsidev_clocks(dsidev, s); | |
1749 | } | |
1750 | } | |
1751 | ||
dfc0fd8d | 1752 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
5a8b572d AT |
1753 | static void dsi_dump_dsidev_irqs(struct platform_device *dsidev, |
1754 | struct seq_file *s) | |
dfc0fd8d | 1755 | { |
f1da39d9 | 1756 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
dfc0fd8d TV |
1757 | unsigned long flags; |
1758 | struct dsi_irq_stats stats; | |
1759 | ||
f1da39d9 | 1760 | spin_lock_irqsave(&dsi->irq_stats_lock, flags); |
dfc0fd8d | 1761 | |
f1da39d9 AT |
1762 | stats = dsi->irq_stats; |
1763 | memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); | |
1764 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d | 1765 | |
f1da39d9 | 1766 | spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); |
dfc0fd8d TV |
1767 | |
1768 | seq_printf(s, "period %u ms\n", | |
1769 | jiffies_to_msecs(jiffies - stats.last_reset)); | |
1770 | ||
1771 | seq_printf(s, "irqs %d\n", stats.irq_count); | |
1772 | #define PIS(x) \ | |
1773 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); | |
1774 | ||
11ee9606 | 1775 | seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); |
dfc0fd8d TV |
1776 | PIS(VC0); |
1777 | PIS(VC1); | |
1778 | PIS(VC2); | |
1779 | PIS(VC3); | |
1780 | PIS(WAKEUP); | |
1781 | PIS(RESYNC); | |
1782 | PIS(PLL_LOCK); | |
1783 | PIS(PLL_UNLOCK); | |
1784 | PIS(PLL_RECALL); | |
1785 | PIS(COMPLEXIO_ERR); | |
1786 | PIS(HS_TX_TIMEOUT); | |
1787 | PIS(LP_RX_TIMEOUT); | |
1788 | PIS(TE_TRIGGER); | |
1789 | PIS(ACK_TRIGGER); | |
1790 | PIS(SYNC_LOST); | |
1791 | PIS(LDO_POWER_GOOD); | |
1792 | PIS(TA_TIMEOUT); | |
1793 | #undef PIS | |
1794 | ||
1795 | #define PIS(x) \ | |
1796 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ | |
1797 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ | |
1798 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ | |
1799 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ | |
1800 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); | |
1801 | ||
1802 | seq_printf(s, "-- VC interrupts --\n"); | |
1803 | PIS(CS); | |
1804 | PIS(ECC_CORR); | |
1805 | PIS(PACKET_SENT); | |
1806 | PIS(FIFO_TX_OVF); | |
1807 | PIS(FIFO_RX_OVF); | |
1808 | PIS(BTA); | |
1809 | PIS(ECC_NO_CORR); | |
1810 | PIS(FIFO_TX_UDF); | |
1811 | PIS(PP_BUSY_CHANGE); | |
1812 | #undef PIS | |
1813 | ||
1814 | #define PIS(x) \ | |
1815 | seq_printf(s, "%-20s %10d\n", #x, \ | |
1816 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); | |
1817 | ||
1818 | seq_printf(s, "-- CIO interrupts --\n"); | |
1819 | PIS(ERRSYNCESC1); | |
1820 | PIS(ERRSYNCESC2); | |
1821 | PIS(ERRSYNCESC3); | |
1822 | PIS(ERRESC1); | |
1823 | PIS(ERRESC2); | |
1824 | PIS(ERRESC3); | |
1825 | PIS(ERRCONTROL1); | |
1826 | PIS(ERRCONTROL2); | |
1827 | PIS(ERRCONTROL3); | |
1828 | PIS(STATEULPS1); | |
1829 | PIS(STATEULPS2); | |
1830 | PIS(STATEULPS3); | |
1831 | PIS(ERRCONTENTIONLP0_1); | |
1832 | PIS(ERRCONTENTIONLP1_1); | |
1833 | PIS(ERRCONTENTIONLP0_2); | |
1834 | PIS(ERRCONTENTIONLP1_2); | |
1835 | PIS(ERRCONTENTIONLP0_3); | |
1836 | PIS(ERRCONTENTIONLP1_3); | |
1837 | PIS(ULPSACTIVENOT_ALL0); | |
1838 | PIS(ULPSACTIVENOT_ALL1); | |
1839 | #undef PIS | |
1840 | } | |
dfc0fd8d | 1841 | |
5a8b572d | 1842 | static void dsi1_dump_irqs(struct seq_file *s) |
3de7a1dc | 1843 | { |
a72b64b9 AT |
1844 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); |
1845 | ||
5a8b572d AT |
1846 | dsi_dump_dsidev_irqs(dsidev, s); |
1847 | } | |
1848 | ||
1849 | static void dsi2_dump_irqs(struct seq_file *s) | |
1850 | { | |
1851 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1852 | ||
1853 | dsi_dump_dsidev_irqs(dsidev, s); | |
1854 | } | |
5a8b572d AT |
1855 | #endif |
1856 | ||
1857 | static void dsi_dump_dsidev_regs(struct platform_device *dsidev, | |
1858 | struct seq_file *s) | |
1859 | { | |
a72b64b9 | 1860 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r)) |
3de7a1dc | 1861 | |
4fbafaf3 TV |
1862 | if (dsi_runtime_get(dsidev)) |
1863 | return; | |
a72b64b9 | 1864 | dsi_enable_scp_clk(dsidev); |
3de7a1dc TV |
1865 | |
1866 | DUMPREG(DSI_REVISION); | |
1867 | DUMPREG(DSI_SYSCONFIG); | |
1868 | DUMPREG(DSI_SYSSTATUS); | |
1869 | DUMPREG(DSI_IRQSTATUS); | |
1870 | DUMPREG(DSI_IRQENABLE); | |
1871 | DUMPREG(DSI_CTRL); | |
1872 | DUMPREG(DSI_COMPLEXIO_CFG1); | |
1873 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); | |
1874 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); | |
1875 | DUMPREG(DSI_CLK_CTRL); | |
1876 | DUMPREG(DSI_TIMING1); | |
1877 | DUMPREG(DSI_TIMING2); | |
1878 | DUMPREG(DSI_VM_TIMING1); | |
1879 | DUMPREG(DSI_VM_TIMING2); | |
1880 | DUMPREG(DSI_VM_TIMING3); | |
1881 | DUMPREG(DSI_CLK_TIMING); | |
1882 | DUMPREG(DSI_TX_FIFO_VC_SIZE); | |
1883 | DUMPREG(DSI_RX_FIFO_VC_SIZE); | |
1884 | DUMPREG(DSI_COMPLEXIO_CFG2); | |
1885 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); | |
1886 | DUMPREG(DSI_VM_TIMING4); | |
1887 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); | |
1888 | DUMPREG(DSI_VM_TIMING5); | |
1889 | DUMPREG(DSI_VM_TIMING6); | |
1890 | DUMPREG(DSI_VM_TIMING7); | |
1891 | DUMPREG(DSI_STOPCLK_TIMING); | |
1892 | ||
1893 | DUMPREG(DSI_VC_CTRL(0)); | |
1894 | DUMPREG(DSI_VC_TE(0)); | |
1895 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); | |
1896 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); | |
1897 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); | |
1898 | DUMPREG(DSI_VC_IRQSTATUS(0)); | |
1899 | DUMPREG(DSI_VC_IRQENABLE(0)); | |
1900 | ||
1901 | DUMPREG(DSI_VC_CTRL(1)); | |
1902 | DUMPREG(DSI_VC_TE(1)); | |
1903 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); | |
1904 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); | |
1905 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); | |
1906 | DUMPREG(DSI_VC_IRQSTATUS(1)); | |
1907 | DUMPREG(DSI_VC_IRQENABLE(1)); | |
1908 | ||
1909 | DUMPREG(DSI_VC_CTRL(2)); | |
1910 | DUMPREG(DSI_VC_TE(2)); | |
1911 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); | |
1912 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); | |
1913 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); | |
1914 | DUMPREG(DSI_VC_IRQSTATUS(2)); | |
1915 | DUMPREG(DSI_VC_IRQENABLE(2)); | |
1916 | ||
1917 | DUMPREG(DSI_VC_CTRL(3)); | |
1918 | DUMPREG(DSI_VC_TE(3)); | |
1919 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); | |
1920 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); | |
1921 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); | |
1922 | DUMPREG(DSI_VC_IRQSTATUS(3)); | |
1923 | DUMPREG(DSI_VC_IRQENABLE(3)); | |
1924 | ||
1925 | DUMPREG(DSI_DSIPHY_CFG0); | |
1926 | DUMPREG(DSI_DSIPHY_CFG1); | |
1927 | DUMPREG(DSI_DSIPHY_CFG2); | |
1928 | DUMPREG(DSI_DSIPHY_CFG5); | |
1929 | ||
1930 | DUMPREG(DSI_PLL_CONTROL); | |
1931 | DUMPREG(DSI_PLL_STATUS); | |
1932 | DUMPREG(DSI_PLL_GO); | |
1933 | DUMPREG(DSI_PLL_CONFIGURATION1); | |
1934 | DUMPREG(DSI_PLL_CONFIGURATION2); | |
1935 | ||
a72b64b9 | 1936 | dsi_disable_scp_clk(dsidev); |
4fbafaf3 | 1937 | dsi_runtime_put(dsidev); |
3de7a1dc TV |
1938 | #undef DUMPREG |
1939 | } | |
1940 | ||
5a8b572d AT |
1941 | static void dsi1_dump_regs(struct seq_file *s) |
1942 | { | |
1943 | struct platform_device *dsidev = dsi_get_dsidev_from_id(0); | |
1944 | ||
1945 | dsi_dump_dsidev_regs(dsidev, s); | |
1946 | } | |
1947 | ||
1948 | static void dsi2_dump_regs(struct seq_file *s) | |
1949 | { | |
1950 | struct platform_device *dsidev = dsi_get_dsidev_from_id(1); | |
1951 | ||
1952 | dsi_dump_dsidev_regs(dsidev, s); | |
1953 | } | |
1954 | ||
cc5c1850 | 1955 | enum dsi_cio_power_state { |
3de7a1dc TV |
1956 | DSI_COMPLEXIO_POWER_OFF = 0x0, |
1957 | DSI_COMPLEXIO_POWER_ON = 0x1, | |
1958 | DSI_COMPLEXIO_POWER_ULPS = 0x2, | |
1959 | }; | |
1960 | ||
a72b64b9 AT |
1961 | static int dsi_cio_power(struct platform_device *dsidev, |
1962 | enum dsi_cio_power_state state) | |
3de7a1dc TV |
1963 | { |
1964 | int t = 0; | |
1965 | ||
1966 | /* PWR_CMD */ | |
a72b64b9 | 1967 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); |
3de7a1dc TV |
1968 | |
1969 | /* PWR_STATUS */ | |
a72b64b9 AT |
1970 | while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1), |
1971 | 26, 25) != state) { | |
24be78b3 | 1972 | if (++t > 1000) { |
3de7a1dc TV |
1973 | DSSERR("failed to set complexio power state to " |
1974 | "%d\n", state); | |
1975 | return -ENODEV; | |
1976 | } | |
24be78b3 | 1977 | udelay(1); |
3de7a1dc TV |
1978 | } |
1979 | ||
1980 | return 0; | |
1981 | } | |
1982 | ||
0c65622b AT |
1983 | static unsigned dsi_get_line_buf_size(struct platform_device *dsidev) |
1984 | { | |
1985 | int val; | |
1986 | ||
1987 | /* line buffer on OMAP3 is 1024 x 24bits */ | |
1988 | /* XXX: for some reason using full buffer size causes | |
1989 | * considerable TX slowdown with update sizes that fill the | |
1990 | * whole buffer */ | |
1991 | if (!dss_has_feature(FEAT_DSI_GNQ)) | |
1992 | return 1023 * 3; | |
1993 | ||
1994 | val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ | |
1995 | ||
1996 | switch (val) { | |
1997 | case 1: | |
1998 | return 512 * 3; /* 512x24 bits */ | |
1999 | case 2: | |
2000 | return 682 * 3; /* 682x24 bits */ | |
2001 | case 3: | |
2002 | return 853 * 3; /* 853x24 bits */ | |
2003 | case 4: | |
2004 | return 1024 * 3; /* 1024x24 bits */ | |
2005 | case 5: | |
2006 | return 1194 * 3; /* 1194x24 bits */ | |
2007 | case 6: | |
2008 | return 1365 * 3; /* 1365x24 bits */ | |
2009 | default: | |
2010 | BUG(); | |
c6eee968 | 2011 | return 0; |
0c65622b AT |
2012 | } |
2013 | } | |
2014 | ||
48368395 | 2015 | static int dsi_set_lane_config(struct omap_dss_device *dssdev) |
3de7a1dc | 2016 | { |
a72b64b9 | 2017 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
48368395 TV |
2018 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2019 | static const u8 offsets[] = { 0, 4, 8, 12, 16 }; | |
2020 | static const enum dsi_lane_function functions[] = { | |
2021 | DSI_LANE_CLK, | |
2022 | DSI_LANE_DATA1, | |
2023 | DSI_LANE_DATA2, | |
2024 | DSI_LANE_DATA3, | |
2025 | DSI_LANE_DATA4, | |
2026 | }; | |
3de7a1dc | 2027 | u32 r; |
48368395 | 2028 | int i; |
3de7a1dc | 2029 | |
a72b64b9 | 2030 | r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1); |
48368395 TV |
2031 | |
2032 | for (i = 0; i < dsi->num_lanes_used; ++i) { | |
2033 | unsigned offset = offsets[i]; | |
2034 | unsigned polarity, lane_number; | |
2035 | unsigned t; | |
2036 | ||
2037 | for (t = 0; t < dsi->num_lanes_supported; ++t) | |
2038 | if (dsi->lanes[t].function == functions[i]) | |
2039 | break; | |
2040 | ||
2041 | if (t == dsi->num_lanes_supported) | |
2042 | return -EINVAL; | |
2043 | ||
2044 | lane_number = t; | |
2045 | polarity = dsi->lanes[t].polarity; | |
2046 | ||
2047 | r = FLD_MOD(r, lane_number + 1, offset + 2, offset); | |
2048 | r = FLD_MOD(r, polarity, offset + 3, offset + 3); | |
75d7247c | 2049 | } |
75d7247c | 2050 | |
48368395 TV |
2051 | /* clear the unused lanes */ |
2052 | for (; i < dsi->num_lanes_supported; ++i) { | |
2053 | unsigned offset = offsets[i]; | |
2054 | ||
2055 | r = FLD_MOD(r, 0, offset + 2, offset); | |
2056 | r = FLD_MOD(r, 0, offset + 3, offset + 3); | |
75d7247c | 2057 | } |
3de7a1dc | 2058 | |
48368395 | 2059 | dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r); |
3de7a1dc | 2060 | |
48368395 | 2061 | return 0; |
3de7a1dc TV |
2062 | } |
2063 | ||
a72b64b9 | 2064 | static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns) |
3de7a1dc | 2065 | { |
f1da39d9 AT |
2066 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2067 | ||
3de7a1dc | 2068 | /* convert time in ns to ddr ticks, rounding up */ |
f1da39d9 | 2069 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; |
3de7a1dc TV |
2070 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; |
2071 | } | |
2072 | ||
a72b64b9 | 2073 | static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr) |
3de7a1dc | 2074 | { |
f1da39d9 AT |
2075 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2076 | ||
2077 | unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4; | |
3de7a1dc TV |
2078 | return ddr * 1000 * 1000 / (ddr_clk / 1000); |
2079 | } | |
2080 | ||
a72b64b9 | 2081 | static void dsi_cio_timings(struct platform_device *dsidev) |
3de7a1dc TV |
2082 | { |
2083 | u32 r; | |
2084 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; | |
2085 | u32 tlpx_half, tclk_trail, tclk_zero; | |
2086 | u32 tclk_prepare; | |
2087 | ||
2088 | /* calculate timings */ | |
2089 | ||
2090 | /* 1 * DDR_CLK = 2 * UI */ | |
2091 | ||
2092 | /* min 40ns + 4*UI max 85ns + 6*UI */ | |
a72b64b9 | 2093 | ths_prepare = ns2ddr(dsidev, 70) + 2; |
3de7a1dc TV |
2094 | |
2095 | /* min 145ns + 10*UI */ | |
a72b64b9 | 2096 | ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2; |
3de7a1dc TV |
2097 | |
2098 | /* min max(8*UI, 60ns+4*UI) */ | |
a72b64b9 | 2099 | ths_trail = ns2ddr(dsidev, 60) + 5; |
3de7a1dc TV |
2100 | |
2101 | /* min 100ns */ | |
a72b64b9 | 2102 | ths_exit = ns2ddr(dsidev, 145); |
3de7a1dc TV |
2103 | |
2104 | /* tlpx min 50n */ | |
a72b64b9 | 2105 | tlpx_half = ns2ddr(dsidev, 25); |
3de7a1dc TV |
2106 | |
2107 | /* min 60ns */ | |
a72b64b9 | 2108 | tclk_trail = ns2ddr(dsidev, 60) + 2; |
3de7a1dc TV |
2109 | |
2110 | /* min 38ns, max 95ns */ | |
a72b64b9 | 2111 | tclk_prepare = ns2ddr(dsidev, 65); |
3de7a1dc TV |
2112 | |
2113 | /* min tclk-prepare + tclk-zero = 300ns */ | |
a72b64b9 | 2114 | tclk_zero = ns2ddr(dsidev, 260); |
3de7a1dc TV |
2115 | |
2116 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", | |
a72b64b9 AT |
2117 | ths_prepare, ddr2ns(dsidev, ths_prepare), |
2118 | ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero)); | |
3de7a1dc | 2119 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", |
a72b64b9 AT |
2120 | ths_trail, ddr2ns(dsidev, ths_trail), |
2121 | ths_exit, ddr2ns(dsidev, ths_exit)); | |
3de7a1dc TV |
2122 | |
2123 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " | |
2124 | "tclk_zero %u (%uns)\n", | |
a72b64b9 AT |
2125 | tlpx_half, ddr2ns(dsidev, tlpx_half), |
2126 | tclk_trail, ddr2ns(dsidev, tclk_trail), | |
2127 | tclk_zero, ddr2ns(dsidev, tclk_zero)); | |
3de7a1dc | 2128 | DSSDBG("tclk_prepare %u (%uns)\n", |
a72b64b9 | 2129 | tclk_prepare, ddr2ns(dsidev, tclk_prepare)); |
3de7a1dc TV |
2130 | |
2131 | /* program timings */ | |
2132 | ||
a72b64b9 | 2133 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
2134 | r = FLD_MOD(r, ths_prepare, 31, 24); |
2135 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); | |
2136 | r = FLD_MOD(r, ths_trail, 15, 8); | |
2137 | r = FLD_MOD(r, ths_exit, 7, 0); | |
a72b64b9 | 2138 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r); |
3de7a1dc | 2139 | |
a72b64b9 | 2140 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
3de7a1dc TV |
2141 | r = FLD_MOD(r, tlpx_half, 22, 16); |
2142 | r = FLD_MOD(r, tclk_trail, 15, 8); | |
2143 | r = FLD_MOD(r, tclk_zero, 7, 0); | |
a72b64b9 | 2144 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r); |
3de7a1dc | 2145 | |
a72b64b9 | 2146 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
3de7a1dc | 2147 | r = FLD_MOD(r, tclk_prepare, 7, 0); |
a72b64b9 | 2148 | dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r); |
3de7a1dc TV |
2149 | } |
2150 | ||
9b4362f2 | 2151 | /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ |
cc5c1850 | 2152 | static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev, |
9b4362f2 | 2153 | unsigned mask_p, unsigned mask_n) |
0a0ee46b | 2154 | { |
a72b64b9 | 2155 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
75d7247c | 2156 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
9b4362f2 TV |
2157 | int i; |
2158 | u32 l; | |
d9820850 | 2159 | u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; |
0a0ee46b | 2160 | |
9b4362f2 TV |
2161 | l = 0; |
2162 | ||
2163 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
2164 | unsigned p = dsi->lanes[i].polarity; | |
2165 | ||
2166 | if (mask_p & (1 << i)) | |
2167 | l |= 1 << (i * 2 + (p ? 0 : 1)); | |
2168 | ||
2169 | if (mask_n & (1 << i)) | |
2170 | l |= 1 << (i * 2 + (p ? 1 : 0)); | |
2171 | } | |
2172 | ||
0a0ee46b TV |
2173 | /* |
2174 | * Bits in REGLPTXSCPDAT4TO0DXDY: | |
2175 | * 17: DY0 18: DX0 | |
2176 | * 19: DY1 20: DX1 | |
2177 | * 21: DY2 22: DX2 | |
75d7247c AT |
2178 | * 23: DY3 24: DX3 |
2179 | * 25: DY4 26: DX4 | |
0a0ee46b TV |
2180 | */ |
2181 | ||
2182 | /* Set the lane override configuration */ | |
a72b64b9 AT |
2183 | |
2184 | /* REGLPTXSCPDAT4TO0DXDY */ | |
75d7247c | 2185 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); |
0a0ee46b TV |
2186 | |
2187 | /* Enable lane override */ | |
a72b64b9 AT |
2188 | |
2189 | /* ENLPTXSCPDAT */ | |
2190 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27); | |
0a0ee46b TV |
2191 | } |
2192 | ||
a72b64b9 | 2193 | static void dsi_cio_disable_lane_override(struct platform_device *dsidev) |
0a0ee46b TV |
2194 | { |
2195 | /* Disable lane override */ | |
a72b64b9 | 2196 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ |
0a0ee46b | 2197 | /* Reset the lane override configuration */ |
a72b64b9 AT |
2198 | /* REGLPTXSCPDAT4TO0DXDY */ |
2199 | REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17); | |
0a0ee46b | 2200 | } |
3de7a1dc | 2201 | |
03329ace TV |
2202 | static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev) |
2203 | { | |
a72b64b9 | 2204 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
8dc0766f TV |
2205 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2206 | int t, i; | |
2207 | bool in_use[DSI_MAX_NR_LANES]; | |
2208 | static const u8 offsets_old[] = { 28, 27, 26 }; | |
2209 | static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; | |
2210 | const u8 *offsets; | |
2211 | ||
2212 | if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) | |
2213 | offsets = offsets_old; | |
2214 | else | |
2215 | offsets = offsets_new; | |
03329ace | 2216 | |
8dc0766f TV |
2217 | for (i = 0; i < dsi->num_lanes_supported; ++i) |
2218 | in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; | |
03329ace TV |
2219 | |
2220 | t = 100000; | |
2221 | while (true) { | |
2222 | u32 l; | |
03329ace TV |
2223 | int ok; |
2224 | ||
a72b64b9 | 2225 | l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
03329ace TV |
2226 | |
2227 | ok = 0; | |
8dc0766f TV |
2228 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2229 | if (!in_use[i] || (l & (1 << offsets[i]))) | |
03329ace TV |
2230 | ok++; |
2231 | } | |
2232 | ||
8dc0766f | 2233 | if (ok == dsi->num_lanes_supported) |
03329ace TV |
2234 | break; |
2235 | ||
2236 | if (--t == 0) { | |
8dc0766f TV |
2237 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2238 | if (!in_use[i] || (l & (1 << offsets[i]))) | |
03329ace TV |
2239 | continue; |
2240 | ||
2241 | DSSERR("CIO TXCLKESC%d domain not coming " \ | |
2242 | "out of reset\n", i); | |
2243 | } | |
2244 | return -EIO; | |
2245 | } | |
2246 | } | |
2247 | ||
2248 | return 0; | |
2249 | } | |
2250 | ||
85f17e8e | 2251 | /* return bitmask of enabled lanes, lane0 being the lsb */ |
5bc416cb TV |
2252 | static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev) |
2253 | { | |
85f17e8e TV |
2254 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
2255 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
2256 | unsigned mask = 0; | |
2257 | int i; | |
5bc416cb | 2258 | |
85f17e8e TV |
2259 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2260 | if (dsi->lanes[i].function != DSI_LANE_UNUSED) | |
2261 | mask |= 1 << i; | |
2262 | } | |
5bc416cb | 2263 | |
85f17e8e | 2264 | return mask; |
5bc416cb TV |
2265 | } |
2266 | ||
cc5c1850 | 2267 | static int dsi_cio_init(struct omap_dss_device *dssdev) |
3de7a1dc | 2268 | { |
a72b64b9 | 2269 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 2270 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
65c62bb9 | 2271 | int r; |
40885ab3 | 2272 | u32 l; |
3de7a1dc | 2273 | |
cc5c1850 | 2274 | DSSDBGF(); |
3de7a1dc | 2275 | |
11ee9606 | 2276 | r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dssdev)); |
5bc416cb TV |
2277 | if (r) |
2278 | return r; | |
d1f5857e | 2279 | |
a72b64b9 | 2280 | dsi_enable_scp_clk(dsidev); |
40885ab3 | 2281 | |
3de7a1dc TV |
2282 | /* A dummy read using the SCP interface to any DSIPHY register is |
2283 | * required after DSIPHY reset to complete the reset of the DSI complex | |
2284 | * I/O. */ | |
a72b64b9 | 2285 | dsi_read_reg(dsidev, DSI_DSIPHY_CFG5); |
3de7a1dc | 2286 | |
a72b64b9 | 2287 | if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) { |
65c62bb9 TV |
2288 | DSSERR("CIO SCP Clock domain not coming out of reset.\n"); |
2289 | r = -EIO; | |
2290 | goto err_scp_clk_dom; | |
3de7a1dc TV |
2291 | } |
2292 | ||
48368395 TV |
2293 | r = dsi_set_lane_config(dssdev); |
2294 | if (r) | |
2295 | goto err_scp_clk_dom; | |
3de7a1dc | 2296 | |
40885ab3 | 2297 | /* set TX STOP MODE timer to maximum for this operation */ |
a72b64b9 | 2298 | l = dsi_read_reg(dsidev, DSI_TIMING1); |
40885ab3 TV |
2299 | l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
2300 | l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ | |
2301 | l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ | |
2302 | l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ | |
a72b64b9 | 2303 | dsi_write_reg(dsidev, DSI_TIMING1, l); |
40885ab3 | 2304 | |
f1da39d9 | 2305 | if (dsi->ulps_enabled) { |
9b4362f2 TV |
2306 | unsigned mask_p; |
2307 | int i; | |
75d7247c | 2308 | |
65c62bb9 TV |
2309 | DSSDBG("manual ulps exit\n"); |
2310 | ||
40885ab3 TV |
2311 | /* ULPS is exited by Mark-1 state for 1ms, followed by |
2312 | * stop state. DSS HW cannot do this via the normal | |
2313 | * ULPS exit sequence, as after reset the DSS HW thinks | |
2314 | * that we are not in ULPS mode, and refuses to send the | |
2315 | * sequence. So we need to send the ULPS exit sequence | |
9b4362f2 TV |
2316 | * manually by setting positive lines high and negative lines |
2317 | * low for 1ms. | |
40885ab3 TV |
2318 | */ |
2319 | ||
9b4362f2 | 2320 | mask_p = 0; |
75d7247c | 2321 | |
9b4362f2 TV |
2322 | for (i = 0; i < dsi->num_lanes_supported; ++i) { |
2323 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) | |
2324 | continue; | |
2325 | mask_p |= 1 << i; | |
2326 | } | |
75d7247c | 2327 | |
9b4362f2 | 2328 | dsi_cio_enable_lane_override(dssdev, mask_p, 0); |
40885ab3 | 2329 | } |
3de7a1dc | 2330 | |
a72b64b9 | 2331 | r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON); |
3de7a1dc | 2332 | if (r) |
65c62bb9 TV |
2333 | goto err_cio_pwr; |
2334 | ||
a72b64b9 | 2335 | if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) { |
65c62bb9 TV |
2336 | DSSERR("CIO PWR clock domain not coming out of reset.\n"); |
2337 | r = -ENODEV; | |
2338 | goto err_cio_pwr_dom; | |
2339 | } | |
2340 | ||
a72b64b9 AT |
2341 | dsi_if_enable(dsidev, true); |
2342 | dsi_if_enable(dsidev, false); | |
2343 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ | |
3de7a1dc | 2344 | |
03329ace TV |
2345 | r = dsi_cio_wait_tx_clk_esc_reset(dssdev); |
2346 | if (r) | |
2347 | goto err_tx_clk_esc_rst; | |
2348 | ||
f1da39d9 | 2349 | if (dsi->ulps_enabled) { |
40885ab3 TV |
2350 | /* Keep Mark-1 state for 1ms (as per DSI spec) */ |
2351 | ktime_t wait = ns_to_ktime(1000 * 1000); | |
2352 | set_current_state(TASK_UNINTERRUPTIBLE); | |
2353 | schedule_hrtimeout(&wait, HRTIMER_MODE_REL); | |
2354 | ||
2355 | /* Disable the override. The lanes should be set to Mark-11 | |
2356 | * state by the HW */ | |
a72b64b9 | 2357 | dsi_cio_disable_lane_override(dsidev); |
40885ab3 TV |
2358 | } |
2359 | ||
2360 | /* FORCE_TX_STOP_MODE_IO */ | |
a72b64b9 | 2361 | REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15); |
40885ab3 | 2362 | |
a72b64b9 | 2363 | dsi_cio_timings(dsidev); |
3de7a1dc | 2364 | |
8af6ff01 AT |
2365 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
2366 | /* DDR_CLK_ALWAYS_ON */ | |
2367 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, | |
2368 | dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13); | |
2369 | } | |
2370 | ||
f1da39d9 | 2371 | dsi->ulps_enabled = false; |
3de7a1dc TV |
2372 | |
2373 | DSSDBG("CIO init done\n"); | |
65c62bb9 TV |
2374 | |
2375 | return 0; | |
2376 | ||
03329ace | 2377 | err_tx_clk_esc_rst: |
a72b64b9 | 2378 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ |
65c62bb9 | 2379 | err_cio_pwr_dom: |
a72b64b9 | 2380 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
65c62bb9 | 2381 | err_cio_pwr: |
f1da39d9 | 2382 | if (dsi->ulps_enabled) |
a72b64b9 | 2383 | dsi_cio_disable_lane_override(dsidev); |
65c62bb9 | 2384 | err_scp_clk_dom: |
a72b64b9 | 2385 | dsi_disable_scp_clk(dsidev); |
11ee9606 | 2386 | dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dssdev)); |
3de7a1dc TV |
2387 | return r; |
2388 | } | |
2389 | ||
5bc416cb | 2390 | static void dsi_cio_uninit(struct omap_dss_device *dssdev) |
3de7a1dc | 2391 | { |
5bc416cb | 2392 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
11ee9606 | 2393 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
f1da39d9 | 2394 | |
8af6ff01 AT |
2395 | /* DDR_CLK_ALWAYS_ON */ |
2396 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); | |
2397 | ||
a72b64b9 AT |
2398 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF); |
2399 | dsi_disable_scp_clk(dsidev); | |
11ee9606 | 2400 | dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dssdev)); |
3de7a1dc TV |
2401 | } |
2402 | ||
a72b64b9 AT |
2403 | static void dsi_config_tx_fifo(struct platform_device *dsidev, |
2404 | enum fifo_size size1, enum fifo_size size2, | |
3de7a1dc TV |
2405 | enum fifo_size size3, enum fifo_size size4) |
2406 | { | |
f1da39d9 | 2407 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2408 | u32 r = 0; |
2409 | int add = 0; | |
2410 | int i; | |
2411 | ||
f1da39d9 AT |
2412 | dsi->vc[0].fifo_size = size1; |
2413 | dsi->vc[1].fifo_size = size2; | |
2414 | dsi->vc[2].fifo_size = size3; | |
2415 | dsi->vc[3].fifo_size = size4; | |
3de7a1dc TV |
2416 | |
2417 | for (i = 0; i < 4; i++) { | |
2418 | u8 v; | |
f1da39d9 | 2419 | int size = dsi->vc[i].fifo_size; |
3de7a1dc TV |
2420 | |
2421 | if (add + size > 4) { | |
2422 | DSSERR("Illegal FIFO configuration\n"); | |
2423 | BUG(); | |
c6eee968 | 2424 | return; |
3de7a1dc TV |
2425 | } |
2426 | ||
2427 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2428 | r |= v << (8 * i); | |
2429 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2430 | add += size; | |
2431 | } | |
2432 | ||
a72b64b9 | 2433 | dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2434 | } |
2435 | ||
a72b64b9 AT |
2436 | static void dsi_config_rx_fifo(struct platform_device *dsidev, |
2437 | enum fifo_size size1, enum fifo_size size2, | |
3de7a1dc TV |
2438 | enum fifo_size size3, enum fifo_size size4) |
2439 | { | |
f1da39d9 | 2440 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2441 | u32 r = 0; |
2442 | int add = 0; | |
2443 | int i; | |
2444 | ||
f1da39d9 AT |
2445 | dsi->vc[0].fifo_size = size1; |
2446 | dsi->vc[1].fifo_size = size2; | |
2447 | dsi->vc[2].fifo_size = size3; | |
2448 | dsi->vc[3].fifo_size = size4; | |
3de7a1dc TV |
2449 | |
2450 | for (i = 0; i < 4; i++) { | |
2451 | u8 v; | |
f1da39d9 | 2452 | int size = dsi->vc[i].fifo_size; |
3de7a1dc TV |
2453 | |
2454 | if (add + size > 4) { | |
2455 | DSSERR("Illegal FIFO configuration\n"); | |
2456 | BUG(); | |
c6eee968 | 2457 | return; |
3de7a1dc TV |
2458 | } |
2459 | ||
2460 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2461 | r |= v << (8 * i); | |
2462 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2463 | add += size; | |
2464 | } | |
2465 | ||
a72b64b9 | 2466 | dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r); |
3de7a1dc TV |
2467 | } |
2468 | ||
a72b64b9 | 2469 | static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev) |
3de7a1dc TV |
2470 | { |
2471 | u32 r; | |
2472 | ||
a72b64b9 | 2473 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 2474 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
a72b64b9 | 2475 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 2476 | |
a72b64b9 | 2477 | if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) { |
3de7a1dc TV |
2478 | DSSERR("TX_STOP bit not going down\n"); |
2479 | return -EIO; | |
2480 | } | |
2481 | ||
2482 | return 0; | |
2483 | } | |
2484 | ||
a72b64b9 | 2485 | static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel) |
cf398fb3 | 2486 | { |
a72b64b9 | 2487 | return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); |
cf398fb3 AT |
2488 | } |
2489 | ||
2490 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) | |
2491 | { | |
2e868dbe AT |
2492 | struct dsi_packet_sent_handler_data *vp_data = |
2493 | (struct dsi_packet_sent_handler_data *) data; | |
2494 | struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev); | |
f1da39d9 AT |
2495 | const int channel = dsi->update_channel; |
2496 | u8 bit = dsi->te_enabled ? 30 : 31; | |
cf398fb3 | 2497 | |
2e868dbe AT |
2498 | if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) |
2499 | complete(vp_data->completion); | |
cf398fb3 AT |
2500 | } |
2501 | ||
a72b64b9 | 2502 | static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel) |
cf398fb3 | 2503 | { |
f1da39d9 | 2504 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2e868dbe AT |
2505 | DECLARE_COMPLETION_ONSTACK(completion); |
2506 | struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion }; | |
cf398fb3 AT |
2507 | int r = 0; |
2508 | u8 bit; | |
2509 | ||
f1da39d9 | 2510 | bit = dsi->te_enabled ? 30 : 31; |
cf398fb3 | 2511 | |
a72b64b9 | 2512 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2513 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2514 | if (r) |
2515 | goto err0; | |
2516 | ||
2517 | /* Wait for completion only if TE_EN/TE_START is still set */ | |
a72b64b9 | 2518 | if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { |
cf398fb3 AT |
2519 | if (wait_for_completion_timeout(&completion, |
2520 | msecs_to_jiffies(10)) == 0) { | |
2521 | DSSERR("Failed to complete previous frame transfer\n"); | |
2522 | r = -EIO; | |
2523 | goto err1; | |
2524 | } | |
2525 | } | |
2526 | ||
a72b64b9 | 2527 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2528 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2529 | |
2530 | return 0; | |
2531 | err1: | |
a72b64b9 | 2532 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp, |
2e868dbe | 2533 | &vp_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2534 | err0: |
2535 | return r; | |
2536 | } | |
2537 | ||
2538 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) | |
2539 | { | |
2e868dbe AT |
2540 | struct dsi_packet_sent_handler_data *l4_data = |
2541 | (struct dsi_packet_sent_handler_data *) data; | |
2542 | struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev); | |
f1da39d9 | 2543 | const int channel = dsi->update_channel; |
cf398fb3 | 2544 | |
2e868dbe AT |
2545 | if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) |
2546 | complete(l4_data->completion); | |
cf398fb3 AT |
2547 | } |
2548 | ||
a72b64b9 | 2549 | static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel) |
cf398fb3 | 2550 | { |
cf398fb3 | 2551 | DECLARE_COMPLETION_ONSTACK(completion); |
2e868dbe AT |
2552 | struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion }; |
2553 | int r = 0; | |
cf398fb3 | 2554 | |
a72b64b9 | 2555 | r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2556 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2557 | if (r) |
2558 | goto err0; | |
2559 | ||
2560 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ | |
a72b64b9 | 2561 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { |
cf398fb3 AT |
2562 | if (wait_for_completion_timeout(&completion, |
2563 | msecs_to_jiffies(10)) == 0) { | |
2564 | DSSERR("Failed to complete previous l4 transfer\n"); | |
2565 | r = -EIO; | |
2566 | goto err1; | |
2567 | } | |
2568 | } | |
2569 | ||
a72b64b9 | 2570 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2571 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2572 | |
2573 | return 0; | |
2574 | err1: | |
a72b64b9 | 2575 | dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4, |
2e868dbe | 2576 | &l4_data, DSI_VC_IRQ_PACKET_SENT); |
cf398fb3 AT |
2577 | err0: |
2578 | return r; | |
2579 | } | |
2580 | ||
a72b64b9 | 2581 | static int dsi_sync_vc(struct platform_device *dsidev, int channel) |
cf398fb3 | 2582 | { |
f1da39d9 AT |
2583 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2584 | ||
a72b64b9 | 2585 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
cf398fb3 AT |
2586 | |
2587 | WARN_ON(in_interrupt()); | |
2588 | ||
a72b64b9 | 2589 | if (!dsi_vc_is_enabled(dsidev, channel)) |
cf398fb3 AT |
2590 | return 0; |
2591 | ||
d6049144 AT |
2592 | switch (dsi->vc[channel].source) { |
2593 | case DSI_VC_SOURCE_VP: | |
a72b64b9 | 2594 | return dsi_sync_vc_vp(dsidev, channel); |
d6049144 | 2595 | case DSI_VC_SOURCE_L4: |
a72b64b9 | 2596 | return dsi_sync_vc_l4(dsidev, channel); |
cf398fb3 AT |
2597 | default: |
2598 | BUG(); | |
c6eee968 | 2599 | return -EINVAL; |
cf398fb3 AT |
2600 | } |
2601 | } | |
2602 | ||
a72b64b9 AT |
2603 | static int dsi_vc_enable(struct platform_device *dsidev, int channel, |
2604 | bool enable) | |
3de7a1dc | 2605 | { |
446f7bff TV |
2606 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
2607 | channel, enable); | |
3de7a1dc TV |
2608 | |
2609 | enable = enable ? 1 : 0; | |
2610 | ||
a72b64b9 | 2611 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0); |
3de7a1dc | 2612 | |
a72b64b9 AT |
2613 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), |
2614 | 0, enable) != enable) { | |
3de7a1dc TV |
2615 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); |
2616 | return -EIO; | |
2617 | } | |
2618 | ||
2619 | return 0; | |
2620 | } | |
2621 | ||
a72b64b9 | 2622 | static void dsi_vc_initial_config(struct platform_device *dsidev, int channel) |
3de7a1dc TV |
2623 | { |
2624 | u32 r; | |
2625 | ||
2626 | DSSDBGF("%d", channel); | |
2627 | ||
a72b64b9 | 2628 | r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); |
3de7a1dc TV |
2629 | |
2630 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ | |
2631 | DSSERR("VC(%d) busy when trying to configure it!\n", | |
2632 | channel); | |
2633 | ||
2634 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ | |
2635 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ | |
2636 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ | |
2637 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ | |
2638 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ | |
2639 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ | |
2640 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ | |
9613c02b AT |
2641 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
2642 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ | |
3de7a1dc TV |
2643 | |
2644 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ | |
2645 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ | |
2646 | ||
a72b64b9 | 2647 | dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r); |
3de7a1dc TV |
2648 | } |
2649 | ||
d6049144 AT |
2650 | static int dsi_vc_config_source(struct platform_device *dsidev, int channel, |
2651 | enum dsi_vc_source source) | |
3de7a1dc | 2652 | { |
f1da39d9 AT |
2653 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2654 | ||
d6049144 | 2655 | if (dsi->vc[channel].source == source) |
9ecd9684 | 2656 | return 0; |
3de7a1dc TV |
2657 | |
2658 | DSSDBGF("%d", channel); | |
2659 | ||
a72b64b9 | 2660 | dsi_sync_vc(dsidev, channel); |
cf398fb3 | 2661 | |
a72b64b9 | 2662 | dsi_vc_enable(dsidev, channel, 0); |
3de7a1dc | 2663 | |
9ecd9684 | 2664 | /* VC_BUSY */ |
a72b64b9 | 2665 | if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) { |
3de7a1dc | 2666 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
9ecd9684 TV |
2667 | return -EIO; |
2668 | } | |
3de7a1dc | 2669 | |
d6049144 AT |
2670 | /* SOURCE, 0 = L4, 1 = video port */ |
2671 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1); | |
3de7a1dc | 2672 | |
9613c02b | 2673 | /* DCS_CMD_ENABLE */ |
d6049144 AT |
2674 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
2675 | bool enable = source == DSI_VC_SOURCE_VP; | |
2676 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30); | |
2677 | } | |
9613c02b | 2678 | |
a72b64b9 | 2679 | dsi_vc_enable(dsidev, channel, 1); |
3de7a1dc | 2680 | |
d6049144 | 2681 | dsi->vc[channel].source = source; |
9ecd9684 TV |
2682 | |
2683 | return 0; | |
3de7a1dc TV |
2684 | } |
2685 | ||
1ffefe75 AT |
2686 | void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, |
2687 | bool enable) | |
3de7a1dc | 2688 | { |
a72b64b9 AT |
2689 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
2690 | ||
3de7a1dc TV |
2691 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); |
2692 | ||
a72b64b9 | 2693 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
61140c9a | 2694 | |
a72b64b9 AT |
2695 | dsi_vc_enable(dsidev, channel, 0); |
2696 | dsi_if_enable(dsidev, 0); | |
3de7a1dc | 2697 | |
a72b64b9 | 2698 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9); |
3de7a1dc | 2699 | |
a72b64b9 AT |
2700 | dsi_vc_enable(dsidev, channel, 1); |
2701 | dsi_if_enable(dsidev, 1); | |
3de7a1dc | 2702 | |
a72b64b9 | 2703 | dsi_force_tx_stop_mode_io(dsidev); |
8af6ff01 AT |
2704 | |
2705 | /* start the DDR clock by sending a NULL packet */ | |
2706 | if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable) | |
2707 | dsi_vc_send_null(dssdev, channel); | |
3de7a1dc | 2708 | } |
61140c9a | 2709 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
3de7a1dc | 2710 | |
a72b64b9 | 2711 | static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel) |
3de7a1dc | 2712 | { |
a72b64b9 | 2713 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc | 2714 | u32 val; |
a72b64b9 | 2715 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
3de7a1dc TV |
2716 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", |
2717 | (val >> 0) & 0xff, | |
2718 | (val >> 8) & 0xff, | |
2719 | (val >> 16) & 0xff, | |
2720 | (val >> 24) & 0xff); | |
2721 | } | |
2722 | } | |
2723 | ||
2724 | static void dsi_show_rx_ack_with_err(u16 err) | |
2725 | { | |
2726 | DSSERR("\tACK with ERROR (%#x):\n", err); | |
2727 | if (err & (1 << 0)) | |
2728 | DSSERR("\t\tSoT Error\n"); | |
2729 | if (err & (1 << 1)) | |
2730 | DSSERR("\t\tSoT Sync Error\n"); | |
2731 | if (err & (1 << 2)) | |
2732 | DSSERR("\t\tEoT Sync Error\n"); | |
2733 | if (err & (1 << 3)) | |
2734 | DSSERR("\t\tEscape Mode Entry Command Error\n"); | |
2735 | if (err & (1 << 4)) | |
2736 | DSSERR("\t\tLP Transmit Sync Error\n"); | |
2737 | if (err & (1 << 5)) | |
2738 | DSSERR("\t\tHS Receive Timeout Error\n"); | |
2739 | if (err & (1 << 6)) | |
2740 | DSSERR("\t\tFalse Control Error\n"); | |
2741 | if (err & (1 << 7)) | |
2742 | DSSERR("\t\t(reserved7)\n"); | |
2743 | if (err & (1 << 8)) | |
2744 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); | |
2745 | if (err & (1 << 9)) | |
2746 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); | |
2747 | if (err & (1 << 10)) | |
2748 | DSSERR("\t\tChecksum Error\n"); | |
2749 | if (err & (1 << 11)) | |
2750 | DSSERR("\t\tData type not recognized\n"); | |
2751 | if (err & (1 << 12)) | |
2752 | DSSERR("\t\tInvalid VC ID\n"); | |
2753 | if (err & (1 << 13)) | |
2754 | DSSERR("\t\tInvalid Transmission Length\n"); | |
2755 | if (err & (1 << 14)) | |
2756 | DSSERR("\t\t(reserved14)\n"); | |
2757 | if (err & (1 << 15)) | |
2758 | DSSERR("\t\tDSI Protocol Violation\n"); | |
2759 | } | |
2760 | ||
a72b64b9 AT |
2761 | static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev, |
2762 | int channel) | |
3de7a1dc TV |
2763 | { |
2764 | /* RX_FIFO_NOT_EMPTY */ | |
a72b64b9 | 2765 | while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { |
3de7a1dc TV |
2766 | u32 val; |
2767 | u8 dt; | |
a72b64b9 | 2768 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
86a7867e | 2769 | DSSERR("\trawval %#08x\n", val); |
3de7a1dc | 2770 | dt = FLD_GET(val, 5, 0); |
7a7c48f9 | 2771 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
2772 | u16 err = FLD_GET(val, 23, 8); |
2773 | dsi_show_rx_ack_with_err(err); | |
7a7c48f9 | 2774 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { |
86a7867e | 2775 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
3de7a1dc | 2776 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2777 | } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { |
86a7867e | 2778 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
3de7a1dc | 2779 | FLD_GET(val, 23, 8)); |
7a7c48f9 | 2780 | } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { |
86a7867e | 2781 | DSSERR("\tDCS long response, len %d\n", |
3de7a1dc | 2782 | FLD_GET(val, 23, 8)); |
a72b64b9 | 2783 | dsi_vc_flush_long_data(dsidev, channel); |
3de7a1dc TV |
2784 | } else { |
2785 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
2786 | } | |
2787 | } | |
2788 | return 0; | |
2789 | } | |
2790 | ||
a72b64b9 | 2791 | static int dsi_vc_send_bta(struct platform_device *dsidev, int channel) |
3de7a1dc | 2792 | { |
f1da39d9 AT |
2793 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
2794 | ||
2795 | if (dsi->debug_write || dsi->debug_read) | |
3de7a1dc TV |
2796 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
2797 | ||
a72b64b9 | 2798 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2799 | |
a72b64b9 AT |
2800 | /* RX_FIFO_NOT_EMPTY */ |
2801 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
3de7a1dc | 2802 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); |
a72b64b9 | 2803 | dsi_vc_flush_receive_data(dsidev, channel); |
3de7a1dc TV |
2804 | } |
2805 | ||
a72b64b9 | 2806 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ |
3de7a1dc | 2807 | |
968f8e97 TV |
2808 | /* flush posted write */ |
2809 | dsi_read_reg(dsidev, DSI_VC_CTRL(channel)); | |
2810 | ||
3de7a1dc TV |
2811 | return 0; |
2812 | } | |
2813 | ||
1ffefe75 | 2814 | int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 2815 | { |
a72b64b9 | 2816 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f36a06e7 | 2817 | DECLARE_COMPLETION_ONSTACK(completion); |
3de7a1dc TV |
2818 | int r = 0; |
2819 | u32 err; | |
2820 | ||
a72b64b9 | 2821 | r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler, |
f36a06e7 TV |
2822 | &completion, DSI_VC_IRQ_BTA); |
2823 | if (r) | |
2824 | goto err0; | |
3de7a1dc | 2825 | |
a72b64b9 | 2826 | r = dsi_register_isr(dsidev, dsi_completion_handler, &completion, |
773b30b2 | 2827 | DSI_IRQ_ERROR_MASK); |
3de7a1dc | 2828 | if (r) |
f36a06e7 | 2829 | goto err1; |
3de7a1dc | 2830 | |
a72b64b9 | 2831 | r = dsi_vc_send_bta(dsidev, channel); |
773b30b2 TV |
2832 | if (r) |
2833 | goto err2; | |
2834 | ||
f36a06e7 | 2835 | if (wait_for_completion_timeout(&completion, |
3de7a1dc TV |
2836 | msecs_to_jiffies(500)) == 0) { |
2837 | DSSERR("Failed to receive BTA\n"); | |
2838 | r = -EIO; | |
773b30b2 | 2839 | goto err2; |
3de7a1dc TV |
2840 | } |
2841 | ||
a72b64b9 | 2842 | err = dsi_get_errors(dsidev); |
3de7a1dc TV |
2843 | if (err) { |
2844 | DSSERR("Error while sending BTA: %x\n", err); | |
2845 | r = -EIO; | |
773b30b2 | 2846 | goto err2; |
3de7a1dc | 2847 | } |
773b30b2 | 2848 | err2: |
a72b64b9 | 2849 | dsi_unregister_isr(dsidev, dsi_completion_handler, &completion, |
773b30b2 | 2850 | DSI_IRQ_ERROR_MASK); |
f36a06e7 | 2851 | err1: |
a72b64b9 | 2852 | dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler, |
f36a06e7 TV |
2853 | &completion, DSI_VC_IRQ_BTA); |
2854 | err0: | |
3de7a1dc TV |
2855 | return r; |
2856 | } | |
2857 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); | |
2858 | ||
a72b64b9 AT |
2859 | static inline void dsi_vc_write_long_header(struct platform_device *dsidev, |
2860 | int channel, u8 data_type, u16 len, u8 ecc) | |
3de7a1dc | 2861 | { |
f1da39d9 | 2862 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2863 | u32 val; |
2864 | u8 data_id; | |
2865 | ||
a72b64b9 | 2866 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2867 | |
f1da39d9 | 2868 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
2869 | |
2870 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | | |
2871 | FLD_VAL(ecc, 31, 24); | |
2872 | ||
a72b64b9 | 2873 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val); |
3de7a1dc TV |
2874 | } |
2875 | ||
a72b64b9 AT |
2876 | static inline void dsi_vc_write_long_payload(struct platform_device *dsidev, |
2877 | int channel, u8 b1, u8 b2, u8 b3, u8 b4) | |
3de7a1dc TV |
2878 | { |
2879 | u32 val; | |
2880 | ||
2881 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; | |
2882 | ||
2883 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", | |
2884 | b1, b2, b3, b4, val); */ | |
2885 | ||
a72b64b9 | 2886 | dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); |
3de7a1dc TV |
2887 | } |
2888 | ||
a72b64b9 AT |
2889 | static int dsi_vc_send_long(struct platform_device *dsidev, int channel, |
2890 | u8 data_type, u8 *data, u16 len, u8 ecc) | |
3de7a1dc TV |
2891 | { |
2892 | /*u32 val; */ | |
f1da39d9 | 2893 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2894 | int i; |
2895 | u8 *p; | |
2896 | int r = 0; | |
2897 | u8 b1, b2, b3, b4; | |
2898 | ||
f1da39d9 | 2899 | if (dsi->debug_write) |
3de7a1dc TV |
2900 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); |
2901 | ||
2902 | /* len + header */ | |
f1da39d9 | 2903 | if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) { |
3de7a1dc TV |
2904 | DSSERR("unable to send long packet: packet too long.\n"); |
2905 | return -EINVAL; | |
2906 | } | |
2907 | ||
d6049144 | 2908 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 2909 | |
a72b64b9 | 2910 | dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc); |
3de7a1dc | 2911 | |
3de7a1dc TV |
2912 | p = data; |
2913 | for (i = 0; i < len >> 2; i++) { | |
f1da39d9 | 2914 | if (dsi->debug_write) |
3de7a1dc | 2915 | DSSDBG("\tsending full packet %d\n", i); |
3de7a1dc TV |
2916 | |
2917 | b1 = *p++; | |
2918 | b2 = *p++; | |
2919 | b3 = *p++; | |
2920 | b4 = *p++; | |
2921 | ||
a72b64b9 | 2922 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4); |
3de7a1dc TV |
2923 | } |
2924 | ||
2925 | i = len % 4; | |
2926 | if (i) { | |
2927 | b1 = 0; b2 = 0; b3 = 0; | |
2928 | ||
f1da39d9 | 2929 | if (dsi->debug_write) |
3de7a1dc TV |
2930 | DSSDBG("\tsending remainder bytes %d\n", i); |
2931 | ||
2932 | switch (i) { | |
2933 | case 3: | |
2934 | b1 = *p++; | |
2935 | b2 = *p++; | |
2936 | b3 = *p++; | |
2937 | break; | |
2938 | case 2: | |
2939 | b1 = *p++; | |
2940 | b2 = *p++; | |
2941 | break; | |
2942 | case 1: | |
2943 | b1 = *p++; | |
2944 | break; | |
2945 | } | |
2946 | ||
a72b64b9 | 2947 | dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0); |
3de7a1dc TV |
2948 | } |
2949 | ||
2950 | return r; | |
2951 | } | |
2952 | ||
a72b64b9 AT |
2953 | static int dsi_vc_send_short(struct platform_device *dsidev, int channel, |
2954 | u8 data_type, u16 data, u8 ecc) | |
3de7a1dc | 2955 | { |
f1da39d9 | 2956 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
2957 | u32 r; |
2958 | u8 data_id; | |
2959 | ||
a72b64b9 | 2960 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 2961 | |
f1da39d9 | 2962 | if (dsi->debug_write) |
3de7a1dc TV |
2963 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", |
2964 | channel, | |
2965 | data_type, data & 0xff, (data >> 8) & 0xff); | |
2966 | ||
d6049144 | 2967 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4); |
3de7a1dc | 2968 | |
a72b64b9 | 2969 | if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) { |
3de7a1dc TV |
2970 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); |
2971 | return -EINVAL; | |
2972 | } | |
2973 | ||
f1da39d9 | 2974 | data_id = data_type | dsi->vc[channel].vc_id << 6; |
3de7a1dc TV |
2975 | |
2976 | r = (data_id << 0) | (data << 8) | (ecc << 24); | |
2977 | ||
a72b64b9 | 2978 | dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r); |
3de7a1dc TV |
2979 | |
2980 | return 0; | |
2981 | } | |
2982 | ||
1ffefe75 | 2983 | int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel) |
3de7a1dc | 2984 | { |
a72b64b9 | 2985 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
a72b64b9 | 2986 | |
18b7d099 AT |
2987 | return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL, |
2988 | 0, 0); | |
3de7a1dc TV |
2989 | } |
2990 | EXPORT_SYMBOL(dsi_vc_send_null); | |
2991 | ||
6ff8aa31 AT |
2992 | static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev, |
2993 | int channel, u8 *data, int len, enum dss_dsi_content_type type) | |
3de7a1dc | 2994 | { |
a72b64b9 | 2995 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
2996 | int r; |
2997 | ||
6ff8aa31 AT |
2998 | if (len == 0) { |
2999 | BUG_ON(type == DSS_DSI_CONTENT_DCS); | |
7a7c48f9 | 3000 | r = dsi_vc_send_short(dsidev, channel, |
6ff8aa31 AT |
3001 | MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); |
3002 | } else if (len == 1) { | |
3003 | r = dsi_vc_send_short(dsidev, channel, | |
3004 | type == DSS_DSI_CONTENT_GENERIC ? | |
3005 | MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : | |
7a7c48f9 | 3006 | MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); |
3de7a1dc | 3007 | } else if (len == 2) { |
7a7c48f9 | 3008 | r = dsi_vc_send_short(dsidev, channel, |
6ff8aa31 AT |
3009 | type == DSS_DSI_CONTENT_GENERIC ? |
3010 | MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : | |
7a7c48f9 | 3011 | MIPI_DSI_DCS_SHORT_WRITE_PARAM, |
3de7a1dc TV |
3012 | data[0] | (data[1] << 8), 0); |
3013 | } else { | |
6ff8aa31 AT |
3014 | r = dsi_vc_send_long(dsidev, channel, |
3015 | type == DSS_DSI_CONTENT_GENERIC ? | |
3016 | MIPI_DSI_GENERIC_LONG_WRITE : | |
3017 | MIPI_DSI_DCS_LONG_WRITE, data, len, 0); | |
3de7a1dc TV |
3018 | } |
3019 | ||
3020 | return r; | |
3021 | } | |
6ff8aa31 AT |
3022 | |
3023 | int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, | |
3024 | u8 *data, int len) | |
3025 | { | |
3026 | return dsi_vc_write_nosync_common(dssdev, channel, data, len, | |
3027 | DSS_DSI_CONTENT_DCS); | |
3028 | } | |
3de7a1dc TV |
3029 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); |
3030 | ||
6ff8aa31 AT |
3031 | int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, |
3032 | u8 *data, int len) | |
3033 | { | |
3034 | return dsi_vc_write_nosync_common(dssdev, channel, data, len, | |
3035 | DSS_DSI_CONTENT_GENERIC); | |
3036 | } | |
3037 | EXPORT_SYMBOL(dsi_vc_generic_write_nosync); | |
3038 | ||
3039 | static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel, | |
3040 | u8 *data, int len, enum dss_dsi_content_type type) | |
3de7a1dc | 3041 | { |
a72b64b9 | 3042 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
3043 | int r; |
3044 | ||
6ff8aa31 | 3045 | r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type); |
3de7a1dc | 3046 | if (r) |
5d68e032 | 3047 | goto err; |
3de7a1dc | 3048 | |
1ffefe75 | 3049 | r = dsi_vc_send_bta_sync(dssdev, channel); |
5d68e032 TV |
3050 | if (r) |
3051 | goto err; | |
3de7a1dc | 3052 | |
a72b64b9 AT |
3053 | /* RX_FIFO_NOT_EMPTY */ |
3054 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { | |
b63ac1e3 | 3055 | DSSERR("rx fifo not empty after write, dumping data:\n"); |
a72b64b9 | 3056 | dsi_vc_flush_receive_data(dsidev, channel); |
b63ac1e3 TV |
3057 | r = -EIO; |
3058 | goto err; | |
3059 | } | |
3060 | ||
5d68e032 TV |
3061 | return 0; |
3062 | err: | |
6ff8aa31 | 3063 | DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", |
5d68e032 | 3064 | channel, data[0], len); |
3de7a1dc TV |
3065 | return r; |
3066 | } | |
6ff8aa31 AT |
3067 | |
3068 | int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, | |
3069 | int len) | |
3070 | { | |
3071 | return dsi_vc_write_common(dssdev, channel, data, len, | |
3072 | DSS_DSI_CONTENT_DCS); | |
3073 | } | |
3de7a1dc TV |
3074 | EXPORT_SYMBOL(dsi_vc_dcs_write); |
3075 | ||
6ff8aa31 AT |
3076 | int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, |
3077 | int len) | |
3078 | { | |
3079 | return dsi_vc_write_common(dssdev, channel, data, len, | |
3080 | DSS_DSI_CONTENT_GENERIC); | |
3081 | } | |
3082 | EXPORT_SYMBOL(dsi_vc_generic_write); | |
3083 | ||
1ffefe75 | 3084 | int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd) |
828c48f8 | 3085 | { |
1ffefe75 | 3086 | return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1); |
828c48f8 TV |
3087 | } |
3088 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); | |
3089 | ||
6ff8aa31 AT |
3090 | int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel) |
3091 | { | |
3092 | return dsi_vc_generic_write(dssdev, channel, NULL, 0); | |
3093 | } | |
3094 | EXPORT_SYMBOL(dsi_vc_generic_write_0); | |
3095 | ||
1ffefe75 AT |
3096 | int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, |
3097 | u8 param) | |
828c48f8 TV |
3098 | { |
3099 | u8 buf[2]; | |
3100 | buf[0] = dcs_cmd; | |
3101 | buf[1] = param; | |
1ffefe75 | 3102 | return dsi_vc_dcs_write(dssdev, channel, buf, 2); |
828c48f8 TV |
3103 | } |
3104 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); | |
3105 | ||
6ff8aa31 AT |
3106 | int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel, |
3107 | u8 param) | |
3108 | { | |
3109 | return dsi_vc_generic_write(dssdev, channel, ¶m, 1); | |
3110 | } | |
3111 | EXPORT_SYMBOL(dsi_vc_generic_write_1); | |
3112 | ||
3113 | int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel, | |
3114 | u8 param1, u8 param2) | |
3115 | { | |
3116 | u8 buf[2]; | |
3117 | buf[0] = param1; | |
3118 | buf[1] = param2; | |
3119 | return dsi_vc_generic_write(dssdev, channel, buf, 2); | |
3120 | } | |
3121 | EXPORT_SYMBOL(dsi_vc_generic_write_2); | |
3122 | ||
b850975c AT |
3123 | static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev, |
3124 | int channel, u8 dcs_cmd) | |
3de7a1dc | 3125 | { |
a72b64b9 | 3126 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 3127 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3128 | int r; |
3129 | ||
f1da39d9 | 3130 | if (dsi->debug_read) |
b850975c AT |
3131 | DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", |
3132 | channel, dcs_cmd); | |
3de7a1dc | 3133 | |
7a7c48f9 | 3134 | r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); |
b850975c AT |
3135 | if (r) { |
3136 | DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" | |
3137 | " failed\n", channel, dcs_cmd); | |
3138 | return r; | |
3139 | } | |
3de7a1dc | 3140 | |
b850975c AT |
3141 | return 0; |
3142 | } | |
3143 | ||
b3b89c05 AT |
3144 | static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev, |
3145 | int channel, u8 *reqdata, int reqlen) | |
3146 | { | |
3147 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3148 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3149 | u16 data; | |
3150 | u8 data_type; | |
3151 | int r; | |
3152 | ||
3153 | if (dsi->debug_read) | |
3154 | DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", | |
3155 | channel, reqlen); | |
3156 | ||
3157 | if (reqlen == 0) { | |
3158 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; | |
3159 | data = 0; | |
3160 | } else if (reqlen == 1) { | |
3161 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; | |
3162 | data = reqdata[0]; | |
3163 | } else if (reqlen == 2) { | |
3164 | data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; | |
3165 | data = reqdata[0] | (reqdata[1] << 8); | |
3166 | } else { | |
3167 | BUG(); | |
c6eee968 | 3168 | return -EINVAL; |
b3b89c05 AT |
3169 | } |
3170 | ||
3171 | r = dsi_vc_send_short(dsidev, channel, data_type, data, 0); | |
3172 | if (r) { | |
3173 | DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" | |
3174 | " failed\n", channel, reqlen); | |
3175 | return r; | |
3176 | } | |
3177 | ||
3178 | return 0; | |
3179 | } | |
3180 | ||
3181 | static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel, | |
3182 | u8 *buf, int buflen, enum dss_dsi_content_type type) | |
b850975c AT |
3183 | { |
3184 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3185 | u32 val; | |
3186 | u8 dt; | |
3187 | int r; | |
3de7a1dc TV |
3188 | |
3189 | /* RX_FIFO_NOT_EMPTY */ | |
a72b64b9 | 3190 | if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) { |
3de7a1dc | 3191 | DSSERR("RX fifo empty when trying to read.\n"); |
5d68e032 TV |
3192 | r = -EIO; |
3193 | goto err; | |
3de7a1dc TV |
3194 | } |
3195 | ||
a72b64b9 | 3196 | val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel)); |
f1da39d9 | 3197 | if (dsi->debug_read) |
3de7a1dc TV |
3198 | DSSDBG("\theader: %08x\n", val); |
3199 | dt = FLD_GET(val, 5, 0); | |
7a7c48f9 | 3200 | if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { |
3de7a1dc TV |
3201 | u16 err = FLD_GET(val, 23, 8); |
3202 | dsi_show_rx_ack_with_err(err); | |
5d68e032 TV |
3203 | r = -EIO; |
3204 | goto err; | |
3de7a1dc | 3205 | |
b3b89c05 AT |
3206 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3207 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : | |
3208 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { | |
3de7a1dc | 3209 | u8 data = FLD_GET(val, 15, 8); |
f1da39d9 | 3210 | if (dsi->debug_read) |
b3b89c05 AT |
3211 | DSSDBG("\t%s short response, 1 byte: %02x\n", |
3212 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3213 | "DCS", data); | |
3de7a1dc | 3214 | |
5d68e032 TV |
3215 | if (buflen < 1) { |
3216 | r = -EIO; | |
3217 | goto err; | |
3218 | } | |
3de7a1dc TV |
3219 | |
3220 | buf[0] = data; | |
3221 | ||
3222 | return 1; | |
b3b89c05 AT |
3223 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3224 | MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : | |
3225 | MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { | |
3de7a1dc | 3226 | u16 data = FLD_GET(val, 23, 8); |
f1da39d9 | 3227 | if (dsi->debug_read) |
b3b89c05 AT |
3228 | DSSDBG("\t%s short response, 2 byte: %04x\n", |
3229 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3230 | "DCS", data); | |
3de7a1dc | 3231 | |
5d68e032 TV |
3232 | if (buflen < 2) { |
3233 | r = -EIO; | |
3234 | goto err; | |
3235 | } | |
3de7a1dc TV |
3236 | |
3237 | buf[0] = data & 0xff; | |
3238 | buf[1] = (data >> 8) & 0xff; | |
3239 | ||
3240 | return 2; | |
b3b89c05 AT |
3241 | } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? |
3242 | MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : | |
3243 | MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { | |
3de7a1dc TV |
3244 | int w; |
3245 | int len = FLD_GET(val, 23, 8); | |
f1da39d9 | 3246 | if (dsi->debug_read) |
b3b89c05 AT |
3247 | DSSDBG("\t%s long response, len %d\n", |
3248 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : | |
3249 | "DCS", len); | |
3de7a1dc | 3250 | |
5d68e032 TV |
3251 | if (len > buflen) { |
3252 | r = -EIO; | |
3253 | goto err; | |
3254 | } | |
3de7a1dc TV |
3255 | |
3256 | /* two byte checksum ends the packet, not included in len */ | |
3257 | for (w = 0; w < len + 2;) { | |
3258 | int b; | |
a72b64b9 AT |
3259 | val = dsi_read_reg(dsidev, |
3260 | DSI_VC_SHORT_PACKET_HEADER(channel)); | |
f1da39d9 | 3261 | if (dsi->debug_read) |
3de7a1dc TV |
3262 | DSSDBG("\t\t%02x %02x %02x %02x\n", |
3263 | (val >> 0) & 0xff, | |
3264 | (val >> 8) & 0xff, | |
3265 | (val >> 16) & 0xff, | |
3266 | (val >> 24) & 0xff); | |
3267 | ||
3268 | for (b = 0; b < 4; ++b) { | |
3269 | if (w < len) | |
3270 | buf[w] = (val >> (b * 8)) & 0xff; | |
3271 | /* we discard the 2 byte checksum */ | |
3272 | ++w; | |
3273 | } | |
3274 | } | |
3275 | ||
3276 | return len; | |
3de7a1dc TV |
3277 | } else { |
3278 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
5d68e032 TV |
3279 | r = -EIO; |
3280 | goto err; | |
3de7a1dc | 3281 | } |
5d68e032 | 3282 | |
5d68e032 | 3283 | err: |
b3b89c05 AT |
3284 | DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, |
3285 | type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); | |
b850975c | 3286 | |
5d68e032 | 3287 | return r; |
b850975c AT |
3288 | } |
3289 | ||
3290 | int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, | |
3291 | u8 *buf, int buflen) | |
3292 | { | |
3293 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3294 | int r; | |
3295 | ||
3296 | r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd); | |
3297 | if (r) | |
3298 | goto err; | |
5d68e032 | 3299 | |
b850975c AT |
3300 | r = dsi_vc_send_bta_sync(dssdev, channel); |
3301 | if (r) | |
3302 | goto err; | |
3303 | ||
b3b89c05 AT |
3304 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, |
3305 | DSS_DSI_CONTENT_DCS); | |
b850975c AT |
3306 | if (r < 0) |
3307 | goto err; | |
3308 | ||
3309 | if (r != buflen) { | |
3310 | r = -EIO; | |
3311 | goto err; | |
3312 | } | |
3313 | ||
3314 | return 0; | |
3315 | err: | |
3316 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); | |
3317 | return r; | |
3de7a1dc TV |
3318 | } |
3319 | EXPORT_SYMBOL(dsi_vc_dcs_read); | |
3320 | ||
b3b89c05 AT |
3321 | static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, |
3322 | u8 *reqdata, int reqlen, u8 *buf, int buflen) | |
3323 | { | |
3324 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3325 | int r; | |
3326 | ||
3327 | r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen); | |
3328 | if (r) | |
3329 | return r; | |
3330 | ||
3331 | r = dsi_vc_send_bta_sync(dssdev, channel); | |
3332 | if (r) | |
3333 | return r; | |
3334 | ||
3335 | r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen, | |
3336 | DSS_DSI_CONTENT_GENERIC); | |
3337 | if (r < 0) | |
3338 | return r; | |
3339 | ||
3340 | if (r != buflen) { | |
3341 | r = -EIO; | |
3342 | return r; | |
3343 | } | |
3344 | ||
3345 | return 0; | |
3346 | } | |
3347 | ||
3348 | int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf, | |
3349 | int buflen) | |
3350 | { | |
3351 | int r; | |
3352 | ||
3353 | r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen); | |
3354 | if (r) { | |
3355 | DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel); | |
3356 | return r; | |
3357 | } | |
3358 | ||
3359 | return 0; | |
3360 | } | |
3361 | EXPORT_SYMBOL(dsi_vc_generic_read_0); | |
3362 | ||
3363 | int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param, | |
3364 | u8 *buf, int buflen) | |
3365 | { | |
3366 | int r; | |
3367 | ||
3368 | r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen); | |
3369 | if (r) { | |
3370 | DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel); | |
3371 | return r; | |
3372 | } | |
3373 | ||
3374 | return 0; | |
3375 | } | |
3376 | EXPORT_SYMBOL(dsi_vc_generic_read_1); | |
3377 | ||
3378 | int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel, | |
3379 | u8 param1, u8 param2, u8 *buf, int buflen) | |
3380 | { | |
3381 | int r; | |
3382 | u8 reqdata[2]; | |
3383 | ||
3384 | reqdata[0] = param1; | |
3385 | reqdata[1] = param2; | |
3386 | ||
3387 | r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen); | |
3388 | if (r) { | |
3389 | DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel); | |
3390 | return r; | |
3391 | } | |
3392 | ||
3393 | return 0; | |
3394 | } | |
3395 | EXPORT_SYMBOL(dsi_vc_generic_read_2); | |
3396 | ||
1ffefe75 AT |
3397 | int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, |
3398 | u16 len) | |
3de7a1dc | 3399 | { |
a72b64b9 AT |
3400 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3401 | ||
7a7c48f9 AT |
3402 | return dsi_vc_send_short(dsidev, channel, |
3403 | MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); | |
3de7a1dc TV |
3404 | } |
3405 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); | |
3406 | ||
a72b64b9 | 3407 | static int dsi_enter_ulps(struct platform_device *dsidev) |
40885ab3 | 3408 | { |
f1da39d9 | 3409 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
40885ab3 | 3410 | DECLARE_COMPLETION_ONSTACK(completion); |
522a0c2f TV |
3411 | int r, i; |
3412 | unsigned mask; | |
40885ab3 TV |
3413 | |
3414 | DSSDBGF(); | |
3415 | ||
a72b64b9 | 3416 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
40885ab3 | 3417 | |
f1da39d9 | 3418 | WARN_ON(dsi->ulps_enabled); |
40885ab3 | 3419 | |
f1da39d9 | 3420 | if (dsi->ulps_enabled) |
40885ab3 TV |
3421 | return 0; |
3422 | ||
6cc78aa9 | 3423 | /* DDR_CLK_ALWAYS_ON */ |
a72b64b9 | 3424 | if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) { |
6cc78aa9 TV |
3425 | dsi_if_enable(dsidev, 0); |
3426 | REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13); | |
3427 | dsi_if_enable(dsidev, 1); | |
40885ab3 TV |
3428 | } |
3429 | ||
a72b64b9 AT |
3430 | dsi_sync_vc(dsidev, 0); |
3431 | dsi_sync_vc(dsidev, 1); | |
3432 | dsi_sync_vc(dsidev, 2); | |
3433 | dsi_sync_vc(dsidev, 3); | |
40885ab3 | 3434 | |
a72b64b9 | 3435 | dsi_force_tx_stop_mode_io(dsidev); |
40885ab3 | 3436 | |
a72b64b9 AT |
3437 | dsi_vc_enable(dsidev, 0, false); |
3438 | dsi_vc_enable(dsidev, 1, false); | |
3439 | dsi_vc_enable(dsidev, 2, false); | |
3440 | dsi_vc_enable(dsidev, 3, false); | |
40885ab3 | 3441 | |
a72b64b9 | 3442 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ |
40885ab3 TV |
3443 | DSSERR("HS busy when enabling ULPS\n"); |
3444 | return -EIO; | |
3445 | } | |
3446 | ||
a72b64b9 | 3447 | if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ |
40885ab3 TV |
3448 | DSSERR("LP busy when enabling ULPS\n"); |
3449 | return -EIO; | |
3450 | } | |
3451 | ||
a72b64b9 | 3452 | r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3453 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3454 | if (r) | |
3455 | return r; | |
3456 | ||
522a0c2f TV |
3457 | mask = 0; |
3458 | ||
3459 | for (i = 0; i < dsi->num_lanes_supported; ++i) { | |
3460 | if (dsi->lanes[i].function == DSI_LANE_UNUSED) | |
3461 | continue; | |
3462 | mask |= 1 << i; | |
3463 | } | |
40885ab3 TV |
3464 | /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ |
3465 | /* LANEx_ULPS_SIG2 */ | |
522a0c2f | 3466 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5); |
40885ab3 | 3467 | |
a702c859 TV |
3468 | /* flush posted write and wait for SCP interface to finish the write */ |
3469 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); | |
40885ab3 TV |
3470 | |
3471 | if (wait_for_completion_timeout(&completion, | |
3472 | msecs_to_jiffies(1000)) == 0) { | |
3473 | DSSERR("ULPS enable timeout\n"); | |
3474 | r = -EIO; | |
3475 | goto err; | |
3476 | } | |
3477 | ||
a72b64b9 | 3478 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3479 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3480 | ||
8ef0e614 | 3481 | /* Reset LANEx_ULPS_SIG2 */ |
522a0c2f | 3482 | REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5); |
8ef0e614 | 3483 | |
a702c859 TV |
3484 | /* flush posted write and wait for SCP interface to finish the write */ |
3485 | dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2); | |
8ef0e614 | 3486 | |
a72b64b9 | 3487 | dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS); |
40885ab3 | 3488 | |
a72b64b9 | 3489 | dsi_if_enable(dsidev, false); |
40885ab3 | 3490 | |
f1da39d9 | 3491 | dsi->ulps_enabled = true; |
40885ab3 TV |
3492 | |
3493 | return 0; | |
3494 | ||
3495 | err: | |
a72b64b9 | 3496 | dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion, |
40885ab3 TV |
3497 | DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); |
3498 | return r; | |
3499 | } | |
3500 | ||
a72b64b9 AT |
3501 | static void dsi_set_lp_rx_timeout(struct platform_device *dsidev, |
3502 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3503 | { |
3de7a1dc | 3504 | unsigned long fck; |
4ffa3571 TV |
3505 | unsigned long total_ticks; |
3506 | u32 r; | |
3de7a1dc | 3507 | |
4ffa3571 | 3508 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3509 | |
4ffa3571 | 3510 | /* ticks in DSI_FCK */ |
a72b64b9 | 3511 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3512 | |
a72b64b9 | 3513 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
3de7a1dc | 3514 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ |
4ffa3571 TV |
3515 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
3516 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ | |
3de7a1dc | 3517 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
a72b64b9 | 3518 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
3de7a1dc | 3519 | |
4ffa3571 TV |
3520 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3521 | ||
3522 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3523 | total_ticks, | |
3524 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3525 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3526 | } |
3527 | ||
a72b64b9 AT |
3528 | static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks, |
3529 | bool x8, bool x16) | |
3de7a1dc | 3530 | { |
3de7a1dc | 3531 | unsigned long fck; |
4ffa3571 TV |
3532 | unsigned long total_ticks; |
3533 | u32 r; | |
3534 | ||
3535 | BUG_ON(ticks > 0x1fff); | |
3de7a1dc TV |
3536 | |
3537 | /* ticks in DSI_FCK */ | |
a72b64b9 | 3538 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3539 | |
a72b64b9 | 3540 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 3541 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ |
4ffa3571 TV |
3542 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
3543 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ | |
3de7a1dc | 3544 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
a72b64b9 | 3545 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 3546 | |
4ffa3571 TV |
3547 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
3548 | ||
3549 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3550 | total_ticks, | |
3551 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", | |
3552 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3553 | } |
3554 | ||
a72b64b9 AT |
3555 | static void dsi_set_stop_state_counter(struct platform_device *dsidev, |
3556 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3557 | { |
3de7a1dc | 3558 | unsigned long fck; |
4ffa3571 TV |
3559 | unsigned long total_ticks; |
3560 | u32 r; | |
3de7a1dc | 3561 | |
4ffa3571 | 3562 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3563 | |
4ffa3571 | 3564 | /* ticks in DSI_FCK */ |
a72b64b9 | 3565 | fck = dsi_fclk_rate(dsidev); |
3de7a1dc | 3566 | |
a72b64b9 | 3567 | r = dsi_read_reg(dsidev, DSI_TIMING1); |
3de7a1dc | 3568 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ |
4ffa3571 TV |
3569 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
3570 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ | |
3de7a1dc | 3571 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
a72b64b9 | 3572 | dsi_write_reg(dsidev, DSI_TIMING1, r); |
3de7a1dc | 3573 | |
4ffa3571 TV |
3574 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3575 | ||
3576 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", | |
3577 | total_ticks, | |
3578 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3579 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
3580 | } |
3581 | ||
a72b64b9 AT |
3582 | static void dsi_set_hs_tx_timeout(struct platform_device *dsidev, |
3583 | unsigned ticks, bool x4, bool x16) | |
3de7a1dc | 3584 | { |
3de7a1dc | 3585 | unsigned long fck; |
4ffa3571 TV |
3586 | unsigned long total_ticks; |
3587 | u32 r; | |
3de7a1dc | 3588 | |
4ffa3571 | 3589 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 3590 | |
4ffa3571 | 3591 | /* ticks in TxByteClkHS */ |
a72b64b9 | 3592 | fck = dsi_get_txbyteclkhs(dsidev); |
3de7a1dc | 3593 | |
a72b64b9 | 3594 | r = dsi_read_reg(dsidev, DSI_TIMING2); |
3de7a1dc | 3595 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ |
4ffa3571 TV |
3596 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
3597 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ | |
3de7a1dc | 3598 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
a72b64b9 | 3599 | dsi_write_reg(dsidev, DSI_TIMING2, r); |
3de7a1dc | 3600 | |
4ffa3571 TV |
3601 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
3602 | ||
3603 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
3604 | total_ticks, | |
3605 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
3606 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc | 3607 | } |
8af6ff01 AT |
3608 | |
3609 | static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev) | |
3610 | { | |
3611 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3612 | int num_line_buffers; | |
3613 | ||
3614 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
e67458a8 | 3615 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
02c3960b | 3616 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
8af6ff01 | 3617 | unsigned line_buf_size = dsi_get_line_buf_size(dsidev); |
e67458a8 | 3618 | struct omap_video_timings *timings = &dsi->timings; |
8af6ff01 AT |
3619 | /* |
3620 | * Don't use line buffers if width is greater than the video | |
3621 | * port's line buffer size | |
3622 | */ | |
3623 | if (line_buf_size <= timings->x_res * bpp / 8) | |
3624 | num_line_buffers = 0; | |
3625 | else | |
3626 | num_line_buffers = 2; | |
3627 | } else { | |
3628 | /* Use maximum number of line buffers in command mode */ | |
3629 | num_line_buffers = 2; | |
3630 | } | |
3631 | ||
3632 | /* LINE_BUFFER */ | |
3633 | REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12); | |
3634 | } | |
3635 | ||
3636 | static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev) | |
3637 | { | |
3638 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
8af6ff01 AT |
3639 | bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end; |
3640 | bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end; | |
3641 | u32 r; | |
3642 | ||
3643 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
bd5a7b11 AT |
3644 | r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ |
3645 | r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ | |
3646 | r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ | |
8af6ff01 AT |
3647 | r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ |
3648 | r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */ | |
3649 | r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ | |
3650 | r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */ | |
3651 | dsi_write_reg(dsidev, DSI_CTRL, r); | |
3652 | } | |
3653 | ||
3654 | static void dsi_config_blanking_modes(struct omap_dss_device *dssdev) | |
3655 | { | |
3656 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3657 | int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode; | |
3658 | int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode; | |
3659 | int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode; | |
3660 | int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode; | |
3661 | u32 r; | |
3662 | ||
3663 | /* | |
3664 | * 0 = TX FIFO packets sent or LPS in corresponding blanking periods | |
3665 | * 1 = Long blanking packets are sent in corresponding blanking periods | |
3666 | */ | |
3667 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3668 | r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ | |
3669 | r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ | |
3670 | r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ | |
3671 | r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ | |
3672 | dsi_write_reg(dsidev, DSI_CTRL, r); | |
3673 | } | |
3674 | ||
6f28c296 AT |
3675 | /* |
3676 | * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 | |
3677 | * results in maximum transition time for data and clock lanes to enter and | |
3678 | * exit HS mode. Hence, this is the scenario where the least amount of command | |
3679 | * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS | |
3680 | * clock cycles that can be used to interleave command mode data in HS so that | |
3681 | * all scenarios are satisfied. | |
3682 | */ | |
3683 | static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, | |
3684 | int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) | |
3685 | { | |
3686 | int transition; | |
3687 | ||
3688 | /* | |
3689 | * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition | |
3690 | * time of data lanes only, if it isn't set, we need to consider HS | |
3691 | * transition time of both data and clock lanes. HS transition time | |
3692 | * of Scenario 3 is considered. | |
3693 | */ | |
3694 | if (ddr_alwon) { | |
3695 | transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; | |
3696 | } else { | |
3697 | int trans1, trans2; | |
3698 | trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; | |
3699 | trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + | |
3700 | enter_hs + 1; | |
3701 | transition = max(trans1, trans2); | |
3702 | } | |
3703 | ||
3704 | return blank > transition ? blank - transition : 0; | |
3705 | } | |
3706 | ||
3707 | /* | |
3708 | * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 | |
3709 | * results in maximum transition time for data lanes to enter and exit LP mode. | |
3710 | * Hence, this is the scenario where the least amount of command mode data can | |
3711 | * be interleaved. We program the minimum amount of bytes that can be | |
3712 | * interleaved in LP so that all scenarios are satisfied. | |
3713 | */ | |
3714 | static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, | |
3715 | int lp_clk_div, int tdsi_fclk) | |
3716 | { | |
3717 | int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ | |
3718 | int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ | |
3719 | int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ | |
3720 | int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ | |
3721 | int lp_inter; /* cmd mode data that can be interleaved, in bytes */ | |
3722 | ||
3723 | /* maximum LP transition time according to Scenario 1 */ | |
3724 | trans_lp = exit_hs + max(enter_hs, 2) + 1; | |
3725 | ||
3726 | /* CLKIN4DDR = 16 * TXBYTECLKHS */ | |
3727 | tlp_avail = thsbyte_clk * (blank - trans_lp); | |
3728 | ||
2e063c30 | 3729 | ttxclkesc = tdsi_fclk * lp_clk_div; |
6f28c296 AT |
3730 | |
3731 | lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - | |
3732 | 26) / 16; | |
3733 | ||
3734 | return max(lp_inter, 0); | |
3735 | } | |
3736 | ||
3737 | static void dsi_config_cmd_mode_interleaving(struct omap_dss_device *dssdev) | |
3738 | { | |
3739 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
3740 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
3741 | int blanking_mode; | |
3742 | int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; | |
3743 | int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; | |
3744 | int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; | |
3745 | int tclk_trail, ths_exit, exiths_clk; | |
3746 | bool ddr_alwon; | |
e67458a8 | 3747 | struct omap_video_timings *timings = &dsi->timings; |
02c3960b | 3748 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
6f28c296 AT |
3749 | int ndl = dsi->num_lanes_used - 1; |
3750 | int dsi_fclk_hsdiv = dssdev->clocks.dsi.regm_dsi + 1; | |
3751 | int hsa_interleave_hs = 0, hsa_interleave_lp = 0; | |
3752 | int hfp_interleave_hs = 0, hfp_interleave_lp = 0; | |
3753 | int hbp_interleave_hs = 0, hbp_interleave_lp = 0; | |
3754 | int bl_interleave_hs = 0, bl_interleave_lp = 0; | |
3755 | u32 r; | |
3756 | ||
3757 | r = dsi_read_reg(dsidev, DSI_CTRL); | |
3758 | blanking_mode = FLD_GET(r, 20, 20); | |
3759 | hfp_blanking_mode = FLD_GET(r, 21, 21); | |
3760 | hbp_blanking_mode = FLD_GET(r, 22, 22); | |
3761 | hsa_blanking_mode = FLD_GET(r, 23, 23); | |
3762 | ||
3763 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); | |
3764 | hbp = FLD_GET(r, 11, 0); | |
3765 | hfp = FLD_GET(r, 23, 12); | |
3766 | hsa = FLD_GET(r, 31, 24); | |
3767 | ||
3768 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); | |
3769 | ddr_clk_post = FLD_GET(r, 7, 0); | |
3770 | ddr_clk_pre = FLD_GET(r, 15, 8); | |
3771 | ||
3772 | r = dsi_read_reg(dsidev, DSI_VM_TIMING7); | |
3773 | exit_hs_mode_lat = FLD_GET(r, 15, 0); | |
3774 | enter_hs_mode_lat = FLD_GET(r, 31, 16); | |
3775 | ||
3776 | r = dsi_read_reg(dsidev, DSI_CLK_CTRL); | |
3777 | lp_clk_div = FLD_GET(r, 12, 0); | |
3778 | ddr_alwon = FLD_GET(r, 13, 13); | |
3779 | ||
3780 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); | |
3781 | ths_exit = FLD_GET(r, 7, 0); | |
3782 | ||
3783 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); | |
3784 | tclk_trail = FLD_GET(r, 15, 8); | |
3785 | ||
3786 | exiths_clk = ths_exit + tclk_trail; | |
3787 | ||
3788 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); | |
3789 | bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); | |
3790 | ||
3791 | if (!hsa_blanking_mode) { | |
3792 | hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, | |
3793 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3794 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3795 | hsa_interleave_lp = dsi_compute_interleave_lp(hsa, | |
3796 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3797 | lp_clk_div, dsi_fclk_hsdiv); | |
3798 | } | |
3799 | ||
3800 | if (!hfp_blanking_mode) { | |
3801 | hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, | |
3802 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3803 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3804 | hfp_interleave_lp = dsi_compute_interleave_lp(hfp, | |
3805 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3806 | lp_clk_div, dsi_fclk_hsdiv); | |
3807 | } | |
3808 | ||
3809 | if (!hbp_blanking_mode) { | |
3810 | hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, | |
3811 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3812 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3813 | ||
3814 | hbp_interleave_lp = dsi_compute_interleave_lp(hbp, | |
3815 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3816 | lp_clk_div, dsi_fclk_hsdiv); | |
3817 | } | |
3818 | ||
3819 | if (!blanking_mode) { | |
3820 | bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, | |
3821 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3822 | exiths_clk, ddr_clk_pre, ddr_clk_post); | |
3823 | ||
3824 | bl_interleave_lp = dsi_compute_interleave_lp(bllp, | |
3825 | enter_hs_mode_lat, exit_hs_mode_lat, | |
3826 | lp_clk_div, dsi_fclk_hsdiv); | |
3827 | } | |
3828 | ||
3829 | DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", | |
3830 | hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, | |
3831 | bl_interleave_hs); | |
3832 | ||
3833 | DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", | |
3834 | hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, | |
3835 | bl_interleave_lp); | |
3836 | ||
3837 | r = dsi_read_reg(dsidev, DSI_VM_TIMING4); | |
3838 | r = FLD_MOD(r, hsa_interleave_hs, 23, 16); | |
3839 | r = FLD_MOD(r, hfp_interleave_hs, 15, 8); | |
3840 | r = FLD_MOD(r, hbp_interleave_hs, 7, 0); | |
3841 | dsi_write_reg(dsidev, DSI_VM_TIMING4, r); | |
3842 | ||
3843 | r = dsi_read_reg(dsidev, DSI_VM_TIMING5); | |
3844 | r = FLD_MOD(r, hsa_interleave_lp, 23, 16); | |
3845 | r = FLD_MOD(r, hfp_interleave_lp, 15, 8); | |
3846 | r = FLD_MOD(r, hbp_interleave_lp, 7, 0); | |
3847 | dsi_write_reg(dsidev, DSI_VM_TIMING5, r); | |
3848 | ||
3849 | r = dsi_read_reg(dsidev, DSI_VM_TIMING6); | |
3850 | r = FLD_MOD(r, bl_interleave_hs, 31, 15); | |
3851 | r = FLD_MOD(r, bl_interleave_lp, 16, 0); | |
3852 | dsi_write_reg(dsidev, DSI_VM_TIMING6, r); | |
3853 | } | |
3854 | ||
3de7a1dc TV |
3855 | static int dsi_proto_config(struct omap_dss_device *dssdev) |
3856 | { | |
a72b64b9 | 3857 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
02c3960b | 3858 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3859 | u32 r; |
3860 | int buswidth = 0; | |
3861 | ||
a72b64b9 | 3862 | dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3863 | DSI_FIFO_SIZE_32, |
3864 | DSI_FIFO_SIZE_32, | |
3865 | DSI_FIFO_SIZE_32); | |
3de7a1dc | 3866 | |
a72b64b9 | 3867 | dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32, |
dd8079d6 TV |
3868 | DSI_FIFO_SIZE_32, |
3869 | DSI_FIFO_SIZE_32, | |
3870 | DSI_FIFO_SIZE_32); | |
3de7a1dc TV |
3871 | |
3872 | /* XXX what values for the timeouts? */ | |
a72b64b9 AT |
3873 | dsi_set_stop_state_counter(dsidev, 0x1000, false, false); |
3874 | dsi_set_ta_timeout(dsidev, 0x1fff, true, true); | |
3875 | dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true); | |
3876 | dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true); | |
3de7a1dc | 3877 | |
02c3960b | 3878 | switch (dsi_get_pixel_size(dsi->pix_fmt)) { |
3de7a1dc TV |
3879 | case 16: |
3880 | buswidth = 0; | |
3881 | break; | |
3882 | case 18: | |
3883 | buswidth = 1; | |
3884 | break; | |
3885 | case 24: | |
3886 | buswidth = 2; | |
3887 | break; | |
3888 | default: | |
3889 | BUG(); | |
c6eee968 | 3890 | return -EINVAL; |
3de7a1dc TV |
3891 | } |
3892 | ||
a72b64b9 | 3893 | r = dsi_read_reg(dsidev, DSI_CTRL); |
3de7a1dc TV |
3894 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ |
3895 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ | |
3896 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ | |
3897 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ | |
3898 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ | |
3899 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ | |
3de7a1dc TV |
3900 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ |
3901 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ | |
9613c02b AT |
3902 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
3903 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ | |
3904 | /* DCS_CMD_CODE, 1=start, 0=continue */ | |
3905 | r = FLD_MOD(r, 0, 25, 25); | |
3906 | } | |
3de7a1dc | 3907 | |
a72b64b9 | 3908 | dsi_write_reg(dsidev, DSI_CTRL, r); |
3de7a1dc | 3909 | |
8af6ff01 AT |
3910 | dsi_config_vp_num_line_buffers(dssdev); |
3911 | ||
3912 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3913 | dsi_config_vp_sync_events(dssdev); | |
3914 | dsi_config_blanking_modes(dssdev); | |
6f28c296 | 3915 | dsi_config_cmd_mode_interleaving(dssdev); |
8af6ff01 AT |
3916 | } |
3917 | ||
a72b64b9 AT |
3918 | dsi_vc_initial_config(dsidev, 0); |
3919 | dsi_vc_initial_config(dsidev, 1); | |
3920 | dsi_vc_initial_config(dsidev, 2); | |
3921 | dsi_vc_initial_config(dsidev, 3); | |
3de7a1dc TV |
3922 | |
3923 | return 0; | |
3924 | } | |
3925 | ||
3926 | static void dsi_proto_timings(struct omap_dss_device *dssdev) | |
3927 | { | |
a72b64b9 | 3928 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
db18644f | 3929 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
3930 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; |
3931 | unsigned tclk_pre, tclk_post; | |
3932 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; | |
3933 | unsigned ths_trail, ths_exit; | |
3934 | unsigned ddr_clk_pre, ddr_clk_post; | |
3935 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; | |
3936 | unsigned ths_eot; | |
db18644f | 3937 | int ndl = dsi->num_lanes_used - 1; |
3de7a1dc TV |
3938 | u32 r; |
3939 | ||
a72b64b9 | 3940 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0); |
3de7a1dc TV |
3941 | ths_prepare = FLD_GET(r, 31, 24); |
3942 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); | |
3943 | ths_zero = ths_prepare_ths_zero - ths_prepare; | |
3944 | ths_trail = FLD_GET(r, 15, 8); | |
3945 | ths_exit = FLD_GET(r, 7, 0); | |
3946 | ||
a72b64b9 | 3947 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1); |
3de7a1dc TV |
3948 | tlpx = FLD_GET(r, 22, 16) * 2; |
3949 | tclk_trail = FLD_GET(r, 15, 8); | |
3950 | tclk_zero = FLD_GET(r, 7, 0); | |
3951 | ||
a72b64b9 | 3952 | r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2); |
3de7a1dc TV |
3953 | tclk_prepare = FLD_GET(r, 7, 0); |
3954 | ||
3955 | /* min 8*UI */ | |
3956 | tclk_pre = 20; | |
3957 | /* min 60ns + 52*UI */ | |
a72b64b9 | 3958 | tclk_post = ns2ddr(dsidev, 60) + 26; |
3de7a1dc | 3959 | |
8af6ff01 | 3960 | ths_eot = DIV_ROUND_UP(4, ndl); |
3de7a1dc TV |
3961 | |
3962 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, | |
3963 | 4); | |
3964 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; | |
3965 | ||
3966 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); | |
3967 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); | |
3968 | ||
a72b64b9 | 3969 | r = dsi_read_reg(dsidev, DSI_CLK_TIMING); |
3de7a1dc TV |
3970 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); |
3971 | r = FLD_MOD(r, ddr_clk_post, 7, 0); | |
a72b64b9 | 3972 | dsi_write_reg(dsidev, DSI_CLK_TIMING, r); |
3de7a1dc TV |
3973 | |
3974 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", | |
3975 | ddr_clk_pre, | |
3976 | ddr_clk_post); | |
3977 | ||
3978 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + | |
3979 | DIV_ROUND_UP(ths_prepare, 4) + | |
3980 | DIV_ROUND_UP(ths_zero + 3, 4); | |
3981 | ||
3982 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; | |
3983 | ||
3984 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | | |
3985 | FLD_VAL(exit_hs_mode_lat, 15, 0); | |
a72b64b9 | 3986 | dsi_write_reg(dsidev, DSI_VM_TIMING7, r); |
3de7a1dc TV |
3987 | |
3988 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", | |
3989 | enter_hs_mode_lat, exit_hs_mode_lat); | |
8af6ff01 AT |
3990 | |
3991 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
3992 | /* TODO: Implement a video mode check_timings function */ | |
3993 | int hsa = dssdev->panel.dsi_vm_data.hsa; | |
3994 | int hfp = dssdev->panel.dsi_vm_data.hfp; | |
3995 | int hbp = dssdev->panel.dsi_vm_data.hbp; | |
3996 | int vsa = dssdev->panel.dsi_vm_data.vsa; | |
3997 | int vfp = dssdev->panel.dsi_vm_data.vfp; | |
3998 | int vbp = dssdev->panel.dsi_vm_data.vbp; | |
3999 | int window_sync = dssdev->panel.dsi_vm_data.window_sync; | |
4000 | bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end; | |
e67458a8 | 4001 | struct omap_video_timings *timings = &dsi->timings; |
02c3960b | 4002 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
8af6ff01 AT |
4003 | int tl, t_he, width_bytes; |
4004 | ||
4005 | t_he = hsync_end ? | |
4006 | ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; | |
4007 | ||
4008 | width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8); | |
4009 | ||
4010 | /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ | |
4011 | tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + | |
4012 | DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; | |
4013 | ||
4014 | DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, | |
4015 | hfp, hsync_end ? hsa : 0, tl); | |
4016 | DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, | |
4017 | vsa, timings->y_res); | |
4018 | ||
4019 | r = dsi_read_reg(dsidev, DSI_VM_TIMING1); | |
4020 | r = FLD_MOD(r, hbp, 11, 0); /* HBP */ | |
4021 | r = FLD_MOD(r, hfp, 23, 12); /* HFP */ | |
4022 | r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ | |
4023 | dsi_write_reg(dsidev, DSI_VM_TIMING1, r); | |
4024 | ||
4025 | r = dsi_read_reg(dsidev, DSI_VM_TIMING2); | |
4026 | r = FLD_MOD(r, vbp, 7, 0); /* VBP */ | |
4027 | r = FLD_MOD(r, vfp, 15, 8); /* VFP */ | |
4028 | r = FLD_MOD(r, vsa, 23, 16); /* VSA */ | |
4029 | r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ | |
4030 | dsi_write_reg(dsidev, DSI_VM_TIMING2, r); | |
4031 | ||
4032 | r = dsi_read_reg(dsidev, DSI_VM_TIMING3); | |
4033 | r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */ | |
4034 | r = FLD_MOD(r, tl, 31, 16); /* TL */ | |
4035 | dsi_write_reg(dsidev, DSI_VM_TIMING3, r); | |
4036 | } | |
4037 | } | |
4038 | ||
e4a9e94c TV |
4039 | int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev, |
4040 | const struct omap_dsi_pin_config *pin_cfg) | |
4041 | { | |
4042 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4043 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4044 | int num_pins; | |
4045 | const int *pins; | |
4046 | struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; | |
4047 | int num_lanes; | |
4048 | int i; | |
4049 | ||
4050 | static const enum dsi_lane_function functions[] = { | |
4051 | DSI_LANE_CLK, | |
4052 | DSI_LANE_DATA1, | |
4053 | DSI_LANE_DATA2, | |
4054 | DSI_LANE_DATA3, | |
4055 | DSI_LANE_DATA4, | |
4056 | }; | |
4057 | ||
4058 | num_pins = pin_cfg->num_pins; | |
4059 | pins = pin_cfg->pins; | |
4060 | ||
4061 | if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 | |
4062 | || num_pins % 2 != 0) | |
4063 | return -EINVAL; | |
4064 | ||
4065 | for (i = 0; i < DSI_MAX_NR_LANES; ++i) | |
4066 | lanes[i].function = DSI_LANE_UNUSED; | |
4067 | ||
4068 | num_lanes = 0; | |
4069 | ||
4070 | for (i = 0; i < num_pins; i += 2) { | |
4071 | u8 lane, pol; | |
4072 | int dx, dy; | |
4073 | ||
4074 | dx = pins[i]; | |
4075 | dy = pins[i + 1]; | |
4076 | ||
4077 | if (dx < 0 || dx >= dsi->num_lanes_supported * 2) | |
4078 | return -EINVAL; | |
4079 | ||
4080 | if (dy < 0 || dy >= dsi->num_lanes_supported * 2) | |
4081 | return -EINVAL; | |
4082 | ||
4083 | if (dx & 1) { | |
4084 | if (dy != dx - 1) | |
4085 | return -EINVAL; | |
4086 | pol = 1; | |
4087 | } else { | |
4088 | if (dy != dx + 1) | |
4089 | return -EINVAL; | |
4090 | pol = 0; | |
4091 | } | |
4092 | ||
4093 | lane = dx / 2; | |
4094 | ||
4095 | lanes[lane].function = functions[i / 2]; | |
4096 | lanes[lane].polarity = pol; | |
4097 | num_lanes++; | |
4098 | } | |
4099 | ||
4100 | memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); | |
4101 | dsi->num_lanes_used = num_lanes; | |
4102 | ||
4103 | return 0; | |
4104 | } | |
4105 | EXPORT_SYMBOL(omapdss_dsi_configure_pins); | |
4106 | ||
9a147a65 | 4107 | int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) |
8af6ff01 AT |
4108 | { |
4109 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
e67458a8 | 4110 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
02c3960b | 4111 | int bpp = dsi_get_pixel_size(dsi->pix_fmt); |
8af6ff01 AT |
4112 | u8 data_type; |
4113 | u16 word_count; | |
33ca237f | 4114 | int r; |
8af6ff01 | 4115 | |
9a147a65 | 4116 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
02c3960b | 4117 | switch (dsi->pix_fmt) { |
9a147a65 TV |
4118 | case OMAP_DSS_DSI_FMT_RGB888: |
4119 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; | |
4120 | break; | |
4121 | case OMAP_DSS_DSI_FMT_RGB666: | |
4122 | data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; | |
4123 | break; | |
4124 | case OMAP_DSS_DSI_FMT_RGB666_PACKED: | |
4125 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; | |
4126 | break; | |
4127 | case OMAP_DSS_DSI_FMT_RGB565: | |
4128 | data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; | |
4129 | break; | |
4130 | default: | |
4131 | BUG(); | |
c6eee968 | 4132 | return -EINVAL; |
9a147a65 | 4133 | }; |
8af6ff01 | 4134 | |
9a147a65 TV |
4135 | dsi_if_enable(dsidev, false); |
4136 | dsi_vc_enable(dsidev, channel, false); | |
8af6ff01 | 4137 | |
9a147a65 TV |
4138 | /* MODE, 1 = video mode */ |
4139 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4); | |
8af6ff01 | 4140 | |
e67458a8 | 4141 | word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8); |
8af6ff01 | 4142 | |
9a147a65 TV |
4143 | dsi_vc_write_long_header(dsidev, channel, data_type, |
4144 | word_count, 0); | |
8af6ff01 | 4145 | |
9a147a65 TV |
4146 | dsi_vc_enable(dsidev, channel, true); |
4147 | dsi_if_enable(dsidev, true); | |
4148 | } | |
8af6ff01 | 4149 | |
33ca237f TV |
4150 | r = dss_mgr_enable(dssdev->manager); |
4151 | if (r) { | |
4152 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { | |
4153 | dsi_if_enable(dsidev, false); | |
4154 | dsi_vc_enable(dsidev, channel, false); | |
4155 | } | |
4156 | ||
4157 | return r; | |
4158 | } | |
8af6ff01 AT |
4159 | |
4160 | return 0; | |
4161 | } | |
9a147a65 | 4162 | EXPORT_SYMBOL(dsi_enable_video_output); |
8af6ff01 | 4163 | |
9a147a65 | 4164 | void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) |
8af6ff01 AT |
4165 | { |
4166 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4167 | ||
9a147a65 TV |
4168 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) { |
4169 | dsi_if_enable(dsidev, false); | |
4170 | dsi_vc_enable(dsidev, channel, false); | |
8af6ff01 | 4171 | |
9a147a65 TV |
4172 | /* MODE, 0 = command mode */ |
4173 | REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4); | |
8af6ff01 | 4174 | |
9a147a65 TV |
4175 | dsi_vc_enable(dsidev, channel, true); |
4176 | dsi_if_enable(dsidev, true); | |
4177 | } | |
8af6ff01 | 4178 | |
7797c6da | 4179 | dss_mgr_disable(dssdev->manager); |
3de7a1dc | 4180 | } |
9a147a65 | 4181 | EXPORT_SYMBOL(dsi_disable_video_output); |
3de7a1dc | 4182 | |
55cd63ac | 4183 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev) |
3de7a1dc | 4184 | { |
a72b64b9 | 4185 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4186 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4187 | unsigned bytespp; |
4188 | unsigned bytespl; | |
4189 | unsigned bytespf; | |
4190 | unsigned total_len; | |
4191 | unsigned packet_payload; | |
4192 | unsigned packet_len; | |
4193 | u32 l; | |
0f16aa0a | 4194 | int r; |
f1da39d9 | 4195 | const unsigned channel = dsi->update_channel; |
0c65622b | 4196 | const unsigned line_buf_size = dsi_get_line_buf_size(dsidev); |
55cd63ac AT |
4197 | u16 w = dsi->timings.x_res; |
4198 | u16 h = dsi->timings.y_res; | |
3de7a1dc | 4199 | |
5476e74a | 4200 | DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); |
3de7a1dc | 4201 | |
d6049144 | 4202 | dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP); |
18946f62 | 4203 | |
02c3960b | 4204 | bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; |
3de7a1dc TV |
4205 | bytespl = w * bytespp; |
4206 | bytespf = bytespl * h; | |
4207 | ||
4208 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is | |
4209 | * number of lines in a packet. See errata about VP_CLK_RATIO */ | |
4210 | ||
4211 | if (bytespf < line_buf_size) | |
4212 | packet_payload = bytespf; | |
4213 | else | |
4214 | packet_payload = (line_buf_size) / bytespl * bytespl; | |
4215 | ||
4216 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ | |
4217 | total_len = (bytespf / packet_payload) * packet_len; | |
4218 | ||
4219 | if (bytespf % packet_payload) | |
4220 | total_len += (bytespf % packet_payload) + 1; | |
4221 | ||
3de7a1dc | 4222 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
a72b64b9 | 4223 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
3de7a1dc | 4224 | |
7a7c48f9 | 4225 | dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE, |
a72b64b9 | 4226 | packet_len, 0); |
3de7a1dc | 4227 | |
f1da39d9 | 4228 | if (dsi->te_enabled) |
3de7a1dc TV |
4229 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
4230 | else | |
4231 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ | |
a72b64b9 | 4232 | dsi_write_reg(dsidev, DSI_VC_TE(channel), l); |
3de7a1dc TV |
4233 | |
4234 | /* We put SIDLEMODE to no-idle for the duration of the transfer, | |
4235 | * because DSS interrupts are not capable of waking up the CPU and the | |
4236 | * framedone interrupt could be delayed for quite a long time. I think | |
4237 | * the same goes for any DSS interrupts, but for some reason I have not | |
4238 | * seen the problem anywhere else than here. | |
4239 | */ | |
4240 | dispc_disable_sidle(); | |
4241 | ||
a72b64b9 | 4242 | dsi_perf_mark_start(dsidev); |
18946f62 | 4243 | |
49dbf589 AT |
4244 | r = schedule_delayed_work(&dsi->framedone_timeout_work, |
4245 | msecs_to_jiffies(250)); | |
0f16aa0a | 4246 | BUG_ON(r == 0); |
18946f62 | 4247 | |
55cd63ac AT |
4248 | dss_mgr_set_timings(dssdev->manager, &dsi->timings); |
4249 | ||
1cb00178 | 4250 | dss_mgr_start_update(dssdev->manager); |
3de7a1dc | 4251 | |
f1da39d9 | 4252 | if (dsi->te_enabled) { |
3de7a1dc TV |
4253 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
4254 | * for TE is longer than the timer allows */ | |
a72b64b9 | 4255 | REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ |
3de7a1dc | 4256 | |
a72b64b9 | 4257 | dsi_vc_send_bta(dsidev, channel); |
3de7a1dc TV |
4258 | |
4259 | #ifdef DSI_CATCH_MISSING_TE | |
f1da39d9 | 4260 | mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); |
3de7a1dc TV |
4261 | #endif |
4262 | } | |
4263 | } | |
4264 | ||
4265 | #ifdef DSI_CATCH_MISSING_TE | |
4266 | static void dsi_te_timeout(unsigned long arg) | |
4267 | { | |
4268 | DSSERR("TE not received for 250ms!\n"); | |
4269 | } | |
4270 | #endif | |
4271 | ||
a72b64b9 | 4272 | static void dsi_handle_framedone(struct platform_device *dsidev, int error) |
3de7a1dc | 4273 | { |
f1da39d9 AT |
4274 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4275 | ||
3de7a1dc TV |
4276 | /* SIDLEMODE back to smart-idle */ |
4277 | dispc_enable_sidle(); | |
4278 | ||
f1da39d9 | 4279 | if (dsi->te_enabled) { |
18946f62 | 4280 | /* enable LP_RX_TO again after the TE */ |
a72b64b9 | 4281 | REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ |
3de7a1dc TV |
4282 | } |
4283 | ||
f1da39d9 | 4284 | dsi->framedone_callback(error, dsi->framedone_data); |
ab83b14c TV |
4285 | |
4286 | if (!error) | |
a72b64b9 | 4287 | dsi_perf_show(dsidev, "DISPC"); |
18946f62 | 4288 | } |
3de7a1dc | 4289 | |
ab83b14c | 4290 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
18946f62 | 4291 | { |
f1da39d9 AT |
4292 | struct dsi_data *dsi = container_of(work, struct dsi_data, |
4293 | framedone_timeout_work.work); | |
ab83b14c TV |
4294 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
4295 | * 250ms which would conflict with this timeout work. What should be | |
4296 | * done is first cancel the transfer on the HW, and then cancel the | |
4297 | * possibly scheduled framedone work. However, cancelling the transfer | |
4298 | * on the HW is buggy, and would probably require resetting the whole | |
4299 | * DSI */ | |
18946f62 | 4300 | |
ab83b14c | 4301 | DSSERR("Framedone not received for 250ms!\n"); |
3de7a1dc | 4302 | |
f1da39d9 | 4303 | dsi_handle_framedone(dsi->pdev, -ETIMEDOUT); |
3de7a1dc TV |
4304 | } |
4305 | ||
ab83b14c | 4306 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
3de7a1dc | 4307 | { |
a72b64b9 AT |
4308 | struct omap_dss_device *dssdev = (struct omap_dss_device *) data; |
4309 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
f1da39d9 AT |
4310 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4311 | ||
ab83b14c TV |
4312 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
4313 | * turns itself off. However, DSI still has the pixels in its buffers, | |
4314 | * and is sending the data. | |
4315 | */ | |
3de7a1dc | 4316 | |
f1da39d9 | 4317 | __cancel_delayed_work(&dsi->framedone_timeout_work); |
3de7a1dc | 4318 | |
a72b64b9 | 4319 | dsi_handle_framedone(dsidev, 0); |
18946f62 | 4320 | } |
3de7a1dc | 4321 | |
5476e74a TV |
4322 | int omap_dsi_update(struct omap_dss_device *dssdev, int channel, |
4323 | void (*callback)(int, void *), void *data) | |
18946f62 | 4324 | { |
a72b64b9 | 4325 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
5476e74a | 4326 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
18946f62 | 4327 | u16 dw, dh; |
3de7a1dc | 4328 | |
a72b64b9 | 4329 | dsi_perf_mark_setup(dsidev); |
3de7a1dc | 4330 | |
f1da39d9 | 4331 | dsi->update_channel = channel; |
3de7a1dc | 4332 | |
4a9e78ab TV |
4333 | dsi->framedone_callback = callback; |
4334 | dsi->framedone_data = data; | |
e9c31afc | 4335 | |
e352574d AT |
4336 | dw = dsi->timings.x_res; |
4337 | dh = dsi->timings.y_res; | |
e9c31afc | 4338 | |
5476e74a TV |
4339 | #ifdef DEBUG |
4340 | dsi->update_bytes = dw * dh * | |
02c3960b | 4341 | dsi_get_pixel_size(dsi->pix_fmt) / 8; |
5476e74a | 4342 | #endif |
55cd63ac | 4343 | dsi_update_screen_dispc(dssdev); |
3de7a1dc | 4344 | |
3de7a1dc TV |
4345 | return 0; |
4346 | } | |
18946f62 | 4347 | EXPORT_SYMBOL(omap_dsi_update); |
3de7a1dc TV |
4348 | |
4349 | /* Display funcs */ | |
4350 | ||
7d2572f8 | 4351 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) |
3de7a1dc | 4352 | { |
7d2572f8 AT |
4353 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4354 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4355 | struct dispc_clock_info dispc_cinfo; | |
3de7a1dc | 4356 | int r; |
7d2572f8 AT |
4357 | unsigned long long fck; |
4358 | ||
4359 | fck = dsi_get_pll_hsdiv_dispc_rate(dsidev); | |
4360 | ||
4361 | dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div; | |
4362 | dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div; | |
4363 | ||
4364 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); | |
4365 | if (r) { | |
4366 | DSSERR("Failed to calc dispc clocks\n"); | |
4367 | return r; | |
4368 | } | |
4369 | ||
4370 | dsi->mgr_config.clock_info = dispc_cinfo; | |
4371 | ||
4372 | return 0; | |
4373 | } | |
4374 | ||
4375 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) | |
4376 | { | |
4377 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4378 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
7d2572f8 AT |
4379 | int r; |
4380 | u32 irq = 0; | |
3de7a1dc | 4381 | |
8af6ff01 | 4382 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
e67458a8 AT |
4383 | dsi->timings.hsw = 1; |
4384 | dsi->timings.hfp = 1; | |
4385 | dsi->timings.hbp = 1; | |
4386 | dsi->timings.vsw = 1; | |
4387 | dsi->timings.vfp = 0; | |
4388 | dsi->timings.vbp = 0; | |
5476e74a | 4389 | |
efa70b3b | 4390 | irq = dispc_mgr_get_framedone_irq(dssdev->manager->id); |
8af6ff01 AT |
4391 | |
4392 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, | |
4393 | (void *) dssdev, irq); | |
4394 | if (r) { | |
4395 | DSSERR("can't get FRAMEDONE irq\n"); | |
7d2572f8 | 4396 | goto err; |
8af6ff01 AT |
4397 | } |
4398 | ||
7d2572f8 AT |
4399 | dsi->mgr_config.stallmode = true; |
4400 | dsi->mgr_config.fifohandcheck = true; | |
8af6ff01 | 4401 | } else { |
7d2572f8 AT |
4402 | dsi->mgr_config.stallmode = false; |
4403 | dsi->mgr_config.fifohandcheck = false; | |
3de7a1dc TV |
4404 | } |
4405 | ||
bd5a7b11 AT |
4406 | /* |
4407 | * override interlace, logic level and edge related parameters in | |
4408 | * omap_video_timings with default values | |
4409 | */ | |
e67458a8 AT |
4410 | dsi->timings.interlace = false; |
4411 | dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4412 | dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4413 | dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE; | |
4414 | dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH; | |
4415 | dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES; | |
bd5a7b11 | 4416 | |
e67458a8 | 4417 | dss_mgr_set_timings(dssdev->manager, &dsi->timings); |
bd5a7b11 | 4418 | |
7d2572f8 AT |
4419 | r = dsi_configure_dispc_clocks(dssdev); |
4420 | if (r) | |
4421 | goto err1; | |
4422 | ||
4423 | dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; | |
4424 | dsi->mgr_config.video_port_width = | |
02c3960b | 4425 | dsi_get_pixel_size(dsi->pix_fmt); |
7d2572f8 AT |
4426 | dsi->mgr_config.lcden_sig_polarity = 0; |
4427 | ||
f476ae9d | 4428 | dss_mgr_set_lcd_config(dssdev->manager, &dsi->mgr_config); |
d21f43bc | 4429 | |
3de7a1dc | 4430 | return 0; |
7d2572f8 AT |
4431 | err1: |
4432 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) | |
4433 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, | |
4434 | (void *) dssdev, irq); | |
4435 | err: | |
4436 | return r; | |
3de7a1dc TV |
4437 | } |
4438 | ||
4439 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) | |
4440 | { | |
8af6ff01 AT |
4441 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
4442 | u32 irq; | |
5a8b572d | 4443 | |
efa70b3b | 4444 | irq = dispc_mgr_get_framedone_irq(dssdev->manager->id); |
5a8b572d | 4445 | |
8af6ff01 AT |
4446 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, |
4447 | (void *) dssdev, irq); | |
4448 | } | |
3de7a1dc TV |
4449 | } |
4450 | ||
4451 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) | |
4452 | { | |
a72b64b9 | 4453 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
3de7a1dc TV |
4454 | struct dsi_clock_info cinfo; |
4455 | int r; | |
4456 | ||
c6940a3d TV |
4457 | cinfo.regn = dssdev->clocks.dsi.regn; |
4458 | cinfo.regm = dssdev->clocks.dsi.regm; | |
4459 | cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc; | |
4460 | cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi; | |
b6e695ab | 4461 | r = dsi_calc_clock_rates(dsidev, &cinfo); |
ebf0a3fe VS |
4462 | if (r) { |
4463 | DSSERR("Failed to calc dsi clocks\n"); | |
3de7a1dc | 4464 | return r; |
ebf0a3fe | 4465 | } |
3de7a1dc | 4466 | |
a72b64b9 | 4467 | r = dsi_pll_set_clock_div(dsidev, &cinfo); |
3de7a1dc TV |
4468 | if (r) { |
4469 | DSSERR("Failed to set dsi clocks\n"); | |
4470 | return r; | |
4471 | } | |
4472 | ||
4473 | return 0; | |
4474 | } | |
4475 | ||
3de7a1dc TV |
4476 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) |
4477 | { | |
a72b64b9 | 4478 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
11ee9606 | 4479 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4480 | int r; |
4481 | ||
a72b64b9 | 4482 | r = dsi_pll_init(dsidev, true, true); |
3de7a1dc TV |
4483 | if (r) |
4484 | goto err0; | |
4485 | ||
4486 | r = dsi_configure_dsi_clocks(dssdev); | |
4487 | if (r) | |
4488 | goto err1; | |
4489 | ||
e8881662 | 4490 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
11ee9606 | 4491 | dss_select_dsi_clk_source(dsi->module_id, dssdev->clocks.dsi.dsi_fclk_src); |
9613c02b | 4492 | dss_select_lcd_clk_source(dssdev->manager->id, |
e8881662 | 4493 | dssdev->clocks.dispc.channel.lcd_clk_src); |
3de7a1dc TV |
4494 | |
4495 | DSSDBG("PLL OK\n"); | |
4496 | ||
cc5c1850 | 4497 | r = dsi_cio_init(dssdev); |
3de7a1dc TV |
4498 | if (r) |
4499 | goto err2; | |
4500 | ||
a72b64b9 | 4501 | _dsi_print_reset_status(dsidev); |
3de7a1dc TV |
4502 | |
4503 | dsi_proto_timings(dssdev); | |
4504 | dsi_set_lp_clk_divisor(dssdev); | |
4505 | ||
4506 | if (1) | |
a72b64b9 | 4507 | _dsi_print_reset_status(dsidev); |
3de7a1dc TV |
4508 | |
4509 | r = dsi_proto_config(dssdev); | |
4510 | if (r) | |
4511 | goto err3; | |
4512 | ||
4513 | /* enable interface */ | |
a72b64b9 AT |
4514 | dsi_vc_enable(dsidev, 0, 1); |
4515 | dsi_vc_enable(dsidev, 1, 1); | |
4516 | dsi_vc_enable(dsidev, 2, 1); | |
4517 | dsi_vc_enable(dsidev, 3, 1); | |
4518 | dsi_if_enable(dsidev, 1); | |
4519 | dsi_force_tx_stop_mode_io(dsidev); | |
3de7a1dc | 4520 | |
3de7a1dc | 4521 | return 0; |
3de7a1dc | 4522 | err3: |
5bc416cb | 4523 | dsi_cio_uninit(dssdev); |
3de7a1dc | 4524 | err2: |
89a35e51 | 4525 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
11ee9606 | 4526 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); |
5e785091 TV |
4527 | dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK); |
4528 | ||
3de7a1dc | 4529 | err1: |
a72b64b9 | 4530 | dsi_pll_uninit(dsidev, true); |
3de7a1dc TV |
4531 | err0: |
4532 | return r; | |
4533 | } | |
4534 | ||
2a89dc15 | 4535 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev, |
22d6d676 | 4536 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4537 | { |
a72b64b9 | 4538 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4539 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 4540 | |
f1da39d9 | 4541 | if (enter_ulps && !dsi->ulps_enabled) |
a72b64b9 | 4542 | dsi_enter_ulps(dsidev); |
40885ab3 | 4543 | |
d7370104 | 4544 | /* disable interface */ |
a72b64b9 AT |
4545 | dsi_if_enable(dsidev, 0); |
4546 | dsi_vc_enable(dsidev, 0, 0); | |
4547 | dsi_vc_enable(dsidev, 1, 0); | |
4548 | dsi_vc_enable(dsidev, 2, 0); | |
4549 | dsi_vc_enable(dsidev, 3, 0); | |
d7370104 | 4550 | |
89a35e51 | 4551 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
11ee9606 | 4552 | dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK); |
5e785091 | 4553 | dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK); |
5bc416cb | 4554 | dsi_cio_uninit(dssdev); |
a72b64b9 | 4555 | dsi_pll_uninit(dsidev, disconnect_lanes); |
3de7a1dc TV |
4556 | } |
4557 | ||
37ac60e4 | 4558 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
3de7a1dc | 4559 | { |
a72b64b9 | 4560 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4561 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
3de7a1dc TV |
4562 | int r = 0; |
4563 | ||
4564 | DSSDBG("dsi_display_enable\n"); | |
4565 | ||
a72b64b9 | 4566 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
37ac60e4 | 4567 | |
f1da39d9 | 4568 | mutex_lock(&dsi->lock); |
3de7a1dc | 4569 | |
05e1d606 TV |
4570 | if (dssdev->manager == NULL) { |
4571 | DSSERR("failed to enable display: no manager\n"); | |
4572 | r = -ENODEV; | |
4573 | goto err_start_dev; | |
4574 | } | |
4575 | ||
3de7a1dc TV |
4576 | r = omap_dss_start_device(dssdev); |
4577 | if (r) { | |
4578 | DSSERR("failed to start device\n"); | |
4fbafaf3 | 4579 | goto err_start_dev; |
3de7a1dc TV |
4580 | } |
4581 | ||
4fbafaf3 | 4582 | r = dsi_runtime_get(dsidev); |
3de7a1dc | 4583 | if (r) |
4fbafaf3 TV |
4584 | goto err_get_dsi; |
4585 | ||
4586 | dsi_enable_pll_clock(dsidev, 1); | |
3de7a1dc | 4587 | |
4fbafaf3 | 4588 | _dsi_initialize_irq(dsidev); |
3de7a1dc TV |
4589 | |
4590 | r = dsi_display_init_dispc(dssdev); | |
4591 | if (r) | |
4fbafaf3 | 4592 | goto err_init_dispc; |
3de7a1dc TV |
4593 | |
4594 | r = dsi_display_init_dsi(dssdev); | |
4595 | if (r) | |
4fbafaf3 | 4596 | goto err_init_dsi; |
3de7a1dc | 4597 | |
f1da39d9 | 4598 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4599 | |
4600 | return 0; | |
4601 | ||
4fbafaf3 | 4602 | err_init_dsi: |
37ac60e4 | 4603 | dsi_display_uninit_dispc(dssdev); |
4fbafaf3 | 4604 | err_init_dispc: |
a72b64b9 | 4605 | dsi_enable_pll_clock(dsidev, 0); |
4fbafaf3 TV |
4606 | dsi_runtime_put(dsidev); |
4607 | err_get_dsi: | |
3de7a1dc | 4608 | omap_dss_stop_device(dssdev); |
4fbafaf3 | 4609 | err_start_dev: |
f1da39d9 | 4610 | mutex_unlock(&dsi->lock); |
3de7a1dc TV |
4611 | DSSDBG("dsi_display_enable FAILED\n"); |
4612 | return r; | |
4613 | } | |
37ac60e4 | 4614 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
3de7a1dc | 4615 | |
2a89dc15 | 4616 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev, |
22d6d676 | 4617 | bool disconnect_lanes, bool enter_ulps) |
3de7a1dc | 4618 | { |
a72b64b9 | 4619 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
f1da39d9 | 4620 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
a72b64b9 | 4621 | |
3de7a1dc TV |
4622 | DSSDBG("dsi_display_disable\n"); |
4623 | ||
a72b64b9 | 4624 | WARN_ON(!dsi_bus_is_locked(dsidev)); |
3de7a1dc | 4625 | |
f1da39d9 | 4626 | mutex_lock(&dsi->lock); |
3de7a1dc | 4627 | |
15ffa1da TV |
4628 | dsi_sync_vc(dsidev, 0); |
4629 | dsi_sync_vc(dsidev, 1); | |
4630 | dsi_sync_vc(dsidev, 2); | |
4631 | dsi_sync_vc(dsidev, 3); | |
4632 | ||
3de7a1dc TV |
4633 | dsi_display_uninit_dispc(dssdev); |
4634 | ||
22d6d676 | 4635 | dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps); |
3de7a1dc | 4636 | |
4fbafaf3 | 4637 | dsi_runtime_put(dsidev); |
a72b64b9 | 4638 | dsi_enable_pll_clock(dsidev, 0); |
3de7a1dc | 4639 | |
37ac60e4 | 4640 | omap_dss_stop_device(dssdev); |
3de7a1dc | 4641 | |
f1da39d9 | 4642 | mutex_unlock(&dsi->lock); |
3de7a1dc | 4643 | } |
37ac60e4 | 4644 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
3de7a1dc | 4645 | |
225b650d | 4646 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
3de7a1dc | 4647 | { |
f1da39d9 AT |
4648 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4649 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4650 | ||
4651 | dsi->te_enabled = enable; | |
225b650d | 4652 | return 0; |
3de7a1dc | 4653 | } |
225b650d | 4654 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
3de7a1dc | 4655 | |
e67458a8 AT |
4656 | void omapdss_dsi_set_timings(struct omap_dss_device *dssdev, |
4657 | struct omap_video_timings *timings) | |
4658 | { | |
4659 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4660 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4661 | ||
4662 | mutex_lock(&dsi->lock); | |
4663 | ||
4664 | dsi->timings = *timings; | |
4665 | ||
4666 | mutex_unlock(&dsi->lock); | |
4667 | } | |
4668 | EXPORT_SYMBOL(omapdss_dsi_set_timings); | |
4669 | ||
e352574d AT |
4670 | void omapdss_dsi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h) |
4671 | { | |
4672 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4673 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4674 | ||
4675 | mutex_lock(&dsi->lock); | |
4676 | ||
4677 | dsi->timings.x_res = w; | |
4678 | dsi->timings.y_res = h; | |
4679 | ||
4680 | mutex_unlock(&dsi->lock); | |
4681 | } | |
4682 | EXPORT_SYMBOL(omapdss_dsi_set_size); | |
4683 | ||
02c3960b AT |
4684 | void omapdss_dsi_set_pixel_format(struct omap_dss_device *dssdev, |
4685 | enum omap_dss_dsi_pixel_format fmt) | |
4686 | { | |
4687 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); | |
4688 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4689 | ||
4690 | mutex_lock(&dsi->lock); | |
4691 | ||
4692 | dsi->pix_fmt = fmt; | |
4693 | ||
4694 | mutex_unlock(&dsi->lock); | |
4695 | } | |
4696 | EXPORT_SYMBOL(omapdss_dsi_set_pixel_format); | |
4697 | ||
9d8232a7 | 4698 | static int __init dsi_init_display(struct omap_dss_device *dssdev) |
3de7a1dc | 4699 | { |
f1da39d9 AT |
4700 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4701 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4702 | ||
3de7a1dc TV |
4703 | DSSDBG("DSI init\n"); |
4704 | ||
7e951ee9 AT |
4705 | if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) { |
4706 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | | |
4707 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; | |
4708 | } | |
3de7a1dc | 4709 | |
f1da39d9 | 4710 | if (dsi->vdds_dsi_reg == NULL) { |
5f42f2ce TV |
4711 | struct regulator *vdds_dsi; |
4712 | ||
f1da39d9 | 4713 | vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi"); |
5f42f2ce TV |
4714 | |
4715 | if (IS_ERR(vdds_dsi)) { | |
4716 | DSSERR("can't get VDDS_DSI regulator\n"); | |
4717 | return PTR_ERR(vdds_dsi); | |
4718 | } | |
4719 | ||
f1da39d9 | 4720 | dsi->vdds_dsi_reg = vdds_dsi; |
5f42f2ce TV |
4721 | } |
4722 | ||
3de7a1dc TV |
4723 | return 0; |
4724 | } | |
4725 | ||
5ee3c144 AT |
4726 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
4727 | { | |
f1da39d9 AT |
4728 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4729 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
5ee3c144 AT |
4730 | int i; |
4731 | ||
f1da39d9 AT |
4732 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
4733 | if (!dsi->vc[i].dssdev) { | |
4734 | dsi->vc[i].dssdev = dssdev; | |
5ee3c144 AT |
4735 | *channel = i; |
4736 | return 0; | |
4737 | } | |
4738 | } | |
4739 | ||
4740 | DSSERR("cannot get VC for display %s", dssdev->name); | |
4741 | return -ENOSPC; | |
4742 | } | |
4743 | EXPORT_SYMBOL(omap_dsi_request_vc); | |
4744 | ||
4745 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) | |
4746 | { | |
f1da39d9 AT |
4747 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4748 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4749 | ||
5ee3c144 AT |
4750 | if (vc_id < 0 || vc_id > 3) { |
4751 | DSSERR("VC ID out of range\n"); | |
4752 | return -EINVAL; | |
4753 | } | |
4754 | ||
4755 | if (channel < 0 || channel > 3) { | |
4756 | DSSERR("Virtual Channel out of range\n"); | |
4757 | return -EINVAL; | |
4758 | } | |
4759 | ||
f1da39d9 | 4760 | if (dsi->vc[channel].dssdev != dssdev) { |
5ee3c144 AT |
4761 | DSSERR("Virtual Channel not allocated to display %s\n", |
4762 | dssdev->name); | |
4763 | return -EINVAL; | |
4764 | } | |
4765 | ||
f1da39d9 | 4766 | dsi->vc[channel].vc_id = vc_id; |
5ee3c144 AT |
4767 | |
4768 | return 0; | |
4769 | } | |
4770 | EXPORT_SYMBOL(omap_dsi_set_vc_id); | |
4771 | ||
4772 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) | |
4773 | { | |
f1da39d9 AT |
4774 | struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev); |
4775 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4776 | ||
5ee3c144 | 4777 | if ((channel >= 0 && channel <= 3) && |
f1da39d9 AT |
4778 | dsi->vc[channel].dssdev == dssdev) { |
4779 | dsi->vc[channel].dssdev = NULL; | |
4780 | dsi->vc[channel].vc_id = 0; | |
5ee3c144 AT |
4781 | } |
4782 | } | |
4783 | EXPORT_SYMBOL(omap_dsi_release_vc); | |
4784 | ||
a72b64b9 | 4785 | void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev) |
e406f907 | 4786 | { |
a72b64b9 | 4787 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1) |
067a57e4 | 4788 | DSSERR("%s (%s) not active\n", |
89a35e51 AT |
4789 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
4790 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); | |
e406f907 TV |
4791 | } |
4792 | ||
a72b64b9 | 4793 | void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev) |
e406f907 | 4794 | { |
a72b64b9 | 4795 | if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1) |
067a57e4 | 4796 | DSSERR("%s (%s) not active\n", |
89a35e51 AT |
4797 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
4798 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); | |
e406f907 TV |
4799 | } |
4800 | ||
a72b64b9 | 4801 | static void dsi_calc_clock_param_ranges(struct platform_device *dsidev) |
49641116 | 4802 | { |
f1da39d9 AT |
4803 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4804 | ||
4805 | dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); | |
4806 | dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); | |
4807 | dsi->regm_dispc_max = | |
4808 | dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); | |
4809 | dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); | |
4810 | dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); | |
4811 | dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); | |
4812 | dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); | |
49641116 TA |
4813 | } |
4814 | ||
4fbafaf3 TV |
4815 | static int dsi_get_clocks(struct platform_device *dsidev) |
4816 | { | |
4817 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4818 | struct clk *clk; | |
4819 | ||
4820 | clk = clk_get(&dsidev->dev, "fck"); | |
4821 | if (IS_ERR(clk)) { | |
4822 | DSSERR("can't get fck\n"); | |
4823 | return PTR_ERR(clk); | |
4824 | } | |
4825 | ||
4826 | dsi->dss_clk = clk; | |
4827 | ||
bfe4f8d3 | 4828 | clk = clk_get(&dsidev->dev, "sys_clk"); |
4fbafaf3 TV |
4829 | if (IS_ERR(clk)) { |
4830 | DSSERR("can't get sys_clk\n"); | |
4831 | clk_put(dsi->dss_clk); | |
4832 | dsi->dss_clk = NULL; | |
4833 | return PTR_ERR(clk); | |
4834 | } | |
4835 | ||
4836 | dsi->sys_clk = clk; | |
4837 | ||
4838 | return 0; | |
4839 | } | |
4840 | ||
4841 | static void dsi_put_clocks(struct platform_device *dsidev) | |
4842 | { | |
4843 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4844 | ||
4845 | if (dsi->dss_clk) | |
4846 | clk_put(dsi->dss_clk); | |
4847 | if (dsi->sys_clk) | |
4848 | clk_put(dsi->sys_clk); | |
4849 | } | |
4850 | ||
38f3daf6 TV |
4851 | static void __init dsi_probe_pdata(struct platform_device *dsidev) |
4852 | { | |
4853 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); | |
4854 | struct omap_dss_board_info *pdata = dsidev->dev.platform_data; | |
4855 | int i, r; | |
4856 | ||
4857 | for (i = 0; i < pdata->num_devices; ++i) { | |
4858 | struct omap_dss_device *dssdev = pdata->devices[i]; | |
4859 | ||
4860 | if (dssdev->type != OMAP_DISPLAY_TYPE_DSI) | |
4861 | continue; | |
4862 | ||
4863 | if (dssdev->phy.dsi.module != dsi->module_id) | |
4864 | continue; | |
4865 | ||
4866 | r = dsi_init_display(dssdev); | |
4867 | if (r) { | |
4868 | DSSERR("device %s init failed: %d\n", dssdev->name, r); | |
4869 | continue; | |
4870 | } | |
4871 | ||
4872 | r = omap_dss_register_device(dssdev, &dsidev->dev, i); | |
4873 | if (r) | |
4874 | DSSERR("device %s register failed: %d\n", | |
4875 | dssdev->name, r); | |
4876 | } | |
4877 | } | |
4878 | ||
b98482ed | 4879 | /* DSI1 HW IP initialisation */ |
6e7e8f06 | 4880 | static int __init omap_dsihw_probe(struct platform_device *dsidev) |
3de7a1dc TV |
4881 | { |
4882 | u32 rev; | |
11ee9606 | 4883 | int r, i; |
ea9da36a | 4884 | struct resource *dsi_mem; |
f1da39d9 AT |
4885 | struct dsi_data *dsi; |
4886 | ||
6e2a14d2 | 4887 | dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL); |
cd3b3449 TV |
4888 | if (!dsi) |
4889 | return -ENOMEM; | |
3de7a1dc | 4890 | |
11ee9606 | 4891 | dsi->module_id = dsidev->id; |
f1da39d9 | 4892 | dsi->pdev = dsidev; |
11ee9606 | 4893 | dsi_pdev_map[dsi->module_id] = dsidev; |
f1da39d9 | 4894 | dev_set_drvdata(&dsidev->dev, dsi); |
a72b64b9 | 4895 | |
f1da39d9 AT |
4896 | spin_lock_init(&dsi->irq_lock); |
4897 | spin_lock_init(&dsi->errors_lock); | |
4898 | dsi->errors = 0; | |
3de7a1dc | 4899 | |
dfc0fd8d | 4900 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
f1da39d9 AT |
4901 | spin_lock_init(&dsi->irq_stats_lock); |
4902 | dsi->irq_stats.last_reset = jiffies; | |
dfc0fd8d TV |
4903 | #endif |
4904 | ||
f1da39d9 AT |
4905 | mutex_init(&dsi->lock); |
4906 | sema_init(&dsi->bus_lock, 1); | |
3de7a1dc | 4907 | |
f1da39d9 | 4908 | INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work, |
18946f62 TV |
4909 | dsi_framedone_timeout_work_callback); |
4910 | ||
3de7a1dc | 4911 | #ifdef DSI_CATCH_MISSING_TE |
f1da39d9 AT |
4912 | init_timer(&dsi->te_timer); |
4913 | dsi->te_timer.function = dsi_te_timeout; | |
4914 | dsi->te_timer.data = 0; | |
3de7a1dc | 4915 | #endif |
f1da39d9 | 4916 | dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0); |
ea9da36a SG |
4917 | if (!dsi_mem) { |
4918 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
cd3b3449 | 4919 | return -EINVAL; |
ea9da36a | 4920 | } |
cd3b3449 | 4921 | |
6e2a14d2 JL |
4922 | dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start, |
4923 | resource_size(dsi_mem)); | |
f1da39d9 | 4924 | if (!dsi->base) { |
3de7a1dc | 4925 | DSSERR("can't ioremap DSI\n"); |
cd3b3449 | 4926 | return -ENOMEM; |
3de7a1dc | 4927 | } |
cd3b3449 | 4928 | |
f1da39d9 AT |
4929 | dsi->irq = platform_get_irq(dsi->pdev, 0); |
4930 | if (dsi->irq < 0) { | |
affe360d | 4931 | DSSERR("platform_get_irq failed\n"); |
cd3b3449 | 4932 | return -ENODEV; |
affe360d | 4933 | } |
4934 | ||
6e2a14d2 JL |
4935 | r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler, |
4936 | IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev); | |
affe360d | 4937 | if (r < 0) { |
4938 | DSSERR("request_irq failed\n"); | |
cd3b3449 | 4939 | return r; |
affe360d | 4940 | } |
3de7a1dc | 4941 | |
5ee3c144 | 4942 | /* DSI VCs initialization */ |
f1da39d9 | 4943 | for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { |
d6049144 | 4944 | dsi->vc[i].source = DSI_VC_SOURCE_L4; |
f1da39d9 AT |
4945 | dsi->vc[i].dssdev = NULL; |
4946 | dsi->vc[i].vc_id = 0; | |
5ee3c144 AT |
4947 | } |
4948 | ||
a72b64b9 | 4949 | dsi_calc_clock_param_ranges(dsidev); |
49641116 | 4950 | |
cd3b3449 TV |
4951 | r = dsi_get_clocks(dsidev); |
4952 | if (r) | |
4953 | return r; | |
4954 | ||
4955 | pm_runtime_enable(&dsidev->dev); | |
4956 | ||
4fbafaf3 TV |
4957 | r = dsi_runtime_get(dsidev); |
4958 | if (r) | |
cd3b3449 | 4959 | goto err_runtime_get; |
3de7a1dc | 4960 | |
a72b64b9 AT |
4961 | rev = dsi_read_reg(dsidev, DSI_REVISION); |
4962 | dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n", | |
3de7a1dc TV |
4963 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
4964 | ||
d9820850 TV |
4965 | /* DSI on OMAP3 doesn't have register DSI_GNQ, set number |
4966 | * of data to 3 by default */ | |
4967 | if (dss_has_feature(FEAT_DSI_GNQ)) | |
4968 | /* NB_DATA_LANES */ | |
4969 | dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9); | |
4970 | else | |
4971 | dsi->num_lanes_supported = 3; | |
75d7247c | 4972 | |
38f3daf6 | 4973 | dsi_probe_pdata(dsidev); |
35deca3d | 4974 | |
4fbafaf3 | 4975 | dsi_runtime_put(dsidev); |
3de7a1dc | 4976 | |
11ee9606 | 4977 | if (dsi->module_id == 0) |
e40402cf | 4978 | dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs); |
11ee9606 | 4979 | else if (dsi->module_id == 1) |
e40402cf TV |
4980 | dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs); |
4981 | ||
4982 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
11ee9606 | 4983 | if (dsi->module_id == 0) |
e40402cf | 4984 | dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs); |
11ee9606 | 4985 | else if (dsi->module_id == 1) |
e40402cf TV |
4986 | dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs); |
4987 | #endif | |
3de7a1dc | 4988 | return 0; |
4fbafaf3 | 4989 | |
cd3b3449 | 4990 | err_runtime_get: |
4fbafaf3 | 4991 | pm_runtime_disable(&dsidev->dev); |
cd3b3449 | 4992 | dsi_put_clocks(dsidev); |
3de7a1dc TV |
4993 | return r; |
4994 | } | |
4995 | ||
6e7e8f06 | 4996 | static int __exit omap_dsihw_remove(struct platform_device *dsidev) |
3de7a1dc | 4997 | { |
f1da39d9 AT |
4998 | struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); |
4999 | ||
b98482ed TV |
5000 | WARN_ON(dsi->scp_clk_refcount > 0); |
5001 | ||
35deca3d TV |
5002 | omap_dss_unregister_child_devices(&dsidev->dev); |
5003 | ||
4fbafaf3 TV |
5004 | pm_runtime_disable(&dsidev->dev); |
5005 | ||
5006 | dsi_put_clocks(dsidev); | |
5007 | ||
f1da39d9 AT |
5008 | if (dsi->vdds_dsi_reg != NULL) { |
5009 | if (dsi->vdds_dsi_enabled) { | |
5010 | regulator_disable(dsi->vdds_dsi_reg); | |
5011 | dsi->vdds_dsi_enabled = false; | |
88257b26 TV |
5012 | } |
5013 | ||
f1da39d9 AT |
5014 | regulator_put(dsi->vdds_dsi_reg); |
5015 | dsi->vdds_dsi_reg = NULL; | |
c8aac01b SG |
5016 | } |
5017 | ||
c8aac01b SG |
5018 | return 0; |
5019 | } | |
5020 | ||
4fbafaf3 TV |
5021 | static int dsi_runtime_suspend(struct device *dev) |
5022 | { | |
4fbafaf3 | 5023 | dispc_runtime_put(); |
4fbafaf3 TV |
5024 | |
5025 | return 0; | |
5026 | } | |
5027 | ||
5028 | static int dsi_runtime_resume(struct device *dev) | |
5029 | { | |
4fbafaf3 TV |
5030 | int r; |
5031 | ||
4fbafaf3 TV |
5032 | r = dispc_runtime_get(); |
5033 | if (r) | |
852f0838 | 5034 | return r; |
4fbafaf3 | 5035 | |
4fbafaf3 | 5036 | return 0; |
4fbafaf3 TV |
5037 | } |
5038 | ||
5039 | static const struct dev_pm_ops dsi_pm_ops = { | |
5040 | .runtime_suspend = dsi_runtime_suspend, | |
5041 | .runtime_resume = dsi_runtime_resume, | |
5042 | }; | |
5043 | ||
7c68dd96 | 5044 | static struct platform_driver omap_dsihw_driver = { |
6e7e8f06 | 5045 | .remove = __exit_p(omap_dsihw_remove), |
c8aac01b | 5046 | .driver = { |
7c68dd96 | 5047 | .name = "omapdss_dsi", |
c8aac01b | 5048 | .owner = THIS_MODULE, |
4fbafaf3 | 5049 | .pm = &dsi_pm_ops, |
c8aac01b SG |
5050 | }, |
5051 | }; | |
5052 | ||
6e7e8f06 | 5053 | int __init dsi_init_platform_driver(void) |
c8aac01b | 5054 | { |
61055d4b | 5055 | return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe); |
c8aac01b SG |
5056 | } |
5057 | ||
6e7e8f06 | 5058 | void __exit dsi_uninit_platform_driver(void) |
c8aac01b | 5059 | { |
04c742c3 | 5060 | platform_driver_unregister(&omap_dsihw_driver); |
c8aac01b | 5061 | } |