Commit | Line | Data |
---|---|---|
3de7a1dc TV |
1 | /* |
2 | * linux/drivers/video/omap2/dss/dsi.c | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
12 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | * more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License along with | |
17 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
20 | #define DSS_SUBSYS_NAME "DSI" | |
21 | ||
22 | #include <linux/kernel.h> | |
23 | #include <linux/io.h> | |
24 | #include <linux/clk.h> | |
25 | #include <linux/device.h> | |
26 | #include <linux/err.h> | |
27 | #include <linux/interrupt.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/mutex.h> | |
b9eb5d7d | 30 | #include <linux/semaphore.h> |
3de7a1dc TV |
31 | #include <linux/seq_file.h> |
32 | #include <linux/platform_device.h> | |
33 | #include <linux/regulator/consumer.h> | |
3de7a1dc | 34 | #include <linux/wait.h> |
18946f62 | 35 | #include <linux/workqueue.h> |
3de7a1dc | 36 | |
a0b38cc4 | 37 | #include <video/omapdss.h> |
3de7a1dc TV |
38 | #include <plat/clock.h> |
39 | ||
40 | #include "dss.h" | |
819d807c | 41 | #include "dss_features.h" |
3de7a1dc TV |
42 | |
43 | /*#define VERBOSE_IRQ*/ | |
44 | #define DSI_CATCH_MISSING_TE | |
45 | ||
3de7a1dc TV |
46 | struct dsi_reg { u16 idx; }; |
47 | ||
48 | #define DSI_REG(idx) ((const struct dsi_reg) { idx }) | |
49 | ||
50 | #define DSI_SZ_REGS SZ_1K | |
51 | /* DSI Protocol Engine */ | |
52 | ||
53 | #define DSI_REVISION DSI_REG(0x0000) | |
54 | #define DSI_SYSCONFIG DSI_REG(0x0010) | |
55 | #define DSI_SYSSTATUS DSI_REG(0x0014) | |
56 | #define DSI_IRQSTATUS DSI_REG(0x0018) | |
57 | #define DSI_IRQENABLE DSI_REG(0x001C) | |
58 | #define DSI_CTRL DSI_REG(0x0040) | |
59 | #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048) | |
60 | #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C) | |
61 | #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050) | |
62 | #define DSI_CLK_CTRL DSI_REG(0x0054) | |
63 | #define DSI_TIMING1 DSI_REG(0x0058) | |
64 | #define DSI_TIMING2 DSI_REG(0x005C) | |
65 | #define DSI_VM_TIMING1 DSI_REG(0x0060) | |
66 | #define DSI_VM_TIMING2 DSI_REG(0x0064) | |
67 | #define DSI_VM_TIMING3 DSI_REG(0x0068) | |
68 | #define DSI_CLK_TIMING DSI_REG(0x006C) | |
69 | #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070) | |
70 | #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074) | |
71 | #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078) | |
72 | #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C) | |
73 | #define DSI_VM_TIMING4 DSI_REG(0x0080) | |
74 | #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084) | |
75 | #define DSI_VM_TIMING5 DSI_REG(0x0088) | |
76 | #define DSI_VM_TIMING6 DSI_REG(0x008C) | |
77 | #define DSI_VM_TIMING7 DSI_REG(0x0090) | |
78 | #define DSI_STOPCLK_TIMING DSI_REG(0x0094) | |
79 | #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20)) | |
80 | #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20)) | |
81 | #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20)) | |
82 | #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20)) | |
83 | #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20)) | |
84 | #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20)) | |
85 | #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20)) | |
86 | ||
87 | /* DSIPHY_SCP */ | |
88 | ||
89 | #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000) | |
90 | #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004) | |
91 | #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008) | |
92 | #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014) | |
0a0ee46b | 93 | #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028) |
3de7a1dc TV |
94 | |
95 | /* DSI_PLL_CTRL_SCP */ | |
96 | ||
97 | #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000) | |
98 | #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004) | |
99 | #define DSI_PLL_GO DSI_REG(0x300 + 0x0008) | |
100 | #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C) | |
101 | #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010) | |
102 | ||
103 | #define REG_GET(idx, start, end) \ | |
104 | FLD_GET(dsi_read_reg(idx), start, end) | |
105 | ||
106 | #define REG_FLD_MOD(idx, val, start, end) \ | |
107 | dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end)) | |
108 | ||
109 | /* Global interrupts */ | |
110 | #define DSI_IRQ_VC0 (1 << 0) | |
111 | #define DSI_IRQ_VC1 (1 << 1) | |
112 | #define DSI_IRQ_VC2 (1 << 2) | |
113 | #define DSI_IRQ_VC3 (1 << 3) | |
114 | #define DSI_IRQ_WAKEUP (1 << 4) | |
115 | #define DSI_IRQ_RESYNC (1 << 5) | |
116 | #define DSI_IRQ_PLL_LOCK (1 << 7) | |
117 | #define DSI_IRQ_PLL_UNLOCK (1 << 8) | |
118 | #define DSI_IRQ_PLL_RECALL (1 << 9) | |
119 | #define DSI_IRQ_COMPLEXIO_ERR (1 << 10) | |
120 | #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) | |
121 | #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) | |
122 | #define DSI_IRQ_TE_TRIGGER (1 << 16) | |
123 | #define DSI_IRQ_ACK_TRIGGER (1 << 17) | |
124 | #define DSI_IRQ_SYNC_LOST (1 << 18) | |
125 | #define DSI_IRQ_LDO_POWER_GOOD (1 << 19) | |
126 | #define DSI_IRQ_TA_TIMEOUT (1 << 20) | |
127 | #define DSI_IRQ_ERROR_MASK \ | |
128 | (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ | |
129 | DSI_IRQ_TA_TIMEOUT) | |
130 | #define DSI_IRQ_CHANNEL_MASK 0xf | |
131 | ||
132 | /* Virtual channel interrupts */ | |
133 | #define DSI_VC_IRQ_CS (1 << 0) | |
134 | #define DSI_VC_IRQ_ECC_CORR (1 << 1) | |
135 | #define DSI_VC_IRQ_PACKET_SENT (1 << 2) | |
136 | #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) | |
137 | #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) | |
138 | #define DSI_VC_IRQ_BTA (1 << 5) | |
139 | #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) | |
140 | #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) | |
141 | #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) | |
142 | #define DSI_VC_IRQ_ERROR_MASK \ | |
143 | (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ | |
144 | DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ | |
145 | DSI_VC_IRQ_FIFO_TX_UDF) | |
146 | ||
147 | /* ComplexIO interrupts */ | |
148 | #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) | |
149 | #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) | |
150 | #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) | |
151 | #define DSI_CIO_IRQ_ERRESC1 (1 << 5) | |
152 | #define DSI_CIO_IRQ_ERRESC2 (1 << 6) | |
153 | #define DSI_CIO_IRQ_ERRESC3 (1 << 7) | |
154 | #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) | |
155 | #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) | |
156 | #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) | |
157 | #define DSI_CIO_IRQ_STATEULPS1 (1 << 15) | |
158 | #define DSI_CIO_IRQ_STATEULPS2 (1 << 16) | |
159 | #define DSI_CIO_IRQ_STATEULPS3 (1 << 17) | |
160 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) | |
161 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) | |
162 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) | |
163 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) | |
164 | #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) | |
165 | #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) | |
166 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) | |
167 | #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) | |
bbecb50b TV |
168 | #define DSI_CIO_IRQ_ERROR_MASK \ |
169 | (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ | |
170 | DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ | |
171 | DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \ | |
172 | DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \ | |
173 | DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ | |
174 | DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ | |
175 | DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3) | |
3de7a1dc TV |
176 | |
177 | #define DSI_DT_DCS_SHORT_WRITE_0 0x05 | |
178 | #define DSI_DT_DCS_SHORT_WRITE_1 0x15 | |
179 | #define DSI_DT_DCS_READ 0x06 | |
180 | #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37 | |
181 | #define DSI_DT_NULL_PACKET 0x09 | |
182 | #define DSI_DT_DCS_LONG_WRITE 0x39 | |
183 | ||
184 | #define DSI_DT_RX_ACK_WITH_ERR 0x02 | |
185 | #define DSI_DT_RX_DCS_LONG_READ 0x1c | |
186 | #define DSI_DT_RX_SHORT_READ_1 0x21 | |
187 | #define DSI_DT_RX_SHORT_READ_2 0x22 | |
188 | ||
4ae2dddd TV |
189 | typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); |
190 | ||
191 | #define DSI_MAX_NR_ISRS 2 | |
192 | ||
193 | struct dsi_isr_data { | |
194 | omap_dsi_isr_t isr; | |
195 | void *arg; | |
196 | u32 mask; | |
197 | }; | |
198 | ||
3de7a1dc TV |
199 | enum fifo_size { |
200 | DSI_FIFO_SIZE_0 = 0, | |
201 | DSI_FIFO_SIZE_32 = 1, | |
202 | DSI_FIFO_SIZE_64 = 2, | |
203 | DSI_FIFO_SIZE_96 = 3, | |
204 | DSI_FIFO_SIZE_128 = 4, | |
205 | }; | |
206 | ||
207 | enum dsi_vc_mode { | |
208 | DSI_VC_MODE_L4 = 0, | |
209 | DSI_VC_MODE_VP, | |
210 | }; | |
211 | ||
0a0ee46b TV |
212 | enum dsi_lane { |
213 | DSI_CLK_P = 1 << 0, | |
214 | DSI_CLK_N = 1 << 1, | |
215 | DSI_DATA1_P = 1 << 2, | |
216 | DSI_DATA1_N = 1 << 3, | |
217 | DSI_DATA2_P = 1 << 4, | |
218 | DSI_DATA2_N = 1 << 5, | |
219 | }; | |
220 | ||
3de7a1dc | 221 | struct dsi_update_region { |
3de7a1dc TV |
222 | u16 x, y, w, h; |
223 | struct omap_dss_device *device; | |
224 | }; | |
225 | ||
dfc0fd8d TV |
226 | struct dsi_irq_stats { |
227 | unsigned long last_reset; | |
228 | unsigned irq_count; | |
229 | unsigned dsi_irqs[32]; | |
230 | unsigned vc_irqs[4][32]; | |
231 | unsigned cio_irqs[32]; | |
232 | }; | |
233 | ||
4ae2dddd TV |
234 | struct dsi_isr_tables { |
235 | struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; | |
236 | struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; | |
237 | struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; | |
238 | }; | |
239 | ||
3de7a1dc TV |
240 | static struct |
241 | { | |
c8aac01b | 242 | struct platform_device *pdev; |
3de7a1dc | 243 | void __iomem *base; |
affe360d | 244 | int irq; |
3de7a1dc TV |
245 | |
246 | struct dsi_clock_info current_cinfo; | |
247 | ||
248 | struct regulator *vdds_dsi_reg; | |
249 | ||
250 | struct { | |
251 | enum dsi_vc_mode mode; | |
252 | struct omap_dss_device *dssdev; | |
253 | enum fifo_size fifo_size; | |
5ee3c144 | 254 | int vc_id; |
3de7a1dc TV |
255 | } vc[4]; |
256 | ||
257 | struct mutex lock; | |
b9eb5d7d | 258 | struct semaphore bus_lock; |
3de7a1dc TV |
259 | |
260 | unsigned pll_locked; | |
261 | ||
4ae2dddd TV |
262 | spinlock_t irq_lock; |
263 | struct dsi_isr_tables isr_tables; | |
264 | /* space for a copy used by the interrupt handler */ | |
265 | struct dsi_isr_tables isr_tables_copy; | |
266 | ||
18946f62 | 267 | int update_channel; |
3de7a1dc | 268 | struct dsi_update_region update_region; |
3de7a1dc | 269 | |
3de7a1dc | 270 | bool te_enabled; |
3de7a1dc | 271 | |
0f16aa0a TV |
272 | struct workqueue_struct *workqueue; |
273 | ||
18946f62 TV |
274 | void (*framedone_callback)(int, void *); |
275 | void *framedone_data; | |
276 | ||
277 | struct delayed_work framedone_timeout_work; | |
278 | ||
3de7a1dc TV |
279 | #ifdef DSI_CATCH_MISSING_TE |
280 | struct timer_list te_timer; | |
281 | #endif | |
282 | ||
283 | unsigned long cache_req_pck; | |
284 | unsigned long cache_clk_freq; | |
285 | struct dsi_clock_info cache_cinfo; | |
286 | ||
287 | u32 errors; | |
288 | spinlock_t errors_lock; | |
289 | #ifdef DEBUG | |
290 | ktime_t perf_setup_time; | |
291 | ktime_t perf_start_time; | |
3de7a1dc TV |
292 | #endif |
293 | int debug_read; | |
294 | int debug_write; | |
dfc0fd8d TV |
295 | |
296 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS | |
297 | spinlock_t irq_stats_lock; | |
298 | struct dsi_irq_stats irq_stats; | |
299 | #endif | |
49641116 TA |
300 | /* DSI PLL Parameter Ranges */ |
301 | unsigned long regm_max, regn_max; | |
302 | unsigned long regm_dispc_max, regm_dsi_max; | |
303 | unsigned long fint_min, fint_max; | |
304 | unsigned long lpdiv_max; | |
3de7a1dc TV |
305 | } dsi; |
306 | ||
307 | #ifdef DEBUG | |
308 | static unsigned int dsi_perf; | |
309 | module_param_named(dsi_perf, dsi_perf, bool, 0644); | |
310 | #endif | |
311 | ||
312 | static inline void dsi_write_reg(const struct dsi_reg idx, u32 val) | |
313 | { | |
314 | __raw_writel(val, dsi.base + idx.idx); | |
315 | } | |
316 | ||
317 | static inline u32 dsi_read_reg(const struct dsi_reg idx) | |
318 | { | |
319 | return __raw_readl(dsi.base + idx.idx); | |
320 | } | |
321 | ||
322 | ||
323 | void dsi_save_context(void) | |
324 | { | |
325 | } | |
326 | ||
327 | void dsi_restore_context(void) | |
328 | { | |
329 | } | |
330 | ||
331 | void dsi_bus_lock(void) | |
332 | { | |
b9eb5d7d | 333 | down(&dsi.bus_lock); |
3de7a1dc TV |
334 | } |
335 | EXPORT_SYMBOL(dsi_bus_lock); | |
336 | ||
337 | void dsi_bus_unlock(void) | |
338 | { | |
b9eb5d7d | 339 | up(&dsi.bus_lock); |
3de7a1dc TV |
340 | } |
341 | EXPORT_SYMBOL(dsi_bus_unlock); | |
342 | ||
4f765023 TV |
343 | static bool dsi_bus_is_locked(void) |
344 | { | |
b9eb5d7d | 345 | return dsi.bus_lock.count == 0; |
4f765023 TV |
346 | } |
347 | ||
f36a06e7 TV |
348 | static void dsi_completion_handler(void *data, u32 mask) |
349 | { | |
350 | complete((struct completion *)data); | |
351 | } | |
352 | ||
3de7a1dc TV |
353 | static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum, |
354 | int value) | |
355 | { | |
356 | int t = 100000; | |
357 | ||
358 | while (REG_GET(idx, bitnum, bitnum) != value) { | |
359 | if (--t == 0) | |
360 | return !value; | |
361 | } | |
362 | ||
363 | return value; | |
364 | } | |
365 | ||
366 | #ifdef DEBUG | |
367 | static void dsi_perf_mark_setup(void) | |
368 | { | |
369 | dsi.perf_setup_time = ktime_get(); | |
370 | } | |
371 | ||
372 | static void dsi_perf_mark_start(void) | |
373 | { | |
374 | dsi.perf_start_time = ktime_get(); | |
375 | } | |
376 | ||
3de7a1dc TV |
377 | static void dsi_perf_show(const char *name) |
378 | { | |
379 | ktime_t t, setup_time, trans_time; | |
380 | u32 total_bytes; | |
381 | u32 setup_us, trans_us, total_us; | |
382 | ||
383 | if (!dsi_perf) | |
384 | return; | |
385 | ||
3de7a1dc TV |
386 | t = ktime_get(); |
387 | ||
388 | setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time); | |
389 | setup_us = (u32)ktime_to_us(setup_time); | |
390 | if (setup_us == 0) | |
391 | setup_us = 1; | |
392 | ||
393 | trans_time = ktime_sub(t, dsi.perf_start_time); | |
394 | trans_us = (u32)ktime_to_us(trans_time); | |
395 | if (trans_us == 0) | |
396 | trans_us = 1; | |
397 | ||
398 | total_us = setup_us + trans_us; | |
399 | ||
18946f62 TV |
400 | total_bytes = dsi.update_region.w * |
401 | dsi.update_region.h * | |
402 | dsi.update_region.device->ctrl.pixel_size / 8; | |
3de7a1dc | 403 | |
1bbb275e TV |
404 | printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), " |
405 | "%u bytes, %u kbytes/sec\n", | |
406 | name, | |
407 | setup_us, | |
408 | trans_us, | |
409 | total_us, | |
410 | 1000*1000 / total_us, | |
411 | total_bytes, | |
412 | total_bytes * 1000 / total_us); | |
3de7a1dc TV |
413 | } |
414 | #else | |
415 | #define dsi_perf_mark_setup() | |
416 | #define dsi_perf_mark_start() | |
3de7a1dc TV |
417 | #define dsi_perf_show(x) |
418 | #endif | |
419 | ||
420 | static void print_irq_status(u32 status) | |
421 | { | |
d80d499e TV |
422 | if (status == 0) |
423 | return; | |
424 | ||
3de7a1dc TV |
425 | #ifndef VERBOSE_IRQ |
426 | if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0) | |
427 | return; | |
428 | #endif | |
429 | printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status); | |
430 | ||
431 | #define PIS(x) \ | |
432 | if (status & DSI_IRQ_##x) \ | |
433 | printk(#x " "); | |
434 | #ifdef VERBOSE_IRQ | |
435 | PIS(VC0); | |
436 | PIS(VC1); | |
437 | PIS(VC2); | |
438 | PIS(VC3); | |
439 | #endif | |
440 | PIS(WAKEUP); | |
441 | PIS(RESYNC); | |
442 | PIS(PLL_LOCK); | |
443 | PIS(PLL_UNLOCK); | |
444 | PIS(PLL_RECALL); | |
445 | PIS(COMPLEXIO_ERR); | |
446 | PIS(HS_TX_TIMEOUT); | |
447 | PIS(LP_RX_TIMEOUT); | |
448 | PIS(TE_TRIGGER); | |
449 | PIS(ACK_TRIGGER); | |
450 | PIS(SYNC_LOST); | |
451 | PIS(LDO_POWER_GOOD); | |
452 | PIS(TA_TIMEOUT); | |
453 | #undef PIS | |
454 | ||
455 | printk("\n"); | |
456 | } | |
457 | ||
458 | static void print_irq_status_vc(int channel, u32 status) | |
459 | { | |
d80d499e TV |
460 | if (status == 0) |
461 | return; | |
462 | ||
3de7a1dc TV |
463 | #ifndef VERBOSE_IRQ |
464 | if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0) | |
465 | return; | |
466 | #endif | |
467 | printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status); | |
468 | ||
469 | #define PIS(x) \ | |
470 | if (status & DSI_VC_IRQ_##x) \ | |
471 | printk(#x " "); | |
472 | PIS(CS); | |
473 | PIS(ECC_CORR); | |
474 | #ifdef VERBOSE_IRQ | |
475 | PIS(PACKET_SENT); | |
476 | #endif | |
477 | PIS(FIFO_TX_OVF); | |
478 | PIS(FIFO_RX_OVF); | |
479 | PIS(BTA); | |
480 | PIS(ECC_NO_CORR); | |
481 | PIS(FIFO_TX_UDF); | |
482 | PIS(PP_BUSY_CHANGE); | |
483 | #undef PIS | |
484 | printk("\n"); | |
485 | } | |
486 | ||
487 | static void print_irq_status_cio(u32 status) | |
488 | { | |
d80d499e TV |
489 | if (status == 0) |
490 | return; | |
491 | ||
3de7a1dc TV |
492 | printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status); |
493 | ||
494 | #define PIS(x) \ | |
495 | if (status & DSI_CIO_IRQ_##x) \ | |
496 | printk(#x " "); | |
497 | PIS(ERRSYNCESC1); | |
498 | PIS(ERRSYNCESC2); | |
499 | PIS(ERRSYNCESC3); | |
500 | PIS(ERRESC1); | |
501 | PIS(ERRESC2); | |
502 | PIS(ERRESC3); | |
503 | PIS(ERRCONTROL1); | |
504 | PIS(ERRCONTROL2); | |
505 | PIS(ERRCONTROL3); | |
506 | PIS(STATEULPS1); | |
507 | PIS(STATEULPS2); | |
508 | PIS(STATEULPS3); | |
509 | PIS(ERRCONTENTIONLP0_1); | |
510 | PIS(ERRCONTENTIONLP1_1); | |
511 | PIS(ERRCONTENTIONLP0_2); | |
512 | PIS(ERRCONTENTIONLP1_2); | |
513 | PIS(ERRCONTENTIONLP0_3); | |
514 | PIS(ERRCONTENTIONLP1_3); | |
515 | PIS(ULPSACTIVENOT_ALL0); | |
516 | PIS(ULPSACTIVENOT_ALL1); | |
517 | #undef PIS | |
518 | ||
519 | printk("\n"); | |
520 | } | |
521 | ||
69b281a6 TV |
522 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
523 | static void dsi_collect_irq_stats(u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
3de7a1dc | 524 | { |
3de7a1dc TV |
525 | int i; |
526 | ||
dfc0fd8d | 527 | spin_lock(&dsi.irq_stats_lock); |
69b281a6 | 528 | |
dfc0fd8d TV |
529 | dsi.irq_stats.irq_count++; |
530 | dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs); | |
69b281a6 TV |
531 | |
532 | for (i = 0; i < 4; ++i) | |
533 | dss_collect_irq_stats(vcstatus[i], dsi.irq_stats.vc_irqs[i]); | |
534 | ||
535 | dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs); | |
536 | ||
537 | spin_unlock(&dsi.irq_stats_lock); | |
538 | } | |
539 | #else | |
540 | #define dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus) | |
dfc0fd8d TV |
541 | #endif |
542 | ||
69b281a6 TV |
543 | static int debug_irq; |
544 | ||
545 | static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
546 | { | |
547 | int i; | |
548 | ||
3de7a1dc TV |
549 | if (irqstatus & DSI_IRQ_ERROR_MASK) { |
550 | DSSERR("DSI error, irqstatus %x\n", irqstatus); | |
551 | print_irq_status(irqstatus); | |
552 | spin_lock(&dsi.errors_lock); | |
553 | dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK; | |
554 | spin_unlock(&dsi.errors_lock); | |
555 | } else if (debug_irq) { | |
556 | print_irq_status(irqstatus); | |
557 | } | |
558 | ||
3de7a1dc | 559 | for (i = 0; i < 4; ++i) { |
69b281a6 TV |
560 | if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { |
561 | DSSERR("DSI VC(%d) error, vc irqstatus %x\n", | |
562 | i, vcstatus[i]); | |
563 | print_irq_status_vc(i, vcstatus[i]); | |
564 | } else if (debug_irq) { | |
565 | print_irq_status_vc(i, vcstatus[i]); | |
566 | } | |
567 | } | |
3de7a1dc | 568 | |
69b281a6 TV |
569 | if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { |
570 | DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); | |
571 | print_irq_status_cio(ciostatus); | |
572 | } else if (debug_irq) { | |
573 | print_irq_status_cio(ciostatus); | |
574 | } | |
575 | } | |
3de7a1dc | 576 | |
4ae2dddd TV |
577 | static void dsi_call_isrs(struct dsi_isr_data *isr_array, |
578 | unsigned isr_array_size, u32 irqstatus) | |
579 | { | |
580 | struct dsi_isr_data *isr_data; | |
581 | int i; | |
582 | ||
583 | for (i = 0; i < isr_array_size; i++) { | |
584 | isr_data = &isr_array[i]; | |
585 | if (isr_data->isr && isr_data->mask & irqstatus) | |
586 | isr_data->isr(isr_data->arg, irqstatus); | |
587 | } | |
588 | } | |
589 | ||
590 | static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, | |
591 | u32 irqstatus, u32 *vcstatus, u32 ciostatus) | |
592 | { | |
593 | int i; | |
594 | ||
595 | dsi_call_isrs(isr_tables->isr_table, | |
596 | ARRAY_SIZE(isr_tables->isr_table), | |
597 | irqstatus); | |
598 | ||
599 | for (i = 0; i < 4; ++i) { | |
600 | if (vcstatus[i] == 0) | |
601 | continue; | |
602 | dsi_call_isrs(isr_tables->isr_table_vc[i], | |
603 | ARRAY_SIZE(isr_tables->isr_table_vc[i]), | |
604 | vcstatus[i]); | |
605 | } | |
606 | ||
607 | if (ciostatus != 0) | |
608 | dsi_call_isrs(isr_tables->isr_table_cio, | |
609 | ARRAY_SIZE(isr_tables->isr_table_cio), | |
610 | ciostatus); | |
611 | } | |
612 | ||
69b281a6 TV |
613 | static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) |
614 | { | |
615 | u32 irqstatus, vcstatus[4], ciostatus; | |
616 | int i; | |
dfc0fd8d | 617 | |
4ae2dddd TV |
618 | spin_lock(&dsi.irq_lock); |
619 | ||
69b281a6 | 620 | irqstatus = dsi_read_reg(DSI_IRQSTATUS); |
3de7a1dc | 621 | |
69b281a6 | 622 | /* IRQ is not for us */ |
4ae2dddd TV |
623 | if (!irqstatus) { |
624 | spin_unlock(&dsi.irq_lock); | |
69b281a6 | 625 | return IRQ_NONE; |
4ae2dddd | 626 | } |
ab83b14c | 627 | |
69b281a6 TV |
628 | dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); |
629 | /* flush posted write */ | |
630 | dsi_read_reg(DSI_IRQSTATUS); | |
631 | ||
632 | for (i = 0; i < 4; ++i) { | |
633 | if ((irqstatus & (1 << i)) == 0) { | |
634 | vcstatus[i] = 0; | |
635 | continue; | |
3de7a1dc TV |
636 | } |
637 | ||
69b281a6 TV |
638 | vcstatus[i] = dsi_read_reg(DSI_VC_IRQSTATUS(i)); |
639 | ||
640 | dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus[i]); | |
3de7a1dc TV |
641 | /* flush posted write */ |
642 | dsi_read_reg(DSI_VC_IRQSTATUS(i)); | |
643 | } | |
644 | ||
645 | if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { | |
646 | ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); | |
647 | ||
648 | dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus); | |
649 | /* flush posted write */ | |
650 | dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS); | |
69b281a6 TV |
651 | } else { |
652 | ciostatus = 0; | |
653 | } | |
3de7a1dc | 654 | |
69b281a6 TV |
655 | #ifdef DSI_CATCH_MISSING_TE |
656 | if (irqstatus & DSI_IRQ_TE_TRIGGER) | |
657 | del_timer(&dsi.te_timer); | |
658 | #endif | |
659 | ||
4ae2dddd TV |
660 | /* make a copy and unlock, so that isrs can unregister |
661 | * themselves */ | |
662 | memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables)); | |
663 | ||
664 | spin_unlock(&dsi.irq_lock); | |
665 | ||
666 | dsi_handle_isrs(&dsi.isr_tables_copy, irqstatus, vcstatus, ciostatus); | |
667 | ||
69b281a6 TV |
668 | dsi_handle_irq_errors(irqstatus, vcstatus, ciostatus); |
669 | ||
670 | dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus); | |
dfc0fd8d | 671 | |
affe360d | 672 | return IRQ_HANDLED; |
3de7a1dc TV |
673 | } |
674 | ||
4ae2dddd TV |
675 | /* dsi.irq_lock has to be locked by the caller */ |
676 | static void _omap_dsi_configure_irqs(struct dsi_isr_data *isr_array, | |
677 | unsigned isr_array_size, u32 default_mask, | |
678 | const struct dsi_reg enable_reg, | |
679 | const struct dsi_reg status_reg) | |
3de7a1dc | 680 | { |
4ae2dddd TV |
681 | struct dsi_isr_data *isr_data; |
682 | u32 mask; | |
683 | u32 old_mask; | |
3de7a1dc TV |
684 | int i; |
685 | ||
4ae2dddd | 686 | mask = default_mask; |
3de7a1dc | 687 | |
4ae2dddd TV |
688 | for (i = 0; i < isr_array_size; i++) { |
689 | isr_data = &isr_array[i]; | |
3de7a1dc | 690 | |
4ae2dddd TV |
691 | if (isr_data->isr == NULL) |
692 | continue; | |
693 | ||
694 | mask |= isr_data->mask; | |
3de7a1dc TV |
695 | } |
696 | ||
4ae2dddd TV |
697 | old_mask = dsi_read_reg(enable_reg); |
698 | /* clear the irqstatus for newly enabled irqs */ | |
699 | dsi_write_reg(status_reg, (mask ^ old_mask) & mask); | |
700 | dsi_write_reg(enable_reg, mask); | |
701 | ||
702 | /* flush posted writes */ | |
703 | dsi_read_reg(enable_reg); | |
704 | dsi_read_reg(status_reg); | |
705 | } | |
3de7a1dc | 706 | |
4ae2dddd TV |
707 | /* dsi.irq_lock has to be locked by the caller */ |
708 | static void _omap_dsi_set_irqs(void) | |
709 | { | |
710 | u32 mask = DSI_IRQ_ERROR_MASK; | |
3de7a1dc | 711 | #ifdef DSI_CATCH_MISSING_TE |
4ae2dddd | 712 | mask |= DSI_IRQ_TE_TRIGGER; |
3de7a1dc | 713 | #endif |
4ae2dddd TV |
714 | _omap_dsi_configure_irqs(dsi.isr_tables.isr_table, |
715 | ARRAY_SIZE(dsi.isr_tables.isr_table), mask, | |
716 | DSI_IRQENABLE, DSI_IRQSTATUS); | |
717 | } | |
3de7a1dc | 718 | |
4ae2dddd TV |
719 | /* dsi.irq_lock has to be locked by the caller */ |
720 | static void _omap_dsi_set_irqs_vc(int vc) | |
721 | { | |
722 | _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_vc[vc], | |
723 | ARRAY_SIZE(dsi.isr_tables.isr_table_vc[vc]), | |
724 | DSI_VC_IRQ_ERROR_MASK, | |
725 | DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); | |
726 | } | |
727 | ||
728 | /* dsi.irq_lock has to be locked by the caller */ | |
729 | static void _omap_dsi_set_irqs_cio(void) | |
730 | { | |
731 | _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_cio, | |
732 | ARRAY_SIZE(dsi.isr_tables.isr_table_cio), | |
733 | DSI_CIO_IRQ_ERROR_MASK, | |
734 | DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); | |
735 | } | |
736 | ||
737 | static void _dsi_initialize_irq(void) | |
738 | { | |
739 | unsigned long flags; | |
740 | int vc; | |
741 | ||
742 | spin_lock_irqsave(&dsi.irq_lock, flags); | |
743 | ||
744 | memset(&dsi.isr_tables, 0, sizeof(dsi.isr_tables)); | |
745 | ||
746 | _omap_dsi_set_irqs(); | |
747 | for (vc = 0; vc < 4; ++vc) | |
748 | _omap_dsi_set_irqs_vc(vc); | |
749 | _omap_dsi_set_irqs_cio(); | |
750 | ||
751 | spin_unlock_irqrestore(&dsi.irq_lock, flags); | |
752 | } | |
3de7a1dc | 753 | |
4ae2dddd TV |
754 | static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, |
755 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
756 | { | |
757 | struct dsi_isr_data *isr_data; | |
758 | int free_idx; | |
759 | int i; | |
760 | ||
761 | BUG_ON(isr == NULL); | |
762 | ||
763 | /* check for duplicate entry and find a free slot */ | |
764 | free_idx = -1; | |
765 | for (i = 0; i < isr_array_size; i++) { | |
766 | isr_data = &isr_array[i]; | |
767 | ||
768 | if (isr_data->isr == isr && isr_data->arg == arg && | |
769 | isr_data->mask == mask) { | |
770 | return -EINVAL; | |
771 | } | |
772 | ||
773 | if (isr_data->isr == NULL && free_idx == -1) | |
774 | free_idx = i; | |
775 | } | |
776 | ||
777 | if (free_idx == -1) | |
778 | return -EBUSY; | |
779 | ||
780 | isr_data = &isr_array[free_idx]; | |
781 | isr_data->isr = isr; | |
782 | isr_data->arg = arg; | |
783 | isr_data->mask = mask; | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, | |
789 | struct dsi_isr_data *isr_array, unsigned isr_array_size) | |
790 | { | |
791 | struct dsi_isr_data *isr_data; | |
792 | int i; | |
793 | ||
794 | for (i = 0; i < isr_array_size; i++) { | |
795 | isr_data = &isr_array[i]; | |
796 | if (isr_data->isr != isr || isr_data->arg != arg || | |
797 | isr_data->mask != mask) | |
798 | continue; | |
799 | ||
800 | isr_data->isr = NULL; | |
801 | isr_data->arg = NULL; | |
802 | isr_data->mask = 0; | |
803 | ||
804 | return 0; | |
805 | } | |
806 | ||
807 | return -EINVAL; | |
808 | } | |
809 | ||
810 | static int dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask) | |
811 | { | |
812 | unsigned long flags; | |
813 | int r; | |
814 | ||
815 | spin_lock_irqsave(&dsi.irq_lock, flags); | |
816 | ||
817 | r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table, | |
818 | ARRAY_SIZE(dsi.isr_tables.isr_table)); | |
819 | ||
820 | if (r == 0) | |
821 | _omap_dsi_set_irqs(); | |
822 | ||
823 | spin_unlock_irqrestore(&dsi.irq_lock, flags); | |
824 | ||
825 | return r; | |
826 | } | |
827 | ||
828 | static int dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask) | |
829 | { | |
830 | unsigned long flags; | |
831 | int r; | |
832 | ||
833 | spin_lock_irqsave(&dsi.irq_lock, flags); | |
834 | ||
835 | r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table, | |
836 | ARRAY_SIZE(dsi.isr_tables.isr_table)); | |
837 | ||
838 | if (r == 0) | |
839 | _omap_dsi_set_irqs(); | |
840 | ||
841 | spin_unlock_irqrestore(&dsi.irq_lock, flags); | |
842 | ||
843 | return r; | |
844 | } | |
845 | ||
846 | static int dsi_register_isr_vc(int channel, omap_dsi_isr_t isr, void *arg, | |
847 | u32 mask) | |
848 | { | |
849 | unsigned long flags; | |
850 | int r; | |
851 | ||
852 | spin_lock_irqsave(&dsi.irq_lock, flags); | |
853 | ||
854 | r = _dsi_register_isr(isr, arg, mask, | |
855 | dsi.isr_tables.isr_table_vc[channel], | |
856 | ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel])); | |
857 | ||
858 | if (r == 0) | |
859 | _omap_dsi_set_irqs_vc(channel); | |
860 | ||
861 | spin_unlock_irqrestore(&dsi.irq_lock, flags); | |
862 | ||
863 | return r; | |
864 | } | |
865 | ||
866 | static int dsi_unregister_isr_vc(int channel, omap_dsi_isr_t isr, void *arg, | |
867 | u32 mask) | |
868 | { | |
869 | unsigned long flags; | |
870 | int r; | |
871 | ||
872 | spin_lock_irqsave(&dsi.irq_lock, flags); | |
873 | ||
874 | r = _dsi_unregister_isr(isr, arg, mask, | |
875 | dsi.isr_tables.isr_table_vc[channel], | |
876 | ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel])); | |
877 | ||
878 | if (r == 0) | |
879 | _omap_dsi_set_irqs_vc(channel); | |
880 | ||
881 | spin_unlock_irqrestore(&dsi.irq_lock, flags); | |
882 | ||
883 | return r; | |
884 | } | |
885 | ||
886 | static int dsi_register_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask) | |
887 | { | |
888 | unsigned long flags; | |
889 | int r; | |
890 | ||
891 | spin_lock_irqsave(&dsi.irq_lock, flags); | |
892 | ||
893 | r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio, | |
894 | ARRAY_SIZE(dsi.isr_tables.isr_table_cio)); | |
895 | ||
896 | if (r == 0) | |
897 | _omap_dsi_set_irqs_cio(); | |
898 | ||
899 | spin_unlock_irqrestore(&dsi.irq_lock, flags); | |
900 | ||
901 | return r; | |
902 | } | |
903 | ||
904 | static int dsi_unregister_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask) | |
905 | { | |
906 | unsigned long flags; | |
907 | int r; | |
908 | ||
909 | spin_lock_irqsave(&dsi.irq_lock, flags); | |
910 | ||
911 | r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio, | |
912 | ARRAY_SIZE(dsi.isr_tables.isr_table_cio)); | |
913 | ||
914 | if (r == 0) | |
915 | _omap_dsi_set_irqs_cio(); | |
916 | ||
917 | spin_unlock_irqrestore(&dsi.irq_lock, flags); | |
918 | ||
919 | return r; | |
3de7a1dc TV |
920 | } |
921 | ||
922 | static u32 dsi_get_errors(void) | |
923 | { | |
924 | unsigned long flags; | |
925 | u32 e; | |
926 | spin_lock_irqsave(&dsi.errors_lock, flags); | |
927 | e = dsi.errors; | |
928 | dsi.errors = 0; | |
929 | spin_unlock_irqrestore(&dsi.errors_lock, flags); | |
930 | return e; | |
931 | } | |
932 | ||
1bb47835 | 933 | /* DSI func clock. this could also be dsi_pll_hsdiv_dsi_clk */ |
3de7a1dc TV |
934 | static inline void enable_clocks(bool enable) |
935 | { | |
936 | if (enable) | |
6af9cd14 | 937 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
3de7a1dc | 938 | else |
6af9cd14 | 939 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
3de7a1dc TV |
940 | } |
941 | ||
942 | /* source clock for DSI PLL. this could also be PCLKFREE */ | |
943 | static inline void dsi_enable_pll_clock(bool enable) | |
944 | { | |
945 | if (enable) | |
6af9cd14 | 946 | dss_clk_enable(DSS_CLK_SYSCK); |
3de7a1dc | 947 | else |
6af9cd14 | 948 | dss_clk_disable(DSS_CLK_SYSCK); |
3de7a1dc TV |
949 | |
950 | if (enable && dsi.pll_locked) { | |
951 | if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) | |
952 | DSSERR("cannot lock PLL when enabling clocks\n"); | |
953 | } | |
954 | } | |
955 | ||
956 | #ifdef DEBUG | |
957 | static void _dsi_print_reset_status(void) | |
958 | { | |
959 | u32 l; | |
960 | ||
961 | if (!dss_debug) | |
962 | return; | |
963 | ||
964 | /* A dummy read using the SCP interface to any DSIPHY register is | |
965 | * required after DSIPHY reset to complete the reset of the DSI complex | |
966 | * I/O. */ | |
967 | l = dsi_read_reg(DSI_DSIPHY_CFG5); | |
968 | ||
969 | printk(KERN_DEBUG "DSI resets: "); | |
970 | ||
971 | l = dsi_read_reg(DSI_PLL_STATUS); | |
972 | printk("PLL (%d) ", FLD_GET(l, 0, 0)); | |
973 | ||
974 | l = dsi_read_reg(DSI_COMPLEXIO_CFG1); | |
975 | printk("CIO (%d) ", FLD_GET(l, 29, 29)); | |
976 | ||
977 | l = dsi_read_reg(DSI_DSIPHY_CFG5); | |
978 | printk("PHY (%x, %d, %d, %d)\n", | |
979 | FLD_GET(l, 28, 26), | |
980 | FLD_GET(l, 29, 29), | |
981 | FLD_GET(l, 30, 30), | |
982 | FLD_GET(l, 31, 31)); | |
983 | } | |
984 | #else | |
985 | #define _dsi_print_reset_status() | |
986 | #endif | |
987 | ||
988 | static inline int dsi_if_enable(bool enable) | |
989 | { | |
990 | DSSDBG("dsi_if_enable(%d)\n", enable); | |
991 | ||
992 | enable = enable ? 1 : 0; | |
993 | REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */ | |
994 | ||
995 | if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) { | |
996 | DSSERR("Failed to set dsi_if_enable to %d\n", enable); | |
997 | return -EIO; | |
998 | } | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
1bb47835 | 1003 | unsigned long dsi_get_pll_hsdiv_dispc_rate(void) |
3de7a1dc | 1004 | { |
1bb47835 | 1005 | return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk; |
3de7a1dc TV |
1006 | } |
1007 | ||
1bb47835 | 1008 | static unsigned long dsi_get_pll_hsdiv_dsi_rate(void) |
3de7a1dc | 1009 | { |
1bb47835 | 1010 | return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk; |
3de7a1dc TV |
1011 | } |
1012 | ||
1013 | static unsigned long dsi_get_txbyteclkhs(void) | |
1014 | { | |
1015 | return dsi.current_cinfo.clkin4ddr / 16; | |
1016 | } | |
1017 | ||
1018 | static unsigned long dsi_fclk_rate(void) | |
1019 | { | |
1020 | unsigned long r; | |
1021 | ||
89a35e51 | 1022 | if (dss_get_dsi_clk_source() == OMAP_DSS_CLK_SRC_FCK) { |
1bb47835 | 1023 | /* DSI FCLK source is DSS_CLK_FCK */ |
6af9cd14 | 1024 | r = dss_clk_get_rate(DSS_CLK_FCK); |
3de7a1dc | 1025 | } else { |
1bb47835 AT |
1026 | /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ |
1027 | r = dsi_get_pll_hsdiv_dsi_rate(); | |
3de7a1dc TV |
1028 | } |
1029 | ||
1030 | return r; | |
1031 | } | |
1032 | ||
1033 | static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev) | |
1034 | { | |
1035 | unsigned long dsi_fclk; | |
1036 | unsigned lp_clk_div; | |
1037 | unsigned long lp_clk; | |
1038 | ||
c6940a3d | 1039 | lp_clk_div = dssdev->clocks.dsi.lp_clk_div; |
3de7a1dc | 1040 | |
49641116 | 1041 | if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max) |
3de7a1dc TV |
1042 | return -EINVAL; |
1043 | ||
1044 | dsi_fclk = dsi_fclk_rate(); | |
1045 | ||
1046 | lp_clk = dsi_fclk / 2 / lp_clk_div; | |
1047 | ||
1048 | DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); | |
1049 | dsi.current_cinfo.lp_clk = lp_clk; | |
1050 | dsi.current_cinfo.lp_clk_div = lp_clk_div; | |
1051 | ||
1052 | REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */ | |
1053 | ||
1054 | REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, | |
1055 | 21, 21); /* LP_RX_SYNCHRO_ENABLE */ | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | ||
1061 | enum dsi_pll_power_state { | |
1062 | DSI_PLL_POWER_OFF = 0x0, | |
1063 | DSI_PLL_POWER_ON_HSCLK = 0x1, | |
1064 | DSI_PLL_POWER_ON_ALL = 0x2, | |
1065 | DSI_PLL_POWER_ON_DIV = 0x3, | |
1066 | }; | |
1067 | ||
1068 | static int dsi_pll_power(enum dsi_pll_power_state state) | |
1069 | { | |
1070 | int t = 0; | |
1071 | ||
c94dfe05 TV |
1072 | /* DSI-PLL power command 0x3 is not working */ |
1073 | if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) && | |
1074 | state == DSI_PLL_POWER_ON_DIV) | |
1075 | state = DSI_PLL_POWER_ON_ALL; | |
1076 | ||
3de7a1dc TV |
1077 | REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */ |
1078 | ||
1079 | /* PLL_PWR_STATUS */ | |
1080 | while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) { | |
24be78b3 | 1081 | if (++t > 1000) { |
3de7a1dc TV |
1082 | DSSERR("Failed to set DSI PLL power mode to %d\n", |
1083 | state); | |
1084 | return -ENODEV; | |
1085 | } | |
24be78b3 | 1086 | udelay(1); |
3de7a1dc TV |
1087 | } |
1088 | ||
1089 | return 0; | |
1090 | } | |
1091 | ||
1092 | /* calculate clock rates using dividers in cinfo */ | |
ff1b2cde SS |
1093 | static int dsi_calc_clock_rates(struct omap_dss_device *dssdev, |
1094 | struct dsi_clock_info *cinfo) | |
3de7a1dc | 1095 | { |
49641116 | 1096 | if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max) |
3de7a1dc TV |
1097 | return -EINVAL; |
1098 | ||
49641116 | 1099 | if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max) |
3de7a1dc TV |
1100 | return -EINVAL; |
1101 | ||
49641116 | 1102 | if (cinfo->regm_dispc > dsi.regm_dispc_max) |
3de7a1dc TV |
1103 | return -EINVAL; |
1104 | ||
49641116 | 1105 | if (cinfo->regm_dsi > dsi.regm_dsi_max) |
3de7a1dc TV |
1106 | return -EINVAL; |
1107 | ||
1bb47835 | 1108 | if (cinfo->use_sys_clk) { |
6af9cd14 | 1109 | cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK); |
3de7a1dc | 1110 | /* XXX it is unclear if highfreq should be used |
1bb47835 | 1111 | * with DSS_SYS_CLK source also */ |
3de7a1dc TV |
1112 | cinfo->highfreq = 0; |
1113 | } else { | |
ff1b2cde | 1114 | cinfo->clkin = dispc_pclk_rate(dssdev->manager->id); |
3de7a1dc TV |
1115 | |
1116 | if (cinfo->clkin < 32000000) | |
1117 | cinfo->highfreq = 0; | |
1118 | else | |
1119 | cinfo->highfreq = 1; | |
1120 | } | |
1121 | ||
1122 | cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1)); | |
1123 | ||
49641116 | 1124 | if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min) |
3de7a1dc TV |
1125 | return -EINVAL; |
1126 | ||
1127 | cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint; | |
1128 | ||
1129 | if (cinfo->clkin4ddr > 1800 * 1000 * 1000) | |
1130 | return -EINVAL; | |
1131 | ||
1bb47835 AT |
1132 | if (cinfo->regm_dispc > 0) |
1133 | cinfo->dsi_pll_hsdiv_dispc_clk = | |
1134 | cinfo->clkin4ddr / cinfo->regm_dispc; | |
3de7a1dc | 1135 | else |
1bb47835 | 1136 | cinfo->dsi_pll_hsdiv_dispc_clk = 0; |
3de7a1dc | 1137 | |
1bb47835 AT |
1138 | if (cinfo->regm_dsi > 0) |
1139 | cinfo->dsi_pll_hsdiv_dsi_clk = | |
1140 | cinfo->clkin4ddr / cinfo->regm_dsi; | |
3de7a1dc | 1141 | else |
1bb47835 | 1142 | cinfo->dsi_pll_hsdiv_dsi_clk = 0; |
3de7a1dc TV |
1143 | |
1144 | return 0; | |
1145 | } | |
1146 | ||
1147 | int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck, | |
1148 | struct dsi_clock_info *dsi_cinfo, | |
1149 | struct dispc_clock_info *dispc_cinfo) | |
1150 | { | |
1151 | struct dsi_clock_info cur, best; | |
1152 | struct dispc_clock_info best_dispc; | |
1153 | int min_fck_per_pck; | |
1154 | int match = 0; | |
1bb47835 | 1155 | unsigned long dss_sys_clk, max_dss_fck; |
3de7a1dc | 1156 | |
1bb47835 | 1157 | dss_sys_clk = dss_clk_get_rate(DSS_CLK_SYSCK); |
3de7a1dc | 1158 | |
31ef8237 | 1159 | max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK); |
819d807c | 1160 | |
3de7a1dc | 1161 | if (req_pck == dsi.cache_req_pck && |
1bb47835 | 1162 | dsi.cache_cinfo.clkin == dss_sys_clk) { |
3de7a1dc TV |
1163 | DSSDBG("DSI clock info found from cache\n"); |
1164 | *dsi_cinfo = dsi.cache_cinfo; | |
1bb47835 AT |
1165 | dispc_find_clk_divs(is_tft, req_pck, |
1166 | dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo); | |
3de7a1dc TV |
1167 | return 0; |
1168 | } | |
1169 | ||
1170 | min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK; | |
1171 | ||
1172 | if (min_fck_per_pck && | |
819d807c | 1173 | req_pck * min_fck_per_pck > max_dss_fck) { |
3de7a1dc TV |
1174 | DSSERR("Requested pixel clock not possible with the current " |
1175 | "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning " | |
1176 | "the constraint off.\n"); | |
1177 | min_fck_per_pck = 0; | |
1178 | } | |
1179 | ||
1180 | DSSDBG("dsi_pll_calc\n"); | |
1181 | ||
1182 | retry: | |
1183 | memset(&best, 0, sizeof(best)); | |
1184 | memset(&best_dispc, 0, sizeof(best_dispc)); | |
1185 | ||
1186 | memset(&cur, 0, sizeof(cur)); | |
1bb47835 AT |
1187 | cur.clkin = dss_sys_clk; |
1188 | cur.use_sys_clk = 1; | |
3de7a1dc TV |
1189 | cur.highfreq = 0; |
1190 | ||
1191 | /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */ | |
1192 | /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */ | |
1193 | /* To reduce PLL lock time, keep Fint high (around 2 MHz) */ | |
49641116 | 1194 | for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) { |
3de7a1dc TV |
1195 | if (cur.highfreq == 0) |
1196 | cur.fint = cur.clkin / cur.regn; | |
1197 | else | |
1198 | cur.fint = cur.clkin / (2 * cur.regn); | |
1199 | ||
49641116 | 1200 | if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min) |
3de7a1dc TV |
1201 | continue; |
1202 | ||
1203 | /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */ | |
49641116 | 1204 | for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) { |
3de7a1dc TV |
1205 | unsigned long a, b; |
1206 | ||
1207 | a = 2 * cur.regm * (cur.clkin/1000); | |
1208 | b = cur.regn * (cur.highfreq + 1); | |
1209 | cur.clkin4ddr = a / b * 1000; | |
1210 | ||
1211 | if (cur.clkin4ddr > 1800 * 1000 * 1000) | |
1212 | break; | |
1213 | ||
1bb47835 AT |
1214 | /* dsi_pll_hsdiv_dispc_clk(MHz) = |
1215 | * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */ | |
49641116 | 1216 | for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max; |
1bb47835 | 1217 | ++cur.regm_dispc) { |
3de7a1dc | 1218 | struct dispc_clock_info cur_dispc; |
1bb47835 AT |
1219 | cur.dsi_pll_hsdiv_dispc_clk = |
1220 | cur.clkin4ddr / cur.regm_dispc; | |
3de7a1dc TV |
1221 | |
1222 | /* this will narrow down the search a bit, | |
1223 | * but still give pixclocks below what was | |
1224 | * requested */ | |
1bb47835 | 1225 | if (cur.dsi_pll_hsdiv_dispc_clk < req_pck) |
3de7a1dc TV |
1226 | break; |
1227 | ||
1bb47835 | 1228 | if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck) |
3de7a1dc TV |
1229 | continue; |
1230 | ||
1231 | if (min_fck_per_pck && | |
1bb47835 | 1232 | cur.dsi_pll_hsdiv_dispc_clk < |
3de7a1dc TV |
1233 | req_pck * min_fck_per_pck) |
1234 | continue; | |
1235 | ||
1236 | match = 1; | |
1237 | ||
1238 | dispc_find_clk_divs(is_tft, req_pck, | |
1bb47835 | 1239 | cur.dsi_pll_hsdiv_dispc_clk, |
3de7a1dc TV |
1240 | &cur_dispc); |
1241 | ||
1242 | if (abs(cur_dispc.pck - req_pck) < | |
1243 | abs(best_dispc.pck - req_pck)) { | |
1244 | best = cur; | |
1245 | best_dispc = cur_dispc; | |
1246 | ||
1247 | if (cur_dispc.pck == req_pck) | |
1248 | goto found; | |
1249 | } | |
1250 | } | |
1251 | } | |
1252 | } | |
1253 | found: | |
1254 | if (!match) { | |
1255 | if (min_fck_per_pck) { | |
1256 | DSSERR("Could not find suitable clock settings.\n" | |
1257 | "Turning FCK/PCK constraint off and" | |
1258 | "trying again.\n"); | |
1259 | min_fck_per_pck = 0; | |
1260 | goto retry; | |
1261 | } | |
1262 | ||
1263 | DSSERR("Could not find suitable clock settings.\n"); | |
1264 | ||
1265 | return -EINVAL; | |
1266 | } | |
1267 | ||
1bb47835 AT |
1268 | /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */ |
1269 | best.regm_dsi = 0; | |
1270 | best.dsi_pll_hsdiv_dsi_clk = 0; | |
3de7a1dc TV |
1271 | |
1272 | if (dsi_cinfo) | |
1273 | *dsi_cinfo = best; | |
1274 | if (dispc_cinfo) | |
1275 | *dispc_cinfo = best_dispc; | |
1276 | ||
1277 | dsi.cache_req_pck = req_pck; | |
1278 | dsi.cache_clk_freq = 0; | |
1279 | dsi.cache_cinfo = best; | |
1280 | ||
1281 | return 0; | |
1282 | } | |
1283 | ||
1284 | int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) | |
1285 | { | |
1286 | int r = 0; | |
1287 | u32 l; | |
9613c02b | 1288 | int f = 0; |
49641116 TA |
1289 | u8 regn_start, regn_end, regm_start, regm_end; |
1290 | u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end; | |
3de7a1dc TV |
1291 | |
1292 | DSSDBGF(); | |
1293 | ||
b2765092 TV |
1294 | dsi.current_cinfo.use_sys_clk = cinfo->use_sys_clk; |
1295 | dsi.current_cinfo.highfreq = cinfo->highfreq; | |
1296 | ||
3de7a1dc TV |
1297 | dsi.current_cinfo.fint = cinfo->fint; |
1298 | dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr; | |
1bb47835 AT |
1299 | dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk = |
1300 | cinfo->dsi_pll_hsdiv_dispc_clk; | |
1301 | dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk = | |
1302 | cinfo->dsi_pll_hsdiv_dsi_clk; | |
3de7a1dc TV |
1303 | |
1304 | dsi.current_cinfo.regn = cinfo->regn; | |
1305 | dsi.current_cinfo.regm = cinfo->regm; | |
1bb47835 AT |
1306 | dsi.current_cinfo.regm_dispc = cinfo->regm_dispc; |
1307 | dsi.current_cinfo.regm_dsi = cinfo->regm_dsi; | |
3de7a1dc TV |
1308 | |
1309 | DSSDBG("DSI Fint %ld\n", cinfo->fint); | |
1310 | ||
1311 | DSSDBG("clkin (%s) rate %ld, highfreq %d\n", | |
1bb47835 | 1312 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree", |
3de7a1dc TV |
1313 | cinfo->clkin, |
1314 | cinfo->highfreq); | |
1315 | ||
1316 | /* DSIPHY == CLKIN4DDR */ | |
1317 | DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n", | |
1318 | cinfo->regm, | |
1319 | cinfo->regn, | |
1320 | cinfo->clkin, | |
1321 | cinfo->highfreq + 1, | |
1322 | cinfo->clkin4ddr); | |
1323 | ||
1324 | DSSDBG("Data rate on 1 DSI lane %ld Mbps\n", | |
1325 | cinfo->clkin4ddr / 1000 / 1000 / 2); | |
1326 | ||
1327 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); | |
1328 | ||
1bb47835 | 1329 | DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc, |
89a35e51 AT |
1330 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1331 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), | |
1bb47835 AT |
1332 | cinfo->dsi_pll_hsdiv_dispc_clk); |
1333 | DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi, | |
89a35e51 AT |
1334 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
1335 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | |
1bb47835 | 1336 | cinfo->dsi_pll_hsdiv_dsi_clk); |
3de7a1dc | 1337 | |
49641116 TA |
1338 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end); |
1339 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end); | |
1340 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start, | |
1341 | ®m_dispc_end); | |
1342 | dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start, | |
1343 | ®m_dsi_end); | |
1344 | ||
3de7a1dc TV |
1345 | REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ |
1346 | ||
1347 | l = dsi_read_reg(DSI_PLL_CONFIGURATION1); | |
1348 | l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */ | |
49641116 TA |
1349 | /* DSI_PLL_REGN */ |
1350 | l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end); | |
1351 | /* DSI_PLL_REGM */ | |
1352 | l = FLD_MOD(l, cinfo->regm, regm_start, regm_end); | |
1353 | /* DSI_CLOCK_DIV */ | |
1bb47835 | 1354 | l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0, |
49641116 TA |
1355 | regm_dispc_start, regm_dispc_end); |
1356 | /* DSIPROTO_CLOCK_DIV */ | |
1bb47835 | 1357 | l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0, |
49641116 | 1358 | regm_dsi_start, regm_dsi_end); |
3de7a1dc TV |
1359 | dsi_write_reg(DSI_PLL_CONFIGURATION1, l); |
1360 | ||
49641116 | 1361 | BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max); |
9613c02b AT |
1362 | |
1363 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) { | |
1364 | f = cinfo->fint < 1000000 ? 0x3 : | |
1365 | cinfo->fint < 1250000 ? 0x4 : | |
1366 | cinfo->fint < 1500000 ? 0x5 : | |
1367 | cinfo->fint < 1750000 ? 0x6 : | |
1368 | 0x7; | |
1369 | } | |
3de7a1dc TV |
1370 | |
1371 | l = dsi_read_reg(DSI_PLL_CONFIGURATION2); | |
9613c02b AT |
1372 | |
1373 | if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) | |
1374 | l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */ | |
1bb47835 | 1375 | l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1, |
3de7a1dc TV |
1376 | 11, 11); /* DSI_PLL_CLKSEL */ |
1377 | l = FLD_MOD(l, cinfo->highfreq, | |
1378 | 12, 12); /* DSI_PLL_HIGHFREQ */ | |
1379 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ | |
1380 | l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */ | |
1381 | l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */ | |
1382 | dsi_write_reg(DSI_PLL_CONFIGURATION2, l); | |
1383 | ||
1384 | REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ | |
1385 | ||
1386 | if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) { | |
1387 | DSSERR("dsi pll go bit not going down.\n"); | |
1388 | r = -EIO; | |
1389 | goto err; | |
1390 | } | |
1391 | ||
1392 | if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) { | |
1393 | DSSERR("cannot lock PLL\n"); | |
1394 | r = -EIO; | |
1395 | goto err; | |
1396 | } | |
1397 | ||
1398 | dsi.pll_locked = 1; | |
1399 | ||
1400 | l = dsi_read_reg(DSI_PLL_CONFIGURATION2); | |
1401 | l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */ | |
1402 | l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */ | |
1403 | l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */ | |
1404 | l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */ | |
1405 | l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */ | |
1406 | l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */ | |
1407 | l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */ | |
1408 | l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */ | |
1409 | l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */ | |
1410 | l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */ | |
1411 | l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */ | |
1412 | l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */ | |
1413 | l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */ | |
1414 | l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */ | |
1415 | dsi_write_reg(DSI_PLL_CONFIGURATION2, l); | |
1416 | ||
1417 | DSSDBG("PLL config done\n"); | |
1418 | err: | |
1419 | return r; | |
1420 | } | |
1421 | ||
1422 | int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk, | |
1423 | bool enable_hsdiv) | |
1424 | { | |
1425 | int r = 0; | |
1426 | enum dsi_pll_power_state pwstate; | |
1427 | ||
1428 | DSSDBG("PLL init\n"); | |
1429 | ||
f2988ab9 TV |
1430 | if (dsi.vdds_dsi_reg == NULL) { |
1431 | struct regulator *vdds_dsi; | |
1432 | ||
1433 | vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); | |
1434 | ||
1435 | if (IS_ERR(vdds_dsi)) { | |
1436 | DSSERR("can't get VDDS_DSI regulator\n"); | |
1437 | return PTR_ERR(vdds_dsi); | |
1438 | } | |
1439 | ||
1440 | dsi.vdds_dsi_reg = vdds_dsi; | |
1441 | } | |
f2988ab9 | 1442 | |
3de7a1dc TV |
1443 | enable_clocks(1); |
1444 | dsi_enable_pll_clock(1); | |
1445 | ||
1446 | r = regulator_enable(dsi.vdds_dsi_reg); | |
1447 | if (r) | |
1448 | goto err0; | |
1449 | ||
1450 | /* XXX PLL does not come out of reset without this... */ | |
1451 | dispc_pck_free_enable(1); | |
1452 | ||
1453 | if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) { | |
1454 | DSSERR("PLL not coming out of reset.\n"); | |
1455 | r = -ENODEV; | |
481dfa0e | 1456 | dispc_pck_free_enable(0); |
3de7a1dc TV |
1457 | goto err1; |
1458 | } | |
1459 | ||
1460 | /* XXX ... but if left on, we get problems when planes do not | |
1461 | * fill the whole display. No idea about this */ | |
1462 | dispc_pck_free_enable(0); | |
1463 | ||
1464 | if (enable_hsclk && enable_hsdiv) | |
1465 | pwstate = DSI_PLL_POWER_ON_ALL; | |
1466 | else if (enable_hsclk) | |
1467 | pwstate = DSI_PLL_POWER_ON_HSCLK; | |
1468 | else if (enable_hsdiv) | |
1469 | pwstate = DSI_PLL_POWER_ON_DIV; | |
1470 | else | |
1471 | pwstate = DSI_PLL_POWER_OFF; | |
1472 | ||
1473 | r = dsi_pll_power(pwstate); | |
1474 | ||
1475 | if (r) | |
1476 | goto err1; | |
1477 | ||
1478 | DSSDBG("PLL init done\n"); | |
1479 | ||
1480 | return 0; | |
1481 | err1: | |
1482 | regulator_disable(dsi.vdds_dsi_reg); | |
1483 | err0: | |
1484 | enable_clocks(0); | |
1485 | dsi_enable_pll_clock(0); | |
1486 | return r; | |
1487 | } | |
1488 | ||
1489 | void dsi_pll_uninit(void) | |
1490 | { | |
1491 | enable_clocks(0); | |
1492 | dsi_enable_pll_clock(0); | |
1493 | ||
1494 | dsi.pll_locked = 0; | |
1495 | dsi_pll_power(DSI_PLL_POWER_OFF); | |
1496 | regulator_disable(dsi.vdds_dsi_reg); | |
1497 | DSSDBG("PLL uninit done\n"); | |
1498 | } | |
1499 | ||
1500 | void dsi_dump_clocks(struct seq_file *s) | |
1501 | { | |
3de7a1dc | 1502 | struct dsi_clock_info *cinfo = &dsi.current_cinfo; |
89a35e51 | 1503 | enum omap_dss_clk_source dispc_clk_src, dsi_clk_src; |
067a57e4 AT |
1504 | |
1505 | dispc_clk_src = dss_get_dispc_clk_source(); | |
1506 | dsi_clk_src = dss_get_dsi_clk_source(); | |
3de7a1dc TV |
1507 | |
1508 | enable_clocks(1); | |
1509 | ||
3de7a1dc TV |
1510 | seq_printf(s, "- DSI PLL -\n"); |
1511 | ||
1512 | seq_printf(s, "dsi pll source = %s\n", | |
a9a6500b | 1513 | cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree"); |
3de7a1dc TV |
1514 | |
1515 | seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn); | |
1516 | ||
1517 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", | |
1518 | cinfo->clkin4ddr, cinfo->regm); | |
1519 | ||
1bb47835 | 1520 | seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n", |
067a57e4 AT |
1521 | dss_get_generic_clk_source_name(dispc_clk_src), |
1522 | dss_feat_get_clk_source_name(dispc_clk_src), | |
1bb47835 AT |
1523 | cinfo->dsi_pll_hsdiv_dispc_clk, |
1524 | cinfo->regm_dispc, | |
89a35e51 | 1525 | dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1526 | "off" : "on"); |
3de7a1dc | 1527 | |
1bb47835 | 1528 | seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n", |
067a57e4 AT |
1529 | dss_get_generic_clk_source_name(dsi_clk_src), |
1530 | dss_feat_get_clk_source_name(dsi_clk_src), | |
1bb47835 AT |
1531 | cinfo->dsi_pll_hsdiv_dsi_clk, |
1532 | cinfo->regm_dsi, | |
89a35e51 | 1533 | dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ? |
63cf28ac | 1534 | "off" : "on"); |
3de7a1dc TV |
1535 | |
1536 | seq_printf(s, "- DSI -\n"); | |
1537 | ||
067a57e4 AT |
1538 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
1539 | dss_get_generic_clk_source_name(dsi_clk_src), | |
1540 | dss_feat_get_clk_source_name(dsi_clk_src)); | |
3de7a1dc TV |
1541 | |
1542 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); | |
1543 | ||
1544 | seq_printf(s, "DDR_CLK\t\t%lu\n", | |
1545 | cinfo->clkin4ddr / 4); | |
1546 | ||
1547 | seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs()); | |
1548 | ||
1549 | seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk); | |
1550 | ||
1551 | seq_printf(s, "VP_CLK\t\t%lu\n" | |
1552 | "VP_PCLK\t\t%lu\n", | |
ff1b2cde SS |
1553 | dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), |
1554 | dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD)); | |
3de7a1dc TV |
1555 | |
1556 | enable_clocks(0); | |
1557 | } | |
1558 | ||
dfc0fd8d TV |
1559 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
1560 | void dsi_dump_irqs(struct seq_file *s) | |
1561 | { | |
1562 | unsigned long flags; | |
1563 | struct dsi_irq_stats stats; | |
1564 | ||
1565 | spin_lock_irqsave(&dsi.irq_stats_lock, flags); | |
1566 | ||
1567 | stats = dsi.irq_stats; | |
1568 | memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats)); | |
1569 | dsi.irq_stats.last_reset = jiffies; | |
1570 | ||
1571 | spin_unlock_irqrestore(&dsi.irq_stats_lock, flags); | |
1572 | ||
1573 | seq_printf(s, "period %u ms\n", | |
1574 | jiffies_to_msecs(jiffies - stats.last_reset)); | |
1575 | ||
1576 | seq_printf(s, "irqs %d\n", stats.irq_count); | |
1577 | #define PIS(x) \ | |
1578 | seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]); | |
1579 | ||
1580 | seq_printf(s, "-- DSI interrupts --\n"); | |
1581 | PIS(VC0); | |
1582 | PIS(VC1); | |
1583 | PIS(VC2); | |
1584 | PIS(VC3); | |
1585 | PIS(WAKEUP); | |
1586 | PIS(RESYNC); | |
1587 | PIS(PLL_LOCK); | |
1588 | PIS(PLL_UNLOCK); | |
1589 | PIS(PLL_RECALL); | |
1590 | PIS(COMPLEXIO_ERR); | |
1591 | PIS(HS_TX_TIMEOUT); | |
1592 | PIS(LP_RX_TIMEOUT); | |
1593 | PIS(TE_TRIGGER); | |
1594 | PIS(ACK_TRIGGER); | |
1595 | PIS(SYNC_LOST); | |
1596 | PIS(LDO_POWER_GOOD); | |
1597 | PIS(TA_TIMEOUT); | |
1598 | #undef PIS | |
1599 | ||
1600 | #define PIS(x) \ | |
1601 | seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ | |
1602 | stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ | |
1603 | stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ | |
1604 | stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ | |
1605 | stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); | |
1606 | ||
1607 | seq_printf(s, "-- VC interrupts --\n"); | |
1608 | PIS(CS); | |
1609 | PIS(ECC_CORR); | |
1610 | PIS(PACKET_SENT); | |
1611 | PIS(FIFO_TX_OVF); | |
1612 | PIS(FIFO_RX_OVF); | |
1613 | PIS(BTA); | |
1614 | PIS(ECC_NO_CORR); | |
1615 | PIS(FIFO_TX_UDF); | |
1616 | PIS(PP_BUSY_CHANGE); | |
1617 | #undef PIS | |
1618 | ||
1619 | #define PIS(x) \ | |
1620 | seq_printf(s, "%-20s %10d\n", #x, \ | |
1621 | stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); | |
1622 | ||
1623 | seq_printf(s, "-- CIO interrupts --\n"); | |
1624 | PIS(ERRSYNCESC1); | |
1625 | PIS(ERRSYNCESC2); | |
1626 | PIS(ERRSYNCESC3); | |
1627 | PIS(ERRESC1); | |
1628 | PIS(ERRESC2); | |
1629 | PIS(ERRESC3); | |
1630 | PIS(ERRCONTROL1); | |
1631 | PIS(ERRCONTROL2); | |
1632 | PIS(ERRCONTROL3); | |
1633 | PIS(STATEULPS1); | |
1634 | PIS(STATEULPS2); | |
1635 | PIS(STATEULPS3); | |
1636 | PIS(ERRCONTENTIONLP0_1); | |
1637 | PIS(ERRCONTENTIONLP1_1); | |
1638 | PIS(ERRCONTENTIONLP0_2); | |
1639 | PIS(ERRCONTENTIONLP1_2); | |
1640 | PIS(ERRCONTENTIONLP0_3); | |
1641 | PIS(ERRCONTENTIONLP1_3); | |
1642 | PIS(ULPSACTIVENOT_ALL0); | |
1643 | PIS(ULPSACTIVENOT_ALL1); | |
1644 | #undef PIS | |
1645 | } | |
1646 | #endif | |
1647 | ||
3de7a1dc TV |
1648 | void dsi_dump_regs(struct seq_file *s) |
1649 | { | |
1650 | #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r)) | |
1651 | ||
6af9cd14 | 1652 | dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK); |
3de7a1dc TV |
1653 | |
1654 | DUMPREG(DSI_REVISION); | |
1655 | DUMPREG(DSI_SYSCONFIG); | |
1656 | DUMPREG(DSI_SYSSTATUS); | |
1657 | DUMPREG(DSI_IRQSTATUS); | |
1658 | DUMPREG(DSI_IRQENABLE); | |
1659 | DUMPREG(DSI_CTRL); | |
1660 | DUMPREG(DSI_COMPLEXIO_CFG1); | |
1661 | DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); | |
1662 | DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); | |
1663 | DUMPREG(DSI_CLK_CTRL); | |
1664 | DUMPREG(DSI_TIMING1); | |
1665 | DUMPREG(DSI_TIMING2); | |
1666 | DUMPREG(DSI_VM_TIMING1); | |
1667 | DUMPREG(DSI_VM_TIMING2); | |
1668 | DUMPREG(DSI_VM_TIMING3); | |
1669 | DUMPREG(DSI_CLK_TIMING); | |
1670 | DUMPREG(DSI_TX_FIFO_VC_SIZE); | |
1671 | DUMPREG(DSI_RX_FIFO_VC_SIZE); | |
1672 | DUMPREG(DSI_COMPLEXIO_CFG2); | |
1673 | DUMPREG(DSI_RX_FIFO_VC_FULLNESS); | |
1674 | DUMPREG(DSI_VM_TIMING4); | |
1675 | DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); | |
1676 | DUMPREG(DSI_VM_TIMING5); | |
1677 | DUMPREG(DSI_VM_TIMING6); | |
1678 | DUMPREG(DSI_VM_TIMING7); | |
1679 | DUMPREG(DSI_STOPCLK_TIMING); | |
1680 | ||
1681 | DUMPREG(DSI_VC_CTRL(0)); | |
1682 | DUMPREG(DSI_VC_TE(0)); | |
1683 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); | |
1684 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); | |
1685 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); | |
1686 | DUMPREG(DSI_VC_IRQSTATUS(0)); | |
1687 | DUMPREG(DSI_VC_IRQENABLE(0)); | |
1688 | ||
1689 | DUMPREG(DSI_VC_CTRL(1)); | |
1690 | DUMPREG(DSI_VC_TE(1)); | |
1691 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); | |
1692 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); | |
1693 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); | |
1694 | DUMPREG(DSI_VC_IRQSTATUS(1)); | |
1695 | DUMPREG(DSI_VC_IRQENABLE(1)); | |
1696 | ||
1697 | DUMPREG(DSI_VC_CTRL(2)); | |
1698 | DUMPREG(DSI_VC_TE(2)); | |
1699 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); | |
1700 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); | |
1701 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); | |
1702 | DUMPREG(DSI_VC_IRQSTATUS(2)); | |
1703 | DUMPREG(DSI_VC_IRQENABLE(2)); | |
1704 | ||
1705 | DUMPREG(DSI_VC_CTRL(3)); | |
1706 | DUMPREG(DSI_VC_TE(3)); | |
1707 | DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); | |
1708 | DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); | |
1709 | DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); | |
1710 | DUMPREG(DSI_VC_IRQSTATUS(3)); | |
1711 | DUMPREG(DSI_VC_IRQENABLE(3)); | |
1712 | ||
1713 | DUMPREG(DSI_DSIPHY_CFG0); | |
1714 | DUMPREG(DSI_DSIPHY_CFG1); | |
1715 | DUMPREG(DSI_DSIPHY_CFG2); | |
1716 | DUMPREG(DSI_DSIPHY_CFG5); | |
1717 | ||
1718 | DUMPREG(DSI_PLL_CONTROL); | |
1719 | DUMPREG(DSI_PLL_STATUS); | |
1720 | DUMPREG(DSI_PLL_GO); | |
1721 | DUMPREG(DSI_PLL_CONFIGURATION1); | |
1722 | DUMPREG(DSI_PLL_CONFIGURATION2); | |
1723 | ||
6af9cd14 | 1724 | dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK); |
3de7a1dc TV |
1725 | #undef DUMPREG |
1726 | } | |
1727 | ||
1728 | enum dsi_complexio_power_state { | |
1729 | DSI_COMPLEXIO_POWER_OFF = 0x0, | |
1730 | DSI_COMPLEXIO_POWER_ON = 0x1, | |
1731 | DSI_COMPLEXIO_POWER_ULPS = 0x2, | |
1732 | }; | |
1733 | ||
1734 | static int dsi_complexio_power(enum dsi_complexio_power_state state) | |
1735 | { | |
1736 | int t = 0; | |
1737 | ||
1738 | /* PWR_CMD */ | |
1739 | REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27); | |
1740 | ||
1741 | /* PWR_STATUS */ | |
1742 | while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) { | |
24be78b3 | 1743 | if (++t > 1000) { |
3de7a1dc TV |
1744 | DSSERR("failed to set complexio power state to " |
1745 | "%d\n", state); | |
1746 | return -ENODEV; | |
1747 | } | |
24be78b3 | 1748 | udelay(1); |
3de7a1dc TV |
1749 | } |
1750 | ||
1751 | return 0; | |
1752 | } | |
1753 | ||
1754 | static void dsi_complexio_config(struct omap_dss_device *dssdev) | |
1755 | { | |
1756 | u32 r; | |
1757 | ||
1758 | int clk_lane = dssdev->phy.dsi.clk_lane; | |
1759 | int data1_lane = dssdev->phy.dsi.data1_lane; | |
1760 | int data2_lane = dssdev->phy.dsi.data2_lane; | |
1761 | int clk_pol = dssdev->phy.dsi.clk_pol; | |
1762 | int data1_pol = dssdev->phy.dsi.data1_pol; | |
1763 | int data2_pol = dssdev->phy.dsi.data2_pol; | |
1764 | ||
1765 | r = dsi_read_reg(DSI_COMPLEXIO_CFG1); | |
1766 | r = FLD_MOD(r, clk_lane, 2, 0); | |
1767 | r = FLD_MOD(r, clk_pol, 3, 3); | |
1768 | r = FLD_MOD(r, data1_lane, 6, 4); | |
1769 | r = FLD_MOD(r, data1_pol, 7, 7); | |
1770 | r = FLD_MOD(r, data2_lane, 10, 8); | |
1771 | r = FLD_MOD(r, data2_pol, 11, 11); | |
1772 | dsi_write_reg(DSI_COMPLEXIO_CFG1, r); | |
1773 | ||
1774 | /* The configuration of the DSI complex I/O (number of data lanes, | |
1775 | position, differential order) should not be changed while | |
1776 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for | |
1777 | the hardware to take into account a new configuration of the complex | |
1778 | I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to | |
1779 | follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, | |
1780 | then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set | |
1781 | DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the | |
1782 | DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the | |
1783 | DSI complex I/O configuration is unknown. */ | |
1784 | ||
1785 | /* | |
1786 | REG_FLD_MOD(DSI_CTRL, 1, 0, 0); | |
1787 | REG_FLD_MOD(DSI_CTRL, 0, 0, 0); | |
1788 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); | |
1789 | REG_FLD_MOD(DSI_CTRL, 1, 0, 0); | |
1790 | */ | |
1791 | } | |
1792 | ||
1793 | static inline unsigned ns2ddr(unsigned ns) | |
1794 | { | |
1795 | /* convert time in ns to ddr ticks, rounding up */ | |
1796 | unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; | |
1797 | return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; | |
1798 | } | |
1799 | ||
1800 | static inline unsigned ddr2ns(unsigned ddr) | |
1801 | { | |
1802 | unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4; | |
1803 | return ddr * 1000 * 1000 / (ddr_clk / 1000); | |
1804 | } | |
1805 | ||
1806 | static void dsi_complexio_timings(void) | |
1807 | { | |
1808 | u32 r; | |
1809 | u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; | |
1810 | u32 tlpx_half, tclk_trail, tclk_zero; | |
1811 | u32 tclk_prepare; | |
1812 | ||
1813 | /* calculate timings */ | |
1814 | ||
1815 | /* 1 * DDR_CLK = 2 * UI */ | |
1816 | ||
1817 | /* min 40ns + 4*UI max 85ns + 6*UI */ | |
1818 | ths_prepare = ns2ddr(70) + 2; | |
1819 | ||
1820 | /* min 145ns + 10*UI */ | |
1821 | ths_prepare_ths_zero = ns2ddr(175) + 2; | |
1822 | ||
1823 | /* min max(8*UI, 60ns+4*UI) */ | |
1824 | ths_trail = ns2ddr(60) + 5; | |
1825 | ||
1826 | /* min 100ns */ | |
1827 | ths_exit = ns2ddr(145); | |
1828 | ||
1829 | /* tlpx min 50n */ | |
1830 | tlpx_half = ns2ddr(25); | |
1831 | ||
1832 | /* min 60ns */ | |
1833 | tclk_trail = ns2ddr(60) + 2; | |
1834 | ||
1835 | /* min 38ns, max 95ns */ | |
1836 | tclk_prepare = ns2ddr(65); | |
1837 | ||
1838 | /* min tclk-prepare + tclk-zero = 300ns */ | |
1839 | tclk_zero = ns2ddr(260); | |
1840 | ||
1841 | DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", | |
1842 | ths_prepare, ddr2ns(ths_prepare), | |
1843 | ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero)); | |
1844 | DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", | |
1845 | ths_trail, ddr2ns(ths_trail), | |
1846 | ths_exit, ddr2ns(ths_exit)); | |
1847 | ||
1848 | DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " | |
1849 | "tclk_zero %u (%uns)\n", | |
1850 | tlpx_half, ddr2ns(tlpx_half), | |
1851 | tclk_trail, ddr2ns(tclk_trail), | |
1852 | tclk_zero, ddr2ns(tclk_zero)); | |
1853 | DSSDBG("tclk_prepare %u (%uns)\n", | |
1854 | tclk_prepare, ddr2ns(tclk_prepare)); | |
1855 | ||
1856 | /* program timings */ | |
1857 | ||
1858 | r = dsi_read_reg(DSI_DSIPHY_CFG0); | |
1859 | r = FLD_MOD(r, ths_prepare, 31, 24); | |
1860 | r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); | |
1861 | r = FLD_MOD(r, ths_trail, 15, 8); | |
1862 | r = FLD_MOD(r, ths_exit, 7, 0); | |
1863 | dsi_write_reg(DSI_DSIPHY_CFG0, r); | |
1864 | ||
1865 | r = dsi_read_reg(DSI_DSIPHY_CFG1); | |
1866 | r = FLD_MOD(r, tlpx_half, 22, 16); | |
1867 | r = FLD_MOD(r, tclk_trail, 15, 8); | |
1868 | r = FLD_MOD(r, tclk_zero, 7, 0); | |
1869 | dsi_write_reg(DSI_DSIPHY_CFG1, r); | |
1870 | ||
1871 | r = dsi_read_reg(DSI_DSIPHY_CFG2); | |
1872 | r = FLD_MOD(r, tclk_prepare, 7, 0); | |
1873 | dsi_write_reg(DSI_DSIPHY_CFG2, r); | |
1874 | } | |
1875 | ||
0a0ee46b TV |
1876 | static void dsi_enable_lane_override(struct omap_dss_device *dssdev, |
1877 | enum dsi_lane lanes) | |
1878 | { | |
1879 | int clk_lane = dssdev->phy.dsi.clk_lane; | |
1880 | int data1_lane = dssdev->phy.dsi.data1_lane; | |
1881 | int data2_lane = dssdev->phy.dsi.data2_lane; | |
1882 | int clk_pol = dssdev->phy.dsi.clk_pol; | |
1883 | int data1_pol = dssdev->phy.dsi.data1_pol; | |
1884 | int data2_pol = dssdev->phy.dsi.data2_pol; | |
1885 | ||
1886 | u32 l = 0; | |
1887 | ||
1888 | if (lanes & DSI_CLK_P) | |
1889 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1)); | |
1890 | if (lanes & DSI_CLK_N) | |
1891 | l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0)); | |
1892 | ||
1893 | if (lanes & DSI_DATA1_P) | |
1894 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1)); | |
1895 | if (lanes & DSI_DATA1_N) | |
1896 | l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0)); | |
1897 | ||
1898 | if (lanes & DSI_DATA2_P) | |
1899 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1)); | |
1900 | if (lanes & DSI_DATA2_N) | |
1901 | l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0)); | |
1902 | ||
1903 | /* | |
1904 | * Bits in REGLPTXSCPDAT4TO0DXDY: | |
1905 | * 17: DY0 18: DX0 | |
1906 | * 19: DY1 20: DX1 | |
1907 | * 21: DY2 22: DX2 | |
1908 | */ | |
1909 | ||
1910 | /* Set the lane override configuration */ | |
1911 | REG_FLD_MOD(DSI_DSIPHY_CFG10, l, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */ | |
1912 | ||
1913 | /* Enable lane override */ | |
1914 | REG_FLD_MOD(DSI_DSIPHY_CFG10, 1, 27, 27); /* ENLPTXSCPDAT */ | |
1915 | } | |
1916 | ||
1917 | static void dsi_disable_lane_override(void) | |
1918 | { | |
1919 | /* Disable lane override */ | |
1920 | REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ | |
1921 | /* Reset the lane override configuration */ | |
1922 | REG_FLD_MOD(DSI_DSIPHY_CFG10, 0, 22, 17); /* REGLPTXSCPDAT4TO0DXDY */ | |
1923 | } | |
3de7a1dc TV |
1924 | |
1925 | static int dsi_complexio_init(struct omap_dss_device *dssdev) | |
1926 | { | |
1927 | int r = 0; | |
1928 | ||
1929 | DSSDBG("dsi_complexio_init\n"); | |
1930 | ||
3de7a1dc TV |
1931 | /* A dummy read using the SCP interface to any DSIPHY register is |
1932 | * required after DSIPHY reset to complete the reset of the DSI complex | |
1933 | * I/O. */ | |
1934 | dsi_read_reg(DSI_DSIPHY_CFG5); | |
1935 | ||
1936 | if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) { | |
1937 | DSSERR("ComplexIO PHY not coming out of reset.\n"); | |
1938 | r = -ENODEV; | |
1939 | goto err; | |
1940 | } | |
1941 | ||
1942 | dsi_complexio_config(dssdev); | |
1943 | ||
1944 | r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON); | |
1945 | ||
1946 | if (r) | |
1947 | goto err; | |
1948 | ||
1949 | if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) { | |
1950 | DSSERR("ComplexIO not coming out of reset.\n"); | |
1951 | r = -ENODEV; | |
1952 | goto err; | |
1953 | } | |
1954 | ||
3de7a1dc TV |
1955 | dsi_complexio_timings(); |
1956 | ||
1957 | /* | |
1958 | The configuration of the DSI complex I/O (number of data lanes, | |
1959 | position, differential order) should not be changed while | |
1960 | DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the | |
1961 | hardware to recognize a new configuration of the complex I/O (done | |
1962 | in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow | |
1963 | this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next | |
1964 | reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20] | |
1965 | LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN | |
1966 | bit to 1. If the sequence is not followed, the DSi complex I/O | |
1967 | configuration is undetermined. | |
1968 | */ | |
1969 | dsi_if_enable(1); | |
1970 | dsi_if_enable(0); | |
1971 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ | |
1972 | dsi_if_enable(1); | |
1973 | dsi_if_enable(0); | |
1974 | ||
1975 | DSSDBG("CIO init done\n"); | |
1976 | err: | |
1977 | return r; | |
1978 | } | |
1979 | ||
1980 | static void dsi_complexio_uninit(void) | |
1981 | { | |
1982 | dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF); | |
1983 | } | |
1984 | ||
1985 | static int _dsi_wait_reset(void) | |
1986 | { | |
24be78b3 | 1987 | int t = 0; |
3de7a1dc TV |
1988 | |
1989 | while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) { | |
24be78b3 | 1990 | if (++t > 5) { |
3de7a1dc TV |
1991 | DSSERR("soft reset failed\n"); |
1992 | return -ENODEV; | |
1993 | } | |
1994 | udelay(1); | |
1995 | } | |
1996 | ||
1997 | return 0; | |
1998 | } | |
1999 | ||
2000 | static int _dsi_reset(void) | |
2001 | { | |
2002 | /* Soft reset */ | |
2003 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1); | |
2004 | return _dsi_wait_reset(); | |
2005 | } | |
2006 | ||
3de7a1dc TV |
2007 | static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2, |
2008 | enum fifo_size size3, enum fifo_size size4) | |
2009 | { | |
2010 | u32 r = 0; | |
2011 | int add = 0; | |
2012 | int i; | |
2013 | ||
2014 | dsi.vc[0].fifo_size = size1; | |
2015 | dsi.vc[1].fifo_size = size2; | |
2016 | dsi.vc[2].fifo_size = size3; | |
2017 | dsi.vc[3].fifo_size = size4; | |
2018 | ||
2019 | for (i = 0; i < 4; i++) { | |
2020 | u8 v; | |
2021 | int size = dsi.vc[i].fifo_size; | |
2022 | ||
2023 | if (add + size > 4) { | |
2024 | DSSERR("Illegal FIFO configuration\n"); | |
2025 | BUG(); | |
2026 | } | |
2027 | ||
2028 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2029 | r |= v << (8 * i); | |
2030 | /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2031 | add += size; | |
2032 | } | |
2033 | ||
2034 | dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r); | |
2035 | } | |
2036 | ||
2037 | static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2, | |
2038 | enum fifo_size size3, enum fifo_size size4) | |
2039 | { | |
2040 | u32 r = 0; | |
2041 | int add = 0; | |
2042 | int i; | |
2043 | ||
2044 | dsi.vc[0].fifo_size = size1; | |
2045 | dsi.vc[1].fifo_size = size2; | |
2046 | dsi.vc[2].fifo_size = size3; | |
2047 | dsi.vc[3].fifo_size = size4; | |
2048 | ||
2049 | for (i = 0; i < 4; i++) { | |
2050 | u8 v; | |
2051 | int size = dsi.vc[i].fifo_size; | |
2052 | ||
2053 | if (add + size > 4) { | |
2054 | DSSERR("Illegal FIFO configuration\n"); | |
2055 | BUG(); | |
2056 | } | |
2057 | ||
2058 | v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); | |
2059 | r |= v << (8 * i); | |
2060 | /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ | |
2061 | add += size; | |
2062 | } | |
2063 | ||
2064 | dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r); | |
2065 | } | |
2066 | ||
2067 | static int dsi_force_tx_stop_mode_io(void) | |
2068 | { | |
2069 | u32 r; | |
2070 | ||
2071 | r = dsi_read_reg(DSI_TIMING1); | |
2072 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ | |
2073 | dsi_write_reg(DSI_TIMING1, r); | |
2074 | ||
2075 | if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) { | |
2076 | DSSERR("TX_STOP bit not going down\n"); | |
2077 | return -EIO; | |
2078 | } | |
2079 | ||
2080 | return 0; | |
2081 | } | |
2082 | ||
cf398fb3 AT |
2083 | static bool dsi_vc_is_enabled(int channel) |
2084 | { | |
2085 | return REG_GET(DSI_VC_CTRL(channel), 0, 0); | |
2086 | } | |
2087 | ||
2088 | static void dsi_packet_sent_handler_vp(void *data, u32 mask) | |
2089 | { | |
2090 | const int channel = dsi.update_channel; | |
2091 | u8 bit = dsi.te_enabled ? 30 : 31; | |
2092 | ||
2093 | if (REG_GET(DSI_VC_TE(channel), bit, bit) == 0) | |
2094 | complete((struct completion *)data); | |
2095 | } | |
2096 | ||
2097 | static int dsi_sync_vc_vp(int channel) | |
2098 | { | |
2099 | int r = 0; | |
2100 | u8 bit; | |
2101 | ||
2102 | DECLARE_COMPLETION_ONSTACK(completion); | |
2103 | ||
2104 | bit = dsi.te_enabled ? 30 : 31; | |
2105 | ||
2106 | r = dsi_register_isr_vc(channel, dsi_packet_sent_handler_vp, | |
2107 | &completion, DSI_VC_IRQ_PACKET_SENT); | |
2108 | if (r) | |
2109 | goto err0; | |
2110 | ||
2111 | /* Wait for completion only if TE_EN/TE_START is still set */ | |
2112 | if (REG_GET(DSI_VC_TE(channel), bit, bit)) { | |
2113 | if (wait_for_completion_timeout(&completion, | |
2114 | msecs_to_jiffies(10)) == 0) { | |
2115 | DSSERR("Failed to complete previous frame transfer\n"); | |
2116 | r = -EIO; | |
2117 | goto err1; | |
2118 | } | |
2119 | } | |
2120 | ||
2121 | dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_vp, | |
2122 | &completion, DSI_VC_IRQ_PACKET_SENT); | |
2123 | ||
2124 | return 0; | |
2125 | err1: | |
2126 | dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_vp, &completion, | |
2127 | DSI_VC_IRQ_PACKET_SENT); | |
2128 | err0: | |
2129 | return r; | |
2130 | } | |
2131 | ||
2132 | static void dsi_packet_sent_handler_l4(void *data, u32 mask) | |
2133 | { | |
2134 | const int channel = dsi.update_channel; | |
2135 | ||
2136 | if (REG_GET(DSI_VC_CTRL(channel), 5, 5) == 0) | |
2137 | complete((struct completion *)data); | |
2138 | } | |
2139 | ||
2140 | static int dsi_sync_vc_l4(int channel) | |
2141 | { | |
2142 | int r = 0; | |
2143 | ||
2144 | DECLARE_COMPLETION_ONSTACK(completion); | |
2145 | ||
2146 | r = dsi_register_isr_vc(channel, dsi_packet_sent_handler_l4, | |
2147 | &completion, DSI_VC_IRQ_PACKET_SENT); | |
2148 | if (r) | |
2149 | goto err0; | |
2150 | ||
2151 | /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ | |
2152 | if (REG_GET(DSI_VC_CTRL(channel), 5, 5)) { | |
2153 | if (wait_for_completion_timeout(&completion, | |
2154 | msecs_to_jiffies(10)) == 0) { | |
2155 | DSSERR("Failed to complete previous l4 transfer\n"); | |
2156 | r = -EIO; | |
2157 | goto err1; | |
2158 | } | |
2159 | } | |
2160 | ||
2161 | dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_l4, | |
2162 | &completion, DSI_VC_IRQ_PACKET_SENT); | |
2163 | ||
2164 | return 0; | |
2165 | err1: | |
2166 | dsi_unregister_isr_vc(channel, dsi_packet_sent_handler_l4, | |
2167 | &completion, DSI_VC_IRQ_PACKET_SENT); | |
2168 | err0: | |
2169 | return r; | |
2170 | } | |
2171 | ||
2172 | static int dsi_sync_vc(int channel) | |
2173 | { | |
2174 | WARN_ON(!dsi_bus_is_locked()); | |
2175 | ||
2176 | WARN_ON(in_interrupt()); | |
2177 | ||
2178 | if (!dsi_vc_is_enabled(channel)) | |
2179 | return 0; | |
2180 | ||
2181 | switch (dsi.vc[channel].mode) { | |
2182 | case DSI_VC_MODE_VP: | |
2183 | return dsi_sync_vc_vp(channel); | |
2184 | case DSI_VC_MODE_L4: | |
2185 | return dsi_sync_vc_l4(channel); | |
2186 | default: | |
2187 | BUG(); | |
2188 | } | |
2189 | } | |
2190 | ||
3de7a1dc TV |
2191 | static int dsi_vc_enable(int channel, bool enable) |
2192 | { | |
446f7bff TV |
2193 | DSSDBG("dsi_vc_enable channel %d, enable %d\n", |
2194 | channel, enable); | |
3de7a1dc TV |
2195 | |
2196 | enable = enable ? 1 : 0; | |
2197 | ||
2198 | REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0); | |
2199 | ||
2200 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) { | |
2201 | DSSERR("Failed to set dsi_vc_enable to %d\n", enable); | |
2202 | return -EIO; | |
2203 | } | |
2204 | ||
2205 | return 0; | |
2206 | } | |
2207 | ||
2208 | static void dsi_vc_initial_config(int channel) | |
2209 | { | |
2210 | u32 r; | |
2211 | ||
2212 | DSSDBGF("%d", channel); | |
2213 | ||
2214 | r = dsi_read_reg(DSI_VC_CTRL(channel)); | |
2215 | ||
2216 | if (FLD_GET(r, 15, 15)) /* VC_BUSY */ | |
2217 | DSSERR("VC(%d) busy when trying to configure it!\n", | |
2218 | channel); | |
2219 | ||
2220 | r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ | |
2221 | r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ | |
2222 | r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ | |
2223 | r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ | |
2224 | r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ | |
2225 | r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ | |
2226 | r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ | |
9613c02b AT |
2227 | if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH)) |
2228 | r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ | |
3de7a1dc TV |
2229 | |
2230 | r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ | |
2231 | r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ | |
2232 | ||
2233 | dsi_write_reg(DSI_VC_CTRL(channel), r); | |
3de7a1dc TV |
2234 | } |
2235 | ||
9ecd9684 | 2236 | static int dsi_vc_config_l4(int channel) |
3de7a1dc TV |
2237 | { |
2238 | if (dsi.vc[channel].mode == DSI_VC_MODE_L4) | |
9ecd9684 | 2239 | return 0; |
3de7a1dc TV |
2240 | |
2241 | DSSDBGF("%d", channel); | |
2242 | ||
cf398fb3 AT |
2243 | dsi_sync_vc(channel); |
2244 | ||
3de7a1dc TV |
2245 | dsi_vc_enable(channel, 0); |
2246 | ||
9ecd9684 TV |
2247 | /* VC_BUSY */ |
2248 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { | |
3de7a1dc | 2249 | DSSERR("vc(%d) busy when trying to config for L4\n", channel); |
9ecd9684 TV |
2250 | return -EIO; |
2251 | } | |
3de7a1dc TV |
2252 | |
2253 | REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */ | |
2254 | ||
9613c02b AT |
2255 | /* DCS_CMD_ENABLE */ |
2256 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) | |
2257 | REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 30, 30); | |
2258 | ||
3de7a1dc TV |
2259 | dsi_vc_enable(channel, 1); |
2260 | ||
2261 | dsi.vc[channel].mode = DSI_VC_MODE_L4; | |
9ecd9684 TV |
2262 | |
2263 | return 0; | |
3de7a1dc TV |
2264 | } |
2265 | ||
9ecd9684 | 2266 | static int dsi_vc_config_vp(int channel) |
3de7a1dc TV |
2267 | { |
2268 | if (dsi.vc[channel].mode == DSI_VC_MODE_VP) | |
9ecd9684 | 2269 | return 0; |
3de7a1dc TV |
2270 | |
2271 | DSSDBGF("%d", channel); | |
2272 | ||
cf398fb3 AT |
2273 | dsi_sync_vc(channel); |
2274 | ||
3de7a1dc TV |
2275 | dsi_vc_enable(channel, 0); |
2276 | ||
9ecd9684 TV |
2277 | /* VC_BUSY */ |
2278 | if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) { | |
3de7a1dc | 2279 | DSSERR("vc(%d) busy when trying to config for VP\n", channel); |
9ecd9684 TV |
2280 | return -EIO; |
2281 | } | |
3de7a1dc TV |
2282 | |
2283 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */ | |
2284 | ||
9613c02b AT |
2285 | /* DCS_CMD_ENABLE */ |
2286 | if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) | |
2287 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 30, 30); | |
2288 | ||
3de7a1dc TV |
2289 | dsi_vc_enable(channel, 1); |
2290 | ||
2291 | dsi.vc[channel].mode = DSI_VC_MODE_VP; | |
9ecd9684 TV |
2292 | |
2293 | return 0; | |
3de7a1dc TV |
2294 | } |
2295 | ||
2296 | ||
61140c9a | 2297 | void omapdss_dsi_vc_enable_hs(int channel, bool enable) |
3de7a1dc TV |
2298 | { |
2299 | DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); | |
2300 | ||
61140c9a TV |
2301 | WARN_ON(!dsi_bus_is_locked()); |
2302 | ||
3de7a1dc TV |
2303 | dsi_vc_enable(channel, 0); |
2304 | dsi_if_enable(0); | |
2305 | ||
2306 | REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9); | |
2307 | ||
2308 | dsi_vc_enable(channel, 1); | |
2309 | dsi_if_enable(1); | |
2310 | ||
2311 | dsi_force_tx_stop_mode_io(); | |
2312 | } | |
61140c9a | 2313 | EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs); |
3de7a1dc TV |
2314 | |
2315 | static void dsi_vc_flush_long_data(int channel) | |
2316 | { | |
2317 | while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { | |
2318 | u32 val; | |
2319 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); | |
2320 | DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", | |
2321 | (val >> 0) & 0xff, | |
2322 | (val >> 8) & 0xff, | |
2323 | (val >> 16) & 0xff, | |
2324 | (val >> 24) & 0xff); | |
2325 | } | |
2326 | } | |
2327 | ||
2328 | static void dsi_show_rx_ack_with_err(u16 err) | |
2329 | { | |
2330 | DSSERR("\tACK with ERROR (%#x):\n", err); | |
2331 | if (err & (1 << 0)) | |
2332 | DSSERR("\t\tSoT Error\n"); | |
2333 | if (err & (1 << 1)) | |
2334 | DSSERR("\t\tSoT Sync Error\n"); | |
2335 | if (err & (1 << 2)) | |
2336 | DSSERR("\t\tEoT Sync Error\n"); | |
2337 | if (err & (1 << 3)) | |
2338 | DSSERR("\t\tEscape Mode Entry Command Error\n"); | |
2339 | if (err & (1 << 4)) | |
2340 | DSSERR("\t\tLP Transmit Sync Error\n"); | |
2341 | if (err & (1 << 5)) | |
2342 | DSSERR("\t\tHS Receive Timeout Error\n"); | |
2343 | if (err & (1 << 6)) | |
2344 | DSSERR("\t\tFalse Control Error\n"); | |
2345 | if (err & (1 << 7)) | |
2346 | DSSERR("\t\t(reserved7)\n"); | |
2347 | if (err & (1 << 8)) | |
2348 | DSSERR("\t\tECC Error, single-bit (corrected)\n"); | |
2349 | if (err & (1 << 9)) | |
2350 | DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); | |
2351 | if (err & (1 << 10)) | |
2352 | DSSERR("\t\tChecksum Error\n"); | |
2353 | if (err & (1 << 11)) | |
2354 | DSSERR("\t\tData type not recognized\n"); | |
2355 | if (err & (1 << 12)) | |
2356 | DSSERR("\t\tInvalid VC ID\n"); | |
2357 | if (err & (1 << 13)) | |
2358 | DSSERR("\t\tInvalid Transmission Length\n"); | |
2359 | if (err & (1 << 14)) | |
2360 | DSSERR("\t\t(reserved14)\n"); | |
2361 | if (err & (1 << 15)) | |
2362 | DSSERR("\t\tDSI Protocol Violation\n"); | |
2363 | } | |
2364 | ||
2365 | static u16 dsi_vc_flush_receive_data(int channel) | |
2366 | { | |
2367 | /* RX_FIFO_NOT_EMPTY */ | |
2368 | while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { | |
2369 | u32 val; | |
2370 | u8 dt; | |
2371 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); | |
86a7867e | 2372 | DSSERR("\trawval %#08x\n", val); |
3de7a1dc TV |
2373 | dt = FLD_GET(val, 5, 0); |
2374 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { | |
2375 | u16 err = FLD_GET(val, 23, 8); | |
2376 | dsi_show_rx_ack_with_err(err); | |
2377 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { | |
86a7867e | 2378 | DSSERR("\tDCS short response, 1 byte: %#x\n", |
3de7a1dc TV |
2379 | FLD_GET(val, 23, 8)); |
2380 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { | |
86a7867e | 2381 | DSSERR("\tDCS short response, 2 byte: %#x\n", |
3de7a1dc TV |
2382 | FLD_GET(val, 23, 8)); |
2383 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { | |
86a7867e | 2384 | DSSERR("\tDCS long response, len %d\n", |
3de7a1dc TV |
2385 | FLD_GET(val, 23, 8)); |
2386 | dsi_vc_flush_long_data(channel); | |
2387 | } else { | |
2388 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
2389 | } | |
2390 | } | |
2391 | return 0; | |
2392 | } | |
2393 | ||
2394 | static int dsi_vc_send_bta(int channel) | |
2395 | { | |
446f7bff | 2396 | if (dsi.debug_write || dsi.debug_read) |
3de7a1dc TV |
2397 | DSSDBG("dsi_vc_send_bta %d\n", channel); |
2398 | ||
4f765023 | 2399 | WARN_ON(!dsi_bus_is_locked()); |
3de7a1dc TV |
2400 | |
2401 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ | |
2402 | DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); | |
2403 | dsi_vc_flush_receive_data(channel); | |
2404 | } | |
2405 | ||
2406 | REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ | |
2407 | ||
2408 | return 0; | |
2409 | } | |
2410 | ||
2411 | int dsi_vc_send_bta_sync(int channel) | |
2412 | { | |
f36a06e7 | 2413 | DECLARE_COMPLETION_ONSTACK(completion); |
3de7a1dc TV |
2414 | int r = 0; |
2415 | u32 err; | |
2416 | ||
f36a06e7 TV |
2417 | r = dsi_register_isr_vc(channel, dsi_completion_handler, |
2418 | &completion, DSI_VC_IRQ_BTA); | |
2419 | if (r) | |
2420 | goto err0; | |
3de7a1dc | 2421 | |
773b30b2 TV |
2422 | r = dsi_register_isr(dsi_completion_handler, &completion, |
2423 | DSI_IRQ_ERROR_MASK); | |
3de7a1dc | 2424 | if (r) |
f36a06e7 | 2425 | goto err1; |
3de7a1dc | 2426 | |
773b30b2 TV |
2427 | r = dsi_vc_send_bta(channel); |
2428 | if (r) | |
2429 | goto err2; | |
2430 | ||
f36a06e7 | 2431 | if (wait_for_completion_timeout(&completion, |
3de7a1dc TV |
2432 | msecs_to_jiffies(500)) == 0) { |
2433 | DSSERR("Failed to receive BTA\n"); | |
2434 | r = -EIO; | |
773b30b2 | 2435 | goto err2; |
3de7a1dc TV |
2436 | } |
2437 | ||
2438 | err = dsi_get_errors(); | |
2439 | if (err) { | |
2440 | DSSERR("Error while sending BTA: %x\n", err); | |
2441 | r = -EIO; | |
773b30b2 | 2442 | goto err2; |
3de7a1dc | 2443 | } |
773b30b2 TV |
2444 | err2: |
2445 | dsi_unregister_isr(dsi_completion_handler, &completion, | |
2446 | DSI_IRQ_ERROR_MASK); | |
f36a06e7 TV |
2447 | err1: |
2448 | dsi_unregister_isr_vc(channel, dsi_completion_handler, | |
2449 | &completion, DSI_VC_IRQ_BTA); | |
2450 | err0: | |
3de7a1dc TV |
2451 | return r; |
2452 | } | |
2453 | EXPORT_SYMBOL(dsi_vc_send_bta_sync); | |
2454 | ||
2455 | static inline void dsi_vc_write_long_header(int channel, u8 data_type, | |
2456 | u16 len, u8 ecc) | |
2457 | { | |
2458 | u32 val; | |
2459 | u8 data_id; | |
2460 | ||
4f765023 | 2461 | WARN_ON(!dsi_bus_is_locked()); |
3de7a1dc | 2462 | |
5ee3c144 | 2463 | data_id = data_type | dsi.vc[channel].vc_id << 6; |
3de7a1dc TV |
2464 | |
2465 | val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | | |
2466 | FLD_VAL(ecc, 31, 24); | |
2467 | ||
2468 | dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val); | |
2469 | } | |
2470 | ||
2471 | static inline void dsi_vc_write_long_payload(int channel, | |
2472 | u8 b1, u8 b2, u8 b3, u8 b4) | |
2473 | { | |
2474 | u32 val; | |
2475 | ||
2476 | val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; | |
2477 | ||
2478 | /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", | |
2479 | b1, b2, b3, b4, val); */ | |
2480 | ||
2481 | dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val); | |
2482 | } | |
2483 | ||
2484 | static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len, | |
2485 | u8 ecc) | |
2486 | { | |
2487 | /*u32 val; */ | |
2488 | int i; | |
2489 | u8 *p; | |
2490 | int r = 0; | |
2491 | u8 b1, b2, b3, b4; | |
2492 | ||
2493 | if (dsi.debug_write) | |
2494 | DSSDBG("dsi_vc_send_long, %d bytes\n", len); | |
2495 | ||
2496 | /* len + header */ | |
2497 | if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) { | |
2498 | DSSERR("unable to send long packet: packet too long.\n"); | |
2499 | return -EINVAL; | |
2500 | } | |
2501 | ||
2502 | dsi_vc_config_l4(channel); | |
2503 | ||
2504 | dsi_vc_write_long_header(channel, data_type, len, ecc); | |
2505 | ||
3de7a1dc TV |
2506 | p = data; |
2507 | for (i = 0; i < len >> 2; i++) { | |
2508 | if (dsi.debug_write) | |
2509 | DSSDBG("\tsending full packet %d\n", i); | |
3de7a1dc TV |
2510 | |
2511 | b1 = *p++; | |
2512 | b2 = *p++; | |
2513 | b3 = *p++; | |
2514 | b4 = *p++; | |
2515 | ||
2516 | dsi_vc_write_long_payload(channel, b1, b2, b3, b4); | |
2517 | } | |
2518 | ||
2519 | i = len % 4; | |
2520 | if (i) { | |
2521 | b1 = 0; b2 = 0; b3 = 0; | |
2522 | ||
2523 | if (dsi.debug_write) | |
2524 | DSSDBG("\tsending remainder bytes %d\n", i); | |
2525 | ||
2526 | switch (i) { | |
2527 | case 3: | |
2528 | b1 = *p++; | |
2529 | b2 = *p++; | |
2530 | b3 = *p++; | |
2531 | break; | |
2532 | case 2: | |
2533 | b1 = *p++; | |
2534 | b2 = *p++; | |
2535 | break; | |
2536 | case 1: | |
2537 | b1 = *p++; | |
2538 | break; | |
2539 | } | |
2540 | ||
2541 | dsi_vc_write_long_payload(channel, b1, b2, b3, 0); | |
2542 | } | |
2543 | ||
2544 | return r; | |
2545 | } | |
2546 | ||
2547 | static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc) | |
2548 | { | |
2549 | u32 r; | |
2550 | u8 data_id; | |
2551 | ||
4f765023 | 2552 | WARN_ON(!dsi_bus_is_locked()); |
3de7a1dc TV |
2553 | |
2554 | if (dsi.debug_write) | |
2555 | DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", | |
2556 | channel, | |
2557 | data_type, data & 0xff, (data >> 8) & 0xff); | |
2558 | ||
2559 | dsi_vc_config_l4(channel); | |
2560 | ||
2561 | if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) { | |
2562 | DSSERR("ERROR FIFO FULL, aborting transfer\n"); | |
2563 | return -EINVAL; | |
2564 | } | |
2565 | ||
5ee3c144 | 2566 | data_id = data_type | dsi.vc[channel].vc_id << 6; |
3de7a1dc TV |
2567 | |
2568 | r = (data_id << 0) | (data << 8) | (ecc << 24); | |
2569 | ||
2570 | dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r); | |
2571 | ||
2572 | return 0; | |
2573 | } | |
2574 | ||
2575 | int dsi_vc_send_null(int channel) | |
2576 | { | |
2577 | u8 nullpkg[] = {0, 0, 0, 0}; | |
397bb3c2 | 2578 | return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0); |
3de7a1dc TV |
2579 | } |
2580 | EXPORT_SYMBOL(dsi_vc_send_null); | |
2581 | ||
2582 | int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len) | |
2583 | { | |
2584 | int r; | |
2585 | ||
2586 | BUG_ON(len == 0); | |
2587 | ||
2588 | if (len == 1) { | |
2589 | r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0, | |
2590 | data[0], 0); | |
2591 | } else if (len == 2) { | |
2592 | r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1, | |
2593 | data[0] | (data[1] << 8), 0); | |
2594 | } else { | |
2595 | /* 0x39 = DCS Long Write */ | |
2596 | r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE, | |
2597 | data, len, 0); | |
2598 | } | |
2599 | ||
2600 | return r; | |
2601 | } | |
2602 | EXPORT_SYMBOL(dsi_vc_dcs_write_nosync); | |
2603 | ||
2604 | int dsi_vc_dcs_write(int channel, u8 *data, int len) | |
2605 | { | |
2606 | int r; | |
2607 | ||
2608 | r = dsi_vc_dcs_write_nosync(channel, data, len); | |
2609 | if (r) | |
5d68e032 | 2610 | goto err; |
3de7a1dc TV |
2611 | |
2612 | r = dsi_vc_send_bta_sync(channel); | |
5d68e032 TV |
2613 | if (r) |
2614 | goto err; | |
3de7a1dc | 2615 | |
b63ac1e3 TV |
2616 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */ |
2617 | DSSERR("rx fifo not empty after write, dumping data:\n"); | |
2618 | dsi_vc_flush_receive_data(channel); | |
2619 | r = -EIO; | |
2620 | goto err; | |
2621 | } | |
2622 | ||
5d68e032 TV |
2623 | return 0; |
2624 | err: | |
2625 | DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n", | |
2626 | channel, data[0], len); | |
3de7a1dc TV |
2627 | return r; |
2628 | } | |
2629 | EXPORT_SYMBOL(dsi_vc_dcs_write); | |
2630 | ||
828c48f8 TV |
2631 | int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd) |
2632 | { | |
2633 | return dsi_vc_dcs_write(channel, &dcs_cmd, 1); | |
2634 | } | |
2635 | EXPORT_SYMBOL(dsi_vc_dcs_write_0); | |
2636 | ||
2637 | int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param) | |
2638 | { | |
2639 | u8 buf[2]; | |
2640 | buf[0] = dcs_cmd; | |
2641 | buf[1] = param; | |
2642 | return dsi_vc_dcs_write(channel, buf, 2); | |
2643 | } | |
2644 | EXPORT_SYMBOL(dsi_vc_dcs_write_1); | |
2645 | ||
3de7a1dc TV |
2646 | int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen) |
2647 | { | |
2648 | u32 val; | |
2649 | u8 dt; | |
2650 | int r; | |
2651 | ||
2652 | if (dsi.debug_read) | |
ff90a348 | 2653 | DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd); |
3de7a1dc TV |
2654 | |
2655 | r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0); | |
2656 | if (r) | |
5d68e032 | 2657 | goto err; |
3de7a1dc TV |
2658 | |
2659 | r = dsi_vc_send_bta_sync(channel); | |
2660 | if (r) | |
5d68e032 | 2661 | goto err; |
3de7a1dc TV |
2662 | |
2663 | /* RX_FIFO_NOT_EMPTY */ | |
2664 | if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) { | |
2665 | DSSERR("RX fifo empty when trying to read.\n"); | |
5d68e032 TV |
2666 | r = -EIO; |
2667 | goto err; | |
3de7a1dc TV |
2668 | } |
2669 | ||
2670 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); | |
2671 | if (dsi.debug_read) | |
2672 | DSSDBG("\theader: %08x\n", val); | |
2673 | dt = FLD_GET(val, 5, 0); | |
2674 | if (dt == DSI_DT_RX_ACK_WITH_ERR) { | |
2675 | u16 err = FLD_GET(val, 23, 8); | |
2676 | dsi_show_rx_ack_with_err(err); | |
5d68e032 TV |
2677 | r = -EIO; |
2678 | goto err; | |
3de7a1dc TV |
2679 | |
2680 | } else if (dt == DSI_DT_RX_SHORT_READ_1) { | |
2681 | u8 data = FLD_GET(val, 15, 8); | |
2682 | if (dsi.debug_read) | |
2683 | DSSDBG("\tDCS short response, 1 byte: %02x\n", data); | |
2684 | ||
5d68e032 TV |
2685 | if (buflen < 1) { |
2686 | r = -EIO; | |
2687 | goto err; | |
2688 | } | |
3de7a1dc TV |
2689 | |
2690 | buf[0] = data; | |
2691 | ||
2692 | return 1; | |
2693 | } else if (dt == DSI_DT_RX_SHORT_READ_2) { | |
2694 | u16 data = FLD_GET(val, 23, 8); | |
2695 | if (dsi.debug_read) | |
2696 | DSSDBG("\tDCS short response, 2 byte: %04x\n", data); | |
2697 | ||
5d68e032 TV |
2698 | if (buflen < 2) { |
2699 | r = -EIO; | |
2700 | goto err; | |
2701 | } | |
3de7a1dc TV |
2702 | |
2703 | buf[0] = data & 0xff; | |
2704 | buf[1] = (data >> 8) & 0xff; | |
2705 | ||
2706 | return 2; | |
2707 | } else if (dt == DSI_DT_RX_DCS_LONG_READ) { | |
2708 | int w; | |
2709 | int len = FLD_GET(val, 23, 8); | |
2710 | if (dsi.debug_read) | |
2711 | DSSDBG("\tDCS long response, len %d\n", len); | |
2712 | ||
5d68e032 TV |
2713 | if (len > buflen) { |
2714 | r = -EIO; | |
2715 | goto err; | |
2716 | } | |
3de7a1dc TV |
2717 | |
2718 | /* two byte checksum ends the packet, not included in len */ | |
2719 | for (w = 0; w < len + 2;) { | |
2720 | int b; | |
2721 | val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel)); | |
2722 | if (dsi.debug_read) | |
2723 | DSSDBG("\t\t%02x %02x %02x %02x\n", | |
2724 | (val >> 0) & 0xff, | |
2725 | (val >> 8) & 0xff, | |
2726 | (val >> 16) & 0xff, | |
2727 | (val >> 24) & 0xff); | |
2728 | ||
2729 | for (b = 0; b < 4; ++b) { | |
2730 | if (w < len) | |
2731 | buf[w] = (val >> (b * 8)) & 0xff; | |
2732 | /* we discard the 2 byte checksum */ | |
2733 | ++w; | |
2734 | } | |
2735 | } | |
2736 | ||
2737 | return len; | |
3de7a1dc TV |
2738 | } else { |
2739 | DSSERR("\tunknown datatype 0x%02x\n", dt); | |
5d68e032 TV |
2740 | r = -EIO; |
2741 | goto err; | |
3de7a1dc | 2742 | } |
5d68e032 TV |
2743 | |
2744 | BUG(); | |
2745 | err: | |
2746 | DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", | |
2747 | channel, dcs_cmd); | |
2748 | return r; | |
2749 | ||
3de7a1dc TV |
2750 | } |
2751 | EXPORT_SYMBOL(dsi_vc_dcs_read); | |
2752 | ||
828c48f8 TV |
2753 | int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data) |
2754 | { | |
2755 | int r; | |
2756 | ||
2757 | r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1); | |
2758 | ||
2759 | if (r < 0) | |
2760 | return r; | |
2761 | ||
2762 | if (r != 1) | |
2763 | return -EIO; | |
2764 | ||
2765 | return 0; | |
2766 | } | |
2767 | EXPORT_SYMBOL(dsi_vc_dcs_read_1); | |
3de7a1dc | 2768 | |
0c244f77 | 2769 | int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2) |
53055aae | 2770 | { |
0c244f77 | 2771 | u8 buf[2]; |
53055aae TV |
2772 | int r; |
2773 | ||
0c244f77 | 2774 | r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2); |
53055aae TV |
2775 | |
2776 | if (r < 0) | |
2777 | return r; | |
2778 | ||
2779 | if (r != 2) | |
2780 | return -EIO; | |
2781 | ||
0c244f77 TV |
2782 | *data1 = buf[0]; |
2783 | *data2 = buf[1]; | |
2784 | ||
53055aae TV |
2785 | return 0; |
2786 | } | |
2787 | EXPORT_SYMBOL(dsi_vc_dcs_read_2); | |
2788 | ||
3de7a1dc TV |
2789 | int dsi_vc_set_max_rx_packet_size(int channel, u16 len) |
2790 | { | |
fa15c79b | 2791 | return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE, |
3de7a1dc | 2792 | len, 0); |
3de7a1dc TV |
2793 | } |
2794 | EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size); | |
2795 | ||
4ffa3571 | 2796 | static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16) |
3de7a1dc | 2797 | { |
3de7a1dc | 2798 | unsigned long fck; |
4ffa3571 TV |
2799 | unsigned long total_ticks; |
2800 | u32 r; | |
3de7a1dc | 2801 | |
4ffa3571 | 2802 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 2803 | |
4ffa3571 | 2804 | /* ticks in DSI_FCK */ |
3de7a1dc | 2805 | fck = dsi_fclk_rate(); |
3de7a1dc TV |
2806 | |
2807 | r = dsi_read_reg(DSI_TIMING2); | |
2808 | r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ | |
4ffa3571 TV |
2809 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ |
2810 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ | |
3de7a1dc TV |
2811 | r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ |
2812 | dsi_write_reg(DSI_TIMING2, r); | |
2813 | ||
4ffa3571 TV |
2814 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
2815 | ||
2816 | DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
2817 | total_ticks, | |
2818 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
2819 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
2820 | } |
2821 | ||
4ffa3571 | 2822 | static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16) |
3de7a1dc | 2823 | { |
3de7a1dc | 2824 | unsigned long fck; |
4ffa3571 TV |
2825 | unsigned long total_ticks; |
2826 | u32 r; | |
2827 | ||
2828 | BUG_ON(ticks > 0x1fff); | |
3de7a1dc TV |
2829 | |
2830 | /* ticks in DSI_FCK */ | |
2831 | fck = dsi_fclk_rate(); | |
3de7a1dc TV |
2832 | |
2833 | r = dsi_read_reg(DSI_TIMING1); | |
2834 | r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ | |
4ffa3571 TV |
2835 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ |
2836 | r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ | |
3de7a1dc TV |
2837 | r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ |
2838 | dsi_write_reg(DSI_TIMING1, r); | |
2839 | ||
4ffa3571 TV |
2840 | total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); |
2841 | ||
2842 | DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
2843 | total_ticks, | |
2844 | ticks, x8 ? " x8" : "", x16 ? " x16" : "", | |
2845 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
2846 | } |
2847 | ||
4ffa3571 | 2848 | static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16) |
3de7a1dc | 2849 | { |
3de7a1dc | 2850 | unsigned long fck; |
4ffa3571 TV |
2851 | unsigned long total_ticks; |
2852 | u32 r; | |
3de7a1dc | 2853 | |
4ffa3571 | 2854 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 2855 | |
4ffa3571 | 2856 | /* ticks in DSI_FCK */ |
3de7a1dc | 2857 | fck = dsi_fclk_rate(); |
3de7a1dc TV |
2858 | |
2859 | r = dsi_read_reg(DSI_TIMING1); | |
2860 | r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ | |
4ffa3571 TV |
2861 | r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ |
2862 | r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ | |
3de7a1dc TV |
2863 | r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ |
2864 | dsi_write_reg(DSI_TIMING1, r); | |
2865 | ||
4ffa3571 TV |
2866 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
2867 | ||
2868 | DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", | |
2869 | total_ticks, | |
2870 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
2871 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
2872 | } |
2873 | ||
4ffa3571 | 2874 | static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16) |
3de7a1dc | 2875 | { |
3de7a1dc | 2876 | unsigned long fck; |
4ffa3571 TV |
2877 | unsigned long total_ticks; |
2878 | u32 r; | |
3de7a1dc | 2879 | |
4ffa3571 | 2880 | BUG_ON(ticks > 0x1fff); |
3de7a1dc | 2881 | |
4ffa3571 | 2882 | /* ticks in TxByteClkHS */ |
3de7a1dc | 2883 | fck = dsi_get_txbyteclkhs(); |
3de7a1dc TV |
2884 | |
2885 | r = dsi_read_reg(DSI_TIMING2); | |
2886 | r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ | |
4ffa3571 TV |
2887 | r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ |
2888 | r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ | |
3de7a1dc TV |
2889 | r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ |
2890 | dsi_write_reg(DSI_TIMING2, r); | |
2891 | ||
4ffa3571 TV |
2892 | total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); |
2893 | ||
2894 | DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", | |
2895 | total_ticks, | |
2896 | ticks, x4 ? " x4" : "", x16 ? " x16" : "", | |
2897 | (total_ticks * 1000) / (fck / 1000 / 1000)); | |
3de7a1dc TV |
2898 | } |
2899 | static int dsi_proto_config(struct omap_dss_device *dssdev) | |
2900 | { | |
2901 | u32 r; | |
2902 | int buswidth = 0; | |
2903 | ||
dd8079d6 TV |
2904 | dsi_config_tx_fifo(DSI_FIFO_SIZE_32, |
2905 | DSI_FIFO_SIZE_32, | |
2906 | DSI_FIFO_SIZE_32, | |
2907 | DSI_FIFO_SIZE_32); | |
3de7a1dc | 2908 | |
dd8079d6 TV |
2909 | dsi_config_rx_fifo(DSI_FIFO_SIZE_32, |
2910 | DSI_FIFO_SIZE_32, | |
2911 | DSI_FIFO_SIZE_32, | |
2912 | DSI_FIFO_SIZE_32); | |
3de7a1dc TV |
2913 | |
2914 | /* XXX what values for the timeouts? */ | |
4ffa3571 TV |
2915 | dsi_set_stop_state_counter(0x1000, false, false); |
2916 | dsi_set_ta_timeout(0x1fff, true, true); | |
2917 | dsi_set_lp_rx_timeout(0x1fff, true, true); | |
2918 | dsi_set_hs_tx_timeout(0x1fff, true, true); | |
3de7a1dc TV |
2919 | |
2920 | switch (dssdev->ctrl.pixel_size) { | |
2921 | case 16: | |
2922 | buswidth = 0; | |
2923 | break; | |
2924 | case 18: | |
2925 | buswidth = 1; | |
2926 | break; | |
2927 | case 24: | |
2928 | buswidth = 2; | |
2929 | break; | |
2930 | default: | |
2931 | BUG(); | |
2932 | } | |
2933 | ||
2934 | r = dsi_read_reg(DSI_CTRL); | |
2935 | r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ | |
2936 | r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ | |
2937 | r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ | |
2938 | r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ | |
2939 | r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ | |
2940 | r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ | |
2941 | r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */ | |
2942 | r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ | |
2943 | r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ | |
9613c02b AT |
2944 | if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) { |
2945 | r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ | |
2946 | /* DCS_CMD_CODE, 1=start, 0=continue */ | |
2947 | r = FLD_MOD(r, 0, 25, 25); | |
2948 | } | |
3de7a1dc TV |
2949 | |
2950 | dsi_write_reg(DSI_CTRL, r); | |
2951 | ||
2952 | dsi_vc_initial_config(0); | |
dd8079d6 TV |
2953 | dsi_vc_initial_config(1); |
2954 | dsi_vc_initial_config(2); | |
2955 | dsi_vc_initial_config(3); | |
3de7a1dc TV |
2956 | |
2957 | return 0; | |
2958 | } | |
2959 | ||
2960 | static void dsi_proto_timings(struct omap_dss_device *dssdev) | |
2961 | { | |
2962 | unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail; | |
2963 | unsigned tclk_pre, tclk_post; | |
2964 | unsigned ths_prepare, ths_prepare_ths_zero, ths_zero; | |
2965 | unsigned ths_trail, ths_exit; | |
2966 | unsigned ddr_clk_pre, ddr_clk_post; | |
2967 | unsigned enter_hs_mode_lat, exit_hs_mode_lat; | |
2968 | unsigned ths_eot; | |
2969 | u32 r; | |
2970 | ||
2971 | r = dsi_read_reg(DSI_DSIPHY_CFG0); | |
2972 | ths_prepare = FLD_GET(r, 31, 24); | |
2973 | ths_prepare_ths_zero = FLD_GET(r, 23, 16); | |
2974 | ths_zero = ths_prepare_ths_zero - ths_prepare; | |
2975 | ths_trail = FLD_GET(r, 15, 8); | |
2976 | ths_exit = FLD_GET(r, 7, 0); | |
2977 | ||
2978 | r = dsi_read_reg(DSI_DSIPHY_CFG1); | |
2979 | tlpx = FLD_GET(r, 22, 16) * 2; | |
2980 | tclk_trail = FLD_GET(r, 15, 8); | |
2981 | tclk_zero = FLD_GET(r, 7, 0); | |
2982 | ||
2983 | r = dsi_read_reg(DSI_DSIPHY_CFG2); | |
2984 | tclk_prepare = FLD_GET(r, 7, 0); | |
2985 | ||
2986 | /* min 8*UI */ | |
2987 | tclk_pre = 20; | |
2988 | /* min 60ns + 52*UI */ | |
2989 | tclk_post = ns2ddr(60) + 26; | |
2990 | ||
2991 | /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */ | |
2992 | if (dssdev->phy.dsi.data1_lane != 0 && | |
2993 | dssdev->phy.dsi.data2_lane != 0) | |
2994 | ths_eot = 2; | |
2995 | else | |
2996 | ths_eot = 4; | |
2997 | ||
2998 | ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, | |
2999 | 4); | |
3000 | ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; | |
3001 | ||
3002 | BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); | |
3003 | BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); | |
3004 | ||
3005 | r = dsi_read_reg(DSI_CLK_TIMING); | |
3006 | r = FLD_MOD(r, ddr_clk_pre, 15, 8); | |
3007 | r = FLD_MOD(r, ddr_clk_post, 7, 0); | |
3008 | dsi_write_reg(DSI_CLK_TIMING, r); | |
3009 | ||
3010 | DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", | |
3011 | ddr_clk_pre, | |
3012 | ddr_clk_post); | |
3013 | ||
3014 | enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + | |
3015 | DIV_ROUND_UP(ths_prepare, 4) + | |
3016 | DIV_ROUND_UP(ths_zero + 3, 4); | |
3017 | ||
3018 | exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; | |
3019 | ||
3020 | r = FLD_VAL(enter_hs_mode_lat, 31, 16) | | |
3021 | FLD_VAL(exit_hs_mode_lat, 15, 0); | |
3022 | dsi_write_reg(DSI_VM_TIMING7, r); | |
3023 | ||
3024 | DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", | |
3025 | enter_hs_mode_lat, exit_hs_mode_lat); | |
3026 | } | |
3027 | ||
3028 | ||
3029 | #define DSI_DECL_VARS \ | |
3030 | int __dsi_cb = 0; u32 __dsi_cv = 0; | |
3031 | ||
3032 | #define DSI_FLUSH(ch) \ | |
3033 | if (__dsi_cb > 0) { \ | |
3034 | /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \ | |
3035 | dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \ | |
3036 | __dsi_cb = __dsi_cv = 0; \ | |
3037 | } | |
3038 | ||
3039 | #define DSI_PUSH(ch, data) \ | |
3040 | do { \ | |
3041 | __dsi_cv |= (data) << (__dsi_cb * 8); \ | |
3042 | /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \ | |
3043 | if (++__dsi_cb > 3) \ | |
3044 | DSI_FLUSH(ch); \ | |
3045 | } while (0) | |
3046 | ||
3047 | static int dsi_update_screen_l4(struct omap_dss_device *dssdev, | |
3048 | int x, int y, int w, int h) | |
3049 | { | |
3050 | /* Note: supports only 24bit colors in 32bit container */ | |
3051 | int first = 1; | |
3052 | int fifo_stalls = 0; | |
3053 | int max_dsi_packet_size; | |
3054 | int max_data_per_packet; | |
3055 | int max_pixels_per_packet; | |
3056 | int pixels_left; | |
3057 | int bytespp = dssdev->ctrl.pixel_size / 8; | |
3058 | int scr_width; | |
3059 | u32 __iomem *data; | |
3060 | int start_offset; | |
3061 | int horiz_inc; | |
3062 | int current_x; | |
3063 | struct omap_overlay *ovl; | |
3064 | ||
3065 | debug_irq = 0; | |
3066 | ||
3067 | DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n", | |
3068 | x, y, w, h); | |
3069 | ||
3070 | ovl = dssdev->manager->overlays[0]; | |
3071 | ||
3072 | if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U) | |
3073 | return -EINVAL; | |
3074 | ||
3075 | if (dssdev->ctrl.pixel_size != 24) | |
3076 | return -EINVAL; | |
3077 | ||
3078 | scr_width = ovl->info.screen_width; | |
3079 | data = ovl->info.vaddr; | |
3080 | ||
3081 | start_offset = scr_width * y + x; | |
3082 | horiz_inc = scr_width - w; | |
3083 | current_x = x; | |
3084 | ||
3085 | /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes | |
3086 | * in fifo */ | |
3087 | ||
3088 | /* When using CPU, max long packet size is TX buffer size */ | |
3089 | max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4; | |
3090 | ||
3091 | /* we seem to get better perf if we divide the tx fifo to half, | |
3092 | and while the other half is being sent, we fill the other half | |
3093 | max_dsi_packet_size /= 2; */ | |
3094 | ||
3095 | max_data_per_packet = max_dsi_packet_size - 4 - 1; | |
3096 | ||
3097 | max_pixels_per_packet = max_data_per_packet / bytespp; | |
3098 | ||
3099 | DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet); | |
3100 | ||
3101 | pixels_left = w * h; | |
3102 | ||
3103 | DSSDBG("total pixels %d\n", pixels_left); | |
3104 | ||
3105 | data += start_offset; | |
3106 | ||
3107 | while (pixels_left > 0) { | |
3108 | /* 0x2c = write_memory_start */ | |
3109 | /* 0x3c = write_memory_continue */ | |
3110 | u8 dcs_cmd = first ? 0x2c : 0x3c; | |
3111 | int pixels; | |
3112 | DSI_DECL_VARS; | |
3113 | first = 0; | |
3114 | ||
3115 | #if 1 | |
3116 | /* using fifo not empty */ | |
3117 | /* TX_FIFO_NOT_EMPTY */ | |
3118 | while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) { | |
3de7a1dc TV |
3119 | fifo_stalls++; |
3120 | if (fifo_stalls > 0xfffff) { | |
3121 | DSSERR("fifo stalls overflow, pixels left %d\n", | |
3122 | pixels_left); | |
3123 | dsi_if_enable(0); | |
3124 | return -EIO; | |
3125 | } | |
24be78b3 | 3126 | udelay(1); |
3de7a1dc TV |
3127 | } |
3128 | #elif 1 | |
3129 | /* using fifo emptiness */ | |
3130 | while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 < | |
3131 | max_dsi_packet_size) { | |
3132 | fifo_stalls++; | |
3133 | if (fifo_stalls > 0xfffff) { | |
3134 | DSSERR("fifo stalls overflow, pixels left %d\n", | |
3135 | pixels_left); | |
3136 | dsi_if_enable(0); | |
3137 | return -EIO; | |
3138 | } | |
3139 | } | |
3140 | #else | |
3141 | while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) { | |
3142 | fifo_stalls++; | |
3143 | if (fifo_stalls > 0xfffff) { | |
3144 | DSSERR("fifo stalls overflow, pixels left %d\n", | |
3145 | pixels_left); | |
3146 | dsi_if_enable(0); | |
3147 | return -EIO; | |
3148 | } | |
3149 | } | |
3150 | #endif | |
3151 | pixels = min(max_pixels_per_packet, pixels_left); | |
3152 | ||
3153 | pixels_left -= pixels; | |
3154 | ||
3155 | dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE, | |
3156 | 1 + pixels * bytespp, 0); | |
3157 | ||
3158 | DSI_PUSH(0, dcs_cmd); | |
3159 | ||
3160 | while (pixels-- > 0) { | |
3161 | u32 pix = __raw_readl(data++); | |
3162 | ||
3163 | DSI_PUSH(0, (pix >> 16) & 0xff); | |
3164 | DSI_PUSH(0, (pix >> 8) & 0xff); | |
3165 | DSI_PUSH(0, (pix >> 0) & 0xff); | |
3166 | ||
3167 | current_x++; | |
3168 | if (current_x == x+w) { | |
3169 | current_x = x; | |
3170 | data += horiz_inc; | |
3171 | } | |
3172 | } | |
3173 | ||
3174 | DSI_FLUSH(0); | |
3175 | } | |
3176 | ||
3177 | return 0; | |
3178 | } | |
3179 | ||
3180 | static void dsi_update_screen_dispc(struct omap_dss_device *dssdev, | |
3181 | u16 x, u16 y, u16 w, u16 h) | |
3182 | { | |
3183 | unsigned bytespp; | |
3184 | unsigned bytespl; | |
3185 | unsigned bytespf; | |
3186 | unsigned total_len; | |
3187 | unsigned packet_payload; | |
3188 | unsigned packet_len; | |
3189 | u32 l; | |
0f16aa0a | 3190 | int r; |
18946f62 | 3191 | const unsigned channel = dsi.update_channel; |
3de7a1dc TV |
3192 | /* line buffer is 1024 x 24bits */ |
3193 | /* XXX: for some reason using full buffer size causes considerable TX | |
3194 | * slowdown with update sizes that fill the whole buffer */ | |
3195 | const unsigned line_buf_size = 1023 * 3; | |
3196 | ||
446f7bff TV |
3197 | DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n", |
3198 | x, y, w, h); | |
3de7a1dc | 3199 | |
18946f62 TV |
3200 | dsi_vc_config_vp(channel); |
3201 | ||
3de7a1dc TV |
3202 | bytespp = dssdev->ctrl.pixel_size / 8; |
3203 | bytespl = w * bytespp; | |
3204 | bytespf = bytespl * h; | |
3205 | ||
3206 | /* NOTE: packet_payload has to be equal to N * bytespl, where N is | |
3207 | * number of lines in a packet. See errata about VP_CLK_RATIO */ | |
3208 | ||
3209 | if (bytespf < line_buf_size) | |
3210 | packet_payload = bytespf; | |
3211 | else | |
3212 | packet_payload = (line_buf_size) / bytespl * bytespl; | |
3213 | ||
3214 | packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ | |
3215 | total_len = (bytespf / packet_payload) * packet_len; | |
3216 | ||
3217 | if (bytespf % packet_payload) | |
3218 | total_len += (bytespf % packet_payload) + 1; | |
3219 | ||
3de7a1dc TV |
3220 | l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ |
3221 | dsi_write_reg(DSI_VC_TE(channel), l); | |
3222 | ||
3223 | dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0); | |
3224 | ||
942a91a6 | 3225 | if (dsi.te_enabled) |
3de7a1dc TV |
3226 | l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ |
3227 | else | |
3228 | l = FLD_MOD(l, 1, 31, 31); /* TE_START */ | |
3229 | dsi_write_reg(DSI_VC_TE(channel), l); | |
3230 | ||
3231 | /* We put SIDLEMODE to no-idle for the duration of the transfer, | |
3232 | * because DSS interrupts are not capable of waking up the CPU and the | |
3233 | * framedone interrupt could be delayed for quite a long time. I think | |
3234 | * the same goes for any DSS interrupts, but for some reason I have not | |
3235 | * seen the problem anywhere else than here. | |
3236 | */ | |
3237 | dispc_disable_sidle(); | |
3238 | ||
18946f62 TV |
3239 | dsi_perf_mark_start(); |
3240 | ||
0f16aa0a | 3241 | r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work, |
18946f62 | 3242 | msecs_to_jiffies(250)); |
0f16aa0a | 3243 | BUG_ON(r == 0); |
18946f62 | 3244 | |
3de7a1dc TV |
3245 | dss_start_update(dssdev); |
3246 | ||
942a91a6 | 3247 | if (dsi.te_enabled) { |
3de7a1dc TV |
3248 | /* disable LP_RX_TO, so that we can receive TE. Time to wait |
3249 | * for TE is longer than the timer allows */ | |
3250 | REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ | |
3251 | ||
3252 | dsi_vc_send_bta(channel); | |
3253 | ||
3254 | #ifdef DSI_CATCH_MISSING_TE | |
3255 | mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250)); | |
3256 | #endif | |
3257 | } | |
3258 | } | |
3259 | ||
3260 | #ifdef DSI_CATCH_MISSING_TE | |
3261 | static void dsi_te_timeout(unsigned long arg) | |
3262 | { | |
3263 | DSSERR("TE not received for 250ms!\n"); | |
3264 | } | |
3265 | #endif | |
3266 | ||
ab83b14c | 3267 | static void dsi_handle_framedone(int error) |
3de7a1dc | 3268 | { |
3de7a1dc TV |
3269 | /* SIDLEMODE back to smart-idle */ |
3270 | dispc_enable_sidle(); | |
3271 | ||
942a91a6 | 3272 | if (dsi.te_enabled) { |
18946f62 TV |
3273 | /* enable LP_RX_TO again after the TE */ |
3274 | REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ | |
3de7a1dc TV |
3275 | } |
3276 | ||
ab83b14c TV |
3277 | dsi.framedone_callback(error, dsi.framedone_data); |
3278 | ||
3279 | if (!error) | |
3280 | dsi_perf_show("DISPC"); | |
18946f62 | 3281 | } |
3de7a1dc | 3282 | |
ab83b14c | 3283 | static void dsi_framedone_timeout_work_callback(struct work_struct *work) |
18946f62 | 3284 | { |
ab83b14c TV |
3285 | /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after |
3286 | * 250ms which would conflict with this timeout work. What should be | |
3287 | * done is first cancel the transfer on the HW, and then cancel the | |
3288 | * possibly scheduled framedone work. However, cancelling the transfer | |
3289 | * on the HW is buggy, and would probably require resetting the whole | |
3290 | * DSI */ | |
18946f62 | 3291 | |
ab83b14c | 3292 | DSSERR("Framedone not received for 250ms!\n"); |
3de7a1dc | 3293 | |
ab83b14c | 3294 | dsi_handle_framedone(-ETIMEDOUT); |
3de7a1dc TV |
3295 | } |
3296 | ||
ab83b14c | 3297 | static void dsi_framedone_irq_callback(void *data, u32 mask) |
3de7a1dc | 3298 | { |
ab83b14c TV |
3299 | /* Note: We get FRAMEDONE when DISPC has finished sending pixels and |
3300 | * turns itself off. However, DSI still has the pixels in its buffers, | |
3301 | * and is sending the data. | |
3302 | */ | |
3de7a1dc | 3303 | |
cf398fb3 | 3304 | __cancel_delayed_work(&dsi.framedone_timeout_work); |
3de7a1dc | 3305 | |
cf398fb3 | 3306 | dsi_handle_framedone(0); |
3de7a1dc | 3307 | |
cf398fb3 AT |
3308 | #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC |
3309 | dispc_fake_vsync_irq(); | |
3310 | #endif | |
18946f62 | 3311 | } |
3de7a1dc | 3312 | |
18946f62 | 3313 | int omap_dsi_prepare_update(struct omap_dss_device *dssdev, |
26a8c250 TV |
3314 | u16 *x, u16 *y, u16 *w, u16 *h, |
3315 | bool enlarge_update_area) | |
18946f62 TV |
3316 | { |
3317 | u16 dw, dh; | |
3de7a1dc | 3318 | |
18946f62 | 3319 | dssdev->driver->get_resolution(dssdev, &dw, &dh); |
3de7a1dc | 3320 | |
18946f62 TV |
3321 | if (*x > dw || *y > dh) |
3322 | return -EINVAL; | |
3de7a1dc | 3323 | |
18946f62 TV |
3324 | if (*x + *w > dw) |
3325 | return -EINVAL; | |
3de7a1dc | 3326 | |
18946f62 TV |
3327 | if (*y + *h > dh) |
3328 | return -EINVAL; | |
3de7a1dc | 3329 | |
18946f62 TV |
3330 | if (*w == 1) |
3331 | return -EINVAL; | |
3de7a1dc | 3332 | |
18946f62 TV |
3333 | if (*w == 0 || *h == 0) |
3334 | return -EINVAL; | |
3de7a1dc | 3335 | |
18946f62 | 3336 | dsi_perf_mark_setup(); |
3de7a1dc | 3337 | |
18946f62 | 3338 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
26a8c250 TV |
3339 | dss_setup_partial_planes(dssdev, x, y, w, h, |
3340 | enlarge_update_area); | |
64ba4f74 | 3341 | dispc_set_lcd_size(dssdev->manager->id, *w, *h); |
18946f62 | 3342 | } |
3de7a1dc | 3343 | |
18946f62 TV |
3344 | return 0; |
3345 | } | |
3346 | EXPORT_SYMBOL(omap_dsi_prepare_update); | |
3de7a1dc | 3347 | |
18946f62 TV |
3348 | int omap_dsi_update(struct omap_dss_device *dssdev, |
3349 | int channel, | |
3350 | u16 x, u16 y, u16 w, u16 h, | |
3351 | void (*callback)(int, void *), void *data) | |
3352 | { | |
3353 | dsi.update_channel = channel; | |
3de7a1dc | 3354 | |
a602771c TV |
3355 | /* OMAP DSS cannot send updates of odd widths. |
3356 | * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON | |
3357 | * here to make sure we catch erroneous updates. Otherwise we'll only | |
3358 | * see rather obscure HW error happening, as DSS halts. */ | |
3359 | BUG_ON(x % 2 == 1); | |
3360 | ||
18946f62 TV |
3361 | if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) { |
3362 | dsi.framedone_callback = callback; | |
3363 | dsi.framedone_data = data; | |
3de7a1dc | 3364 | |
18946f62 TV |
3365 | dsi.update_region.x = x; |
3366 | dsi.update_region.y = y; | |
3367 | dsi.update_region.w = w; | |
3368 | dsi.update_region.h = h; | |
3369 | dsi.update_region.device = dssdev; | |
3de7a1dc | 3370 | |
18946f62 TV |
3371 | dsi_update_screen_dispc(dssdev, x, y, w, h); |
3372 | } else { | |
e9c31afc AT |
3373 | int r; |
3374 | ||
3375 | r = dsi_update_screen_l4(dssdev, x, y, w, h); | |
3376 | if (r) | |
3377 | return r; | |
3378 | ||
18946f62 TV |
3379 | dsi_perf_show("L4"); |
3380 | callback(0, data); | |
3de7a1dc TV |
3381 | } |
3382 | ||
3de7a1dc TV |
3383 | return 0; |
3384 | } | |
18946f62 | 3385 | EXPORT_SYMBOL(omap_dsi_update); |
3de7a1dc TV |
3386 | |
3387 | /* Display funcs */ | |
3388 | ||
3389 | static int dsi_display_init_dispc(struct omap_dss_device *dssdev) | |
3390 | { | |
3391 | int r; | |
3392 | ||
3393 | r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL, | |
3394 | DISPC_IRQ_FRAMEDONE); | |
3395 | if (r) { | |
3396 | DSSERR("can't get FRAMEDONE irq\n"); | |
3397 | return r; | |
3398 | } | |
3399 | ||
64ba4f74 SS |
3400 | dispc_set_lcd_display_type(dssdev->manager->id, |
3401 | OMAP_DSS_LCD_DISPLAY_TFT); | |
3de7a1dc | 3402 | |
64ba4f74 SS |
3403 | dispc_set_parallel_interface_mode(dssdev->manager->id, |
3404 | OMAP_DSS_PARALLELMODE_DSI); | |
3405 | dispc_enable_fifohandcheck(dssdev->manager->id, 1); | |
3de7a1dc | 3406 | |
64ba4f74 | 3407 | dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size); |
3de7a1dc TV |
3408 | |
3409 | { | |
3410 | struct omap_video_timings timings = { | |
3411 | .hsw = 1, | |
3412 | .hfp = 1, | |
3413 | .hbp = 1, | |
3414 | .vsw = 1, | |
3415 | .vfp = 0, | |
3416 | .vbp = 0, | |
3417 | }; | |
3418 | ||
64ba4f74 | 3419 | dispc_set_lcd_timings(dssdev->manager->id, &timings); |
3de7a1dc TV |
3420 | } |
3421 | ||
3422 | return 0; | |
3423 | } | |
3424 | ||
3425 | static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev) | |
3426 | { | |
3427 | omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL, | |
3428 | DISPC_IRQ_FRAMEDONE); | |
3429 | } | |
3430 | ||
3431 | static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev) | |
3432 | { | |
3433 | struct dsi_clock_info cinfo; | |
3434 | int r; | |
3435 | ||
1bb47835 AT |
3436 | /* we always use DSS_CLK_SYSCK as input clock */ |
3437 | cinfo.use_sys_clk = true; | |
c6940a3d TV |
3438 | cinfo.regn = dssdev->clocks.dsi.regn; |
3439 | cinfo.regm = dssdev->clocks.dsi.regm; | |
3440 | cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc; | |
3441 | cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi; | |
ff1b2cde | 3442 | r = dsi_calc_clock_rates(dssdev, &cinfo); |
ebf0a3fe VS |
3443 | if (r) { |
3444 | DSSERR("Failed to calc dsi clocks\n"); | |
3de7a1dc | 3445 | return r; |
ebf0a3fe | 3446 | } |
3de7a1dc TV |
3447 | |
3448 | r = dsi_pll_set_clock_div(&cinfo); | |
3449 | if (r) { | |
3450 | DSSERR("Failed to set dsi clocks\n"); | |
3451 | return r; | |
3452 | } | |
3453 | ||
3454 | return 0; | |
3455 | } | |
3456 | ||
3457 | static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev) | |
3458 | { | |
3459 | struct dispc_clock_info dispc_cinfo; | |
3460 | int r; | |
3461 | unsigned long long fck; | |
3462 | ||
1bb47835 | 3463 | fck = dsi_get_pll_hsdiv_dispc_rate(); |
3de7a1dc | 3464 | |
e8881662 AT |
3465 | dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div; |
3466 | dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div; | |
3de7a1dc TV |
3467 | |
3468 | r = dispc_calc_clock_rates(fck, &dispc_cinfo); | |
3469 | if (r) { | |
3470 | DSSERR("Failed to calc dispc clocks\n"); | |
3471 | return r; | |
3472 | } | |
3473 | ||
ff1b2cde | 3474 | r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo); |
3de7a1dc TV |
3475 | if (r) { |
3476 | DSSERR("Failed to set dispc clocks\n"); | |
3477 | return r; | |
3478 | } | |
3479 | ||
3480 | return 0; | |
3481 | } | |
3482 | ||
3483 | static int dsi_display_init_dsi(struct omap_dss_device *dssdev) | |
3484 | { | |
3485 | int r; | |
3486 | ||
9613c02b AT |
3487 | /* The SCPClk is required for both PLL and CIO registers on OMAP4 */ |
3488 | /* CIO_CLK_ICG, enable L3 clk to CIO */ | |
3489 | REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14); | |
3490 | ||
3de7a1dc TV |
3491 | _dsi_print_reset_status(); |
3492 | ||
3493 | r = dsi_pll_init(dssdev, true, true); | |
3494 | if (r) | |
3495 | goto err0; | |
3496 | ||
3497 | r = dsi_configure_dsi_clocks(dssdev); | |
3498 | if (r) | |
3499 | goto err1; | |
3500 | ||
e8881662 AT |
3501 | dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src); |
3502 | dss_select_dsi_clk_source(dssdev->clocks.dsi.dsi_fclk_src); | |
9613c02b | 3503 | dss_select_lcd_clk_source(dssdev->manager->id, |
e8881662 | 3504 | dssdev->clocks.dispc.channel.lcd_clk_src); |
3de7a1dc TV |
3505 | |
3506 | DSSDBG("PLL OK\n"); | |
3507 | ||
3508 | r = dsi_configure_dispc_clocks(dssdev); | |
3509 | if (r) | |
3510 | goto err2; | |
3511 | ||
3512 | r = dsi_complexio_init(dssdev); | |
3513 | if (r) | |
3514 | goto err2; | |
3515 | ||
3516 | _dsi_print_reset_status(); | |
3517 | ||
3518 | dsi_proto_timings(dssdev); | |
3519 | dsi_set_lp_clk_divisor(dssdev); | |
3520 | ||
3521 | if (1) | |
3522 | _dsi_print_reset_status(); | |
3523 | ||
3524 | r = dsi_proto_config(dssdev); | |
3525 | if (r) | |
3526 | goto err3; | |
3527 | ||
3528 | /* enable interface */ | |
3529 | dsi_vc_enable(0, 1); | |
dd8079d6 TV |
3530 | dsi_vc_enable(1, 1); |
3531 | dsi_vc_enable(2, 1); | |
3532 | dsi_vc_enable(3, 1); | |
3de7a1dc TV |
3533 | dsi_if_enable(1); |
3534 | dsi_force_tx_stop_mode_io(); | |
3535 | ||
3de7a1dc | 3536 | return 0; |
3de7a1dc TV |
3537 | err3: |
3538 | dsi_complexio_uninit(); | |
3539 | err2: | |
89a35e51 AT |
3540 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
3541 | dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK); | |
3de7a1dc TV |
3542 | err1: |
3543 | dsi_pll_uninit(); | |
3544 | err0: | |
3545 | return r; | |
3546 | } | |
3547 | ||
3548 | static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev) | |
3549 | { | |
d7370104 VS |
3550 | /* disable interface */ |
3551 | dsi_if_enable(0); | |
3552 | dsi_vc_enable(0, 0); | |
3553 | dsi_vc_enable(1, 0); | |
3554 | dsi_vc_enable(2, 0); | |
3555 | dsi_vc_enable(3, 0); | |
3556 | ||
89a35e51 AT |
3557 | dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK); |
3558 | dss_select_dsi_clk_source(OMAP_DSS_CLK_SRC_FCK); | |
3de7a1dc TV |
3559 | dsi_complexio_uninit(); |
3560 | dsi_pll_uninit(); | |
3561 | } | |
3562 | ||
3563 | static int dsi_core_init(void) | |
3564 | { | |
3565 | /* Autoidle */ | |
3566 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0); | |
3567 | ||
3568 | /* ENWAKEUP */ | |
3569 | REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2); | |
3570 | ||
3571 | /* SIDLEMODE smart-idle */ | |
3572 | REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3); | |
3573 | ||
3574 | _dsi_initialize_irq(); | |
3575 | ||
3576 | return 0; | |
3577 | } | |
3578 | ||
37ac60e4 | 3579 | int omapdss_dsi_display_enable(struct omap_dss_device *dssdev) |
3de7a1dc TV |
3580 | { |
3581 | int r = 0; | |
3582 | ||
3583 | DSSDBG("dsi_display_enable\n"); | |
3584 | ||
37ac60e4 TV |
3585 | WARN_ON(!dsi_bus_is_locked()); |
3586 | ||
3de7a1dc | 3587 | mutex_lock(&dsi.lock); |
3de7a1dc TV |
3588 | |
3589 | r = omap_dss_start_device(dssdev); | |
3590 | if (r) { | |
3591 | DSSERR("failed to start device\n"); | |
3592 | goto err0; | |
3593 | } | |
3594 | ||
3de7a1dc TV |
3595 | enable_clocks(1); |
3596 | dsi_enable_pll_clock(1); | |
3597 | ||
3598 | r = _dsi_reset(); | |
3599 | if (r) | |
37ac60e4 | 3600 | goto err1; |
3de7a1dc TV |
3601 | |
3602 | dsi_core_init(); | |
3603 | ||
3604 | r = dsi_display_init_dispc(dssdev); | |
3605 | if (r) | |
37ac60e4 | 3606 | goto err1; |
3de7a1dc TV |
3607 | |
3608 | r = dsi_display_init_dsi(dssdev); | |
3609 | if (r) | |
37ac60e4 | 3610 | goto err2; |
3de7a1dc | 3611 | |
3de7a1dc TV |
3612 | mutex_unlock(&dsi.lock); |
3613 | ||
3614 | return 0; | |
3615 | ||
3de7a1dc | 3616 | err2: |
37ac60e4 TV |
3617 | dsi_display_uninit_dispc(dssdev); |
3618 | err1: | |
3de7a1dc TV |
3619 | enable_clocks(0); |
3620 | dsi_enable_pll_clock(0); | |
3de7a1dc TV |
3621 | omap_dss_stop_device(dssdev); |
3622 | err0: | |
3de7a1dc TV |
3623 | mutex_unlock(&dsi.lock); |
3624 | DSSDBG("dsi_display_enable FAILED\n"); | |
3625 | return r; | |
3626 | } | |
37ac60e4 | 3627 | EXPORT_SYMBOL(omapdss_dsi_display_enable); |
3de7a1dc | 3628 | |
37ac60e4 | 3629 | void omapdss_dsi_display_disable(struct omap_dss_device *dssdev) |
3de7a1dc TV |
3630 | { |
3631 | DSSDBG("dsi_display_disable\n"); | |
3632 | ||
37ac60e4 | 3633 | WARN_ON(!dsi_bus_is_locked()); |
3de7a1dc TV |
3634 | |
3635 | mutex_lock(&dsi.lock); | |
3de7a1dc TV |
3636 | |
3637 | dsi_display_uninit_dispc(dssdev); | |
3638 | ||
3639 | dsi_display_uninit_dsi(dssdev); | |
3640 | ||
3641 | enable_clocks(0); | |
3642 | dsi_enable_pll_clock(0); | |
3de7a1dc | 3643 | |
37ac60e4 | 3644 | omap_dss_stop_device(dssdev); |
3de7a1dc | 3645 | |
3de7a1dc | 3646 | mutex_unlock(&dsi.lock); |
3de7a1dc | 3647 | } |
37ac60e4 | 3648 | EXPORT_SYMBOL(omapdss_dsi_display_disable); |
3de7a1dc | 3649 | |
225b650d | 3650 | int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable) |
3de7a1dc | 3651 | { |
3de7a1dc | 3652 | dsi.te_enabled = enable; |
225b650d | 3653 | return 0; |
3de7a1dc | 3654 | } |
225b650d | 3655 | EXPORT_SYMBOL(omapdss_dsi_enable_te); |
3de7a1dc | 3656 | |
3de7a1dc TV |
3657 | void dsi_get_overlay_fifo_thresholds(enum omap_plane plane, |
3658 | u32 fifo_size, enum omap_burst_size *burst_size, | |
3659 | u32 *fifo_low, u32 *fifo_high) | |
3660 | { | |
3661 | unsigned burst_size_bytes; | |
3662 | ||
3663 | *burst_size = OMAP_DSS_BURST_16x32; | |
3664 | burst_size_bytes = 16 * 32 / 8; | |
3665 | ||
3666 | *fifo_high = fifo_size - burst_size_bytes; | |
36194b47 | 3667 | *fifo_low = fifo_size - burst_size_bytes * 2; |
3de7a1dc TV |
3668 | } |
3669 | ||
3670 | int dsi_init_display(struct omap_dss_device *dssdev) | |
3671 | { | |
3672 | DSSDBG("DSI init\n"); | |
3673 | ||
3de7a1dc TV |
3674 | /* XXX these should be figured out dynamically */ |
3675 | dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE | | |
3676 | OMAP_DSS_DISPLAY_CAP_TEAR_ELIM; | |
3677 | ||
5f42f2ce TV |
3678 | if (dsi.vdds_dsi_reg == NULL) { |
3679 | struct regulator *vdds_dsi; | |
3680 | ||
3681 | vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi"); | |
3682 | ||
3683 | if (IS_ERR(vdds_dsi)) { | |
3684 | DSSERR("can't get VDDS_DSI regulator\n"); | |
3685 | return PTR_ERR(vdds_dsi); | |
3686 | } | |
3687 | ||
3688 | dsi.vdds_dsi_reg = vdds_dsi; | |
3689 | } | |
3690 | ||
3de7a1dc TV |
3691 | return 0; |
3692 | } | |
3693 | ||
5ee3c144 AT |
3694 | int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel) |
3695 | { | |
3696 | int i; | |
3697 | ||
3698 | for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { | |
3699 | if (!dsi.vc[i].dssdev) { | |
3700 | dsi.vc[i].dssdev = dssdev; | |
3701 | *channel = i; | |
3702 | return 0; | |
3703 | } | |
3704 | } | |
3705 | ||
3706 | DSSERR("cannot get VC for display %s", dssdev->name); | |
3707 | return -ENOSPC; | |
3708 | } | |
3709 | EXPORT_SYMBOL(omap_dsi_request_vc); | |
3710 | ||
3711 | int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) | |
3712 | { | |
3713 | if (vc_id < 0 || vc_id > 3) { | |
3714 | DSSERR("VC ID out of range\n"); | |
3715 | return -EINVAL; | |
3716 | } | |
3717 | ||
3718 | if (channel < 0 || channel > 3) { | |
3719 | DSSERR("Virtual Channel out of range\n"); | |
3720 | return -EINVAL; | |
3721 | } | |
3722 | ||
3723 | if (dsi.vc[channel].dssdev != dssdev) { | |
3724 | DSSERR("Virtual Channel not allocated to display %s\n", | |
3725 | dssdev->name); | |
3726 | return -EINVAL; | |
3727 | } | |
3728 | ||
3729 | dsi.vc[channel].vc_id = vc_id; | |
3730 | ||
3731 | return 0; | |
3732 | } | |
3733 | EXPORT_SYMBOL(omap_dsi_set_vc_id); | |
3734 | ||
3735 | void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel) | |
3736 | { | |
3737 | if ((channel >= 0 && channel <= 3) && | |
3738 | dsi.vc[channel].dssdev == dssdev) { | |
3739 | dsi.vc[channel].dssdev = NULL; | |
3740 | dsi.vc[channel].vc_id = 0; | |
3741 | } | |
3742 | } | |
3743 | EXPORT_SYMBOL(omap_dsi_release_vc); | |
3744 | ||
1bb47835 | 3745 | void dsi_wait_pll_hsdiv_dispc_active(void) |
e406f907 TV |
3746 | { |
3747 | if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) | |
067a57e4 | 3748 | DSSERR("%s (%s) not active\n", |
89a35e51 AT |
3749 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
3750 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); | |
e406f907 TV |
3751 | } |
3752 | ||
1bb47835 | 3753 | void dsi_wait_pll_hsdiv_dsi_active(void) |
e406f907 TV |
3754 | { |
3755 | if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) | |
067a57e4 | 3756 | DSSERR("%s (%s) not active\n", |
89a35e51 AT |
3757 | dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), |
3758 | dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); | |
e406f907 TV |
3759 | } |
3760 | ||
49641116 TA |
3761 | static void dsi_calc_clock_param_ranges(void) |
3762 | { | |
3763 | dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN); | |
3764 | dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM); | |
3765 | dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC); | |
3766 | dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI); | |
3767 | dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT); | |
3768 | dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT); | |
3769 | dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV); | |
3770 | } | |
3771 | ||
c8aac01b | 3772 | static int dsi_init(struct platform_device *pdev) |
3de7a1dc TV |
3773 | { |
3774 | u32 rev; | |
5ee3c144 | 3775 | int r, i; |
ea9da36a | 3776 | struct resource *dsi_mem; |
3de7a1dc | 3777 | |
4ae2dddd | 3778 | spin_lock_init(&dsi.irq_lock); |
3de7a1dc TV |
3779 | spin_lock_init(&dsi.errors_lock); |
3780 | dsi.errors = 0; | |
3781 | ||
dfc0fd8d TV |
3782 | #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS |
3783 | spin_lock_init(&dsi.irq_stats_lock); | |
3784 | dsi.irq_stats.last_reset = jiffies; | |
3785 | #endif | |
3786 | ||
3de7a1dc | 3787 | mutex_init(&dsi.lock); |
b9eb5d7d | 3788 | sema_init(&dsi.bus_lock, 1); |
3de7a1dc | 3789 | |
0f16aa0a TV |
3790 | dsi.workqueue = create_singlethread_workqueue("dsi"); |
3791 | if (dsi.workqueue == NULL) | |
3792 | return -ENOMEM; | |
3793 | ||
18946f62 TV |
3794 | INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work, |
3795 | dsi_framedone_timeout_work_callback); | |
3796 | ||
3de7a1dc TV |
3797 | #ifdef DSI_CATCH_MISSING_TE |
3798 | init_timer(&dsi.te_timer); | |
3799 | dsi.te_timer.function = dsi_te_timeout; | |
3800 | dsi.te_timer.data = 0; | |
3801 | #endif | |
ea9da36a SG |
3802 | dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0); |
3803 | if (!dsi_mem) { | |
3804 | DSSERR("can't get IORESOURCE_MEM DSI\n"); | |
3805 | r = -EINVAL; | |
3806 | goto err1; | |
3807 | } | |
3808 | dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem)); | |
3de7a1dc TV |
3809 | if (!dsi.base) { |
3810 | DSSERR("can't ioremap DSI\n"); | |
3811 | r = -ENOMEM; | |
3812 | goto err1; | |
3813 | } | |
affe360d | 3814 | dsi.irq = platform_get_irq(dsi.pdev, 0); |
3815 | if (dsi.irq < 0) { | |
3816 | DSSERR("platform_get_irq failed\n"); | |
3817 | r = -ENODEV; | |
3818 | goto err2; | |
3819 | } | |
3820 | ||
3821 | r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED, | |
3822 | "OMAP DSI1", dsi.pdev); | |
3823 | if (r < 0) { | |
3824 | DSSERR("request_irq failed\n"); | |
3825 | goto err2; | |
3826 | } | |
3de7a1dc | 3827 | |
5ee3c144 AT |
3828 | /* DSI VCs initialization */ |
3829 | for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) { | |
3830 | dsi.vc[i].mode = DSI_VC_MODE_L4; | |
3831 | dsi.vc[i].dssdev = NULL; | |
3832 | dsi.vc[i].vc_id = 0; | |
3833 | } | |
3834 | ||
49641116 TA |
3835 | dsi_calc_clock_param_ranges(); |
3836 | ||
3de7a1dc TV |
3837 | enable_clocks(1); |
3838 | ||
3839 | rev = dsi_read_reg(DSI_REVISION); | |
a06b62f8 | 3840 | dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n", |
3de7a1dc TV |
3841 | FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); |
3842 | ||
3843 | enable_clocks(0); | |
3844 | ||
3de7a1dc | 3845 | return 0; |
affe360d | 3846 | err2: |
3847 | iounmap(dsi.base); | |
3de7a1dc | 3848 | err1: |
0f16aa0a | 3849 | destroy_workqueue(dsi.workqueue); |
3de7a1dc TV |
3850 | return r; |
3851 | } | |
3852 | ||
c8aac01b | 3853 | static void dsi_exit(void) |
3de7a1dc | 3854 | { |
c8aac01b SG |
3855 | if (dsi.vdds_dsi_reg != NULL) { |
3856 | regulator_put(dsi.vdds_dsi_reg); | |
3857 | dsi.vdds_dsi_reg = NULL; | |
3858 | } | |
3859 | ||
affe360d | 3860 | free_irq(dsi.irq, dsi.pdev); |
3de7a1dc TV |
3861 | iounmap(dsi.base); |
3862 | ||
0f16aa0a TV |
3863 | destroy_workqueue(dsi.workqueue); |
3864 | ||
3de7a1dc TV |
3865 | DSSDBG("omap_dsi_exit\n"); |
3866 | } | |
3867 | ||
c8aac01b SG |
3868 | /* DSI1 HW IP initialisation */ |
3869 | static int omap_dsi1hw_probe(struct platform_device *pdev) | |
3870 | { | |
3871 | int r; | |
3872 | dsi.pdev = pdev; | |
3873 | r = dsi_init(pdev); | |
3874 | if (r) { | |
3875 | DSSERR("Failed to initialize DSI\n"); | |
3876 | goto err_dsi; | |
3877 | } | |
3878 | err_dsi: | |
3879 | return r; | |
3880 | } | |
3881 | ||
3882 | static int omap_dsi1hw_remove(struct platform_device *pdev) | |
3883 | { | |
3884 | dsi_exit(); | |
3885 | return 0; | |
3886 | } | |
3887 | ||
3888 | static struct platform_driver omap_dsi1hw_driver = { | |
3889 | .probe = omap_dsi1hw_probe, | |
3890 | .remove = omap_dsi1hw_remove, | |
3891 | .driver = { | |
3892 | .name = "omapdss_dsi1", | |
3893 | .owner = THIS_MODULE, | |
3894 | }, | |
3895 | }; | |
3896 | ||
3897 | int dsi_init_platform_driver(void) | |
3898 | { | |
3899 | return platform_driver_register(&omap_dsi1hw_driver); | |
3900 | } | |
3901 | ||
3902 | void dsi_uninit_platform_driver(void) | |
3903 | { | |
3904 | return platform_driver_unregister(&omap_dsi1hw_driver); | |
3905 | } |