[deliverable/linux.git] / drivers / video / omap2 / dss / ti_hdmi.h

/*
 * ti_hdmi.h
 *
 * HDMI driver definition for TI OMAP4, DM81xx, DM38xx  Processor.
 *
 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _TI_HDMI_H
#define _TI_HDMI_H

struct hdmi_ip_data;

enum hdmi_pll_pwr {
	HDMI_PLLPWRCMD_ALLOFF = 0,
	HDMI_PLLPWRCMD_PLLONLY = 1,
	HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
};

enum hdmi_core_hdmi_dvi {
	HDMI_DVI = 0,
	HDMI_HDMI = 1
};

enum hdmi_clk_refsel {
	HDMI_REFSEL_PCLK = 0,
	HDMI_REFSEL_REF1 = 1,
	HDMI_REFSEL_REF2 = 2,
	HDMI_REFSEL_SYSCLK = 3
};

struct hdmi_video_timings {
	u16 x_res;
	u16 y_res;
	/* Unit: KHz */
	u32 pixel_clock;
	u16 hsw;
	u16 hfp;
	u16 hbp;
	u16 vsw;
	u16 vfp;
	u16 vbp;
};

/* HDMI timing structure */
struct hdmi_timings {
	struct hdmi_video_timings timings;
	int vsync_pol;
	int hsync_pol;
};

struct hdmi_cm {
	int	code;
	int	mode;
};

struct hdmi_config {
	struct hdmi_timings timings;
	u16	interlace;
	struct hdmi_cm cm;
};

/* HDMI PLL structure */
struct hdmi_pll_info {
	u16 regn;
	u16 regm;
	u32 regmf;
	u16 regm2;
	u16 regsd;
	u16 dcofreq;
	enum hdmi_clk_refsel refsel;
};

struct ti_hdmi_ip_ops {

	void (*video_configure)(struct hdmi_ip_data *ip_data);

	int (*phy_enable)(struct hdmi_ip_data *ip_data);

	void (*phy_disable)(struct hdmi_ip_data *ip_data);

	int (*read_edid)(struct hdmi_ip_data *ip_data, u8 *edid, int len);

	bool (*detect)(struct hdmi_ip_data *ip_data);

	int (*pll_enable)(struct hdmi_ip_data *ip_data);

	void (*pll_disable)(struct hdmi_ip_data *ip_data);

	void (*video_enable)(struct hdmi_ip_data *ip_data, bool start);

	void (*dump_wrapper)(struct hdmi_ip_data *ip_data, struct seq_file *s);

	void (*dump_core)(struct hdmi_ip_data *ip_data, struct seq_file *s);

	void (*dump_pll)(struct hdmi_ip_data *ip_data, struct seq_file *s);

	void (*dump_phy)(struct hdmi_ip_data *ip_data, struct seq_file *s);

};

struct hdmi_ip_data {
	void __iomem	*base_wp;	/* HDMI wrapper */
	unsigned long	core_sys_offset;
	unsigned long	core_av_offset;
	unsigned long	pll_offset;
	unsigned long	phy_offset;
	const struct ti_hdmi_ip_ops *ops;
	struct hdmi_config cfg;
	struct hdmi_pll_info pll_data;
};
int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data, u8 *edid, int len);
bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data);
void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);
void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s);

#endif
Commit	Line	Data
94c52987 M	1	/*
	2	* ti_hdmi.h
	3	*
	4	* HDMI driver definition for TI OMAP4, DM81xx, DM38xx Processor.
	5	*
	6	* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License version 2 as published by
	10	* the Free Software Foundation.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	15	* more details.
	16	*
	17	* You should have received a copy of the GNU General Public License along with
	18	* this program. If not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#ifndef _TI_HDMI_H
	22	#define _TI_HDMI_H
	23
60634a28 M	24	struct hdmi_ip_data;
60634a28 M	25
94c52987 M	26	enum hdmi_pll_pwr {
	27	HDMI_PLLPWRCMD_ALLOFF = 0,
	28	HDMI_PLLPWRCMD_PLLONLY = 1,
	29	HDMI_PLLPWRCMD_BOTHON_ALLCLKS = 2,
	30	HDMI_PLLPWRCMD_BOTHON_NOPHYCLK = 3
	31	};
	32
	33	enum hdmi_core_hdmi_dvi {
	34	HDMI_DVI = 0,
	35	HDMI_HDMI = 1
	36	};
	37
	38	enum hdmi_clk_refsel {
	39	HDMI_REFSEL_PCLK = 0,
	40	HDMI_REFSEL_REF1 = 1,
	41	HDMI_REFSEL_REF2 = 2,
	42	HDMI_REFSEL_SYSCLK = 3
	43	};
	44
	45	struct hdmi_video_timings {
	46	u16 x_res;
	47	u16 y_res;
	48	/* Unit: KHz */
	49	u32 pixel_clock;
	50	u16 hsw;
	51	u16 hfp;
	52	u16 hbp;
	53	u16 vsw;
	54	u16 vfp;
	55	u16 vbp;
	56	};
	57
	58	/* HDMI timing structure */
	59	struct hdmi_timings {
	60	struct hdmi_video_timings timings;
	61	int vsync_pol;
	62	int hsync_pol;
	63	};
	64
	65	struct hdmi_cm {
	66	int code;
	67	int mode;
	68	};
	69
	70	struct hdmi_config {
	71	struct hdmi_timings timings;
	72	u16 interlace;
	73	struct hdmi_cm cm;
	74	};
	75
	76	/* HDMI PLL structure */
	77	struct hdmi_pll_info {
	78	u16 regn;
	79	u16 regm;
	80	u32 regmf;
	81	u16 regm2;
	82	u16 regsd;
	83	u16 dcofreq;
	84	enum hdmi_clk_refsel refsel;
	85	};
	86
60634a28 M	87	struct ti_hdmi_ip_ops {
	88
	89	void (video_configure)(struct hdmi_ip_data ip_data);
	90
	91	int (phy_enable)(struct hdmi_ip_data ip_data);
	92
	93	void (phy_disable)(struct hdmi_ip_data ip_data);
	94
937fce13	95	int (read_edid)(struct hdmi_ip_data ip_data, u8 *edid, int len);
60634a28	96
759593ff TV	97	bool (detect)(struct hdmi_ip_data ip_data);
759593ff TV	98
60634a28 M	99	int (pll_enable)(struct hdmi_ip_data ip_data);
	100
	101	void (pll_disable)(struct hdmi_ip_data ip_data);
	102
	103	void (video_enable)(struct hdmi_ip_data ip_data, bool start);
162874d5 M	104
	105	void (dump_wrapper)(struct hdmi_ip_data ip_data, struct seq_file *s);
	106
	107	void (dump_core)(struct hdmi_ip_data ip_data, struct seq_file *s);
	108
	109	void (dump_pll)(struct hdmi_ip_data ip_data, struct seq_file *s);
	110
	111	void (dump_phy)(struct hdmi_ip_data ip_data, struct seq_file *s);
	112
60634a28 M	113	};
60634a28 M	114
94c52987 M	115	struct hdmi_ip_data {
	116	void __iomem base_wp; / HDMI wrapper */
	117	unsigned long core_sys_offset;
	118	unsigned long core_av_offset;
	119	unsigned long pll_offset;
	120	unsigned long phy_offset;
60634a28	121	const struct ti_hdmi_ip_ops *ops;
94c52987 M	122	struct hdmi_config cfg;
	123	struct hdmi_pll_info pll_data;
	124	};
176b578b M	125	int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data);
176b578b M	126	void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data);
937fce13	127	int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data ip_data, u8 edid, int len);
759593ff	128	bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data);
176b578b M	129	void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start);
	130	int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data);
	131	void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data);
	132	void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data);
162874d5 M	133	void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data ip_data, struct seq_file s);
	134	void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data ip_data, struct seq_file s);
	135	void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data ip_data, struct seq_file s);
	136	void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data ip_data, struct seq_file s);
	137
94c52987	138	#endif