Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/drivers/video/pxafb.c | |
3 | * | |
4 | * Copyright (C) 1999 Eric A. Thomas. | |
5 | * Copyright (C) 2004 Jean-Frederic Clere. | |
6 | * Copyright (C) 2004 Ian Campbell. | |
7 | * Copyright (C) 2004 Jeff Lackey. | |
8 | * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas | |
9 | * which in turn is | |
10 | * Based on acornfb.c Copyright (C) Russell King. | |
11 | * | |
12 | * This file is subject to the terms and conditions of the GNU General Public | |
13 | * License. See the file COPYING in the main directory of this archive for | |
14 | * more details. | |
15 | * | |
16 | * Intel PXA250/210 LCD Controller Frame Buffer Driver | |
17 | * | |
18 | * Please direct your questions and comments on this driver to the following | |
19 | * email address: | |
20 | * | |
21 | * linux-arm-kernel@lists.arm.linux.org.uk | |
22 | * | |
23 | */ | |
24 | ||
1da177e4 LT |
25 | #include <linux/module.h> |
26 | #include <linux/moduleparam.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/sched.h> | |
29 | #include <linux/errno.h> | |
30 | #include <linux/string.h> | |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/slab.h> | |
33 | #include <linux/fb.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/init.h> | |
36 | #include <linux/ioport.h> | |
37 | #include <linux/cpufreq.h> | |
d052d1be | 38 | #include <linux/platform_device.h> |
1da177e4 | 39 | #include <linux/dma-mapping.h> |
72e3524c RK |
40 | #include <linux/clk.h> |
41 | #include <linux/err.h> | |
2ba162b9 | 42 | #include <linux/completion.h> |
1da177e4 LT |
43 | |
44 | #include <asm/hardware.h> | |
45 | #include <asm/io.h> | |
46 | #include <asm/irq.h> | |
bf1b8ab6 | 47 | #include <asm/div64.h> |
1da177e4 | 48 | #include <asm/arch/pxa-regs.h> |
a683b14d | 49 | #include <asm/arch/pxa2xx-gpio.h> |
1da177e4 LT |
50 | #include <asm/arch/bitfield.h> |
51 | #include <asm/arch/pxafb.h> | |
52 | ||
53 | /* | |
54 | * Complain if VAR is out of range. | |
55 | */ | |
56 | #define DEBUG_VAR 1 | |
57 | ||
58 | #include "pxafb.h" | |
59 | ||
60 | /* Bits which should not be set in machine configuration structures */ | |
b0086efb | 61 | #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\ |
62 | LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\ | |
63 | LCCR0_SFM | LCCR0_LDM | LCCR0_ENB) | |
64 | ||
65 | #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP | LCCR3_VSP |\ | |
66 | LCCR3_PCD | LCCR3_BPP) | |
1da177e4 LT |
67 | |
68 | static void (*pxafb_backlight_power)(int); | |
d14b272b | 69 | static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *); |
1da177e4 | 70 | |
b0086efb | 71 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
72 | struct pxafb_info *); | |
1da177e4 LT |
73 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state); |
74 | ||
a7535ba7 EM |
75 | static inline unsigned long |
76 | lcd_readl(struct pxafb_info *fbi, unsigned int off) | |
77 | { | |
78 | return __raw_readl(fbi->mmio_base + off); | |
79 | } | |
80 | ||
81 | static inline void | |
82 | lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val) | |
83 | { | |
84 | __raw_writel(val, fbi->mmio_base + off); | |
85 | } | |
86 | ||
1da177e4 LT |
87 | static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state) |
88 | { | |
89 | unsigned long flags; | |
90 | ||
91 | local_irq_save(flags); | |
92 | /* | |
93 | * We need to handle two requests being made at the same time. | |
94 | * There are two important cases: | |
b0086efb | 95 | * 1. When we are changing VT (C_REENABLE) while unblanking |
96 | * (C_ENABLE) We must perform the unblanking, which will | |
97 | * do our REENABLE for us. | |
98 | * 2. When we are blanking, but immediately unblank before | |
99 | * we have blanked. We do the "REENABLE" thing here as | |
100 | * well, just to be sure. | |
1da177e4 LT |
101 | */ |
102 | if (fbi->task_state == C_ENABLE && state == C_REENABLE) | |
103 | state = (u_int) -1; | |
104 | if (fbi->task_state == C_DISABLE && state == C_ENABLE) | |
105 | state = C_REENABLE; | |
106 | ||
107 | if (state != (u_int)-1) { | |
108 | fbi->task_state = state; | |
109 | schedule_work(&fbi->task); | |
110 | } | |
111 | local_irq_restore(flags); | |
112 | } | |
113 | ||
114 | static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf) | |
115 | { | |
116 | chan &= 0xffff; | |
117 | chan >>= 16 - bf->length; | |
118 | return chan << bf->offset; | |
119 | } | |
120 | ||
121 | static int | |
122 | pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue, | |
123 | u_int trans, struct fb_info *info) | |
124 | { | |
125 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
9ffa7396 HK |
126 | u_int val; |
127 | ||
128 | if (regno >= fbi->palette_size) | |
129 | return 1; | |
130 | ||
131 | if (fbi->fb.var.grayscale) { | |
132 | fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff); | |
133 | return 0; | |
134 | } | |
135 | ||
136 | switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) { | |
137 | case LCCR4_PAL_FOR_0: | |
138 | val = ((red >> 0) & 0xf800); | |
139 | val |= ((green >> 5) & 0x07e0); | |
140 | val |= ((blue >> 11) & 0x001f); | |
1da177e4 | 141 | fbi->palette_cpu[regno] = val; |
9ffa7396 HK |
142 | break; |
143 | case LCCR4_PAL_FOR_1: | |
144 | val = ((red << 8) & 0x00f80000); | |
145 | val |= ((green >> 0) & 0x0000fc00); | |
146 | val |= ((blue >> 8) & 0x000000f8); | |
b0086efb | 147 | ((u32 *)(fbi->palette_cpu))[regno] = val; |
9ffa7396 HK |
148 | break; |
149 | case LCCR4_PAL_FOR_2: | |
150 | val = ((red << 8) & 0x00fc0000); | |
151 | val |= ((green >> 0) & 0x0000fc00); | |
152 | val |= ((blue >> 8) & 0x000000fc); | |
b0086efb | 153 | ((u32 *)(fbi->palette_cpu))[regno] = val; |
9ffa7396 | 154 | break; |
1da177e4 | 155 | } |
9ffa7396 HK |
156 | |
157 | return 0; | |
1da177e4 LT |
158 | } |
159 | ||
160 | static int | |
161 | pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
162 | u_int trans, struct fb_info *info) | |
163 | { | |
164 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
165 | unsigned int val; | |
166 | int ret = 1; | |
167 | ||
168 | /* | |
169 | * If inverse mode was selected, invert all the colours | |
170 | * rather than the register number. The register number | |
171 | * is what you poke into the framebuffer to produce the | |
172 | * colour you requested. | |
173 | */ | |
174 | if (fbi->cmap_inverse) { | |
175 | red = 0xffff - red; | |
176 | green = 0xffff - green; | |
177 | blue = 0xffff - blue; | |
178 | } | |
179 | ||
180 | /* | |
181 | * If greyscale is true, then we convert the RGB value | |
182 | * to greyscale no matter what visual we are using. | |
183 | */ | |
184 | if (fbi->fb.var.grayscale) | |
185 | red = green = blue = (19595 * red + 38470 * green + | |
186 | 7471 * blue) >> 16; | |
187 | ||
188 | switch (fbi->fb.fix.visual) { | |
189 | case FB_VISUAL_TRUECOLOR: | |
190 | /* | |
191 | * 16-bit True Colour. We encode the RGB value | |
192 | * according to the RGB bitfield information. | |
193 | */ | |
194 | if (regno < 16) { | |
195 | u32 *pal = fbi->fb.pseudo_palette; | |
196 | ||
197 | val = chan_to_field(red, &fbi->fb.var.red); | |
198 | val |= chan_to_field(green, &fbi->fb.var.green); | |
199 | val |= chan_to_field(blue, &fbi->fb.var.blue); | |
200 | ||
201 | pal[regno] = val; | |
202 | ret = 0; | |
203 | } | |
204 | break; | |
205 | ||
206 | case FB_VISUAL_STATIC_PSEUDOCOLOR: | |
207 | case FB_VISUAL_PSEUDOCOLOR: | |
208 | ret = pxafb_setpalettereg(regno, red, green, blue, trans, info); | |
209 | break; | |
210 | } | |
211 | ||
212 | return ret; | |
213 | } | |
214 | ||
215 | /* | |
216 | * pxafb_bpp_to_lccr3(): | |
217 | * Convert a bits per pixel value to the correct bit pattern for LCCR3 | |
218 | */ | |
219 | static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var) | |
220 | { | |
b0086efb | 221 | int ret = 0; |
222 | switch (var->bits_per_pixel) { | |
223 | case 1: ret = LCCR3_1BPP; break; | |
224 | case 2: ret = LCCR3_2BPP; break; | |
225 | case 4: ret = LCCR3_4BPP; break; | |
226 | case 8: ret = LCCR3_8BPP; break; | |
227 | case 16: ret = LCCR3_16BPP; break; | |
228 | } | |
229 | return ret; | |
1da177e4 LT |
230 | } |
231 | ||
232 | #ifdef CONFIG_CPU_FREQ | |
233 | /* | |
234 | * pxafb_display_dma_period() | |
235 | * Calculate the minimum period (in picoseconds) between two DMA | |
236 | * requests for the LCD controller. If we hit this, it means we're | |
237 | * doing nothing but LCD DMA. | |
238 | */ | |
239 | static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var) | |
240 | { | |
b0086efb | 241 | /* |
242 | * Period = pixclock * bits_per_byte * bytes_per_transfer | |
243 | * / memory_bits_per_pixel; | |
244 | */ | |
245 | return var->pixclock * 8 * 16 / var->bits_per_pixel; | |
1da177e4 | 246 | } |
1da177e4 LT |
247 | #endif |
248 | ||
d14b272b RP |
249 | /* |
250 | * Select the smallest mode that allows the desired resolution to be | |
251 | * displayed. If desired parameters can be rounded up. | |
252 | */ | |
b0086efb | 253 | static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, |
254 | struct fb_var_screeninfo *var) | |
d14b272b RP |
255 | { |
256 | struct pxafb_mode_info *mode = NULL; | |
257 | struct pxafb_mode_info *modelist = mach->modes; | |
258 | unsigned int best_x = 0xffffffff, best_y = 0xffffffff; | |
259 | unsigned int i; | |
260 | ||
b0086efb | 261 | for (i = 0; i < mach->num_modes; i++) { |
262 | if (modelist[i].xres >= var->xres && | |
263 | modelist[i].yres >= var->yres && | |
264 | modelist[i].xres < best_x && | |
265 | modelist[i].yres < best_y && | |
266 | modelist[i].bpp >= var->bits_per_pixel) { | |
d14b272b RP |
267 | best_x = modelist[i].xres; |
268 | best_y = modelist[i].yres; | |
269 | mode = &modelist[i]; | |
270 | } | |
271 | } | |
272 | ||
273 | return mode; | |
274 | } | |
275 | ||
b0086efb | 276 | static void pxafb_setmode(struct fb_var_screeninfo *var, |
277 | struct pxafb_mode_info *mode) | |
d14b272b RP |
278 | { |
279 | var->xres = mode->xres; | |
280 | var->yres = mode->yres; | |
281 | var->bits_per_pixel = mode->bpp; | |
282 | var->pixclock = mode->pixclock; | |
283 | var->hsync_len = mode->hsync_len; | |
284 | var->left_margin = mode->left_margin; | |
285 | var->right_margin = mode->right_margin; | |
286 | var->vsync_len = mode->vsync_len; | |
287 | var->upper_margin = mode->upper_margin; | |
288 | var->lower_margin = mode->lower_margin; | |
289 | var->sync = mode->sync; | |
290 | var->grayscale = mode->cmap_greyscale; | |
291 | var->xres_virtual = var->xres; | |
292 | var->yres_virtual = var->yres; | |
293 | } | |
294 | ||
1da177e4 LT |
295 | /* |
296 | * pxafb_check_var(): | |
297 | * Get the video params out of 'var'. If a value doesn't fit, round it up, | |
298 | * if it's too big, return -EINVAL. | |
299 | * | |
300 | * Round up in the following order: bits_per_pixel, xres, | |
301 | * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale, | |
302 | * bitfields, horizontal timing, vertical timing. | |
303 | */ | |
304 | static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
305 | { | |
306 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
d14b272b | 307 | struct pxafb_mach_info *inf = fbi->dev->platform_data; |
1da177e4 LT |
308 | |
309 | if (var->xres < MIN_XRES) | |
310 | var->xres = MIN_XRES; | |
311 | if (var->yres < MIN_YRES) | |
312 | var->yres = MIN_YRES; | |
d14b272b RP |
313 | |
314 | if (inf->fixed_modes) { | |
315 | struct pxafb_mode_info *mode; | |
316 | ||
317 | mode = pxafb_getmode(inf, var); | |
318 | if (!mode) | |
319 | return -EINVAL; | |
320 | pxafb_setmode(var, mode); | |
321 | } else { | |
322 | if (var->xres > inf->modes->xres) | |
323 | return -EINVAL; | |
324 | if (var->yres > inf->modes->yres) | |
325 | return -EINVAL; | |
326 | if (var->bits_per_pixel > inf->modes->bpp) | |
327 | return -EINVAL; | |
328 | } | |
329 | ||
1da177e4 LT |
330 | var->xres_virtual = |
331 | max(var->xres_virtual, var->xres); | |
332 | var->yres_virtual = | |
333 | max(var->yres_virtual, var->yres); | |
334 | ||
b0086efb | 335 | /* |
1da177e4 LT |
336 | * Setup the RGB parameters for this display. |
337 | * | |
338 | * The pixel packing format is described on page 7-11 of the | |
339 | * PXA2XX Developer's Manual. | |
b0086efb | 340 | */ |
1da177e4 LT |
341 | if (var->bits_per_pixel == 16) { |
342 | var->red.offset = 11; var->red.length = 5; | |
343 | var->green.offset = 5; var->green.length = 6; | |
344 | var->blue.offset = 0; var->blue.length = 5; | |
345 | var->transp.offset = var->transp.length = 0; | |
346 | } else { | |
b0086efb | 347 | var->red.offset = var->green.offset = 0; |
348 | var->blue.offset = var->transp.offset = 0; | |
1da177e4 LT |
349 | var->red.length = 8; |
350 | var->green.length = 8; | |
351 | var->blue.length = 8; | |
352 | var->transp.length = 0; | |
353 | } | |
354 | ||
355 | #ifdef CONFIG_CPU_FREQ | |
ca5da710 RK |
356 | pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n", |
357 | pxafb_display_dma_period(var), | |
358 | get_clk_frequency_khz(0)); | |
1da177e4 LT |
359 | #endif |
360 | ||
361 | return 0; | |
362 | } | |
363 | ||
364 | static inline void pxafb_set_truecolor(u_int is_true_color) | |
365 | { | |
b0086efb | 366 | /* do your machine-specific setup if needed */ |
1da177e4 LT |
367 | } |
368 | ||
369 | /* | |
370 | * pxafb_set_par(): | |
371 | * Set the user defined part of the display for the specified console | |
372 | */ | |
373 | static int pxafb_set_par(struct fb_info *info) | |
374 | { | |
375 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
376 | struct fb_var_screeninfo *var = &info->var; | |
1da177e4 | 377 | |
1da177e4 LT |
378 | if (var->bits_per_pixel == 16) |
379 | fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR; | |
380 | else if (!fbi->cmap_static) | |
381 | fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
382 | else { | |
383 | /* | |
384 | * Some people have weird ideas about wanting static | |
385 | * pseudocolor maps. I suspect their user space | |
386 | * applications are broken. | |
387 | */ | |
388 | fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR; | |
389 | } | |
390 | ||
391 | fbi->fb.fix.line_length = var->xres_virtual * | |
392 | var->bits_per_pixel / 8; | |
393 | if (var->bits_per_pixel == 16) | |
394 | fbi->palette_size = 0; | |
395 | else | |
b0086efb | 396 | fbi->palette_size = var->bits_per_pixel == 1 ? |
397 | 4 : 1 << var->bits_per_pixel; | |
1da177e4 | 398 | |
2c42dd8e | 399 | fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; |
1da177e4 LT |
400 | |
401 | /* | |
402 | * Set (any) board control register to handle new color depth | |
403 | */ | |
404 | pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR); | |
405 | ||
406 | if (fbi->fb.var.bits_per_pixel == 16) | |
407 | fb_dealloc_cmap(&fbi->fb.cmap); | |
408 | else | |
409 | fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0); | |
410 | ||
411 | pxafb_activate_var(var, fbi); | |
412 | ||
413 | return 0; | |
414 | } | |
415 | ||
1da177e4 LT |
416 | /* |
417 | * pxafb_blank(): | |
418 | * Blank the display by setting all palette values to zero. Note, the | |
419 | * 16 bpp mode does not really use the palette, so this will not | |
420 | * blank the display in all modes. | |
421 | */ | |
422 | static int pxafb_blank(int blank, struct fb_info *info) | |
423 | { | |
424 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
425 | int i; | |
426 | ||
1da177e4 LT |
427 | switch (blank) { |
428 | case FB_BLANK_POWERDOWN: | |
429 | case FB_BLANK_VSYNC_SUSPEND: | |
430 | case FB_BLANK_HSYNC_SUSPEND: | |
431 | case FB_BLANK_NORMAL: | |
432 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || | |
433 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
434 | for (i = 0; i < fbi->palette_size; i++) | |
435 | pxafb_setpalettereg(i, 0, 0, 0, 0, info); | |
436 | ||
437 | pxafb_schedule_work(fbi, C_DISABLE); | |
b0086efb | 438 | /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ |
1da177e4 LT |
439 | break; |
440 | ||
441 | case FB_BLANK_UNBLANK: | |
b0086efb | 442 | /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */ |
1da177e4 LT |
443 | if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR || |
444 | fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR) | |
445 | fb_set_cmap(&fbi->fb.cmap, info); | |
446 | pxafb_schedule_work(fbi, C_ENABLE); | |
447 | } | |
448 | return 0; | |
449 | } | |
450 | ||
216d526c | 451 | static int pxafb_mmap(struct fb_info *info, |
1da177e4 LT |
452 | struct vm_area_struct *vma) |
453 | { | |
454 | struct pxafb_info *fbi = (struct pxafb_info *)info; | |
455 | unsigned long off = vma->vm_pgoff << PAGE_SHIFT; | |
456 | ||
457 | if (off < info->fix.smem_len) { | |
458 | vma->vm_pgoff += 1; | |
459 | return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu, | |
460 | fbi->map_dma, fbi->map_size); | |
461 | } | |
462 | return -EINVAL; | |
463 | } | |
464 | ||
465 | static struct fb_ops pxafb_ops = { | |
466 | .owner = THIS_MODULE, | |
467 | .fb_check_var = pxafb_check_var, | |
468 | .fb_set_par = pxafb_set_par, | |
469 | .fb_setcolreg = pxafb_setcolreg, | |
470 | .fb_fillrect = cfb_fillrect, | |
471 | .fb_copyarea = cfb_copyarea, | |
472 | .fb_imageblit = cfb_imageblit, | |
473 | .fb_blank = pxafb_blank, | |
1da177e4 LT |
474 | .fb_mmap = pxafb_mmap, |
475 | }; | |
476 | ||
477 | /* | |
478 | * Calculate the PCD value from the clock rate (in picoseconds). | |
479 | * We take account of the PPCR clock setting. | |
480 | * From PXA Developer's Manual: | |
481 | * | |
482 | * PixelClock = LCLK | |
483 | * ------------- | |
484 | * 2 ( PCD + 1 ) | |
485 | * | |
486 | * PCD = LCLK | |
487 | * ------------- - 1 | |
488 | * 2(PixelClock) | |
489 | * | |
490 | * Where: | |
491 | * LCLK = LCD/Memory Clock | |
492 | * PCD = LCCR3[7:0] | |
493 | * | |
494 | * PixelClock here is in Hz while the pixclock argument given is the | |
495 | * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 ) | |
496 | * | |
497 | * The function get_lclk_frequency_10khz returns LCLK in units of | |
498 | * 10khz. Calling the result of this function lclk gives us the | |
499 | * following | |
500 | * | |
501 | * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 ) | |
502 | * -------------------------------------- - 1 | |
503 | * 2 | |
504 | * | |
505 | * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below. | |
506 | */ | |
b0086efb | 507 | static inline unsigned int get_pcd(struct pxafb_info *fbi, |
508 | unsigned int pixclock) | |
1da177e4 LT |
509 | { |
510 | unsigned long long pcd; | |
511 | ||
512 | /* FIXME: Need to take into account Double Pixel Clock mode | |
72e3524c RK |
513 | * (DPC) bit? or perhaps set it based on the various clock |
514 | * speeds */ | |
515 | pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000); | |
516 | pcd *= pixclock; | |
bf1b8ab6 | 517 | do_div(pcd, 100000000 * 2); |
1da177e4 LT |
518 | /* no need for this, since we should subtract 1 anyway. they cancel */ |
519 | /* pcd += 1; */ /* make up for integer math truncations */ | |
520 | return (unsigned int)pcd; | |
521 | } | |
522 | ||
ba44cd2d RP |
523 | /* |
524 | * Some touchscreens need hsync information from the video driver to | |
72e3524c RK |
525 | * function correctly. We export it here. Note that 'hsync_time' and |
526 | * the value returned from pxafb_get_hsync_time() is the *reciprocal* | |
527 | * of the hsync period in seconds. | |
ba44cd2d RP |
528 | */ |
529 | static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd) | |
530 | { | |
72e3524c | 531 | unsigned long htime; |
ba44cd2d RP |
532 | |
533 | if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) { | |
b0086efb | 534 | fbi->hsync_time = 0; |
ba44cd2d RP |
535 | return; |
536 | } | |
537 | ||
72e3524c RK |
538 | htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len); |
539 | ||
ba44cd2d RP |
540 | fbi->hsync_time = htime; |
541 | } | |
542 | ||
543 | unsigned long pxafb_get_hsync_time(struct device *dev) | |
544 | { | |
545 | struct pxafb_info *fbi = dev_get_drvdata(dev); | |
546 | ||
547 | /* If display is blanked/suspended, hsync isn't active */ | |
548 | if (!fbi || (fbi->state != C_ENABLE)) | |
549 | return 0; | |
550 | ||
551 | return fbi->hsync_time; | |
552 | } | |
553 | EXPORT_SYMBOL(pxafb_get_hsync_time); | |
554 | ||
2c42dd8e | 555 | static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal, |
556 | unsigned int offset, size_t size) | |
557 | { | |
558 | struct pxafb_dma_descriptor *dma_desc, *pal_desc; | |
559 | unsigned int dma_desc_off, pal_desc_off; | |
560 | ||
561 | if (dma < 0 || dma >= DMA_MAX) | |
562 | return -EINVAL; | |
563 | ||
564 | dma_desc = &fbi->dma_buff->dma_desc[dma]; | |
565 | dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]); | |
566 | ||
567 | dma_desc->fsadr = fbi->screen_dma + offset; | |
568 | dma_desc->fidr = 0; | |
569 | dma_desc->ldcmd = size; | |
570 | ||
571 | if (pal < 0 || pal >= PAL_MAX) { | |
572 | dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; | |
573 | fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; | |
574 | } else { | |
575 | pal_desc = &fbi->dma_buff->pal_desc[dma]; | |
576 | pal_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[pal]); | |
577 | ||
578 | pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE; | |
579 | pal_desc->fidr = 0; | |
580 | ||
581 | if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0) | |
582 | pal_desc->ldcmd = fbi->palette_size * sizeof(u16); | |
583 | else | |
584 | pal_desc->ldcmd = fbi->palette_size * sizeof(u32); | |
585 | ||
586 | pal_desc->ldcmd |= LDCMD_PAL; | |
587 | ||
588 | /* flip back and forth between palette and frame buffer */ | |
589 | pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off; | |
590 | dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off; | |
591 | fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off; | |
592 | } | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
1da177e4 LT |
597 | /* |
598 | * pxafb_activate_var(): | |
b0086efb | 599 | * Configures LCD Controller based on entries in var parameter. |
600 | * Settings are only written to the controller if changes were made. | |
1da177e4 | 601 | */ |
b0086efb | 602 | static int pxafb_activate_var(struct fb_var_screeninfo *var, |
603 | struct pxafb_info *fbi) | |
1da177e4 LT |
604 | { |
605 | struct pxafb_lcd_reg new_regs; | |
606 | u_long flags; | |
72e3524c | 607 | u_int lines_per_panel, pcd = get_pcd(fbi, var->pixclock); |
2c42dd8e | 608 | size_t nbytes; |
1da177e4 | 609 | |
1da177e4 | 610 | #if DEBUG_VAR |
b0086efb | 611 | if (var->xres < 16 || var->xres > 1024) |
1da177e4 LT |
612 | printk(KERN_ERR "%s: invalid xres %d\n", |
613 | fbi->fb.fix.id, var->xres); | |
b0086efb | 614 | switch (var->bits_per_pixel) { |
1da177e4 LT |
615 | case 1: |
616 | case 2: | |
617 | case 4: | |
618 | case 8: | |
619 | case 16: | |
620 | break; | |
621 | default: | |
622 | printk(KERN_ERR "%s: invalid bit depth %d\n", | |
623 | fbi->fb.fix.id, var->bits_per_pixel); | |
624 | break; | |
625 | } | |
b0086efb | 626 | if (var->hsync_len < 1 || var->hsync_len > 64) |
1da177e4 LT |
627 | printk(KERN_ERR "%s: invalid hsync_len %d\n", |
628 | fbi->fb.fix.id, var->hsync_len); | |
b0086efb | 629 | if (var->left_margin < 1 || var->left_margin > 255) |
1da177e4 LT |
630 | printk(KERN_ERR "%s: invalid left_margin %d\n", |
631 | fbi->fb.fix.id, var->left_margin); | |
632 | if (var->right_margin < 1 || var->right_margin > 255) | |
633 | printk(KERN_ERR "%s: invalid right_margin %d\n", | |
634 | fbi->fb.fix.id, var->right_margin); | |
b0086efb | 635 | if (var->yres < 1 || var->yres > 1024) |
1da177e4 LT |
636 | printk(KERN_ERR "%s: invalid yres %d\n", |
637 | fbi->fb.fix.id, var->yres); | |
b0086efb | 638 | if (var->vsync_len < 1 || var->vsync_len > 64) |
1da177e4 LT |
639 | printk(KERN_ERR "%s: invalid vsync_len %d\n", |
640 | fbi->fb.fix.id, var->vsync_len); | |
641 | if (var->upper_margin < 0 || var->upper_margin > 255) | |
642 | printk(KERN_ERR "%s: invalid upper_margin %d\n", | |
643 | fbi->fb.fix.id, var->upper_margin); | |
644 | if (var->lower_margin < 0 || var->lower_margin > 255) | |
645 | printk(KERN_ERR "%s: invalid lower_margin %d\n", | |
646 | fbi->fb.fix.id, var->lower_margin); | |
647 | #endif | |
648 | ||
649 | new_regs.lccr0 = fbi->lccr0 | | |
650 | (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM | | |
b0086efb | 651 | LCCR0_QDM | LCCR0_BM | LCCR0_OUM); |
1da177e4 LT |
652 | |
653 | new_regs.lccr1 = | |
654 | LCCR1_DisWdth(var->xres) + | |
655 | LCCR1_HorSnchWdth(var->hsync_len) + | |
656 | LCCR1_BegLnDel(var->left_margin) + | |
657 | LCCR1_EndLnDel(var->right_margin); | |
658 | ||
659 | /* | |
660 | * If we have a dual scan LCD, we need to halve | |
661 | * the YRES parameter. | |
662 | */ | |
663 | lines_per_panel = var->yres; | |
664 | if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) | |
665 | lines_per_panel /= 2; | |
666 | ||
667 | new_regs.lccr2 = | |
668 | LCCR2_DisHght(lines_per_panel) + | |
669 | LCCR2_VrtSnchWdth(var->vsync_len) + | |
670 | LCCR2_BegFrmDel(var->upper_margin) + | |
671 | LCCR2_EndFrmDel(var->lower_margin); | |
672 | ||
673 | new_regs.lccr3 = fbi->lccr3 | | |
674 | pxafb_bpp_to_lccr3(var) | | |
b0086efb | 675 | (var->sync & FB_SYNC_HOR_HIGH_ACT ? |
676 | LCCR3_HorSnchH : LCCR3_HorSnchL) | | |
677 | (var->sync & FB_SYNC_VERT_HIGH_ACT ? | |
678 | LCCR3_VrtSnchH : LCCR3_VrtSnchL); | |
1da177e4 LT |
679 | |
680 | if (pcd) | |
681 | new_regs.lccr3 |= LCCR3_PixClkDiv(pcd); | |
682 | ||
1da177e4 LT |
683 | /* Update shadow copy atomically */ |
684 | local_irq_save(flags); | |
685 | ||
2c42dd8e | 686 | nbytes = lines_per_panel * fbi->fb.fix.line_length; |
1da177e4 | 687 | |
2c42dd8e | 688 | if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual) |
689 | setup_frame_dma(fbi, DMA_LOWER, PAL_NONE, nbytes, nbytes); | |
690 | ||
691 | if (var->bits_per_pixel >= 16) | |
692 | setup_frame_dma(fbi, DMA_BASE, PAL_NONE, 0, nbytes); | |
693 | else | |
694 | setup_frame_dma(fbi, DMA_BASE, PAL_BASE, 0, nbytes); | |
1da177e4 | 695 | |
1da177e4 LT |
696 | fbi->reg_lccr0 = new_regs.lccr0; |
697 | fbi->reg_lccr1 = new_regs.lccr1; | |
698 | fbi->reg_lccr2 = new_regs.lccr2; | |
699 | fbi->reg_lccr3 = new_regs.lccr3; | |
a7535ba7 | 700 | fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK; |
9ffa7396 | 701 | fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK); |
ba44cd2d | 702 | set_hsync_time(fbi, pcd); |
1da177e4 LT |
703 | local_irq_restore(flags); |
704 | ||
705 | /* | |
706 | * Only update the registers if the controller is enabled | |
707 | * and something has changed. | |
708 | */ | |
a7535ba7 EM |
709 | if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) || |
710 | (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) || | |
711 | (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) || | |
712 | (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) || | |
713 | (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) || | |
714 | (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])) | |
1da177e4 LT |
715 | pxafb_schedule_work(fbi, C_REENABLE); |
716 | ||
717 | return 0; | |
718 | } | |
719 | ||
720 | /* | |
721 | * NOTE! The following functions are purely helpers for set_ctrlr_state. | |
722 | * Do not call them directly; set_ctrlr_state does the correct serialisation | |
723 | * to ensure that things happen in the right way 100% of time time. | |
724 | * -- rmk | |
725 | */ | |
726 | static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on) | |
727 | { | |
ca5da710 | 728 | pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff"); |
1da177e4 | 729 | |
b0086efb | 730 | if (pxafb_backlight_power) |
731 | pxafb_backlight_power(on); | |
1da177e4 LT |
732 | } |
733 | ||
734 | static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on) | |
735 | { | |
ca5da710 | 736 | pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff"); |
1da177e4 LT |
737 | |
738 | if (pxafb_lcd_power) | |
d14b272b | 739 | pxafb_lcd_power(on, &fbi->fb.var); |
1da177e4 LT |
740 | } |
741 | ||
742 | static void pxafb_setup_gpio(struct pxafb_info *fbi) | |
743 | { | |
744 | int gpio, ldd_bits; | |
b0086efb | 745 | unsigned int lccr0 = fbi->lccr0; |
1da177e4 LT |
746 | |
747 | /* | |
748 | * setup is based on type of panel supported | |
b0086efb | 749 | */ |
1da177e4 LT |
750 | |
751 | /* 4 bit interface */ | |
752 | if ((lccr0 & LCCR0_CMS) == LCCR0_Mono && | |
753 | (lccr0 & LCCR0_SDS) == LCCR0_Sngl && | |
754 | (lccr0 & LCCR0_DPD) == LCCR0_4PixMono) | |
755 | ldd_bits = 4; | |
756 | ||
757 | /* 8 bit interface */ | |
b0086efb | 758 | else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono && |
759 | ((lccr0 & LCCR0_SDS) == LCCR0_Dual || | |
760 | (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) || | |
761 | ((lccr0 & LCCR0_CMS) == LCCR0_Color && | |
762 | (lccr0 & LCCR0_PAS) == LCCR0_Pas && | |
763 | (lccr0 & LCCR0_SDS) == LCCR0_Sngl)) | |
1da177e4 LT |
764 | ldd_bits = 8; |
765 | ||
766 | /* 16 bit interface */ | |
767 | else if ((lccr0 & LCCR0_CMS) == LCCR0_Color && | |
b0086efb | 768 | ((lccr0 & LCCR0_SDS) == LCCR0_Dual || |
769 | (lccr0 & LCCR0_PAS) == LCCR0_Act)) | |
1da177e4 LT |
770 | ldd_bits = 16; |
771 | ||
772 | else { | |
b0086efb | 773 | printk(KERN_ERR "pxafb_setup_gpio: unable to determine " |
774 | "bits per pixel\n"); | |
1da177e4 | 775 | return; |
b0086efb | 776 | } |
1da177e4 LT |
777 | |
778 | for (gpio = 58; ldd_bits; gpio++, ldd_bits--) | |
779 | pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT); | |
780 | pxa_gpio_mode(GPIO74_LCD_FCLK_MD); | |
781 | pxa_gpio_mode(GPIO75_LCD_LCLK_MD); | |
782 | pxa_gpio_mode(GPIO76_LCD_PCLK_MD); | |
783 | pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD); | |
784 | } | |
785 | ||
786 | static void pxafb_enable_controller(struct pxafb_info *fbi) | |
787 | { | |
ca5da710 | 788 | pr_debug("pxafb: Enabling LCD controller\n"); |
2c42dd8e | 789 | pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]); |
790 | pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]); | |
ca5da710 RK |
791 | pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0); |
792 | pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1); | |
793 | pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2); | |
794 | pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3); | |
1da177e4 | 795 | |
8d372266 | 796 | /* enable LCD controller clock */ |
72e3524c | 797 | clk_enable(fbi->clk); |
8d372266 | 798 | |
1da177e4 | 799 | /* Sequence from 11.7.10 */ |
a7535ba7 EM |
800 | lcd_writel(fbi, LCCR3, fbi->reg_lccr3); |
801 | lcd_writel(fbi, LCCR2, fbi->reg_lccr2); | |
802 | lcd_writel(fbi, LCCR1, fbi->reg_lccr1); | |
803 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB); | |
804 | ||
805 | lcd_writel(fbi, FDADR0, fbi->fdadr[0]); | |
806 | lcd_writel(fbi, FDADR1, fbi->fdadr[1]); | |
807 | lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB); | |
1da177e4 LT |
808 | } |
809 | ||
810 | static void pxafb_disable_controller(struct pxafb_info *fbi) | |
811 | { | |
ce4fb7b8 | 812 | uint32_t lccr0; |
813 | ||
ce4fb7b8 | 814 | /* Clear LCD Status Register */ |
a7535ba7 | 815 | lcd_writel(fbi, LCSR, 0xffffffff); |
ce4fb7b8 | 816 | |
a7535ba7 EM |
817 | lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM; |
818 | lcd_writel(fbi, LCCR0, lccr0); | |
819 | lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS); | |
1da177e4 | 820 | |
2ba162b9 | 821 | wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000); |
8d372266 NP |
822 | |
823 | /* disable LCD controller clock */ | |
72e3524c | 824 | clk_disable(fbi->clk); |
1da177e4 LT |
825 | } |
826 | ||
827 | /* | |
828 | * pxafb_handle_irq: Handle 'LCD DONE' interrupts. | |
829 | */ | |
7d12e780 | 830 | static irqreturn_t pxafb_handle_irq(int irq, void *dev_id) |
1da177e4 LT |
831 | { |
832 | struct pxafb_info *fbi = dev_id; | |
a7535ba7 | 833 | unsigned int lccr0, lcsr = lcd_readl(fbi, LCSR); |
1da177e4 LT |
834 | |
835 | if (lcsr & LCSR_LDD) { | |
a7535ba7 EM |
836 | lccr0 = lcd_readl(fbi, LCCR0); |
837 | lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM); | |
2ba162b9 | 838 | complete(&fbi->disable_done); |
1da177e4 LT |
839 | } |
840 | ||
a7535ba7 | 841 | lcd_writel(fbi, LCSR, lcsr); |
1da177e4 LT |
842 | return IRQ_HANDLED; |
843 | } | |
844 | ||
845 | /* | |
846 | * This function must be called from task context only, since it will | |
847 | * sleep when disabling the LCD controller, or if we get two contending | |
848 | * processes trying to alter state. | |
849 | */ | |
850 | static void set_ctrlr_state(struct pxafb_info *fbi, u_int state) | |
851 | { | |
852 | u_int old_state; | |
853 | ||
854 | down(&fbi->ctrlr_sem); | |
855 | ||
856 | old_state = fbi->state; | |
857 | ||
858 | /* | |
859 | * Hack around fbcon initialisation. | |
860 | */ | |
861 | if (old_state == C_STARTUP && state == C_REENABLE) | |
862 | state = C_ENABLE; | |
863 | ||
864 | switch (state) { | |
865 | case C_DISABLE_CLKCHANGE: | |
866 | /* | |
867 | * Disable controller for clock change. If the | |
868 | * controller is already disabled, then do nothing. | |
869 | */ | |
870 | if (old_state != C_DISABLE && old_state != C_DISABLE_PM) { | |
871 | fbi->state = state; | |
b0086efb | 872 | /* TODO __pxafb_lcd_power(fbi, 0); */ |
1da177e4 LT |
873 | pxafb_disable_controller(fbi); |
874 | } | |
875 | break; | |
876 | ||
877 | case C_DISABLE_PM: | |
878 | case C_DISABLE: | |
879 | /* | |
880 | * Disable controller | |
881 | */ | |
882 | if (old_state != C_DISABLE) { | |
883 | fbi->state = state; | |
884 | __pxafb_backlight_power(fbi, 0); | |
885 | __pxafb_lcd_power(fbi, 0); | |
886 | if (old_state != C_DISABLE_CLKCHANGE) | |
887 | pxafb_disable_controller(fbi); | |
888 | } | |
889 | break; | |
890 | ||
891 | case C_ENABLE_CLKCHANGE: | |
892 | /* | |
893 | * Enable the controller after clock change. Only | |
894 | * do this if we were disabled for the clock change. | |
895 | */ | |
896 | if (old_state == C_DISABLE_CLKCHANGE) { | |
897 | fbi->state = C_ENABLE; | |
898 | pxafb_enable_controller(fbi); | |
b0086efb | 899 | /* TODO __pxafb_lcd_power(fbi, 1); */ |
1da177e4 LT |
900 | } |
901 | break; | |
902 | ||
903 | case C_REENABLE: | |
904 | /* | |
905 | * Re-enable the controller only if it was already | |
906 | * enabled. This is so we reprogram the control | |
907 | * registers. | |
908 | */ | |
909 | if (old_state == C_ENABLE) { | |
d14b272b | 910 | __pxafb_lcd_power(fbi, 0); |
1da177e4 LT |
911 | pxafb_disable_controller(fbi); |
912 | pxafb_setup_gpio(fbi); | |
913 | pxafb_enable_controller(fbi); | |
d14b272b | 914 | __pxafb_lcd_power(fbi, 1); |
1da177e4 LT |
915 | } |
916 | break; | |
917 | ||
918 | case C_ENABLE_PM: | |
919 | /* | |
920 | * Re-enable the controller after PM. This is not | |
921 | * perfect - think about the case where we were doing | |
922 | * a clock change, and we suspended half-way through. | |
923 | */ | |
924 | if (old_state != C_DISABLE_PM) | |
925 | break; | |
926 | /* fall through */ | |
927 | ||
928 | case C_ENABLE: | |
929 | /* | |
930 | * Power up the LCD screen, enable controller, and | |
931 | * turn on the backlight. | |
932 | */ | |
933 | if (old_state != C_ENABLE) { | |
934 | fbi->state = C_ENABLE; | |
935 | pxafb_setup_gpio(fbi); | |
936 | pxafb_enable_controller(fbi); | |
937 | __pxafb_lcd_power(fbi, 1); | |
938 | __pxafb_backlight_power(fbi, 1); | |
939 | } | |
940 | break; | |
941 | } | |
942 | up(&fbi->ctrlr_sem); | |
943 | } | |
944 | ||
945 | /* | |
946 | * Our LCD controller task (which is called when we blank or unblank) | |
947 | * via keventd. | |
948 | */ | |
6d5aefb8 | 949 | static void pxafb_task(struct work_struct *work) |
1da177e4 | 950 | { |
6d5aefb8 DH |
951 | struct pxafb_info *fbi = |
952 | container_of(work, struct pxafb_info, task); | |
1da177e4 LT |
953 | u_int state = xchg(&fbi->task_state, -1); |
954 | ||
955 | set_ctrlr_state(fbi, state); | |
956 | } | |
957 | ||
958 | #ifdef CONFIG_CPU_FREQ | |
959 | /* | |
960 | * CPU clock speed change handler. We need to adjust the LCD timing | |
961 | * parameters when the CPU clock is adjusted by the power management | |
962 | * subsystem. | |
963 | * | |
964 | * TODO: Determine why f->new != 10*get_lclk_frequency_10khz() | |
965 | */ | |
966 | static int | |
967 | pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data) | |
968 | { | |
969 | struct pxafb_info *fbi = TO_INF(nb, freq_transition); | |
b0086efb | 970 | /* TODO struct cpufreq_freqs *f = data; */ |
1da177e4 LT |
971 | u_int pcd; |
972 | ||
973 | switch (val) { | |
974 | case CPUFREQ_PRECHANGE: | |
975 | set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE); | |
976 | break; | |
977 | ||
978 | case CPUFREQ_POSTCHANGE: | |
72e3524c | 979 | pcd = get_pcd(fbi, fbi->fb.var.pixclock); |
ba44cd2d | 980 | set_hsync_time(fbi, pcd); |
b0086efb | 981 | fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | |
982 | LCCR3_PixClkDiv(pcd); | |
1da177e4 LT |
983 | set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE); |
984 | break; | |
985 | } | |
986 | return 0; | |
987 | } | |
988 | ||
989 | static int | |
990 | pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data) | |
991 | { | |
992 | struct pxafb_info *fbi = TO_INF(nb, freq_policy); | |
993 | struct fb_var_screeninfo *var = &fbi->fb.var; | |
994 | struct cpufreq_policy *policy = data; | |
995 | ||
996 | switch (val) { | |
997 | case CPUFREQ_ADJUST: | |
998 | case CPUFREQ_INCOMPATIBLE: | |
ac2bf5bd | 999 | pr_debug("min dma period: %d ps, " |
1da177e4 LT |
1000 | "new clock %d kHz\n", pxafb_display_dma_period(var), |
1001 | policy->max); | |
b0086efb | 1002 | /* TODO: fill in min/max values */ |
1da177e4 | 1003 | break; |
1da177e4 LT |
1004 | } |
1005 | return 0; | |
1006 | } | |
1007 | #endif | |
1008 | ||
1009 | #ifdef CONFIG_PM | |
1010 | /* | |
1011 | * Power management hooks. Note that we won't be called from IRQ context, | |
1012 | * unlike the blank functions above, so we may sleep. | |
1013 | */ | |
3ae5eaec | 1014 | static int pxafb_suspend(struct platform_device *dev, pm_message_t state) |
1da177e4 | 1015 | { |
3ae5eaec | 1016 | struct pxafb_info *fbi = platform_get_drvdata(dev); |
1da177e4 | 1017 | |
9480e307 | 1018 | set_ctrlr_state(fbi, C_DISABLE_PM); |
1da177e4 LT |
1019 | return 0; |
1020 | } | |
1021 | ||
3ae5eaec | 1022 | static int pxafb_resume(struct platform_device *dev) |
1da177e4 | 1023 | { |
3ae5eaec | 1024 | struct pxafb_info *fbi = platform_get_drvdata(dev); |
1da177e4 | 1025 | |
9480e307 | 1026 | set_ctrlr_state(fbi, C_ENABLE_PM); |
1da177e4 LT |
1027 | return 0; |
1028 | } | |
1029 | #else | |
1030 | #define pxafb_suspend NULL | |
1031 | #define pxafb_resume NULL | |
1032 | #endif | |
1033 | ||
1034 | /* | |
1035 | * pxafb_map_video_memory(): | |
1036 | * Allocates the DRAM memory for the frame buffer. This buffer is | |
1037 | * remapped into a non-cached, non-buffered, memory region to | |
1038 | * allow palette and pixel writes to occur without flushing the | |
1039 | * cache. Once this area is remapped, all virtual memory | |
1040 | * access to the video memory should occur at the new region. | |
1041 | */ | |
1042 | static int __init pxafb_map_video_memory(struct pxafb_info *fbi) | |
1043 | { | |
1da177e4 LT |
1044 | /* |
1045 | * We reserve one page for the palette, plus the size | |
1046 | * of the framebuffer. | |
1047 | */ | |
1048 | fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE); | |
1049 | fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size, | |
1050 | &fbi->map_dma, GFP_KERNEL); | |
1051 | ||
1052 | if (fbi->map_cpu) { | |
1053 | /* prevent initial garbage on screen */ | |
1054 | memset(fbi->map_cpu, 0, fbi->map_size); | |
1055 | fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE; | |
1056 | fbi->screen_dma = fbi->map_dma + PAGE_SIZE; | |
1057 | /* | |
1058 | * FIXME: this is actually the wrong thing to place in | |
1059 | * smem_start. But fbdev suffers from the problem that | |
1060 | * it needs an API which doesn't exist (in this case, | |
1061 | * dma_writecombine_mmap) | |
1062 | */ | |
1063 | fbi->fb.fix.smem_start = fbi->screen_dma; | |
1da177e4 LT |
1064 | fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16; |
1065 | ||
2c42dd8e | 1066 | fbi->dma_buff = (void *)fbi->map_cpu; |
1067 | fbi->dma_buff_phys = fbi->map_dma; | |
1068 | fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0]; | |
1da177e4 LT |
1069 | } |
1070 | ||
1071 | return fbi->map_cpu ? 0 : -ENOMEM; | |
1072 | } | |
1073 | ||
84f43c30 | 1074 | static void pxafb_decode_mode_info(struct pxafb_info *fbi, |
1075 | struct pxafb_mode_info *modes, | |
1076 | unsigned int num_modes) | |
1077 | { | |
1078 | unsigned int i, smemlen; | |
1079 | ||
1080 | pxafb_setmode(&fbi->fb.var, &modes[0]); | |
1081 | ||
1082 | for (i = 0; i < num_modes; i++) { | |
1083 | smemlen = modes[i].xres * modes[i].yres * modes[i].bpp / 8; | |
1084 | if (smemlen > fbi->fb.fix.smem_len) | |
1085 | fbi->fb.fix.smem_len = smemlen; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | static int pxafb_decode_mach_info(struct pxafb_info *fbi, | |
1090 | struct pxafb_mach_info *inf) | |
1091 | { | |
1092 | unsigned int lcd_conn = inf->lcd_conn; | |
1093 | ||
1094 | fbi->cmap_inverse = inf->cmap_inverse; | |
1095 | fbi->cmap_static = inf->cmap_static; | |
1096 | ||
1097 | switch (lcd_conn & 0xf) { | |
1098 | case LCD_TYPE_MONO_STN: | |
1099 | fbi->lccr0 = LCCR0_CMS; | |
1100 | break; | |
1101 | case LCD_TYPE_MONO_DSTN: | |
1102 | fbi->lccr0 = LCCR0_CMS | LCCR0_SDS; | |
1103 | break; | |
1104 | case LCD_TYPE_COLOR_STN: | |
1105 | fbi->lccr0 = 0; | |
1106 | break; | |
1107 | case LCD_TYPE_COLOR_DSTN: | |
1108 | fbi->lccr0 = LCCR0_SDS; | |
1109 | break; | |
1110 | case LCD_TYPE_COLOR_TFT: | |
1111 | fbi->lccr0 = LCCR0_PAS; | |
1112 | break; | |
1113 | case LCD_TYPE_SMART_PANEL: | |
1114 | fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS; | |
1115 | break; | |
1116 | default: | |
1117 | /* fall back to backward compatibility way */ | |
1118 | fbi->lccr0 = inf->lccr0; | |
1119 | fbi->lccr3 = inf->lccr3; | |
1120 | fbi->lccr4 = inf->lccr4; | |
1121 | return -EINVAL; | |
1122 | } | |
1123 | ||
1124 | if (lcd_conn == LCD_MONO_STN_8BPP) | |
1125 | fbi->lccr0 |= LCCR0_DPD; | |
1126 | ||
1127 | fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff); | |
1128 | fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0; | |
1129 | fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL) ? LCCR3_PCP : 0; | |
1130 | ||
1131 | pxafb_decode_mode_info(fbi, inf->modes, inf->num_modes); | |
1132 | return 0; | |
1133 | } | |
1134 | ||
1da177e4 LT |
1135 | static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev) |
1136 | { | |
1137 | struct pxafb_info *fbi; | |
1138 | void *addr; | |
1139 | struct pxafb_mach_info *inf = dev->platform_data; | |
d14b272b | 1140 | struct pxafb_mode_info *mode = inf->modes; |
1da177e4 LT |
1141 | |
1142 | /* Alloc the pxafb_info and pseudo_palette in one step */ | |
1143 | fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL); | |
1144 | if (!fbi) | |
1145 | return NULL; | |
1146 | ||
1147 | memset(fbi, 0, sizeof(struct pxafb_info)); | |
1148 | fbi->dev = dev; | |
1149 | ||
72e3524c RK |
1150 | fbi->clk = clk_get(dev, "LCDCLK"); |
1151 | if (IS_ERR(fbi->clk)) { | |
1152 | kfree(fbi); | |
1153 | return NULL; | |
1154 | } | |
1155 | ||
1da177e4 LT |
1156 | strcpy(fbi->fb.fix.id, PXA_NAME); |
1157 | ||
1158 | fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS; | |
1159 | fbi->fb.fix.type_aux = 0; | |
1160 | fbi->fb.fix.xpanstep = 0; | |
1161 | fbi->fb.fix.ypanstep = 0; | |
1162 | fbi->fb.fix.ywrapstep = 0; | |
1163 | fbi->fb.fix.accel = FB_ACCEL_NONE; | |
1164 | ||
1165 | fbi->fb.var.nonstd = 0; | |
1166 | fbi->fb.var.activate = FB_ACTIVATE_NOW; | |
1167 | fbi->fb.var.height = -1; | |
1168 | fbi->fb.var.width = -1; | |
1169 | fbi->fb.var.accel_flags = 0; | |
1170 | fbi->fb.var.vmode = FB_VMODE_NONINTERLACED; | |
1171 | ||
1172 | fbi->fb.fbops = &pxafb_ops; | |
1173 | fbi->fb.flags = FBINFO_DEFAULT; | |
1174 | fbi->fb.node = -1; | |
1175 | ||
1176 | addr = fbi; | |
1177 | addr = addr + sizeof(struct pxafb_info); | |
1178 | fbi->fb.pseudo_palette = addr; | |
1179 | ||
b0086efb | 1180 | fbi->state = C_STARTUP; |
1181 | fbi->task_state = (u_char)-1; | |
d14b272b | 1182 | |
84f43c30 | 1183 | pxafb_decode_mach_info(fbi, inf); |
1da177e4 LT |
1184 | |
1185 | init_waitqueue_head(&fbi->ctrlr_wait); | |
6d5aefb8 | 1186 | INIT_WORK(&fbi->task, pxafb_task); |
1da177e4 | 1187 | init_MUTEX(&fbi->ctrlr_sem); |
2ba162b9 | 1188 | init_completion(&fbi->disable_done); |
1da177e4 LT |
1189 | |
1190 | return fbi; | |
1191 | } | |
1192 | ||
1193 | #ifdef CONFIG_FB_PXA_PARAMETERS | |
b0086efb | 1194 | static int __init parse_opt_mode(struct device *dev, const char *this_opt) |
1da177e4 LT |
1195 | { |
1196 | struct pxafb_mach_info *inf = dev->platform_data; | |
817daf14 | 1197 | |
1198 | const char *name = this_opt+5; | |
1199 | unsigned int namelen = strlen(name); | |
1200 | int res_specified = 0, bpp_specified = 0; | |
1201 | unsigned int xres = 0, yres = 0, bpp = 0; | |
1202 | int yres_specified = 0; | |
1203 | int i; | |
1204 | for (i = namelen-1; i >= 0; i--) { | |
1205 | switch (name[i]) { | |
1206 | case '-': | |
1207 | namelen = i; | |
1208 | if (!bpp_specified && !yres_specified) { | |
1209 | bpp = simple_strtoul(&name[i+1], NULL, 0); | |
1210 | bpp_specified = 1; | |
1211 | } else | |
1212 | goto done; | |
1213 | break; | |
1214 | case 'x': | |
1215 | if (!yres_specified) { | |
1216 | yres = simple_strtoul(&name[i+1], NULL, 0); | |
1217 | yres_specified = 1; | |
1218 | } else | |
1219 | goto done; | |
1220 | break; | |
1221 | case '0' ... '9': | |
1222 | break; | |
1223 | default: | |
1224 | goto done; | |
1225 | } | |
1226 | } | |
1227 | if (i < 0 && yres_specified) { | |
1228 | xres = simple_strtoul(name, NULL, 0); | |
1229 | res_specified = 1; | |
1230 | } | |
1231 | done: | |
1232 | if (res_specified) { | |
1233 | dev_info(dev, "overriding resolution: %dx%d\n", xres, yres); | |
1234 | inf->modes[0].xres = xres; inf->modes[0].yres = yres; | |
1235 | } | |
1236 | if (bpp_specified) | |
1237 | switch (bpp) { | |
1238 | case 1: | |
1239 | case 2: | |
1240 | case 4: | |
1241 | case 8: | |
1242 | case 16: | |
1243 | inf->modes[0].bpp = bpp; | |
1244 | dev_info(dev, "overriding bit depth: %d\n", bpp); | |
1245 | break; | |
1246 | default: | |
1247 | dev_err(dev, "Depth %d is not valid\n", bpp); | |
1248 | return -EINVAL; | |
1249 | } | |
1250 | return 0; | |
1251 | } | |
1252 | ||
b0086efb | 1253 | static int __init parse_opt(struct device *dev, char *this_opt) |
817daf14 | 1254 | { |
1255 | struct pxafb_mach_info *inf = dev->platform_data; | |
1256 | struct pxafb_mode_info *mode = &inf->modes[0]; | |
1257 | char s[64]; | |
1258 | ||
1259 | s[0] = '\0'; | |
1260 | ||
1261 | if (!strncmp(this_opt, "mode:", 5)) { | |
1262 | return parse_opt_mode(dev, this_opt); | |
1263 | } else if (!strncmp(this_opt, "pixclock:", 9)) { | |
1264 | mode->pixclock = simple_strtoul(this_opt+9, NULL, 0); | |
1265 | sprintf(s, "pixclock: %ld\n", mode->pixclock); | |
1266 | } else if (!strncmp(this_opt, "left:", 5)) { | |
1267 | mode->left_margin = simple_strtoul(this_opt+5, NULL, 0); | |
1268 | sprintf(s, "left: %u\n", mode->left_margin); | |
1269 | } else if (!strncmp(this_opt, "right:", 6)) { | |
1270 | mode->right_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1271 | sprintf(s, "right: %u\n", mode->right_margin); | |
1272 | } else if (!strncmp(this_opt, "upper:", 6)) { | |
1273 | mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1274 | sprintf(s, "upper: %u\n", mode->upper_margin); | |
1275 | } else if (!strncmp(this_opt, "lower:", 6)) { | |
1276 | mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0); | |
1277 | sprintf(s, "lower: %u\n", mode->lower_margin); | |
1278 | } else if (!strncmp(this_opt, "hsynclen:", 9)) { | |
1279 | mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1280 | sprintf(s, "hsynclen: %u\n", mode->hsync_len); | |
1281 | } else if (!strncmp(this_opt, "vsynclen:", 9)) { | |
1282 | mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0); | |
1283 | sprintf(s, "vsynclen: %u\n", mode->vsync_len); | |
1284 | } else if (!strncmp(this_opt, "hsync:", 6)) { | |
1285 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1286 | sprintf(s, "hsync: Active Low\n"); | |
1287 | mode->sync &= ~FB_SYNC_HOR_HIGH_ACT; | |
1288 | } else { | |
1289 | sprintf(s, "hsync: Active High\n"); | |
1290 | mode->sync |= FB_SYNC_HOR_HIGH_ACT; | |
1291 | } | |
1292 | } else if (!strncmp(this_opt, "vsync:", 6)) { | |
1293 | if (simple_strtoul(this_opt+6, NULL, 0) == 0) { | |
1294 | sprintf(s, "vsync: Active Low\n"); | |
1295 | mode->sync &= ~FB_SYNC_VERT_HIGH_ACT; | |
1296 | } else { | |
1297 | sprintf(s, "vsync: Active High\n"); | |
1298 | mode->sync |= FB_SYNC_VERT_HIGH_ACT; | |
1299 | } | |
1300 | } else if (!strncmp(this_opt, "dpc:", 4)) { | |
1301 | if (simple_strtoul(this_opt+4, NULL, 0) == 0) { | |
1302 | sprintf(s, "double pixel clock: false\n"); | |
1303 | inf->lccr3 &= ~LCCR3_DPC; | |
1304 | } else { | |
1305 | sprintf(s, "double pixel clock: true\n"); | |
1306 | inf->lccr3 |= LCCR3_DPC; | |
1307 | } | |
1308 | } else if (!strncmp(this_opt, "outputen:", 9)) { | |
1309 | if (simple_strtoul(this_opt+9, NULL, 0) == 0) { | |
1310 | sprintf(s, "output enable: active low\n"); | |
1311 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL; | |
1312 | } else { | |
1313 | sprintf(s, "output enable: active high\n"); | |
1314 | inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH; | |
1315 | } | |
1316 | } else if (!strncmp(this_opt, "pixclockpol:", 12)) { | |
1317 | if (simple_strtoul(this_opt+12, NULL, 0) == 0) { | |
1318 | sprintf(s, "pixel clock polarity: falling edge\n"); | |
1319 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg; | |
1320 | } else { | |
1321 | sprintf(s, "pixel clock polarity: rising edge\n"); | |
1322 | inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg; | |
1323 | } | |
1324 | } else if (!strncmp(this_opt, "color", 5)) { | |
1325 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color; | |
1326 | } else if (!strncmp(this_opt, "mono", 4)) { | |
1327 | inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono; | |
1328 | } else if (!strncmp(this_opt, "active", 6)) { | |
1329 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act; | |
1330 | } else if (!strncmp(this_opt, "passive", 7)) { | |
1331 | inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas; | |
1332 | } else if (!strncmp(this_opt, "single", 6)) { | |
1333 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl; | |
1334 | } else if (!strncmp(this_opt, "dual", 4)) { | |
1335 | inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual; | |
1336 | } else if (!strncmp(this_opt, "4pix", 4)) { | |
1337 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono; | |
1338 | } else if (!strncmp(this_opt, "8pix", 4)) { | |
1339 | inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono; | |
1340 | } else { | |
1341 | dev_err(dev, "unknown option: %s\n", this_opt); | |
1342 | return -EINVAL; | |
1343 | } | |
1344 | ||
1345 | if (s[0] != '\0') | |
1346 | dev_info(dev, "override %s", s); | |
1347 | ||
1348 | return 0; | |
1349 | } | |
1350 | ||
1351 | static int __init pxafb_parse_options(struct device *dev, char *options) | |
1352 | { | |
1da177e4 | 1353 | char *this_opt; |
817daf14 | 1354 | int ret; |
1da177e4 | 1355 | |
817daf14 | 1356 | if (!options || !*options) |
1357 | return 0; | |
1da177e4 LT |
1358 | |
1359 | dev_dbg(dev, "options are \"%s\"\n", options ? options : "null"); | |
1360 | ||
1361 | /* could be made table driven or similar?... */ | |
817daf14 | 1362 | while ((this_opt = strsep(&options, ",")) != NULL) { |
1363 | ret = parse_opt(dev, this_opt); | |
1364 | if (ret) | |
1365 | return ret; | |
1366 | } | |
1367 | return 0; | |
1da177e4 | 1368 | } |
92ac73c1 | 1369 | |
1370 | static char g_options[256] __devinitdata = ""; | |
1371 | ||
1372 | #ifndef CONFIG_MODULES | |
1373 | static int __devinit pxafb_setup_options(void) | |
1374 | { | |
1375 | char *options = NULL; | |
1376 | ||
1377 | if (fb_get_options("pxafb", &options)) | |
1378 | return -ENODEV; | |
1379 | ||
1380 | if (options) | |
1381 | strlcpy(g_options, options, sizeof(g_options)); | |
1382 | ||
1383 | return 0; | |
1384 | } | |
1385 | #else | |
1386 | #define pxafb_setup_options() (0) | |
1387 | ||
1388 | module_param_string(options, g_options, sizeof(g_options), 0); | |
1389 | MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)"); | |
1390 | #endif | |
1391 | ||
1392 | #else | |
1393 | #define pxafb_parse_options(...) (0) | |
1394 | #define pxafb_setup_options() (0) | |
1da177e4 LT |
1395 | #endif |
1396 | ||
ac2bf5bd | 1397 | static int __init pxafb_probe(struct platform_device *dev) |
1da177e4 LT |
1398 | { |
1399 | struct pxafb_info *fbi; | |
1400 | struct pxafb_mach_info *inf; | |
ce4fb7b8 | 1401 | struct resource *r; |
1402 | int irq, ret; | |
1da177e4 | 1403 | |
2cbbb3b5 | 1404 | dev_dbg(&dev->dev, "pxafb_probe\n"); |
1da177e4 | 1405 | |
3ae5eaec | 1406 | inf = dev->dev.platform_data; |
1da177e4 LT |
1407 | ret = -ENOMEM; |
1408 | fbi = NULL; | |
1409 | if (!inf) | |
1410 | goto failed; | |
1411 | ||
3ae5eaec | 1412 | ret = pxafb_parse_options(&dev->dev, g_options); |
1da177e4 LT |
1413 | if (ret < 0) |
1414 | goto failed; | |
1da177e4 LT |
1415 | |
1416 | #ifdef DEBUG_VAR | |
b0086efb | 1417 | /* Check for various illegal bit-combinations. Currently only |
1da177e4 LT |
1418 | * a warning is given. */ |
1419 | ||
b0086efb | 1420 | if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK) |
1421 | dev_warn(&dev->dev, "machine LCCR0 setting contains " | |
1422 | "illegal bits: %08x\n", | |
1423 | inf->lccr0 & LCCR0_INVALID_CONFIG_MASK); | |
1424 | if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK) | |
1425 | dev_warn(&dev->dev, "machine LCCR3 setting contains " | |
1426 | "illegal bits: %08x\n", | |
1427 | inf->lccr3 & LCCR3_INVALID_CONFIG_MASK); | |
1428 | if (inf->lccr0 & LCCR0_DPD && | |
1da177e4 LT |
1429 | ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas || |
1430 | (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl || | |
1431 | (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono)) | |
b0086efb | 1432 | dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is " |
1433 | "only valid in passive mono" | |
1434 | " single panel mode\n"); | |
1435 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act && | |
1da177e4 | 1436 | (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual) |
b0086efb | 1437 | dev_warn(&dev->dev, "Dual panel only valid in passive mode\n"); |
1438 | if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas && | |
1439 | (inf->modes->upper_margin || inf->modes->lower_margin)) | |
1440 | dev_warn(&dev->dev, "Upper and lower margins must be 0 in " | |
1441 | "passive mode\n"); | |
1da177e4 LT |
1442 | #endif |
1443 | ||
b0086efb | 1444 | dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n", |
1445 | inf->modes->xres, | |
1446 | inf->modes->yres, | |
1447 | inf->modes->bpp); | |
1448 | if (inf->modes->xres == 0 || | |
1449 | inf->modes->yres == 0 || | |
1450 | inf->modes->bpp == 0) { | |
3ae5eaec | 1451 | dev_err(&dev->dev, "Invalid resolution or bit depth\n"); |
1da177e4 LT |
1452 | ret = -EINVAL; |
1453 | goto failed; | |
1454 | } | |
1455 | pxafb_backlight_power = inf->pxafb_backlight_power; | |
1456 | pxafb_lcd_power = inf->pxafb_lcd_power; | |
3ae5eaec | 1457 | fbi = pxafb_init_fbinfo(&dev->dev); |
1da177e4 | 1458 | if (!fbi) { |
b0086efb | 1459 | /* only reason for pxafb_init_fbinfo to fail is kmalloc */ |
3ae5eaec | 1460 | dev_err(&dev->dev, "Failed to initialize framebuffer device\n"); |
b0086efb | 1461 | ret = -ENOMEM; |
1da177e4 LT |
1462 | goto failed; |
1463 | } | |
1464 | ||
ce4fb7b8 | 1465 | r = platform_get_resource(dev, IORESOURCE_MEM, 0); |
1466 | if (r == NULL) { | |
1467 | dev_err(&dev->dev, "no I/O memory resource defined\n"); | |
1468 | ret = -ENODEV; | |
1469 | goto failed; | |
1470 | } | |
1471 | ||
1472 | r = request_mem_region(r->start, r->end - r->start + 1, dev->name); | |
1473 | if (r == NULL) { | |
1474 | dev_err(&dev->dev, "failed to request I/O memory\n"); | |
1475 | ret = -EBUSY; | |
1476 | goto failed; | |
1477 | } | |
1478 | ||
1479 | fbi->mmio_base = ioremap(r->start, r->end - r->start + 1); | |
1480 | if (fbi->mmio_base == NULL) { | |
1481 | dev_err(&dev->dev, "failed to map I/O memory\n"); | |
1482 | ret = -EBUSY; | |
1483 | goto failed_free_res; | |
1484 | } | |
1485 | ||
1da177e4 LT |
1486 | /* Initialize video memory */ |
1487 | ret = pxafb_map_video_memory(fbi); | |
1488 | if (ret) { | |
3ae5eaec | 1489 | dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret); |
1da177e4 | 1490 | ret = -ENOMEM; |
ce4fb7b8 | 1491 | goto failed_free_io; |
1da177e4 | 1492 | } |
1da177e4 | 1493 | |
ce4fb7b8 | 1494 | irq = platform_get_irq(dev, 0); |
1495 | if (irq < 0) { | |
1496 | dev_err(&dev->dev, "no IRQ defined\n"); | |
1497 | ret = -ENODEV; | |
1498 | goto failed_free_mem; | |
1499 | } | |
1500 | ||
1501 | ret = request_irq(irq, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi); | |
1da177e4 | 1502 | if (ret) { |
3ae5eaec | 1503 | dev_err(&dev->dev, "request_irq failed: %d\n", ret); |
1da177e4 | 1504 | ret = -EBUSY; |
ce4fb7b8 | 1505 | goto failed_free_mem; |
1da177e4 LT |
1506 | } |
1507 | ||
1508 | /* | |
1509 | * This makes sure that our colour bitfield | |
1510 | * descriptors are correctly initialised. | |
1511 | */ | |
1512 | pxafb_check_var(&fbi->fb.var, &fbi->fb); | |
1513 | pxafb_set_par(&fbi->fb); | |
1514 | ||
3ae5eaec | 1515 | platform_set_drvdata(dev, fbi); |
1da177e4 LT |
1516 | |
1517 | ret = register_framebuffer(&fbi->fb); | |
1518 | if (ret < 0) { | |
b0086efb | 1519 | dev_err(&dev->dev, |
1520 | "Failed to register framebuffer device: %d\n", ret); | |
ce4fb7b8 | 1521 | goto failed_free_irq; |
1da177e4 LT |
1522 | } |
1523 | ||
1da177e4 LT |
1524 | #ifdef CONFIG_CPU_FREQ |
1525 | fbi->freq_transition.notifier_call = pxafb_freq_transition; | |
1526 | fbi->freq_policy.notifier_call = pxafb_freq_policy; | |
b0086efb | 1527 | cpufreq_register_notifier(&fbi->freq_transition, |
1528 | CPUFREQ_TRANSITION_NOTIFIER); | |
1529 | cpufreq_register_notifier(&fbi->freq_policy, | |
1530 | CPUFREQ_POLICY_NOTIFIER); | |
1da177e4 LT |
1531 | #endif |
1532 | ||
1533 | /* | |
1534 | * Ok, now enable the LCD controller | |
1535 | */ | |
1536 | set_ctrlr_state(fbi, C_ENABLE); | |
1537 | ||
1538 | return 0; | |
1539 | ||
ce4fb7b8 | 1540 | failed_free_irq: |
1541 | free_irq(irq, fbi); | |
1542 | failed_free_res: | |
1543 | release_mem_region(r->start, r->end - r->start + 1); | |
1544 | failed_free_io: | |
1545 | iounmap(fbi->mmio_base); | |
1546 | failed_free_mem: | |
1547 | dma_free_writecombine(&dev->dev, fbi->map_size, | |
1548 | fbi->map_cpu, fbi->map_dma); | |
1da177e4 | 1549 | failed: |
3ae5eaec | 1550 | platform_set_drvdata(dev, NULL); |
1da177e4 LT |
1551 | kfree(fbi); |
1552 | return ret; | |
1553 | } | |
1554 | ||
3ae5eaec | 1555 | static struct platform_driver pxafb_driver = { |
1da177e4 | 1556 | .probe = pxafb_probe, |
1da177e4 LT |
1557 | .suspend = pxafb_suspend, |
1558 | .resume = pxafb_resume, | |
3ae5eaec RK |
1559 | .driver = { |
1560 | .name = "pxa2xx-fb", | |
1561 | }, | |
1da177e4 LT |
1562 | }; |
1563 | ||
ac2bf5bd | 1564 | static int __devinit pxafb_init(void) |
1da177e4 | 1565 | { |
92ac73c1 | 1566 | if (pxafb_setup_options()) |
1567 | return -EINVAL; | |
1da177e4 | 1568 | |
3ae5eaec | 1569 | return platform_driver_register(&pxafb_driver); |
1da177e4 LT |
1570 | } |
1571 | ||
1572 | module_init(pxafb_init); | |
1573 | ||
1574 | MODULE_DESCRIPTION("loadable framebuffer driver for PXA"); | |
1575 | MODULE_LICENSE("GPL"); |