[deliverable/linux.git] / drivers / video / sh_mipi_dsi.c

/*
 * Renesas SH-mobile MIPI DSI support
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/bitmap.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>
#include <linux/module.h>

#include <video/mipi_display.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>

#define SYSCTRL		0x0000
#define SYSCONF		0x0004
#define TIMSET		0x0008
#define RESREQSET0	0x0018
#define RESREQSET1	0x001c
#define HSTTOVSET	0x0020
#define LPRTOVSET	0x0024
#define TATOVSET	0x0028
#define PRTOVSET	0x002c
#define DSICTRL		0x0030
#define DSIINTE		0x0060
#define PHYCTRL		0x0070

/* relative to linkbase */
#define DTCTR		0x0000
#define VMCTR1		0x0020
#define VMCTR2		0x0024
#define VMLEN1		0x0028
#define CMTSRTREQ	0x0070
#define CMTSRTCTR	0x00d0

/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2

struct sh_mipi {
	void __iomem	*base;
	void __iomem	*linkbase;
	struct clk	*dsit_clk;
	struct clk	*dsip_clk;
	struct device	*dev;

	void	*next_board_data;
	void	(*next_display_on)(void *board_data, struct fb_info *info);
	void	(*next_display_off)(void *board_data);
};

static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];

/* Protect the above array */
static DEFINE_MUTEX(array_lock);

static struct sh_mipi *sh_mipi_by_handle(int handle)
{
	if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
		return NULL;

	return mipi_dsi[handle];
}

static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
			      u8 cmd, u8 param)
{
	u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
	int cnt = 100;

	/* transmit a short packet to LCD panel */
	iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
	iowrite32(1, mipi->linkbase + CMTSRTREQ);

	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
		udelay(1);

	return cnt ? 0 : -ETIMEDOUT;
}

#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
				-EINVAL : (c) - 1)

static int sh_mipi_dcs(int handle, u8 cmd)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
}

static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
				  param);
}

static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
{
	/*
	 * enable LCDC data tx, transition to LPS after completion of each HS
	 * packet
	 */
	iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
}

static void sh_mipi_shutdown(struct platform_device *pdev)
{
	struct sh_mipi *mipi = platform_get_drvdata(pdev);

	sh_mipi_dsi_enable(mipi, false);
}

static void mipi_display_on(void *arg, struct fb_info *info)
{
	struct sh_mipi *mipi = arg;

	pm_runtime_get_sync(mipi->dev);
	sh_mipi_dsi_enable(mipi, true);

	if (mipi->next_display_on)
		mipi->next_display_on(mipi->next_board_data, info);
}

static void mipi_display_off(void *arg)
{
	struct sh_mipi *mipi = arg;

	if (mipi->next_display_off)
		mipi->next_display_off(mipi->next_board_data);

	sh_mipi_dsi_enable(mipi, false);
	pm_runtime_put(mipi->dev);
}

static int __init sh_mipi_setup(struct sh_mipi *mipi,
				struct sh_mipi_dsi_info *pdata)
{
	void __iomem *base = mipi->base;
	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	u32 pctype, datatype, pixfmt, linelength, vmctr2 = 0x00e00000;
	bool yuv;
	u32 tmp;

	/*
	 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
	 * the default videomode. If this ever becomes a problem, We'll have to
	 * move this to mipi_display_on() above and use info->var.xres
	 */
	switch (pdata->data_format) {
	case MIPI_RGB888:
		pctype = 0;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB565:
		pctype = 1;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_RGB666_LP:
		pctype = 2;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB666:
		pctype = 3;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_BGR888:
		pctype = 8;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR565:
		pctype = 9;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_BGR666_LP:
		pctype = 0xa;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR666:
		pctype = 0xb;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_YUYV:
		pctype = 4;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_UYVY:
		pctype = 5;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_YUV420_L:
		pctype = 6;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
		yuv = true;
		break;
	case MIPI_YUV420:
		pctype = 7;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		/* Length of U/V line */
		linelength = (ch->lcd_cfg[0].xres + 1) / 2;
		yuv = true;
		break;
	default:
		return -EINVAL;
	}

	if ((yuv && ch->interface_type != YUV422) ||
	    (!yuv && ch->interface_type != RGB24))
		return -EINVAL;

	if (!pdata->lane)
		return -EINVAL;

	/* reset DSI link */
	iowrite32(0x00000001, base + SYSCTRL);
	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
	udelay(50);
	iowrite32(0x00000000, base + SYSCTRL);

	/* setup DSI link */

	/*
	 * Default = ULPS enable |
	 *	Contention detection enabled |
	 *	EoT packet transmission enable |
	 *	CRC check enable |
	 *	ECC check enable
	 * additionally enable first two lanes
	 */
	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	tmp |= 0x00003700;
	iowrite32(tmp, base + SYSCONF);

	/*
	 * T_wakeup = 0x7000
	 * T_hs-trail = 3
	 * T_hs-prepare = 3
	 * T_clk-trail = 3
	 * T_clk-prepare = 2
	 */
	iowrite32(0x70003332, base + TIMSET);
	/* no responses requested */
	iowrite32(0x00000000, base + RESREQSET0);
	/* request response to packets of type 0x28 */
	iowrite32(0x00000100, base + RESREQSET1);
	/* High-speed transmission timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + HSTTOVSET);
	/* LP reception timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + LPRTOVSET);
	/* Turn-around timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + TATOVSET);
	/* Peripheral reset timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + PRTOVSET);
	/* Enable timeout counters */
	iowrite32(0x00000f00, base + DSICTRL);
	/* Interrupts not used, disable all */
	iowrite32(0, base + DSIINTE);
	/* DSI-Tx bias on */
	iowrite32(0x00000001, base + PHYCTRL);
	udelay(200);
	/* Deassert resets, power on, set multiplier */
	iowrite32(0x03070b01, base + PHYCTRL);

	/* setup l-bridge */

	/*
	 * Enable transmission of all packets,
	 * transmit LPS after each HS packet completion
	 */
	iowrite32(0x00000006, mipi->linkbase + DTCTR);
	/* VSYNC width = 2 (<< 17) */
	iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) |
		  (pdata->clksrc << 16) | (pctype << 12) | datatype,
		  mipi->linkbase + VMCTR1);

	/*
	 * Non-burst mode with sync pulses: VSE and HSE are output,
	 * HSA period allowed, no commands in LP
	 */
	if (pdata->flags & SH_MIPI_DSI_BL2E)
		vmctr2 |= 1 << 17;
	if (pdata->flags & SH_MIPI_DSI_HSABM)
		vmctr2 |= 1 << 5;
	if (pdata->flags & SH_MIPI_DSI_HBPBM)
		vmctr2 |= 1 << 4;
	if (pdata->flags & SH_MIPI_DSI_HFPBM)
		vmctr2 |= 1 << 3;
	iowrite32(vmctr2, mipi->linkbase + VMCTR2);

	/*
	 * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
	 * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
	 * (unused if VMCTR2[HSABM] = 0)
	 */
	iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1);

	msleep(5);

	/* setup LCD panel */

	/* cf. drivers/video/omap/lcd_mipid.c */
	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);
	/*
	 * [7] - Page Address Mode
	 * [6] - Column Address Mode
	 * [5] - Page / Column Address Mode
	 * [4] - Display Device Line Refresh Order
	 * [3] - RGB/BGR Order
	 * [2] - Display Data Latch Data Order
	 * [1] - Flip Horizontal
	 * [0] - Flip Vertical
	 */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	/* cf. set_data_lines() */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
			  pixfmt << 4);
	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);

	return 0;
}

static int __init sh_mipi_probe(struct platform_device *pdev)
{
	struct sh_mipi *mipi;
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	unsigned long rate, f_current;
	int idx = pdev->id, ret;

	if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
		return -ENODEV;

	mutex_lock(&array_lock);
	if (idx < 0)
		for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
			;

	if (idx == ARRAY_SIZE(mipi_dsi)) {
		ret = -EBUSY;
		goto efindslot;
	}

	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	if (!mipi) {
		ret = -ENOMEM;
		goto ealloc;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region already claimed\n");
		ret = -EBUSY;
		goto ereqreg;
	}

	mipi->base = ioremap(res->start, resource_size(res));
	if (!mipi->base) {
		ret = -ENOMEM;
		goto emap;
	}

	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
		ret = -EBUSY;
		goto ereqreg2;
	}

	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	if (!mipi->linkbase) {
		ret = -ENOMEM;
		goto emap2;
	}

	mipi->dev = &pdev->dev;

	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	if (IS_ERR(mipi->dsit_clk)) {
		ret = PTR_ERR(mipi->dsit_clk);
		goto eclktget;
	}

	f_current = clk_get_rate(mipi->dsit_clk);
	/* 80MHz required by the datasheet */
	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsit_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esettrate;

	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);

	mipi->dsip_clk = clk_get(&pdev->dev, "dsip_clk");
	if (IS_ERR(mipi->dsip_clk)) {
		ret = PTR_ERR(mipi->dsip_clk);
		goto eclkpget;
	}

	f_current = clk_get_rate(mipi->dsip_clk);
	/* Between 10 and 50MHz */
	rate = clk_round_rate(mipi->dsip_clk, 24000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsip_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esetprate;

	dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);

	msleep(10);

	ret = clk_enable(mipi->dsit_clk);
	if (ret < 0)
		goto eclkton;

	ret = clk_enable(mipi->dsip_clk);
	if (ret < 0)
		goto eclkpon;

	mipi_dsi[idx] = mipi;

	pm_runtime_enable(&pdev->dev);
	pm_runtime_resume(&pdev->dev);

	ret = sh_mipi_setup(mipi, pdata);
	if (ret < 0)
		goto emipisetup;

	mutex_unlock(&array_lock);
	platform_set_drvdata(pdev, mipi);

	/* Save original LCDC callbacks */
	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;

	/* Set up LCDC callbacks */
	pdata->lcd_chan->board_cfg.board_data = mipi;
	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
	pdata->lcd_chan->board_cfg.owner = THIS_MODULE;

	return 0;

emipisetup:
	mipi_dsi[idx] = NULL;
	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsip_clk);
eclkpon:
	clk_disable(mipi->dsit_clk);
eclkton:
esetprate:
	clk_put(mipi->dsip_clk);
eclkpget:
esettrate:
	clk_put(mipi->dsit_clk);
eclktget:
	iounmap(mipi->linkbase);
emap2:
	release_mem_region(res2->start, resource_size(res2));
ereqreg2:
	iounmap(mipi->base);
emap:
	release_mem_region(res->start, resource_size(res));
ereqreg:
	kfree(mipi);
ealloc:
efindslot:
	mutex_unlock(&array_lock);

	return ret;
}

static int __exit sh_mipi_remove(struct platform_device *pdev)
{
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	int i, ret;

	mutex_lock(&array_lock);

	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
		;

	if (i == ARRAY_SIZE(mipi_dsi)) {
		ret = -EINVAL;
	} else {
		ret = 0;
		mipi_dsi[i] = NULL;
	}

	mutex_unlock(&array_lock);

	if (ret < 0)
		return ret;

	pdata->lcd_chan->board_cfg.owner = NULL;
	pdata->lcd_chan->board_cfg.display_on = NULL;
	pdata->lcd_chan->board_cfg.display_off = NULL;
	pdata->lcd_chan->board_cfg.board_data = NULL;

	pm_runtime_disable(&pdev->dev);
	clk_disable(mipi->dsip_clk);
	clk_disable(mipi->dsit_clk);
	clk_put(mipi->dsit_clk);
	clk_put(mipi->dsip_clk);
	iounmap(mipi->linkbase);
	if (res2)
		release_mem_region(res2->start, resource_size(res2));
	iounmap(mipi->base);
	if (res)
		release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);
	kfree(mipi);

	return 0;
}

static struct platform_driver sh_mipi_driver = {
	.remove		= __exit_p(sh_mipi_remove),
	.shutdown	= sh_mipi_shutdown,
	.driver = {
		.name	= "sh-mipi-dsi",
	},
};

static int __init sh_mipi_init(void)
{
	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
}
module_init(sh_mipi_init);

static void __exit sh_mipi_exit(void)
{
	platform_driver_unregister(&sh_mipi_driver);
}
module_exit(sh_mipi_exit);

MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fd04fe3 GL	1	/*
	2	* Renesas SH-mobile MIPI DSI support
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This is free software; you can redistribute it and/or modify
	7	* it under the terms of version 2 of the GNU General Public License as
	8	* published by the Free Software Foundation.
	9	*/
	10
26c3d7ac	11	#include <linux/bitmap.h>
9fd04fe3 GL	12	#include <linux/clk.h>
	13	#include <linux/delay.h>
	14	#include <linux/init.h>
	15	#include <linux/io.h>
	16	#include <linux/platform_device.h>
236782a5	17	#include <linux/pm_runtime.h>
9fd04fe3 GL	18	#include <linux/slab.h>
	19	#include <linux/string.h>
	20	#include <linux/types.h>
355b200b	21	#include <linux/module.h>
9fd04fe3 GL	22
	23	#include <video/mipi_display.h>
	24	#include <video/sh_mipi_dsi.h>
	25	#include <video/sh_mobile_lcdc.h>
	26
71b146c8 MD	27	#define SYSCTRL 0x0000
	28	#define SYSCONF 0x0004
	29	#define TIMSET 0x0008
	30	#define RESREQSET0 0x0018
	31	#define RESREQSET1 0x001c
	32	#define HSTTOVSET 0x0020
	33	#define LPRTOVSET 0x0024
	34	#define TATOVSET 0x0028
	35	#define PRTOVSET 0x002c
	36	#define DSICTRL 0x0030
	37	#define DSIINTE 0x0060
	38	#define PHYCTRL 0x0070
	39
deaba190 MD	40	/* relative to linkbase */
	41	#define DTCTR 0x0000
	42	#define VMCTR1 0x0020
	43	#define VMCTR2 0x0024
	44	#define VMLEN1 0x0028
	45	#define CMTSRTREQ 0x0070
	46	#define CMTSRTCTR 0x00d0
9fd04fe3 GL	47
	48	/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
	49	#define MAX_SH_MIPI_DSI 2
	50
	51	struct sh_mipi {
	52	void __iomem *base;
deaba190	53	void __iomem *linkbase;
9fd04fe3 GL	54	struct clk *dsit_clk;
9fd04fe3 GL	55	struct clk *dsip_clk;
236782a5 GL	56	struct device *dev;
	57
	58	void *next_board_data;
	59	void (next_display_on)(void board_data, struct fb_info *info);
	60	void (next_display_off)(void board_data);
9fd04fe3 GL	61	};
	62
	63	static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
	64
	65	/* Protect the above array */
	66	static DEFINE_MUTEX(array_lock);
	67
	68	static struct sh_mipi *sh_mipi_by_handle(int handle)
	69	{
	70	if (handle >= ARRAY_SIZE(mipi_dsi) \|\| handle < 0)
	71	return NULL;
	72
	73	return mipi_dsi[handle];
	74	}
	75
	76	static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
	77	u8 cmd, u8 param)
	78	{
	79	u32 data = (dsi_cmd << 24) \| (cmd << 16) \| (param << 8);
	80	int cnt = 100;
	81
	82	/* transmit a short packet to LCD panel */
deaba190 MD	83	iowrite32(1 \| data, mipi->linkbase + CMTSRTCTR);
deaba190 MD	84	iowrite32(1, mipi->linkbase + CMTSRTREQ);
9fd04fe3	85
deaba190	86	while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
9fd04fe3 GL	87	udelay(1);
	88
	89	return cnt ? 0 : -ETIMEDOUT;
	90	}
	91
	92	#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD \|\| (c) > LCDC_CHAN_SUBLCD ? \
	93	-EINVAL : (c) - 1)
	94
	95	static int sh_mipi_dcs(int handle, u8 cmd)
	96	{
	97	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	98	if (!mipi)
	99	return -ENODEV;
	100	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
	101	}
	102
	103	static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
	104	{
	105	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	106	if (!mipi)
	107	return -ENODEV;
	108	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
	109	param);
	110	}
	111
	112	static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
	113	{
	114	/*
	115	* enable LCDC data tx, transition to LPS after completion of each HS
	116	* packet
	117	*/
deaba190	118	iowrite32(0x00000002 \| enable, mipi->linkbase + DTCTR);
9fd04fe3 GL	119	}
	120
	121	static void sh_mipi_shutdown(struct platform_device *pdev)
	122	{
	123	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	124
	125	sh_mipi_dsi_enable(mipi, false);
	126	}
	127
c2439398	128	static void mipi_display_on(void arg, struct fb_info info)
9fd04fe3 GL	129	{
	130	struct sh_mipi *mipi = arg;
	131
236782a5	132	pm_runtime_get_sync(mipi->dev);
9fd04fe3	133	sh_mipi_dsi_enable(mipi, true);
6722a401 MD	134
	135	if (mipi->next_display_on)
	136	mipi->next_display_on(mipi->next_board_data, info);
9fd04fe3 GL	137	}
	138
	139	static void mipi_display_off(void *arg)
	140	{
	141	struct sh_mipi *mipi = arg;
	142
6722a401 MD	143	if (mipi->next_display_off)
	144	mipi->next_display_off(mipi->next_board_data);
	145
9fd04fe3	146	sh_mipi_dsi_enable(mipi, false);
236782a5	147	pm_runtime_put(mipi->dev);
9fd04fe3 GL	148	}
	149
	150	static int __init sh_mipi_setup(struct sh_mipi *mipi,
	151	struct sh_mipi_dsi_info *pdata)
	152	{
	153	void __iomem *base = mipi->base;
	154	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
14bbb7c6	155	u32 pctype, datatype, pixfmt, linelength, vmctr2 = 0x00e00000;
9fd04fe3	156	bool yuv;
26c3d7ac	157	u32 tmp;
9fd04fe3	158
44432407 GL	159	/*
	160	* Select data format. MIPI DSI is not hot-pluggable, so, we just use
	161	* the default videomode. If this ever becomes a problem, We'll have to
	162	* move this to mipi_display_on() above and use info->var.xres
	163	*/
9fd04fe3 GL	164	switch (pdata->data_format) {
	165	case MIPI_RGB888:
	166	pctype = 0;
	167	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	168	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	169	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	170	yuv = false;
	171	break;
	172	case MIPI_RGB565:
	173	pctype = 1;
	174	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	175	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	176	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	177	yuv = false;
	178	break;
	179	case MIPI_RGB666_LP:
	180	pctype = 2;
	181	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	182	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	183	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	184	yuv = false;
	185	break;
	186	case MIPI_RGB666:
	187	pctype = 3;
	188	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	189	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	190	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	191	yuv = false;
	192	break;
	193	case MIPI_BGR888:
	194	pctype = 8;
	195	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	196	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	197	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	198	yuv = false;
	199	break;
	200	case MIPI_BGR565:
	201	pctype = 9;
	202	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	203	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	204	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	205	yuv = false;
	206	break;
	207	case MIPI_BGR666_LP:
	208	pctype = 0xa;
	209	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	210	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	211	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	212	yuv = false;
	213	break;
	214	case MIPI_BGR666:
	215	pctype = 0xb;
	216	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	217	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	218	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	219	yuv = false;
	220	break;
	221	case MIPI_YUYV:
	222	pctype = 4;
	223	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	224	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	225	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	226	yuv = true;
	227	break;
	228	case MIPI_UYVY:
	229	pctype = 5;
	230	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	231	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	232	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	233	yuv = true;
	234	break;
	235	case MIPI_YUV420_L:
	236	pctype = 6;
	237	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	238	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
44432407	239	linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
9fd04fe3 GL	240	yuv = true;
	241	break;
	242	case MIPI_YUV420:
	243	pctype = 7;
	244	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	245	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
	246	/* Length of U/V line */
44432407	247	linelength = (ch->lcd_cfg[0].xres + 1) / 2;
9fd04fe3 GL	248	yuv = true;
	249	break;
	250	default:
	251	return -EINVAL;
	252	}
	253
	254	if ((yuv && ch->interface_type != YUV422) \|\|
	255	(!yuv && ch->interface_type != RGB24))
	256	return -EINVAL;
	257
26c3d7ac KM	258	if (!pdata->lane)
	259	return -EINVAL;
	260
9fd04fe3	261	/* reset DSI link */
71b146c8	262	iowrite32(0x00000001, base + SYSCTRL);
9fd04fe3 GL	263	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
9fd04fe3 GL	264	udelay(50);
71b146c8	265	iowrite32(0x00000000, base + SYSCTRL);
9fd04fe3 GL	266
	267	/* setup DSI link */
	268
	269	/*
	270	* Default = ULPS enable \|
	271	* Contention detection enabled \|
	272	* EoT packet transmission enable \|
	273	* CRC check enable \|
	274	* ECC check enable
	275	* additionally enable first two lanes
	276	*/
26c3d7ac KM	277	bitmap_fill((unsigned long *)&tmp, pdata->lane);
	278	tmp \|= 0x00003700;
	279	iowrite32(tmp, base + SYSCONF);
	280
9fd04fe3 GL	281	/*
	282	* T_wakeup = 0x7000
	283	* T_hs-trail = 3
	284	* T_hs-prepare = 3
	285	* T_clk-trail = 3
	286	* T_clk-prepare = 2
	287	*/
71b146c8	288	iowrite32(0x70003332, base + TIMSET);
9fd04fe3	289	/* no responses requested */
71b146c8	290	iowrite32(0x00000000, base + RESREQSET0);
9fd04fe3	291	/* request response to packets of type 0x28 */
71b146c8	292	iowrite32(0x00000100, base + RESREQSET1);
9fd04fe3	293	/* High-speed transmission timeout, default 0xffffffff */
71b146c8	294	iowrite32(0x0fffffff, base + HSTTOVSET);
9fd04fe3	295	/* LP reception timeout, default 0xffffffff */
71b146c8	296	iowrite32(0x0fffffff, base + LPRTOVSET);
9fd04fe3	297	/* Turn-around timeout, default 0xffffffff */
71b146c8	298	iowrite32(0x0fffffff, base + TATOVSET);
9fd04fe3	299	/* Peripheral reset timeout, default 0xffffffff */
71b146c8	300	iowrite32(0x0fffffff, base + PRTOVSET);
9fd04fe3	301	/* Enable timeout counters */
71b146c8	302	iowrite32(0x00000f00, base + DSICTRL);
9fd04fe3 GL	303	/* Interrupts not used, disable all */
	304	iowrite32(0, base + DSIINTE);
	305	/* DSI-Tx bias on */
71b146c8	306	iowrite32(0x00000001, base + PHYCTRL);
9fd04fe3 GL	307	udelay(200);
9fd04fe3 GL	308	/* Deassert resets, power on, set multiplier */
71b146c8	309	iowrite32(0x03070b01, base + PHYCTRL);
9fd04fe3 GL	310
	311	/* setup l-bridge */
	312
	313	/*
	314	* Enable transmission of all packets,
	315	* transmit LPS after each HS packet completion
	316	*/
deaba190	317	iowrite32(0x00000006, mipi->linkbase + DTCTR);
9fd04fe3	318	/* VSYNC width = 2 (<< 17) */
14bbb7c6 GL	319	iowrite32((ch->lcd_cfg[0].vsync_len << pdata->vsynw_offset) \|
14bbb7c6 GL	320	(pdata->clksrc << 16) \| (pctype << 12) \| datatype,
deaba190	321	mipi->linkbase + VMCTR1);
14bbb7c6	322
9fd04fe3 GL	323	/*
	324	* Non-burst mode with sync pulses: VSE and HSE are output,
	325	* HSA period allowed, no commands in LP
	326	*/
d07a9d2a KM	327	if (pdata->flags & SH_MIPI_DSI_BL2E)
d07a9d2a KM	328	vmctr2 \|= 1 << 17;
14bbb7c6	329	if (pdata->flags & SH_MIPI_DSI_HSABM)
3c2a6599	330	vmctr2 \|= 1 << 5;
32ba95c6	331	if (pdata->flags & SH_MIPI_DSI_HBPBM)
3c2a6599	332	vmctr2 \|= 1 << 4;
f7b0af68 KM	333	if (pdata->flags & SH_MIPI_DSI_HFPBM)
f7b0af68 KM	334	vmctr2 \|= 1 << 3;
14bbb7c6 GL	335	iowrite32(vmctr2, mipi->linkbase + VMCTR2);
14bbb7c6 GL	336
9fd04fe3 GL	337	/*
9fd04fe3 GL	338	* 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
44432407	339	* sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
14bbb7c6	340	* (unused if VMCTR2[HSABM] = 0)
9fd04fe3	341	*/
deaba190	342	iowrite32(1 \| (linelength << 16), mipi->linkbase + VMLEN1);
9fd04fe3 GL	343
	344	msleep(5);
	345
	346	/* setup LCD panel */
	347
	348	/* cf. drivers/video/omap/lcd_mipid.c */
	349	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	350	msleep(120);
	351	/*
	352	* [7] - Page Address Mode
	353	* [6] - Column Address Mode
	354	* [5] - Page / Column Address Mode
	355	* [4] - Display Device Line Refresh Order
	356	* [3] - RGB/BGR Order
	357	* [2] - Display Data Latch Data Order
	358	* [1] - Flip Horizontal
	359	* [0] - Flip Vertical
	360	*/
	361	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	362	/* cf. set_data_lines() */
	363	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
	364	pixfmt << 4);
	365	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
	366
	367	return 0;
	368	}
	369
	370	static int __init sh_mipi_probe(struct platform_device *pdev)
	371	{
	372	struct sh_mipi *mipi;
	373	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	374	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	375	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	376	unsigned long rate, f_current;
9fd04fe3 GL	377	int idx = pdev->id, ret;
9fd04fe3	378
deaba190	379	if (!res \|\| !res2 \|\| idx >= ARRAY_SIZE(mipi_dsi) \|\| !pdata)
9fd04fe3 GL	380	return -ENODEV;
	381
	382	mutex_lock(&array_lock);
	383	if (idx < 0)
	384	for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
	385	;
	386
	387	if (idx == ARRAY_SIZE(mipi_dsi)) {
	388	ret = -EBUSY;
	389	goto efindslot;
	390	}
	391
	392	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	393	if (!mipi) {
	394	ret = -ENOMEM;
	395	goto ealloc;
	396	}
	397
	398	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	399	dev_err(&pdev->dev, "MIPI register region already claimed\n");
	400	ret = -EBUSY;
	401	goto ereqreg;
	402	}
	403
	404	mipi->base = ioremap(res->start, resource_size(res));
	405	if (!mipi->base) {
	406	ret = -ENOMEM;
	407	goto emap;
	408	}
	409
deaba190 MD	410	if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
	411	dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
	412	ret = -EBUSY;
	413	goto ereqreg2;
	414	}
	415
	416	mipi->linkbase = ioremap(res2->start, resource_size(res2));
	417	if (!mipi->linkbase) {
	418	ret = -ENOMEM;
	419	goto emap2;
	420	}
	421
236782a5 GL	422	mipi->dev = &pdev->dev;
236782a5 GL	423
9fd04fe3 GL	424	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	425	if (IS_ERR(mipi->dsit_clk)) {
	426	ret = PTR_ERR(mipi->dsit_clk);
	427	goto eclktget;
	428	}
	429
	430	f_current = clk_get_rate(mipi->dsit_clk);
	431	/* 80MHz required by the datasheet */
	432	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	433	if (rate > 0 && rate != f_current)
	434	ret = clk_set_rate(mipi->dsit_clk, rate);
	435	else
	436	ret = rate;
	437	if (ret < 0)
	438	goto esettrate;
	439
	440	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
	441
9250741e	442	mipi->dsip_clk = clk_get(&pdev->dev, "dsip_clk");
9fd04fe3 GL	443	if (IS_ERR(mipi->dsip_clk)) {
	444	ret = PTR_ERR(mipi->dsip_clk);
	445	goto eclkpget;
	446	}
	447
	448	f_current = clk_get_rate(mipi->dsip_clk);
	449	/* Between 10 and 50MHz */
	450	rate = clk_round_rate(mipi->dsip_clk, 24000000);
	451	if (rate > 0 && rate != f_current)
	452	ret = clk_set_rate(mipi->dsip_clk, rate);
	453	else
	454	ret = rate;
	455	if (ret < 0)
	456	goto esetprate;
	457
	458	dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);
	459
	460	msleep(10);
	461
	462	ret = clk_enable(mipi->dsit_clk);
	463	if (ret < 0)
	464	goto eclkton;
	465
	466	ret = clk_enable(mipi->dsip_clk);
	467	if (ret < 0)
	468	goto eclkpon;
	469
	470	mipi_dsi[idx] = mipi;
	471
236782a5 GL	472	pm_runtime_enable(&pdev->dev);
	473	pm_runtime_resume(&pdev->dev);
	474
9fd04fe3 GL	475	ret = sh_mipi_setup(mipi, pdata);
	476	if (ret < 0)
	477	goto emipisetup;
	478
	479	mutex_unlock(&array_lock);
	480	platform_set_drvdata(pdev, mipi);
	481
6722a401 MD	482	/* Save original LCDC callbacks */
	483	mipi->next_board_data = pdata->lcd_chan->board_cfg.board_data;
	484	mipi->next_display_on = pdata->lcd_chan->board_cfg.display_on;
	485	mipi->next_display_off = pdata->lcd_chan->board_cfg.display_off;
	486
9fd04fe3 GL	487	/* Set up LCDC callbacks */
	488	pdata->lcd_chan->board_cfg.board_data = mipi;
	489	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	490	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
236782a5	491	pdata->lcd_chan->board_cfg.owner = THIS_MODULE;
9fd04fe3 GL	492
	493	return 0;
	494
	495	emipisetup:
	496	mipi_dsi[idx] = NULL;
236782a5	497	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	498	clk_disable(mipi->dsip_clk);
	499	eclkpon:
	500	clk_disable(mipi->dsit_clk);
	501	eclkton:
	502	esetprate:
	503	clk_put(mipi->dsip_clk);
	504	eclkpget:
	505	esettrate:
	506	clk_put(mipi->dsit_clk);
	507	eclktget:
deaba190 MD	508	iounmap(mipi->linkbase);
	509	emap2:
	510	release_mem_region(res2->start, resource_size(res2));
	511	ereqreg2:
9fd04fe3 GL	512	iounmap(mipi->base);
	513	emap:
	514	release_mem_region(res->start, resource_size(res));
	515	ereqreg:
	516	kfree(mipi);
	517	ealloc:
	518	efindslot:
	519	mutex_unlock(&array_lock);
	520
	521	return ret;
	522	}
	523
	524	static int __exit sh_mipi_remove(struct platform_device *pdev)
	525	{
	526	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	527	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
deaba190	528	struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
9fd04fe3 GL	529	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	530	int i, ret;
	531
	532	mutex_lock(&array_lock);
	533
	534	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
	535	;
	536
	537	if (i == ARRAY_SIZE(mipi_dsi)) {
	538	ret = -EINVAL;
	539	} else {
	540	ret = 0;
	541	mipi_dsi[i] = NULL;
	542	}
	543
	544	mutex_unlock(&array_lock);
	545
	546	if (ret < 0)
	547	return ret;
	548
236782a5	549	pdata->lcd_chan->board_cfg.owner = NULL;
9fd04fe3 GL	550	pdata->lcd_chan->board_cfg.display_on = NULL;
	551	pdata->lcd_chan->board_cfg.display_off = NULL;
	552	pdata->lcd_chan->board_cfg.board_data = NULL;
	553
236782a5	554	pm_runtime_disable(&pdev->dev);
9fd04fe3 GL	555	clk_disable(mipi->dsip_clk);
	556	clk_disable(mipi->dsit_clk);
	557	clk_put(mipi->dsit_clk);
	558	clk_put(mipi->dsip_clk);
deaba190 MD	559	iounmap(mipi->linkbase);
	560	if (res2)
	561	release_mem_region(res2->start, resource_size(res2));
9fd04fe3 GL	562	iounmap(mipi->base);
	563	if (res)
	564	release_mem_region(res->start, resource_size(res));
	565	platform_set_drvdata(pdev, NULL);
	566	kfree(mipi);
	567
	568	return 0;
	569	}
	570
	571	static struct platform_driver sh_mipi_driver = {
	572	.remove = __exit_p(sh_mipi_remove),
	573	.shutdown = sh_mipi_shutdown,
	574	.driver = {
	575	.name = "sh-mipi-dsi",
	576	},
	577	};
	578
	579	static int __init sh_mipi_init(void)
	580	{
	581	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
	582	}
	583	module_init(sh_mipi_init);
	584
	585	static void __exit sh_mipi_exit(void)
	586	{
	587	platform_driver_unregister(&sh_mipi_driver);
	588	}
	589	module_exit(sh_mipi_exit);
	590
	591	MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
	592	MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
	593	MODULE_LICENSE("GPL v2");