[deliverable/linux.git] / drivers / video / sh_mipi_dsi.c

/*
 * Renesas SH-mobile MIPI DSI support
 *
 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
 *
 * This is free software; you can redistribute it and/or modify
 * it under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/types.h>

#include <video/mipi_display.h>
#include <video/sh_mipi_dsi.h>
#include <video/sh_mobile_lcdc.h>

#define SYSCTRL		0x0000
#define SYSCONF		0x0004
#define TIMSET		0x0008
#define RESREQSET0	0x0018
#define RESREQSET1	0x001c
#define HSTTOVSET	0x0020
#define LPRTOVSET	0x0024
#define TATOVSET	0x0028
#define PRTOVSET	0x002c
#define DSICTRL		0x0030
#define DSIINTE		0x0060
#define PHYCTRL		0x0070

#define DTCTR		0x8000
#define VMCTR1		0x8020
#define VMCTR2		0x8024
#define VMLEN1		0x8028
#define CMTSRTREQ	0x8070
#define CMTSRTCTR	0x80d0


/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
#define MAX_SH_MIPI_DSI 2

struct sh_mipi {
	void __iomem	*base;
	struct clk	*dsit_clk;
	struct clk	*dsip_clk;
};

static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];

/* Protect the above array */
static DEFINE_MUTEX(array_lock);

static struct sh_mipi *sh_mipi_by_handle(int handle)
{
	if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
		return NULL;

	return mipi_dsi[handle];
}

static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
			      u8 cmd, u8 param)
{
	u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
	int cnt = 100;

	/* transmit a short packet to LCD panel */
	iowrite32(1 | data, mipi->base + CMTSRTCTR);
	iowrite32(1, mipi->base + CMTSRTREQ);

	while ((ioread32(mipi->base + CMTSRTREQ) & 1) && --cnt)
		udelay(1);

	return cnt ? 0 : -ETIMEDOUT;
}

#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
				-EINVAL : (c) - 1)

static int sh_mipi_dcs(int handle, u8 cmd)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
}

static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
{
	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	if (!mipi)
		return -ENODEV;
	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
				  param);
}

static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
{
	/*
	 * enable LCDC data tx, transition to LPS after completion of each HS
	 * packet
	 */
	iowrite32(0x00000002 | enable, mipi->base + DTCTR);
}

static void sh_mipi_shutdown(struct platform_device *pdev)
{
	struct sh_mipi *mipi = platform_get_drvdata(pdev);

	sh_mipi_dsi_enable(mipi, false);
}

static void mipi_display_on(void *arg, struct fb_info *info)
{
	struct sh_mipi *mipi = arg;

	sh_mipi_dsi_enable(mipi, true);
}

static void mipi_display_off(void *arg)
{
	struct sh_mipi *mipi = arg;

	sh_mipi_dsi_enable(mipi, false);
}

static int __init sh_mipi_setup(struct sh_mipi *mipi,
				struct sh_mipi_dsi_info *pdata)
{
	void __iomem *base = mipi->base;
	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	u32 pctype, datatype, pixfmt;
	u32 linelength;
	bool yuv;

	/*
	 * Select data format. MIPI DSI is not hot-pluggable, so, we just use
	 * the default videomode. If this ever becomes a problem, We'll have to
	 * move this to mipi_display_on() above and use info->var.xres
	 */
	switch (pdata->data_format) {
	case MIPI_RGB888:
		pctype = 0;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB565:
		pctype = 1;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_RGB666_LP:
		pctype = 2;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_RGB666:
		pctype = 3;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_BGR888:
		pctype = 8;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR565:
		pctype = 9;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = false;
		break;
	case MIPI_BGR666_LP:
		pctype = 0xa;
		datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
		linelength = ch->lcd_cfg[0].xres * 3;
		yuv = false;
		break;
	case MIPI_BGR666:
		pctype = 0xb;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
		pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
		linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
		yuv = false;
		break;
	case MIPI_YUYV:
		pctype = 4;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_UYVY:
		pctype = 5;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
		pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
		linelength = ch->lcd_cfg[0].xres * 2;
		yuv = true;
		break;
	case MIPI_YUV420_L:
		pctype = 6;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
		yuv = true;
		break;
	case MIPI_YUV420:
		pctype = 7;
		datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
		pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
		/* Length of U/V line */
		linelength = (ch->lcd_cfg[0].xres + 1) / 2;
		yuv = true;
		break;
	default:
		return -EINVAL;
	}

	if ((yuv && ch->interface_type != YUV422) ||
	    (!yuv && ch->interface_type != RGB24))
		return -EINVAL;

	/* reset DSI link */
	iowrite32(0x00000001, base + SYSCTRL);
	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
	udelay(50);
	iowrite32(0x00000000, base + SYSCTRL);

	/* setup DSI link */

	/*
	 * Default = ULPS enable |
	 *	Contention detection enabled |
	 *	EoT packet transmission enable |
	 *	CRC check enable |
	 *	ECC check enable
	 * additionally enable first two lanes
	 */
	iowrite32(0x00003703, base + SYSCONF);
	/*
	 * T_wakeup = 0x7000
	 * T_hs-trail = 3
	 * T_hs-prepare = 3
	 * T_clk-trail = 3
	 * T_clk-prepare = 2
	 */
	iowrite32(0x70003332, base + TIMSET);
	/* no responses requested */
	iowrite32(0x00000000, base + RESREQSET0);
	/* request response to packets of type 0x28 */
	iowrite32(0x00000100, base + RESREQSET1);
	/* High-speed transmission timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + HSTTOVSET);
	/* LP reception timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + LPRTOVSET);
	/* Turn-around timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + TATOVSET);
	/* Peripheral reset timeout, default 0xffffffff */
	iowrite32(0x0fffffff, base + PRTOVSET);
	/* Enable timeout counters */
	iowrite32(0x00000f00, base + DSICTRL);
	/* Interrupts not used, disable all */
	iowrite32(0, base + DSIINTE);
	/* DSI-Tx bias on */
	iowrite32(0x00000001, base + PHYCTRL);
	udelay(200);
	/* Deassert resets, power on, set multiplier */
	iowrite32(0x03070b01, base + PHYCTRL);

	/* setup l-bridge */

	/*
	 * Enable transmission of all packets,
	 * transmit LPS after each HS packet completion
	 */
	iowrite32(0x00000006, base + DTCTR);
	/* VSYNC width = 2 (<< 17) */
	iowrite32(0x00040000 | (pctype << 12) | datatype, base + VMCTR1);
	/*
	 * Non-burst mode with sync pulses: VSE and HSE are output,
	 * HSA period allowed, no commands in LP
	 */
	iowrite32(0x00e00000, base + VMCTR2);
	/*
	 * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
	 * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
	 * (unused, since VMCTR2[HSABM] = 0)
	 */
	iowrite32(1 | (linelength << 16), base + VMLEN1);

	msleep(5);

	/* setup LCD panel */

	/* cf. drivers/video/omap/lcd_mipid.c */
	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	msleep(120);
	/*
	 * [7] - Page Address Mode
	 * [6] - Column Address Mode
	 * [5] - Page / Column Address Mode
	 * [4] - Display Device Line Refresh Order
	 * [3] - RGB/BGR Order
	 * [2] - Display Data Latch Data Order
	 * [1] - Flip Horizontal
	 * [0] - Flip Vertical
	 */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	/* cf. set_data_lines() */
	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
			  pixfmt << 4);
	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);

	return 0;
}

static int __init sh_mipi_probe(struct platform_device *pdev)
{
	struct sh_mipi *mipi;
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	unsigned long rate, f_current;
	int idx = pdev->id, ret;
	char dsip_clk[] = "dsi.p_clk";

	if (!res || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
		return -ENODEV;

	mutex_lock(&array_lock);
	if (idx < 0)
		for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
			;

	if (idx == ARRAY_SIZE(mipi_dsi)) {
		ret = -EBUSY;
		goto efindslot;
	}

	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	if (!mipi) {
		ret = -ENOMEM;
		goto ealloc;
	}

	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
		dev_err(&pdev->dev, "MIPI register region already claimed\n");
		ret = -EBUSY;
		goto ereqreg;
	}

	mipi->base = ioremap(res->start, resource_size(res));
	if (!mipi->base) {
		ret = -ENOMEM;
		goto emap;
	}

	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
	if (IS_ERR(mipi->dsit_clk)) {
		ret = PTR_ERR(mipi->dsit_clk);
		goto eclktget;
	}

	f_current = clk_get_rate(mipi->dsit_clk);
	/* 80MHz required by the datasheet */
	rate = clk_round_rate(mipi->dsit_clk, 80000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsit_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esettrate;

	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);

	sprintf(dsip_clk, "dsi%1.1dp_clk", idx);
	mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk);
	if (IS_ERR(mipi->dsip_clk)) {
		ret = PTR_ERR(mipi->dsip_clk);
		goto eclkpget;
	}

	f_current = clk_get_rate(mipi->dsip_clk);
	/* Between 10 and 50MHz */
	rate = clk_round_rate(mipi->dsip_clk, 24000000);
	if (rate > 0 && rate != f_current)
		ret = clk_set_rate(mipi->dsip_clk, rate);
	else
		ret = rate;
	if (ret < 0)
		goto esetprate;

	dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);

	msleep(10);

	ret = clk_enable(mipi->dsit_clk);
	if (ret < 0)
		goto eclkton;

	ret = clk_enable(mipi->dsip_clk);
	if (ret < 0)
		goto eclkpon;

	mipi_dsi[idx] = mipi;

	ret = sh_mipi_setup(mipi, pdata);
	if (ret < 0)
		goto emipisetup;

	mutex_unlock(&array_lock);
	platform_set_drvdata(pdev, mipi);

	/* Set up LCDC callbacks */
	pdata->lcd_chan->board_cfg.board_data = mipi;
	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;

	return 0;

emipisetup:
	mipi_dsi[idx] = NULL;
	clk_disable(mipi->dsip_clk);
eclkpon:
	clk_disable(mipi->dsit_clk);
eclkton:
esetprate:
	clk_put(mipi->dsip_clk);
eclkpget:
esettrate:
	clk_put(mipi->dsit_clk);
eclktget:
	iounmap(mipi->base);
emap:
	release_mem_region(res->start, resource_size(res));
ereqreg:
	kfree(mipi);
ealloc:
efindslot:
	mutex_unlock(&array_lock);

	return ret;
}

static int __exit sh_mipi_remove(struct platform_device *pdev)
{
	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	int i, ret;

	mutex_lock(&array_lock);

	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
		;

	if (i == ARRAY_SIZE(mipi_dsi)) {
		ret = -EINVAL;
	} else {
		ret = 0;
		mipi_dsi[i] = NULL;
	}

	mutex_unlock(&array_lock);

	if (ret < 0)
		return ret;

	pdata->lcd_chan->board_cfg.display_on = NULL;
	pdata->lcd_chan->board_cfg.display_off = NULL;
	pdata->lcd_chan->board_cfg.board_data = NULL;

	clk_disable(mipi->dsip_clk);
	clk_disable(mipi->dsit_clk);
	clk_put(mipi->dsit_clk);
	clk_put(mipi->dsip_clk);
	iounmap(mipi->base);
	if (res)
		release_mem_region(res->start, resource_size(res));
	platform_set_drvdata(pdev, NULL);
	kfree(mipi);

	return 0;
}

static struct platform_driver sh_mipi_driver = {
	.remove		= __exit_p(sh_mipi_remove),
	.shutdown	= sh_mipi_shutdown,
	.driver = {
		.name	= "sh-mipi-dsi",
	},
};

static int __init sh_mipi_init(void)
{
	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
}
module_init(sh_mipi_init);

static void __exit sh_mipi_exit(void)
{
	platform_driver_unregister(&sh_mipi_driver);
}
module_exit(sh_mipi_exit);

MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
9fd04fe3 GL	1	/*
	2	* Renesas SH-mobile MIPI DSI support
	3	*
	4	* Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
	5	*
	6	* This is free software; you can redistribute it and/or modify
	7	* it under the terms of version 2 of the GNU General Public License as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/clk.h>
	12	#include <linux/delay.h>
	13	#include <linux/init.h>
	14	#include <linux/io.h>
	15	#include <linux/platform_device.h>
	16	#include <linux/slab.h>
	17	#include <linux/string.h>
	18	#include <linux/types.h>
	19
	20	#include <video/mipi_display.h>
	21	#include <video/sh_mipi_dsi.h>
	22	#include <video/sh_mobile_lcdc.h>
	23
71b146c8 MD	24	#define SYSCTRL 0x0000
	25	#define SYSCONF 0x0004
	26	#define TIMSET 0x0008
	27	#define RESREQSET0 0x0018
	28	#define RESREQSET1 0x001c
	29	#define HSTTOVSET 0x0020
	30	#define LPRTOVSET 0x0024
	31	#define TATOVSET 0x0028
	32	#define PRTOVSET 0x002c
	33	#define DSICTRL 0x0030
	34	#define DSIINTE 0x0060
	35	#define PHYCTRL 0x0070
	36
	37	#define DTCTR 0x8000
	38	#define VMCTR1 0x8020
	39	#define VMCTR2 0x8024
	40	#define VMLEN1 0x8028
9fd04fe3	41	#define CMTSRTREQ 0x8070
71b146c8	42	#define CMTSRTCTR 0x80d0
9fd04fe3	43
9fd04fe3 GL	44
	45	/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
	46	#define MAX_SH_MIPI_DSI 2
	47
	48	struct sh_mipi {
	49	void __iomem *base;
	50	struct clk *dsit_clk;
	51	struct clk *dsip_clk;
	52	};
	53
	54	static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
	55
	56	/* Protect the above array */
	57	static DEFINE_MUTEX(array_lock);
	58
	59	static struct sh_mipi *sh_mipi_by_handle(int handle)
	60	{
	61	if (handle >= ARRAY_SIZE(mipi_dsi) \|\| handle < 0)
	62	return NULL;
	63
	64	return mipi_dsi[handle];
	65	}
	66
	67	static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
	68	u8 cmd, u8 param)
	69	{
	70	u32 data = (dsi_cmd << 24) \| (cmd << 16) \| (param << 8);
	71	int cnt = 100;
	72
	73	/* transmit a short packet to LCD panel */
71b146c8 MD	74	iowrite32(1 \| data, mipi->base + CMTSRTCTR);
71b146c8 MD	75	iowrite32(1, mipi->base + CMTSRTREQ);
9fd04fe3	76
71b146c8	77	while ((ioread32(mipi->base + CMTSRTREQ) & 1) && --cnt)
9fd04fe3 GL	78	udelay(1);
	79
	80	return cnt ? 0 : -ETIMEDOUT;
	81	}
	82
	83	#define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD \|\| (c) > LCDC_CHAN_SUBLCD ? \
	84	-EINVAL : (c) - 1)
	85
	86	static int sh_mipi_dcs(int handle, u8 cmd)
	87	{
	88	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	89	if (!mipi)
	90	return -ENODEV;
	91	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
	92	}
	93
	94	static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
	95	{
	96	struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
	97	if (!mipi)
	98	return -ENODEV;
	99	return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
	100	param);
	101	}
	102
	103	static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
	104	{
	105	/*
	106	* enable LCDC data tx, transition to LPS after completion of each HS
	107	* packet
	108	*/
71b146c8	109	iowrite32(0x00000002 \| enable, mipi->base + DTCTR);
9fd04fe3 GL	110	}
	111
	112	static void sh_mipi_shutdown(struct platform_device *pdev)
	113	{
	114	struct sh_mipi *mipi = platform_get_drvdata(pdev);
	115
	116	sh_mipi_dsi_enable(mipi, false);
	117	}
	118
c2439398	119	static void mipi_display_on(void arg, struct fb_info info)
9fd04fe3 GL	120	{
	121	struct sh_mipi *mipi = arg;
	122
	123	sh_mipi_dsi_enable(mipi, true);
	124	}
	125
	126	static void mipi_display_off(void *arg)
	127	{
	128	struct sh_mipi *mipi = arg;
	129
	130	sh_mipi_dsi_enable(mipi, false);
	131	}
	132
	133	static int __init sh_mipi_setup(struct sh_mipi *mipi,
	134	struct sh_mipi_dsi_info *pdata)
	135	{
	136	void __iomem *base = mipi->base;
	137	struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
	138	u32 pctype, datatype, pixfmt;
	139	u32 linelength;
	140	bool yuv;
	141
44432407 GL	142	/*
	143	* Select data format. MIPI DSI is not hot-pluggable, so, we just use
	144	* the default videomode. If this ever becomes a problem, We'll have to
	145	* move this to mipi_display_on() above and use info->var.xres
	146	*/
9fd04fe3 GL	147	switch (pdata->data_format) {
	148	case MIPI_RGB888:
	149	pctype = 0;
	150	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	151	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	152	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	153	yuv = false;
	154	break;
	155	case MIPI_RGB565:
	156	pctype = 1;
	157	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	158	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	159	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	160	yuv = false;
	161	break;
	162	case MIPI_RGB666_LP:
	163	pctype = 2;
	164	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	165	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	166	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	167	yuv = false;
	168	break;
	169	case MIPI_RGB666:
	170	pctype = 3;
	171	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	172	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	173	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	174	yuv = false;
	175	break;
	176	case MIPI_BGR888:
	177	pctype = 8;
	178	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
	179	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	180	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	181	yuv = false;
	182	break;
	183	case MIPI_BGR565:
	184	pctype = 9;
	185	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
	186	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	187	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	188	yuv = false;
	189	break;
	190	case MIPI_BGR666_LP:
	191	pctype = 0xa;
	192	datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
	193	pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
44432407	194	linelength = ch->lcd_cfg[0].xres * 3;
9fd04fe3 GL	195	yuv = false;
	196	break;
	197	case MIPI_BGR666:
	198	pctype = 0xb;
	199	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
	200	pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
44432407	201	linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
9fd04fe3 GL	202	yuv = false;
	203	break;
	204	case MIPI_YUYV:
	205	pctype = 4;
	206	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	207	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	208	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	209	yuv = true;
	210	break;
	211	case MIPI_UYVY:
	212	pctype = 5;
	213	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
	214	pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
44432407	215	linelength = ch->lcd_cfg[0].xres * 2;
9fd04fe3 GL	216	yuv = true;
	217	break;
	218	case MIPI_YUV420_L:
	219	pctype = 6;
	220	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	221	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
44432407	222	linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
9fd04fe3 GL	223	yuv = true;
	224	break;
	225	case MIPI_YUV420:
	226	pctype = 7;
	227	datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
	228	pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
	229	/* Length of U/V line */
44432407	230	linelength = (ch->lcd_cfg[0].xres + 1) / 2;
9fd04fe3 GL	231	yuv = true;
	232	break;
	233	default:
	234	return -EINVAL;
	235	}
	236
	237	if ((yuv && ch->interface_type != YUV422) \|\|
	238	(!yuv && ch->interface_type != RGB24))
	239	return -EINVAL;
	240
	241	/* reset DSI link */
71b146c8	242	iowrite32(0x00000001, base + SYSCTRL);
9fd04fe3 GL	243	/* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
9fd04fe3 GL	244	udelay(50);
71b146c8	245	iowrite32(0x00000000, base + SYSCTRL);
9fd04fe3 GL	246
	247	/* setup DSI link */
	248
	249	/*
	250	* Default = ULPS enable \|
	251	* Contention detection enabled \|
	252	* EoT packet transmission enable \|
	253	* CRC check enable \|
	254	* ECC check enable
	255	* additionally enable first two lanes
	256	*/
71b146c8	257	iowrite32(0x00003703, base + SYSCONF);
9fd04fe3 GL	258	/*
	259	* T_wakeup = 0x7000
	260	* T_hs-trail = 3
	261	* T_hs-prepare = 3
	262	* T_clk-trail = 3
	263	* T_clk-prepare = 2
	264	*/
71b146c8	265	iowrite32(0x70003332, base + TIMSET);
9fd04fe3	266	/* no responses requested */
71b146c8	267	iowrite32(0x00000000, base + RESREQSET0);
9fd04fe3	268	/* request response to packets of type 0x28 */
71b146c8	269	iowrite32(0x00000100, base + RESREQSET1);
9fd04fe3	270	/* High-speed transmission timeout, default 0xffffffff */
71b146c8	271	iowrite32(0x0fffffff, base + HSTTOVSET);
9fd04fe3	272	/* LP reception timeout, default 0xffffffff */
71b146c8	273	iowrite32(0x0fffffff, base + LPRTOVSET);
9fd04fe3	274	/* Turn-around timeout, default 0xffffffff */
71b146c8	275	iowrite32(0x0fffffff, base + TATOVSET);
9fd04fe3	276	/* Peripheral reset timeout, default 0xffffffff */
71b146c8	277	iowrite32(0x0fffffff, base + PRTOVSET);
9fd04fe3	278	/* Enable timeout counters */
71b146c8	279	iowrite32(0x00000f00, base + DSICTRL);
9fd04fe3 GL	280	/* Interrupts not used, disable all */
	281	iowrite32(0, base + DSIINTE);
	282	/* DSI-Tx bias on */
71b146c8	283	iowrite32(0x00000001, base + PHYCTRL);
9fd04fe3 GL	284	udelay(200);
9fd04fe3 GL	285	/* Deassert resets, power on, set multiplier */
71b146c8	286	iowrite32(0x03070b01, base + PHYCTRL);
9fd04fe3 GL	287
	288	/* setup l-bridge */
	289
	290	/*
	291	* Enable transmission of all packets,
	292	* transmit LPS after each HS packet completion
	293	*/
71b146c8	294	iowrite32(0x00000006, base + DTCTR);
9fd04fe3	295	/* VSYNC width = 2 (<< 17) */
71b146c8	296	iowrite32(0x00040000 \| (pctype << 12) \| datatype, base + VMCTR1);
9fd04fe3 GL	297	/*
	298	* Non-burst mode with sync pulses: VSE and HSE are output,
	299	* HSA period allowed, no commands in LP
	300	*/
71b146c8	301	iowrite32(0x00e00000, base + VMCTR2);
9fd04fe3 GL	302	/*
9fd04fe3 GL	303	* 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
44432407	304	* sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
9fd04fe3 GL	305	* (unused, since VMCTR2[HSABM] = 0)
9fd04fe3 GL	306	*/
71b146c8	307	iowrite32(1 \| (linelength << 16), base + VMLEN1);
9fd04fe3 GL	308
	309	msleep(5);
	310
	311	/* setup LCD panel */
	312
	313	/* cf. drivers/video/omap/lcd_mipid.c */
	314	sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
	315	msleep(120);
	316	/*
	317	* [7] - Page Address Mode
	318	* [6] - Column Address Mode
	319	* [5] - Page / Column Address Mode
	320	* [4] - Display Device Line Refresh Order
	321	* [3] - RGB/BGR Order
	322	* [2] - Display Data Latch Data Order
	323	* [1] - Flip Horizontal
	324	* [0] - Flip Vertical
	325	*/
	326	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
	327	/* cf. set_data_lines() */
	328	sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
	329	pixfmt << 4);
	330	sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
	331
	332	return 0;
	333	}
	334
	335	static int __init sh_mipi_probe(struct platform_device *pdev)
	336	{
	337	struct sh_mipi *mipi;
	338	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
	339	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	340	unsigned long rate, f_current;
	341	int idx = pdev->id, ret;
	342	char dsip_clk[] = "dsi.p_clk";
	343
	344	if (!res \|\| idx >= ARRAY_SIZE(mipi_dsi) \|\| !pdata)
	345	return -ENODEV;
	346
	347	mutex_lock(&array_lock);
	348	if (idx < 0)
	349	for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
	350	;
	351
	352	if (idx == ARRAY_SIZE(mipi_dsi)) {
	353	ret = -EBUSY;
	354	goto efindslot;
	355	}
	356
	357	mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
	358	if (!mipi) {
	359	ret = -ENOMEM;
	360	goto ealloc;
	361	}
	362
	363	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
	364	dev_err(&pdev->dev, "MIPI register region already claimed\n");
	365	ret = -EBUSY;
	366	goto ereqreg;
	367	}
	368
	369	mipi->base = ioremap(res->start, resource_size(res));
	370	if (!mipi->base) {
	371	ret = -ENOMEM;
372	goto emap;
373	}
374
375	mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
376	if (IS_ERR(mipi->dsit_clk)) {
377	ret = PTR_ERR(mipi->dsit_clk);
378	goto eclktget;
379	}
380
381	f_current = clk_get_rate(mipi->dsit_clk);
382	/* 80MHz required by the datasheet */
383	rate = clk_round_rate(mipi->dsit_clk, 80000000);
384	if (rate > 0 && rate != f_current)
385	ret = clk_set_rate(mipi->dsit_clk, rate);
386	else
387	ret = rate;
388	if (ret < 0)
389	goto esettrate;
390
391	dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
392
393	sprintf(dsip_clk, "dsi%1.1dp_clk", idx);
394	mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk);
395	if (IS_ERR(mipi->dsip_clk)) {
396	ret = PTR_ERR(mipi->dsip_clk);
397	goto eclkpget;
398	}
399
400	f_current = clk_get_rate(mipi->dsip_clk);
401	/* Between 10 and 50MHz */
402	rate = clk_round_rate(mipi->dsip_clk, 24000000);
403	if (rate > 0 && rate != f_current)
404	ret = clk_set_rate(mipi->dsip_clk, rate);
405	else
406	ret = rate;
407	if (ret < 0)
408	goto esetprate;
409
410	dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);
411
412	msleep(10);
413
414	ret = clk_enable(mipi->dsit_clk);
415	if (ret < 0)
416	goto eclkton;
417
418	ret = clk_enable(mipi->dsip_clk);
419	if (ret < 0)
420	goto eclkpon;
421
422	mipi_dsi[idx] = mipi;
423
424	ret = sh_mipi_setup(mipi, pdata);
425	if (ret < 0)
426	goto emipisetup;
427
428	mutex_unlock(&array_lock);
429	platform_set_drvdata(pdev, mipi);
430
431	/* Set up LCDC callbacks */
432	pdata->lcd_chan->board_cfg.board_data = mipi;
433	pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
434	pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
435
436	return 0;
437
438	emipisetup:
439	mipi_dsi[idx] = NULL;
440	clk_disable(mipi->dsip_clk);
441	eclkpon:
442	clk_disable(mipi->dsit_clk);
443	eclkton:
444	esetprate:
445	clk_put(mipi->dsip_clk);
446	eclkpget:
447	esettrate:
448	clk_put(mipi->dsit_clk);
449	eclktget:
450	iounmap(mipi->base);
451	emap:
452	release_mem_region(res->start, resource_size(res));
453	ereqreg:
454	kfree(mipi);
455	ealloc:
456	efindslot:
457	mutex_unlock(&array_lock);
458
459	return ret;
460	}
461
462	static int __exit sh_mipi_remove(struct platform_device *pdev)
463	{
464	struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
465	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
466	struct sh_mipi *mipi = platform_get_drvdata(pdev);
467	int i, ret;
468
469	mutex_lock(&array_lock);
470
471	for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
472	;
473
474	if (i == ARRAY_SIZE(mipi_dsi)) {
475	ret = -EINVAL;
476	} else {
477	ret = 0;
478	mipi_dsi[i] = NULL;
479	}
480
481	mutex_unlock(&array_lock);
482
483	if (ret < 0)
484	return ret;
485
486	pdata->lcd_chan->board_cfg.display_on = NULL;
487	pdata->lcd_chan->board_cfg.display_off = NULL;
488	pdata->lcd_chan->board_cfg.board_data = NULL;
489
490	clk_disable(mipi->dsip_clk);
491	clk_disable(mipi->dsit_clk);
492	clk_put(mipi->dsit_clk);
493	clk_put(mipi->dsip_clk);
494	iounmap(mipi->base);
495	if (res)
496	release_mem_region(res->start, resource_size(res));
497	platform_set_drvdata(pdev, NULL);
498	kfree(mipi);
499
500	return 0;
501	}
502
503	static struct platform_driver sh_mipi_driver = {
504	.remove = __exit_p(sh_mipi_remove),
505	.shutdown = sh_mipi_shutdown,
506	.driver = {
507	.name = "sh-mipi-dsi",
508	},
509	};
510
511	static int __init sh_mipi_init(void)
512	{
513	return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
514	}
515	module_init(sh_mipi_init);
516
517	static void __exit sh_mipi_exit(void)
518	{
519	platform_driver_unregister(&sh_mipi_driver);
520	}
521	module_exit(sh_mipi_exit);
522
523	MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
524	MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
525	MODULE_LICENSE("GPL v2");