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video: tidy up modedb formatting.
[deliverable/linux.git] / drivers / video / sh_mobile_hdmi.c
CommitLineData
6011bdea
GL		 1/*
2 * SH-Mobile High-Definition Multimedia Interface (HDMI) driver
3 * for SLISHDMI13T and SLIPHDMIT IP cores
4 *
5 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/clk.h>
13#include <linux/console.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/module.h>
20#include <linux/platform_device.h>
21#include <linux/pm_runtime.h>
22#include <linux/slab.h>
23#include <linux/types.h>
24#include <linux/workqueue.h>
1d6be338
KM		 25#include <sound/soc-dapm.h>
26#include <sound/initval.h>
6011bdea
GL		 27
28#include <video/sh_mobile_hdmi.h>
29#include <video/sh_mobile_lcdc.h>
30
6de9edd5
GL		 31#include "sh_mobile_lcdcfb.h"
32
6011bdea
GL		 33#define HDMI_SYSTEM_CTRL 0x00 /* System control */
34#define HDMI_L_R_DATA_SWAP_CTRL_RPKT 0x01 /* L/R data swap control,
35 bits 19..16 of 20-bit N for Audio Clock Regeneration packet */
36#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8 0x02 /* bits 15..8 of 20-bit N for Audio Clock Regeneration packet */
37#define HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0 0x03 /* bits 7..0 of 20-bit N for Audio Clock Regeneration packet */
38#define HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS 0x04 /* SPDIF audio sampling frequency,
39 bits 19..16 of Internal CTS */
40#define HDMI_INTERNAL_CTS_15_8 0x05 /* bits 15..8 of Internal CTS */
41#define HDMI_INTERNAL_CTS_7_0 0x06 /* bits 7..0 of Internal CTS */
42#define HDMI_EXTERNAL_CTS_19_16 0x07 /* External CTS */
43#define HDMI_EXTERNAL_CTS_15_8 0x08 /* External CTS */
44#define HDMI_EXTERNAL_CTS_7_0 0x09 /* External CTS */
45#define HDMI_AUDIO_SETTING_1 0x0A /* Audio setting.1 */
46#define HDMI_AUDIO_SETTING_2 0x0B /* Audio setting.2 */
47#define HDMI_I2S_AUDIO_SET 0x0C /* I2S audio setting */
48#define HDMI_DSD_AUDIO_SET 0x0D /* DSD audio setting */
49#define HDMI_DEBUG_MONITOR_1 0x0E /* Debug monitor.1 */
50#define HDMI_DEBUG_MONITOR_2 0x0F /* Debug monitor.2 */
51#define HDMI_I2S_INPUT_PIN_SWAP 0x10 /* I2S input pin swap */
52#define HDMI_AUDIO_STATUS_BITS_SETTING_1 0x11 /* Audio status bits setting.1 */
53#define HDMI_AUDIO_STATUS_BITS_SETTING_2 0x12 /* Audio status bits setting.2 */
54#define HDMI_CATEGORY_CODE 0x13 /* Category code */
55#define HDMI_SOURCE_NUM_AUDIO_WORD_LEN 0x14 /* Source number/Audio word length */
56#define HDMI_AUDIO_VIDEO_SETTING_1 0x15 /* Audio/Video setting.1 */
57#define HDMI_VIDEO_SETTING_1 0x16 /* Video setting.1 */
58#define HDMI_DEEP_COLOR_MODES 0x17 /* Deep Color Modes */
59
60/* 12 16- and 10-bit Color space conversion parameters: 0x18..0x2f */
61#define HDMI_COLOR_SPACE_CONVERSION_PARAMETERS 0x18
62
63#define HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS 0x30 /* External video parameter settings */
64#define HDMI_EXTERNAL_H_TOTAL_7_0 0x31 /* External horizontal total (LSB) */
65#define HDMI_EXTERNAL_H_TOTAL_11_8 0x32 /* External horizontal total (MSB) */
66#define HDMI_EXTERNAL_H_BLANK_7_0 0x33 /* External horizontal blank (LSB) */
67#define HDMI_EXTERNAL_H_BLANK_9_8 0x34 /* External horizontal blank (MSB) */
68#define HDMI_EXTERNAL_H_DELAY_7_0 0x35 /* External horizontal delay (LSB) */
69#define HDMI_EXTERNAL_H_DELAY_9_8 0x36 /* External horizontal delay (MSB) */
70#define HDMI_EXTERNAL_H_DURATION_7_0 0x37 /* External horizontal duration (LSB) */
71#define HDMI_EXTERNAL_H_DURATION_9_8 0x38 /* External horizontal duration (MSB) */
72#define HDMI_EXTERNAL_V_TOTAL_7_0 0x39 /* External vertical total (LSB) */
73#define HDMI_EXTERNAL_V_TOTAL_9_8 0x3A /* External vertical total (MSB) */
74#define HDMI_AUDIO_VIDEO_SETTING_2 0x3B /* Audio/Video setting.2 */
75#define HDMI_EXTERNAL_V_BLANK 0x3D /* External vertical blank */
76#define HDMI_EXTERNAL_V_DELAY 0x3E /* External vertical delay */
77#define HDMI_EXTERNAL_V_DURATION 0x3F /* External vertical duration */
78#define HDMI_CTRL_PKT_MANUAL_SEND_CONTROL 0x40 /* Control packet manual send control */
79#define HDMI_CTRL_PKT_AUTO_SEND 0x41 /* Control packet auto send with VSYNC control */
80#define HDMI_AUTO_CHECKSUM_OPTION 0x42 /* Auto checksum option */
81#define HDMI_VIDEO_SETTING_2 0x45 /* Video setting.2 */
82#define HDMI_OUTPUT_OPTION 0x46 /* Output option */
83#define HDMI_SLIPHDMIT_PARAM_OPTION 0x51 /* SLIPHDMIT parameter option */
84#define HDMI_HSYNC_PMENT_AT_EMB_7_0 0x52 /* HSYNC placement at embedded sync (LSB) */
85#define HDMI_HSYNC_PMENT_AT_EMB_15_8 0x53 /* HSYNC placement at embedded sync (MSB) */
86#define HDMI_VSYNC_PMENT_AT_EMB_7_0 0x54 /* VSYNC placement at embedded sync (LSB) */
87#define HDMI_VSYNC_PMENT_AT_EMB_14_8 0x55 /* VSYNC placement at embedded sync (MSB) */
88#define HDMI_SLIPHDMIT_PARAM_SETTINGS_1 0x56 /* SLIPHDMIT parameter settings.1 */
89#define HDMI_SLIPHDMIT_PARAM_SETTINGS_2 0x57 /* SLIPHDMIT parameter settings.2 */
90#define HDMI_SLIPHDMIT_PARAM_SETTINGS_3 0x58 /* SLIPHDMIT parameter settings.3 */
91#define HDMI_SLIPHDMIT_PARAM_SETTINGS_5 0x59 /* SLIPHDMIT parameter settings.5 */
92#define HDMI_SLIPHDMIT_PARAM_SETTINGS_6 0x5A /* SLIPHDMIT parameter settings.6 */
93#define HDMI_SLIPHDMIT_PARAM_SETTINGS_7 0x5B /* SLIPHDMIT parameter settings.7 */
94#define HDMI_SLIPHDMIT_PARAM_SETTINGS_8 0x5C /* SLIPHDMIT parameter settings.8 */
95#define HDMI_SLIPHDMIT_PARAM_SETTINGS_9 0x5D /* SLIPHDMIT parameter settings.9 */
96#define HDMI_SLIPHDMIT_PARAM_SETTINGS_10 0x5E /* SLIPHDMIT parameter settings.10 */
97#define HDMI_CTRL_PKT_BUF_INDEX 0x5F /* Control packet buffer index */
98#define HDMI_CTRL_PKT_BUF_ACCESS_HB0 0x60 /* Control packet data buffer access window - HB0 */
99#define HDMI_CTRL_PKT_BUF_ACCESS_HB1 0x61 /* Control packet data buffer access window - HB1 */
100#define HDMI_CTRL_PKT_BUF_ACCESS_HB2 0x62 /* Control packet data buffer access window - HB2 */
101#define HDMI_CTRL_PKT_BUF_ACCESS_PB0 0x63 /* Control packet data buffer access window - PB0 */
102#define HDMI_CTRL_PKT_BUF_ACCESS_PB1 0x64 /* Control packet data buffer access window - PB1 */
103#define HDMI_CTRL_PKT_BUF_ACCESS_PB2 0x65 /* Control packet data buffer access window - PB2 */
104#define HDMI_CTRL_PKT_BUF_ACCESS_PB3 0x66 /* Control packet data buffer access window - PB3 */
105#define HDMI_CTRL_PKT_BUF_ACCESS_PB4 0x67 /* Control packet data buffer access window - PB4 */
106#define HDMI_CTRL_PKT_BUF_ACCESS_PB5 0x68 /* Control packet data buffer access window - PB5 */
107#define HDMI_CTRL_PKT_BUF_ACCESS_PB6 0x69 /* Control packet data buffer access window - PB6 */
108#define HDMI_CTRL_PKT_BUF_ACCESS_PB7 0x6A /* Control packet data buffer access window - PB7 */
109#define HDMI_CTRL_PKT_BUF_ACCESS_PB8 0x6B /* Control packet data buffer access window - PB8 */
110#define HDMI_CTRL_PKT_BUF_ACCESS_PB9 0x6C /* Control packet data buffer access window - PB9 */
111#define HDMI_CTRL_PKT_BUF_ACCESS_PB10 0x6D /* Control packet data buffer access window - PB10 */
112#define HDMI_CTRL_PKT_BUF_ACCESS_PB11 0x6E /* Control packet data buffer access window - PB11 */
113#define HDMI_CTRL_PKT_BUF_ACCESS_PB12 0x6F /* Control packet data buffer access window - PB12 */
114#define HDMI_CTRL_PKT_BUF_ACCESS_PB13 0x70 /* Control packet data buffer access window - PB13 */
115#define HDMI_CTRL_PKT_BUF_ACCESS_PB14 0x71 /* Control packet data buffer access window - PB14 */
116#define HDMI_CTRL_PKT_BUF_ACCESS_PB15 0x72 /* Control packet data buffer access window - PB15 */
117#define HDMI_CTRL_PKT_BUF_ACCESS_PB16 0x73 /* Control packet data buffer access window - PB16 */
118#define HDMI_CTRL_PKT_BUF_ACCESS_PB17 0x74 /* Control packet data buffer access window - PB17 */
119#define HDMI_CTRL_PKT_BUF_ACCESS_PB18 0x75 /* Control packet data buffer access window - PB18 */
120#define HDMI_CTRL_PKT_BUF_ACCESS_PB19 0x76 /* Control packet data buffer access window - PB19 */
121#define HDMI_CTRL_PKT_BUF_ACCESS_PB20 0x77 /* Control packet data buffer access window - PB20 */
122#define HDMI_CTRL_PKT_BUF_ACCESS_PB21 0x78 /* Control packet data buffer access window - PB21 */
123#define HDMI_CTRL_PKT_BUF_ACCESS_PB22 0x79 /* Control packet data buffer access window - PB22 */
124#define HDMI_CTRL_PKT_BUF_ACCESS_PB23 0x7A /* Control packet data buffer access window - PB23 */
125#define HDMI_CTRL_PKT_BUF_ACCESS_PB24 0x7B /* Control packet data buffer access window - PB24 */
126#define HDMI_CTRL_PKT_BUF_ACCESS_PB25 0x7C /* Control packet data buffer access window - PB25 */
127#define HDMI_CTRL_PKT_BUF_ACCESS_PB26 0x7D /* Control packet data buffer access window - PB26 */
128#define HDMI_CTRL_PKT_BUF_ACCESS_PB27 0x7E /* Control packet data buffer access window - PB27 */
129#define HDMI_EDID_KSV_FIFO_ACCESS_WINDOW 0x80 /* EDID/KSV FIFO access window */
130#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_7_0 0x81 /* DDC bus access frequency control (LSB) */
131#define HDMI_DDC_BUS_ACCESS_FREQ_CTRL_15_8 0x82 /* DDC bus access frequency control (MSB) */
132#define HDMI_INTERRUPT_MASK_1 0x92 /* Interrupt mask.1 */
133#define HDMI_INTERRUPT_MASK_2 0x93 /* Interrupt mask.2 */
134#define HDMI_INTERRUPT_STATUS_1 0x94 /* Interrupt status.1 */
135#define HDMI_INTERRUPT_STATUS_2 0x95 /* Interrupt status.2 */
136#define HDMI_INTERRUPT_MASK_3 0x96 /* Interrupt mask.3 */
137#define HDMI_INTERRUPT_MASK_4 0x97 /* Interrupt mask.4 */
138#define HDMI_INTERRUPT_STATUS_3 0x98 /* Interrupt status.3 */
139#define HDMI_INTERRUPT_STATUS_4 0x99 /* Interrupt status.4 */
140#define HDMI_SOFTWARE_HDCP_CONTROL_1 0x9A /* Software HDCP control.1 */
141#define HDMI_FRAME_COUNTER 0x9C /* Frame counter */
142#define HDMI_FRAME_COUNTER_FOR_RI_CHECK 0x9D /* Frame counter for Ri check */
143#define HDMI_HDCP_CONTROL 0xAF /* HDCP control */
144#define HDMI_RI_FRAME_COUNT_REGISTER 0xB2 /* Ri frame count register */
145#define HDMI_DDC_BUS_CONTROL 0xB7 /* DDC bus control */
146#define HDMI_HDCP_STATUS 0xB8 /* HDCP status */
147#define HDMI_SHA0 0xB9 /* sha0 */
148#define HDMI_SHA1 0xBA /* sha1 */
149#define HDMI_SHA2 0xBB /* sha2 */
150#define HDMI_SHA3 0xBC /* sha3 */
151#define HDMI_SHA4 0xBD /* sha4 */
152#define HDMI_BCAPS_READ 0xBE /* BCAPS read / debug */
153#define HDMI_AKSV_BKSV_7_0_MONITOR 0xBF /* AKSV/BKSV[7:0] monitor */
154#define HDMI_AKSV_BKSV_15_8_MONITOR 0xC0 /* AKSV/BKSV[15:8] monitor */
155#define HDMI_AKSV_BKSV_23_16_MONITOR 0xC1 /* AKSV/BKSV[23:16] monitor */
156#define HDMI_AKSV_BKSV_31_24_MONITOR 0xC2 /* AKSV/BKSV[31:24] monitor */
157#define HDMI_AKSV_BKSV_39_32_MONITOR 0xC3 /* AKSV/BKSV[39:32] monitor */
158#define HDMI_EDID_SEGMENT_POINTER 0xC4 /* EDID segment pointer */
159#define HDMI_EDID_WORD_ADDRESS 0xC5 /* EDID word address */
160#define HDMI_EDID_DATA_FIFO_ADDRESS 0xC6 /* EDID data FIFO address */
161#define HDMI_NUM_OF_HDMI_DEVICES 0xC7 /* Number of HDMI devices */
162#define HDMI_HDCP_ERROR_CODE 0xC8 /* HDCP error code */
163#define HDMI_100MS_TIMER_SET 0xC9 /* 100ms timer setting */
164#define HDMI_5SEC_TIMER_SET 0xCA /* 5sec timer setting */
165#define HDMI_RI_READ_COUNT 0xCB /* Ri read count */
166#define HDMI_AN_SEED 0xCC /* An seed */
167#define HDMI_MAX_NUM_OF_RCIVRS_ALLOWED 0xCD /* Maximum number of receivers allowed */
168#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_1 0xCE /* HDCP memory access control.1 */
169#define HDMI_HDCP_MEMORY_ACCESS_CONTROL_2 0xCF /* HDCP memory access control.2 */
170#define HDMI_HDCP_CONTROL_2 0xD0 /* HDCP Control 2 */
171#define HDMI_HDCP_KEY_MEMORY_CONTROL 0xD2 /* HDCP Key Memory Control */
172#define HDMI_COLOR_SPACE_CONV_CONFIG_1 0xD3 /* Color space conversion configuration.1 */
173#define HDMI_VIDEO_SETTING_3 0xD4 /* Video setting.3 */
174#define HDMI_RI_7_0 0xD5 /* Ri[7:0] */
175#define HDMI_RI_15_8 0xD6 /* Ri[15:8] */
176#define HDMI_PJ 0xD7 /* Pj */
177#define HDMI_SHA_RD 0xD8 /* sha_rd */
178#define HDMI_RI_7_0_SAVED 0xD9 /* Ri[7:0] saved */
179#define HDMI_RI_15_8_SAVED 0xDA /* Ri[15:8] saved */
180#define HDMI_PJ_SAVED 0xDB /* Pj saved */
181#define HDMI_NUM_OF_DEVICES 0xDC /* Number of devices */
182#define HDMI_HOT_PLUG_MSENS_STATUS 0xDF /* Hot plug/MSENS status */
183#define HDMI_BCAPS_WRITE 0xE0 /* bcaps */
184#define HDMI_BSTAT_7_0 0xE1 /* bstat[7:0] */
185#define HDMI_BSTAT_15_8 0xE2 /* bstat[15:8] */
186#define HDMI_BKSV_7_0 0xE3 /* bksv[7:0] */
187#define HDMI_BKSV_15_8 0xE4 /* bksv[15:8] */
188#define HDMI_BKSV_23_16 0xE5 /* bksv[23:16] */
189#define HDMI_BKSV_31_24 0xE6 /* bksv[31:24] */
190#define HDMI_BKSV_39_32 0xE7 /* bksv[39:32] */
191#define HDMI_AN_7_0 0xE8 /* An[7:0] */
192#define HDMI_AN_15_8 0xE9 /* An [15:8] */
193#define HDMI_AN_23_16 0xEA /* An [23:16] */
194#define HDMI_AN_31_24 0xEB /* An [31:24] */
195#define HDMI_AN_39_32 0xEC /* An [39:32] */
196#define HDMI_AN_47_40 0xED /* An [47:40] */
197#define HDMI_AN_55_48 0xEE /* An [55:48] */
198#define HDMI_AN_63_56 0xEF /* An [63:56] */
199#define HDMI_PRODUCT_ID 0xF0 /* Product ID */
200#define HDMI_REVISION_ID 0xF1 /* Revision ID */
201#define HDMI_TEST_MODE 0xFE /* Test mode */
202
203enum hotplug_state {
204 HDMI_HOTPLUG_DISCONNECTED,
205 HDMI_HOTPLUG_CONNECTED,
206 HDMI_HOTPLUG_EDID_DONE,
207};
208
209struct sh_hdmi {
210 void __iomem *base;
6aa966e6 211 enum hotplug_state hp_state; /* hot-plug status */
0ea2af1c
GL		 212 u8 preprogrammed_vic; /* use a pre-programmed VIC or
213 the external mode */
4232f607
GL		 214 u8 edid_block_addr;
215 u8 edid_segment_nr;
216 u8 edid_blocks;
6011bdea
GL		 217 struct clk *hdmi_clk;
218 struct device *dev;
219 struct fb_info *info;
6de9edd5 220 struct mutex mutex; /* Protect the info pointer */
6011bdea
GL		 221 struct delayed_work edid_work;
222 struct fb_var_screeninfo var;
afe417c0 223 struct fb_monspecs monspec;
eb0778bd 224 struct notifier_block notifier;
6011bdea
GL		 225};
226
227static void hdmi_write(struct sh_hdmi *hdmi, u8 data, u8 reg)
228{
229 iowrite8(data, hdmi->base + reg);
230}
231
232static u8 hdmi_read(struct sh_hdmi *hdmi, u8 reg)
233{
234 return ioread8(hdmi->base + reg);
235}
236
f4363b7d
KM		 237/*
238 * HDMI sound
239 */
1d6be338
KM		 240static unsigned int sh_hdmi_snd_read(struct snd_soc_codec *codec,
241 unsigned int reg)
242{
243 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
244
245 return hdmi_read(hdmi, reg);
246}
247
248static int sh_hdmi_snd_write(struct snd_soc_codec *codec,
249 unsigned int reg,
250 unsigned int value)
251{
252 struct sh_hdmi *hdmi = snd_soc_codec_get_drvdata(codec);
253
254 hdmi_write(hdmi, value, reg);
255 return 0;
256}
257
258static struct snd_soc_dai_driver sh_hdmi_dai = {
259 .name = "sh_mobile_hdmi-hifi",
260 .playback = {
261 .stream_name = "Playback",
17731f8d
KM		 262 .channels_min = 2,
263 .channels_max = 8,
264 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
265 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
266 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
267 SNDRV_PCM_RATE_192000,
1d6be338
KM		 268 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE,
269 },
270};
271
272static int sh_hdmi_snd_probe(struct snd_soc_codec *codec)
273{
274 dev_info(codec->dev, "SH Mobile HDMI Audio Codec");
275
276 return 0;
277}
278
279static struct snd_soc_codec_driver soc_codec_dev_sh_hdmi = {
280 .probe = sh_hdmi_snd_probe,
281 .read = sh_hdmi_snd_read,
282 .write = sh_hdmi_snd_write,
283};
284
f4363b7d
KM		 285/*
286 * HDMI video
287 */
1d6be338 288
6011bdea 289/* External video parameter settings */
6aa966e6 290static void sh_hdmi_external_video_param(struct sh_hdmi *hdmi)
6011bdea
GL		 291{
292 struct fb_var_screeninfo *var = &hdmi->var;
293 u16 htotal, hblank, hdelay, vtotal, vblank, vdelay, voffset;
294 u8 sync = 0;
295
296 htotal = var->xres + var->right_margin + var->left_margin + var->hsync_len;
297
298 hdelay = var->hsync_len + var->left_margin;
299 hblank = var->right_margin + hdelay;
300
301 /*
302 * Vertical timing looks a bit different in Figure 18,
303 * but let's try the same first by setting offset = 0
304 */
305 vtotal = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
306
307 vdelay = var->vsync_len + var->upper_margin;
308 vblank = var->lower_margin + vdelay;
309 voffset = min(var->upper_margin / 2, 6U);
310
311 /*
312 * [3]: VSYNC polarity: Positive
313 * [2]: HSYNC polarity: Positive
314 * [1]: Interlace/Progressive: Progressive
315 * [0]: External video settings enable: used.
316 */
317 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
318 sync |= 4;
319 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
320 sync |= 8;
321
6aa966e6
GL		 322 dev_dbg(hdmi->dev, "H: %u, %u, %u, %u; V: %u, %u, %u, %u; sync 0x%x\n",
323 htotal, hblank, hdelay, var->hsync_len,
324 vtotal, vblank, vdelay, var->vsync_len, sync);
6011bdea
GL		 325
326 hdmi_write(hdmi, sync | (voffset << 4), HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
327
328 hdmi_write(hdmi, htotal, HDMI_EXTERNAL_H_TOTAL_7_0);
329 hdmi_write(hdmi, htotal >> 8, HDMI_EXTERNAL_H_TOTAL_11_8);
330
331 hdmi_write(hdmi, hblank, HDMI_EXTERNAL_H_BLANK_7_0);
332 hdmi_write(hdmi, hblank >> 8, HDMI_EXTERNAL_H_BLANK_9_8);
333
334 hdmi_write(hdmi, hdelay, HDMI_EXTERNAL_H_DELAY_7_0);
335 hdmi_write(hdmi, hdelay >> 8, HDMI_EXTERNAL_H_DELAY_9_8);
336
337 hdmi_write(hdmi, var->hsync_len, HDMI_EXTERNAL_H_DURATION_7_0);
338 hdmi_write(hdmi, var->hsync_len >> 8, HDMI_EXTERNAL_H_DURATION_9_8);
339
340 hdmi_write(hdmi, vtotal, HDMI_EXTERNAL_V_TOTAL_7_0);
341 hdmi_write(hdmi, vtotal >> 8, HDMI_EXTERNAL_V_TOTAL_9_8);
342
343 hdmi_write(hdmi, vblank, HDMI_EXTERNAL_V_BLANK);
344
345 hdmi_write(hdmi, vdelay, HDMI_EXTERNAL_V_DELAY);
346
347 hdmi_write(hdmi, var->vsync_len, HDMI_EXTERNAL_V_DURATION);
348
89712699 349 /* Set bit 0 of HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS here for external mode */
0ea2af1c 350 if (!hdmi->preprogrammed_vic)
89712699
GL		 351 hdmi_write(hdmi, sync | 1 | (voffset << 4),
352 HDMI_EXTERNAL_VIDEO_PARAM_SETTINGS);
6011bdea
GL		 353}
354
355/**
356 * sh_hdmi_video_config()
357 */
358static void sh_hdmi_video_config(struct sh_hdmi *hdmi)
359{
360 /*
361 * [7:4]: Audio sampling frequency: 48kHz
362 * [3:1]: Input video format: RGB and YCbCr 4:4:4 (Y on Green)
363 * [0]: Internal/External DE select: internal
364 */
365 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
366
367 /*
368 * [7:6]: Video output format: RGB 4:4:4
369 * [5:4]: Input video data width: 8 bit
370 * [3:1]: EAV/SAV location: channel 1
371 * [0]: Video input color space: RGB
372 */
373 hdmi_write(hdmi, 0x34, HDMI_VIDEO_SETTING_1);
374
375 /*
376 * [7:6]: Together with bit [6] of HDMI_AUDIO_VIDEO_SETTING_2, which is
377 * left at 0 by default, this configures 24bpp and sets the Color Depth
378 * (CD) field in the General Control Packet
379 */
380 hdmi_write(hdmi, 0x20, HDMI_DEEP_COLOR_MODES);
381}
382
383/**
384 * sh_hdmi_audio_config()
385 */
386static void sh_hdmi_audio_config(struct sh_hdmi *hdmi)
387{
6d865771
KM		 388 u8 data;
389 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
390
6011bdea
GL		 391 /*
392 * [7:4] L/R data swap control
393 * [3:0] appropriate N[19:16]
394 */
395 hdmi_write(hdmi, 0x00, HDMI_L_R_DATA_SWAP_CTRL_RPKT);
396 /* appropriate N[15:8] */
397 hdmi_write(hdmi, 0x18, HDMI_20_BIT_N_FOR_AUDIO_RPKT_15_8);
398 /* appropriate N[7:0] */
399 hdmi_write(hdmi, 0x00, HDMI_20_BIT_N_FOR_AUDIO_RPKT_7_0);
400
401 /* [7:4] 48 kHz SPDIF not used */
402 hdmi_write(hdmi, 0x20, HDMI_SPDIF_AUDIO_SAMP_FREQ_CTS);
403
404 /*
405 * [6:5] set required down sampling rate if required
406 * [4:3] set required audio source
407 */
dec6aa49 408 switch (pdata->flags & HDMI_SND_SRC_MASK) {
6d865771 409 default:
f4363b7d 410 /* fall through */
dec6aa49
KM		 411 case HDMI_SND_SRC_I2S:
412 data = 0x0 << 3;
6d865771 413 break;
dec6aa49
KM		 414 case HDMI_SND_SRC_SPDIF:
415 data = 0x1 << 3;
6d865771 416 break;
dec6aa49
KM		 417 case HDMI_SND_SRC_DSD:
418 data = 0x2 << 3;
6d865771 419 break;
dec6aa49
KM		 420 case HDMI_SND_SRC_HBR:
421 data = 0x3 << 3;
6d865771
KM		 422 break;
423 }
424 hdmi_write(hdmi, data, HDMI_AUDIO_SETTING_1);
6011bdea
GL		 425
426 /* [3:0] set sending channel number for channel status */
427 hdmi_write(hdmi, 0x40, HDMI_AUDIO_SETTING_2);
428
429 /*
430 * [5:2] set valid I2S source input pin
431 * [1:0] set input I2S source mode
432 */
433 hdmi_write(hdmi, 0x04, HDMI_I2S_AUDIO_SET);
434
435 /* [7:4] set valid DSD source input pin */
436 hdmi_write(hdmi, 0x00, HDMI_DSD_AUDIO_SET);
437
438 /* [7:0] set appropriate I2S input pin swap settings if required */
439 hdmi_write(hdmi, 0x00, HDMI_I2S_INPUT_PIN_SWAP);
440
441 /*
442 * [7] set validity bit for channel status
443 * [3:0] set original sample frequency for channel status
444 */
445 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_1);
446
447 /*
448 * [7] set value for channel status
449 * [6] set value for channel status
450 * [5] set copyright bit for channel status
451 * [4:2] set additional information for channel status
452 * [1:0] set clock accuracy for channel status
453 */
454 hdmi_write(hdmi, 0x00, HDMI_AUDIO_STATUS_BITS_SETTING_2);
455
456 /* [7:0] set category code for channel status */
457 hdmi_write(hdmi, 0x00, HDMI_CATEGORY_CODE);
458
459 /*
460 * [7:4] set source number for channel status
461 * [3:0] set word length for channel status
462 */
463 hdmi_write(hdmi, 0x00, HDMI_SOURCE_NUM_AUDIO_WORD_LEN);
464
465 /* [7:4] set sample frequency for channel status */
466 hdmi_write(hdmi, 0x20, HDMI_AUDIO_VIDEO_SETTING_1);
467}
468
469/**
6e45746c 470 * sh_hdmi_phy_config() - configure the HDMI PHY for the used video mode
6011bdea
GL		 471 */
472static void sh_hdmi_phy_config(struct sh_hdmi *hdmi)
473{
0ea2af1c
GL		 474 if (hdmi->var.pixclock < 10000) {
475 /* for 1080p8bit 148MHz */
476 hdmi_write(hdmi, 0x1d, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
477 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
478 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
479 hdmi_write(hdmi, 0x4c, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
480 hdmi_write(hdmi, 0x1e, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
481 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
482 hdmi_write(hdmi, 0x0e, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
483 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
484 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
485 } else if (hdmi->var.pixclock < 30000) {
6e45746c
GL		 486 /* 720p, 8bit, 74.25MHz. Might need to be adjusted for other formats */
487 /*
488 * [1:0] Speed_A
489 * [3:2] Speed_B
490 * [4] PLLA_Bypass
491 * [6] DRV_TEST_EN
492 * [7] DRV_TEST_IN
493 */
9289c475 494 hdmi_write(hdmi, 0x0f, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
6e45746c
GL		 495 /* PLLB_CONFIG[17], PLLA_CONFIG[17] - not in PHY datasheet */
496 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
497 /*
498 * [2:0] BGR_I_OFFSET
499 * [6:4] BGR_V_OFFSET
500 */
501 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
502 /* PLLA_CONFIG[7:0]: VCO gain, VCO offset, LPF resistance[0] */
503 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
504 /*
505 * PLLA_CONFIG[15:8]: regulator voltage[0], CP current,
506 * LPF capacitance, LPF resistance[1]
507 */
508 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
509 /* PLLB_CONFIG[7:0]: LPF resistance[0], VCO offset, VCO gain */
510 hdmi_write(hdmi, 0x4A, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
511 /*
512 * PLLB_CONFIG[15:8]: regulator voltage[0], CP current,
513 * LPF capacitance, LPF resistance[1]
514 */
9289c475 515 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
6e45746c
GL		 516 /* DRV_CONFIG, PE_CONFIG */
517 hdmi_write(hdmi, 0x25, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
518 /*
519 * [2:0] AMON_SEL (4 == LPF voltage)
520 * [4] PLLA_CONFIG[16]
521 * [5] PLLB_CONFIG[16]
522 */
523 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
524 } else {
525 /* for 480p8bit 27MHz */
526 hdmi_write(hdmi, 0x19, HDMI_SLIPHDMIT_PARAM_SETTINGS_1);
527 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_2);
528 hdmi_write(hdmi, 0x00, HDMI_SLIPHDMIT_PARAM_SETTINGS_3);
529 hdmi_write(hdmi, 0x44, HDMI_SLIPHDMIT_PARAM_SETTINGS_5);
530 hdmi_write(hdmi, 0x32, HDMI_SLIPHDMIT_PARAM_SETTINGS_6);
531 hdmi_write(hdmi, 0x48, HDMI_SLIPHDMIT_PARAM_SETTINGS_7);
532 hdmi_write(hdmi, 0x0F, HDMI_SLIPHDMIT_PARAM_SETTINGS_8);
533 hdmi_write(hdmi, 0x20, HDMI_SLIPHDMIT_PARAM_SETTINGS_9);
534 hdmi_write(hdmi, 0x04, HDMI_SLIPHDMIT_PARAM_SETTINGS_10);
535 }
6011bdea
GL		 536}
537
538/**
539 * sh_hdmi_avi_infoframe_setup() - Auxiliary Video Information InfoFrame CONTROL PACKET
540 */
541static void sh_hdmi_avi_infoframe_setup(struct sh_hdmi *hdmi)
542{
6e45746c
GL		 543 u8 vic;
544
6011bdea
GL		 545 /* AVI InfoFrame */
546 hdmi_write(hdmi, 0x06, HDMI_CTRL_PKT_BUF_INDEX);
547
548 /* Packet Type = 0x82 */
549 hdmi_write(hdmi, 0x82, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
550
551 /* Version = 0x02 */
552 hdmi_write(hdmi, 0x02, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
553
554 /* Length = 13 (0x0D) */
555 hdmi_write(hdmi, 0x0D, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
556
557 /* N. A. Checksum */
558 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
559
560 /*
561 * Y = RGB
562 * A0 = No Data
563 * B = Bar Data not valid
564 * S = No Data
565 */
566 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
567
568 /*
6aa966e6
GL		 569 * [7:6] C = Colorimetry: no data
570 * [5:4] M = 2: 16:9, 1: 4:3 Picture Aspect Ratio
571 * [3:0] R = 8: Active Frame Aspect Ratio: same as picture aspect ratio
6011bdea
GL		 572 */
573 hdmi_write(hdmi, 0x28, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
574
575 /*
576 * ITC = No Data
577 * EC = xvYCC601
578 * Q = Default (depends on video format)
579 * SC = No Known non_uniform Scaling
580 */
581 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
582
583 /*
0ea2af1c
GL		 584 * VIC should be ignored if external config is used, so, we could just use 0,
585 * but play safe and use a valid value in any case just in case
6011bdea 586 */
0ea2af1c
GL		 587 if (hdmi->preprogrammed_vic)
588 vic = hdmi->preprogrammed_vic;
6e45746c
GL		 589 else
590 vic = 4;
591 hdmi_write(hdmi, vic, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
6011bdea
GL		 592
593 /* PR = No Repetition */
594 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
595
596 /* Line Number of End of Top Bar (lower 8 bits) */
597 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
598
599 /* Line Number of End of Top Bar (upper 8 bits) */
600 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
601
602 /* Line Number of Start of Bottom Bar (lower 8 bits) */
603 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
604
605 /* Line Number of Start of Bottom Bar (upper 8 bits) */
606 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
607
608 /* Pixel Number of End of Left Bar (lower 8 bits) */
609 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
610
611 /* Pixel Number of End of Left Bar (upper 8 bits) */
612 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB11);
613
614 /* Pixel Number of Start of Right Bar (lower 8 bits) */
615 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB12);
616
617 /* Pixel Number of Start of Right Bar (upper 8 bits) */
618 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB13);
619}
620
621/**
622 * sh_hdmi_audio_infoframe_setup() - Audio InfoFrame of CONTROL PACKET
623 */
624static void sh_hdmi_audio_infoframe_setup(struct sh_hdmi *hdmi)
625{
626 /* Audio InfoFrame */
627 hdmi_write(hdmi, 0x08, HDMI_CTRL_PKT_BUF_INDEX);
628
629 /* Packet Type = 0x84 */
630 hdmi_write(hdmi, 0x84, HDMI_CTRL_PKT_BUF_ACCESS_HB0);
631
632 /* Version Number = 0x01 */
633 hdmi_write(hdmi, 0x01, HDMI_CTRL_PKT_BUF_ACCESS_HB1);
634
635 /* 0 Length = 10 (0x0A) */
636 hdmi_write(hdmi, 0x0A, HDMI_CTRL_PKT_BUF_ACCESS_HB2);
637
638 /* n. a. Checksum */
639 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB0);
640
641 /* Audio Channel Count = Refer to Stream Header */
642 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB1);
643
644 /* Refer to Stream Header */
645 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB2);
646
647 /* Format depends on coding type (i.e. CT0...CT3) */
648 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB3);
649
650 /* Speaker Channel Allocation = Front Right + Front Left */
651 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB4);
652
653 /* Level Shift Value = 0 dB, Down - mix is permitted or no information */
654 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB5);
655
656 /* Reserved (0) */
657 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB6);
658 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB7);
659 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB8);
660 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB9);
661 hdmi_write(hdmi, 0x00, HDMI_CTRL_PKT_BUF_ACCESS_PB10);
662}
663
6011bdea
GL		 664/**
665 * sh_hdmi_configure() - Initialise HDMI for output
666 */
667static void sh_hdmi_configure(struct sh_hdmi *hdmi)
668{
669 /* Configure video format */
670 sh_hdmi_video_config(hdmi);
671
672 /* Configure audio format */
673 sh_hdmi_audio_config(hdmi);
674
675 /* Configure PHY */
676 sh_hdmi_phy_config(hdmi);
677
678 /* Auxiliary Video Information (AVI) InfoFrame */
679 sh_hdmi_avi_infoframe_setup(hdmi);
680
681 /* Audio InfoFrame */
682 sh_hdmi_audio_infoframe_setup(hdmi);
683
6011bdea
GL		 684 /*
685 * Control packet auto send with VSYNC control: auto send
686 * General control, Gamut metadata, ISRC, and ACP packets
687 */
688 hdmi_write(hdmi, 0x8E, HDMI_CTRL_PKT_AUTO_SEND);
689
690 /* FIXME */
691 msleep(10);
692
693 /* PS mode b->d, reset PLLA and PLLB */
694 hdmi_write(hdmi, 0x4C, HDMI_SYSTEM_CTRL);
695
696 udelay(10);
697
698 hdmi_write(hdmi, 0x40, HDMI_SYSTEM_CTRL);
699}
700
f1198d1e 701static unsigned long sh_hdmi_rate_error(struct sh_hdmi *hdmi,
c36940e6
GL		 702 const struct fb_videomode *mode,
703 unsigned long *hdmi_rate, unsigned long *parent_rate)
6011bdea 704{
c36940e6
GL		 705 unsigned long target = PICOS2KHZ(mode->pixclock) * 1000, rate_error;
706 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
707
708 *hdmi_rate = clk_round_rate(hdmi->hdmi_clk, target);
709 if ((long)*hdmi_rate < 0)
710 *hdmi_rate = clk_get_rate(hdmi->hdmi_clk);
711
712 rate_error = (long)*hdmi_rate > 0 ? abs(*hdmi_rate - target) : ULONG_MAX;
713 if (rate_error && pdata->clk_optimize_parent)
714 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate);
715 else if (clk_get_parent(hdmi->hdmi_clk))
716 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk));
f1198d1e
GL		 717
718 dev_dbg(hdmi->dev, "%u-%u-%u-%u x %u-%u-%u-%u\n",
719 mode->left_margin, mode->xres,
720 mode->right_margin, mode->hsync_len,
721 mode->upper_margin, mode->yres,
722 mode->lower_margin, mode->vsync_len);
723
c36940e6
GL		 724 dev_dbg(hdmi->dev, "\t@%lu(+/-%lu)Hz, e=%lu / 1000, r=%uHz, p=%luHz\n", target,
725 rate_error, rate_error ? 10000 / (10 * target / rate_error) : 0,
726 mode->refresh, *parent_rate);
f1198d1e
GL		 727
728 return rate_error;
729}
730
c36940e6
GL		 731static int sh_hdmi_read_edid(struct sh_hdmi *hdmi, unsigned long *hdmi_rate,
732 unsigned long *parent_rate)
6011bdea 733{
6ee48452 734 struct fb_var_screeninfo tmpvar;
6ee48452 735 struct fb_var_screeninfo *var = &tmpvar;
afe417c0 736 const struct fb_videomode *mode, *found = NULL;
f1198d1e
GL		 737 struct fb_info *info = hdmi->info;
738 struct fb_modelist *modelist = NULL;
739 unsigned int f_width = 0, f_height = 0, f_refresh = 0;
740 unsigned long found_rate_error = ULONG_MAX; /* silly compiler... */
c7321d6f 741 bool scanning = false, preferred_bad = false;
6011bdea 742 u8 edid[128];
f1198d1e
GL		 743 char *forced;
744 int i;
6011bdea
GL		 745
746 /* Read EDID */
6aa966e6 747 dev_dbg(hdmi->dev, "Read back EDID code:");
6011bdea
GL		 748 for (i = 0; i < 128; i++) {
749 edid[i] = hdmi_read(hdmi, HDMI_EDID_KSV_FIFO_ACCESS_WINDOW);
750#ifdef DEBUG
751 if ((i % 16) == 0) {
752 printk(KERN_CONT "\n");
753 printk(KERN_DEBUG "%02X | %02X", i, edid[i]);
754 } else {
755 printk(KERN_CONT " %02X", edid[i]);
756 }
757#endif
758 }
759#ifdef DEBUG
760 printk(KERN_CONT "\n");
761#endif
afe417c0 762
4232f607
GL		 763 if (!hdmi->edid_blocks) {
764 fb_edid_to_monspecs(edid, &hdmi->monspec);
765 hdmi->edid_blocks = edid[126] + 1;
766
767 dev_dbg(hdmi->dev, "%d main modes, %d extension blocks\n",
768 hdmi->monspec.modedb_len, hdmi->edid_blocks - 1);
769 } else {
770 dev_dbg(hdmi->dev, "Extension %u detected, DTD start %u\n",
771 edid[0], edid[2]);
772 fb_edid_add_monspecs(edid, &hdmi->monspec);
773 }
774
775 if (hdmi->edid_blocks > hdmi->edid_segment_nr * 2 +
776 (hdmi->edid_block_addr >> 7) + 1) {
777 /* More blocks to read */
778 if (hdmi->edid_block_addr) {
779 hdmi->edid_block_addr = 0;
780 hdmi->edid_segment_nr++;
781 } else {
782 hdmi->edid_block_addr = 0x80;
783 }
784 /* Set EDID word address */
785 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
786 /* Enable EDID interrupt */
787 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
788 /* Set EDID segment pointer - starts reading EDID */
789 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
790 return -EAGAIN;
791 }
792
793 /* All E-EDID blocks ready */
794 dev_dbg(hdmi->dev, "%d main and extended modes\n", hdmi->monspec.modedb_len);
afe417c0 795
f1198d1e
GL		 796 fb_get_options("sh_mobile_lcdc", &forced);
797 if (forced && *forced) {
798 /* Only primitive parsing so far */
799 i = sscanf(forced, "%ux%u@%u",
800 &f_width, &f_height, &f_refresh);
801 if (i < 2) {
802 f_width = 0;
803 f_height = 0;
c7321d6f
GL		 804 } else {
805 /* The user wants us to use the EDID data */
806 scanning = true;
f1198d1e
GL		 807 }
808 dev_dbg(hdmi->dev, "Forced mode %ux%u@%uHz\n",
809 f_width, f_height, f_refresh);
810 }
811
812 /* Walk monitor modes to find the best or the exact match */
813 for (i = 0, mode = hdmi->monspec.modedb;
c7321d6f 814 i < hdmi->monspec.modedb_len && scanning;
afe417c0 815 i++, mode++) {
c36940e6 816 unsigned long rate_error;
f1198d1e 817
c7321d6f
GL		 818 if (!f_width && !f_height) {
819 /*
820 * A parameter string "video=sh_mobile_lcdc:0x0" means
821 * use the preferred EDID mode. If it is rejected by
822 * .fb_check_var(), keep looking, until an acceptable
823 * one is found.
824 */
825 if ((mode->flag & FB_MODE_IS_FIRST) || preferred_bad)
826 scanning = false;
827 else
828 continue;
829 } else if (f_width != mode->xres || f_height != mode->yres) {
830 /* No interest in unmatching modes */
f1198d1e 831 continue;
c7321d6f 832 }
c36940e6
GL		 833
834 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate);
835
c7321d6f
GL		 836 if (scanning) {
837 if (f_refresh == mode->refresh || (!f_refresh && !rate_error))
838 /*
839 * Exact match if either the refresh rate
840 * matches or it hasn't been specified and we've
841 * found a mode, for which we can configure the
842 * clock precisely
843 */
844 scanning = false;
845 else if (found && found_rate_error <= rate_error)
846 /*
847 * We otherwise search for the closest matching
848 * clock rate - either if no refresh rate has
849 * been specified or we cannot find an exactly
850 * matching one
851 */
852 continue;
853 }
f1198d1e
GL		 854
855 /* Check if supported: sufficient fb memory, supported clock-rate */
856 fb_videomode_to_var(var, mode);
857
c7321d6f
GL		 858 var->bits_per_pixel = info->var.bits_per_pixel;
859
f1198d1e
GL		 860 if (info && info->fbops->fb_check_var &&
861 info->fbops->fb_check_var(var, info)) {
c7321d6f
GL		 862 scanning = true;
863 preferred_bad = true;
f1198d1e 864 continue;
afe417c0 865 }
f1198d1e
GL		 866
867 found = mode;
868 found_rate_error = rate_error;
afe417c0
GL		 869 }
870
8c1ac08b
GL		 871 hdmi->var.width = hdmi->monspec.max_x * 10;
872 hdmi->var.height = hdmi->monspec.max_y * 10;
873
afe417c0 874 /*
f1198d1e
GL		 875 * TODO 1: if no ->info is present, postpone running the config until
876 * after ->info first gets registered.
877 * TODO 2: consider registering the HDMI platform device from the LCDC
878 * driver, and passing ->info with HDMI platform data.
afe417c0 879 */
f1198d1e 880 if (info && !found) {
0d7fa180
GL		 881 modelist = info->modelist.next &&
882 !list_empty(&info->modelist) ?
883 list_entry(info->modelist.next,
f1198d1e
GL		 884 struct fb_modelist, list) :
885 NULL;
886
887 if (modelist) {
888 found = &modelist->mode;
c36940e6 889 found_rate_error = sh_hdmi_rate_error(hdmi, found, hdmi_rate, parent_rate);
afe417c0
GL		 890 }
891 }
892
afe417c0
GL		 893 /* No cookie today */
894 if (!found)
895 return -ENXIO;
896
0ea2af1c
GL		 897 if (found->xres == 640 && found->yres == 480 && found->refresh == 60)
898 hdmi->preprogrammed_vic = 1;
899 else if (found->xres == 720 && found->yres == 480 && found->refresh == 60)
900 hdmi->preprogrammed_vic = 2;
901 else if (found->xres == 720 && found->yres == 576 && found->refresh == 50)
902 hdmi->preprogrammed_vic = 17;
903 else if (found->xres == 1280 && found->yres == 720 && found->refresh == 60)
904 hdmi->preprogrammed_vic = 4;
905 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 24)
906 hdmi->preprogrammed_vic = 32;
907 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 50)
908 hdmi->preprogrammed_vic = 31;
909 else if (found->xres == 1920 && found->yres == 1080 && found->refresh == 60)
910 hdmi->preprogrammed_vic = 16;
89712699 911 else
0ea2af1c 912 hdmi->preprogrammed_vic = 0;
89712699 913
c36940e6 914 dev_dbg(hdmi->dev, "Using %s %s mode %ux%u@%uHz (%luHz), clock error %luHz\n",
0ea2af1c 915 modelist ? "default" : "EDID", hdmi->preprogrammed_vic ? "VIC" : "external",
c36940e6
GL		 916 found->xres, found->yres, found->refresh,
917 PICOS2KHZ(found->pixclock) * 1000, found_rate_error);
918
afe417c0 919 fb_videomode_to_var(&hdmi->var, found);
6aa966e6 920 sh_hdmi_external_video_param(hdmi);
afe417c0
GL		 921
922 return 0;
6011bdea
GL		 923}
924
925static irqreturn_t sh_hdmi_hotplug(int irq, void *dev_id)
926{
927 struct sh_hdmi *hdmi = dev_id;
928 u8 status1, status2, mask1, mask2;
929
930 /* mode_b and PLLA and PLLB reset */
931 hdmi_write(hdmi, 0x2C, HDMI_SYSTEM_CTRL);
932
933 /* How long shall reset be held? */
934 udelay(10);
935
936 /* mode_b and PLLA and PLLB reset release */
937 hdmi_write(hdmi, 0x20, HDMI_SYSTEM_CTRL);
938
939 status1 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_1);
940 status2 = hdmi_read(hdmi, HDMI_INTERRUPT_STATUS_2);
941
942 mask1 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_1);
943 mask2 = hdmi_read(hdmi, HDMI_INTERRUPT_MASK_2);
944
945 /* Correct would be to ack only set bits, but the datasheet requires 0xff */
946 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_1);
947 hdmi_write(hdmi, 0xFF, HDMI_INTERRUPT_STATUS_2);
948
949 if (printk_ratelimit())
6aa966e6
GL		 950 dev_dbg(hdmi->dev, "IRQ #%d: Status #1: 0x%x & 0x%x, #2: 0x%x & 0x%x\n",
951 irq, status1, mask1, status2, mask2);
6011bdea
GL		 952
953 if (!((status1 & mask1) | (status2 & mask2))) {
954 return IRQ_NONE;
955 } else if (status1 & 0xc0) {
956 u8 msens;
957
958 /* Datasheet specifies 10ms... */
959 udelay(500);
960
961 msens = hdmi_read(hdmi, HDMI_HOT_PLUG_MSENS_STATUS);
6aa966e6 962 dev_dbg(hdmi->dev, "MSENS 0x%x\n", msens);
6011bdea
GL		 963 /* Check, if hot plug & MSENS pin status are both high */
964 if ((msens & 0xC0) == 0xC0) {
965 /* Display plug in */
4232f607
GL		 966 hdmi->edid_segment_nr = 0;
967 hdmi->edid_block_addr = 0;
968 hdmi->edid_blocks = 0;
6011bdea
GL		 969 hdmi->hp_state = HDMI_HOTPLUG_CONNECTED;
970
971 /* Set EDID word address */
972 hdmi_write(hdmi, 0x00, HDMI_EDID_WORD_ADDRESS);
6011bdea
GL		 973 /* Enable EDID interrupt */
974 hdmi_write(hdmi, 0xC6, HDMI_INTERRUPT_MASK_1);
4232f607
GL		 975 /* Set EDID segment pointer - starts reading EDID */
976 hdmi_write(hdmi, 0x00, HDMI_EDID_SEGMENT_POINTER);
6011bdea
GL		 977 } else if (!(status1 & 0x80)) {
978 /* Display unplug, beware multiple interrupts */
4232f607
GL		 979 if (hdmi->hp_state != HDMI_HOTPLUG_DISCONNECTED) {
980 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
6011bdea 981 schedule_delayed_work(&hdmi->edid_work, 0);
4232f607 982 }
6011bdea
GL		 983 /* display_off will switch back to mode_a */
984 }
985 } else if (status1 & 2) {
986 /* EDID error interrupt: retry */
987 /* Set EDID word address */
4232f607 988 hdmi_write(hdmi, hdmi->edid_block_addr, HDMI_EDID_WORD_ADDRESS);
6011bdea 989 /* Set EDID segment pointer */
4232f607 990 hdmi_write(hdmi, hdmi->edid_segment_nr, HDMI_EDID_SEGMENT_POINTER);
6011bdea
GL		 991 } else if (status1 & 4) {
992 /* Disable EDID interrupt */
993 hdmi_write(hdmi, 0xC0, HDMI_INTERRUPT_MASK_1);
6011bdea
GL		 994 schedule_delayed_work(&hdmi->edid_work, msecs_to_jiffies(10));
995 }
996
997 return IRQ_HANDLED;
998}
999
6de9edd5 1000/* locking: called with info->lock held, or before register_framebuffer() */
6aa966e6 1001static void sh_hdmi_display_on(void *arg, struct fb_info *info)
6011bdea 1002{
6de9edd5
GL		 1003 /*
1004 * info is guaranteed to be valid, when we are called, because our
1005 * FB_EVENT_FB_UNBIND notify is also called with info->lock held
1006 */
6011bdea
GL		 1007 struct sh_hdmi *hdmi = arg;
1008 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1c120deb 1009 struct sh_mobile_lcdc_chan *ch = info->par;
6011bdea 1010
6aa966e6
GL		 1011 dev_dbg(hdmi->dev, "%s(%p): state %x\n", __func__,
1012 pdata->lcd_dev, info->state);
6de9edd5
GL		 1013
1014 /* No need to lock */
6011bdea 1015 hdmi->info = info;
6011bdea 1016
6011bdea 1017 /*
6aa966e6
GL		 1018 * hp_state can be set to
1019 * HDMI_HOTPLUG_DISCONNECTED: on monitor unplug
1020 * HDMI_HOTPLUG_CONNECTED: on monitor plug-in
1021 * HDMI_HOTPLUG_EDID_DONE: on EDID read completion
6011bdea 1022 */
6011bdea
GL		 1023 switch (hdmi->hp_state) {
1024 case HDMI_HOTPLUG_EDID_DONE:
1025 /* PS mode d->e. All functions are active */
1026 hdmi_write(hdmi, 0x80, HDMI_SYSTEM_CTRL);
6aa966e6 1027 dev_dbg(hdmi->dev, "HDMI running\n");
6011bdea
GL		 1028 break;
1029 case HDMI_HOTPLUG_DISCONNECTED:
1030 info->state = FBINFO_STATE_SUSPENDED;
1031 default:
1c120deb 1032 hdmi->var = ch->display_var;
6011bdea
GL		 1033 }
1034}
1035
6de9edd5 1036/* locking: called with info->lock held */
6aa966e6 1037static void sh_hdmi_display_off(void *arg)
6011bdea
GL		 1038{
1039 struct sh_hdmi *hdmi = arg;
1040 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1041
6aa966e6 1042 dev_dbg(hdmi->dev, "%s(%p)\n", __func__, pdata->lcd_dev);
6011bdea
GL		 1043 /* PS mode e->a */
1044 hdmi_write(hdmi, 0x10, HDMI_SYSTEM_CTRL);
1045}
1046
afe417c0
GL		 1047static bool sh_hdmi_must_reconfigure(struct sh_hdmi *hdmi)
1048{
1049 struct fb_info *info = hdmi->info;
1050 struct sh_mobile_lcdc_chan *ch = info->par;
1051 struct fb_var_screeninfo *new_var = &hdmi->var, *old_var = &ch->display_var;
1052 struct fb_videomode mode1, mode2;
1053
1054 fb_var_to_videomode(&mode1, old_var);
1055 fb_var_to_videomode(&mode2, new_var);
1056
1057 dev_dbg(info->dev, "Old %ux%u, new %ux%u\n",
1058 mode1.xres, mode1.yres, mode2.xres, mode2.yres);
1059
8c1ac08b
GL		 1060 if (fb_mode_is_equal(&mode1, &mode2)) {
1061 /* It can be a different monitor with an equal video-mode */
1062 old_var->width = new_var->width;
1063 old_var->height = new_var->height;
afe417c0 1064 return false;
8c1ac08b 1065 }
afe417c0
GL		 1066
1067 dev_dbg(info->dev, "Switching %u -> %u lines\n",
1068 mode1.yres, mode2.yres);
1069 *old_var = *new_var;
1070
1071 return true;
1072}
1073
1074/**
1075 * sh_hdmi_clk_configure() - set HDMI clock frequency and enable the clock
c36940e6
GL		 1076 * @hdmi: driver context
1077 * @hdmi_rate: HDMI clock frequency in Hz
1078 * @parent_rate: if != 0 - set parent clock rate for optimal precision
1079 * return: configured positive rate if successful
1080 * 0 if couldn't set the rate, but managed to enable the
1081 * clock, negative error, if couldn't enable the clock
afe417c0 1082 */
c36940e6
GL		 1083static long sh_hdmi_clk_configure(struct sh_hdmi *hdmi, unsigned long hdmi_rate,
1084 unsigned long parent_rate)
afe417c0 1085{
afe417c0
GL		 1086 int ret;
1087
c36940e6
GL		 1088 if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) {
1089 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate);
afe417c0 1090 if (ret < 0) {
c36940e6
GL		 1091 dev_warn(hdmi->dev, "Cannot set parent rate %ld: %d\n", parent_rate, ret);
1092 hdmi_rate = clk_round_rate(hdmi->hdmi_clk, hdmi_rate);
afe417c0 1093 } else {
c36940e6 1094 dev_dbg(hdmi->dev, "HDMI set parent frequency %lu\n", parent_rate);
afe417c0 1095 }
afe417c0
GL		 1096 }
1097
c36940e6 1098 ret = clk_set_rate(hdmi->hdmi_clk, hdmi_rate);
afe417c0 1099 if (ret < 0) {
c36940e6
GL		 1100 dev_warn(hdmi->dev, "Cannot set rate %ld: %d\n", hdmi_rate, ret);
1101 hdmi_rate = 0;
1102 } else {
1103 dev_dbg(hdmi->dev, "HDMI set frequency %lu\n", hdmi_rate);
afe417c0
GL		 1104 }
1105
c36940e6 1106 return hdmi_rate;
afe417c0
GL		 1107}
1108
6011bdea 1109/* Hotplug interrupt occurred, read EDID */
6aa966e6 1110static void sh_hdmi_edid_work_fn(struct work_struct *work)
6011bdea
GL		 1111{
1112 struct sh_hdmi *hdmi = container_of(work, struct sh_hdmi, edid_work.work);
1113 struct sh_mobile_hdmi_info *pdata = hdmi->dev->platform_data;
1c120deb 1114 struct sh_mobile_lcdc_chan *ch;
afe417c0 1115 int ret;
6011bdea 1116
6aa966e6
GL		 1117 dev_dbg(hdmi->dev, "%s(%p): begin, hotplug status %d\n", __func__,
1118 pdata->lcd_dev, hdmi->hp_state);
6011bdea
GL		 1119
1120 if (!pdata->lcd_dev)
1121 return;
1122
6de9edd5
GL		 1123 mutex_lock(&hdmi->mutex);
1124
4232f607 1125 if (hdmi->hp_state == HDMI_HOTPLUG_CONNECTED) {
0d7fa180 1126 struct fb_info *info = hdmi->info;
c36940e6
GL		 1127 unsigned long parent_rate = 0, hdmi_rate;
1128
6011bdea 1129 /* A device has been plugged in */
afe417c0
GL		 1130 pm_runtime_get_sync(hdmi->dev);
1131
c36940e6 1132 ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
afe417c0
GL		 1133 if (ret < 0)
1134 goto out;
1135
4232f607
GL		 1136 hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
1137
afe417c0 1138 /* Reconfigure the clock */
c36940e6 1139 ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
afe417c0
GL		 1140 if (ret < 0)
1141 goto out;
1142
6011bdea
GL		 1143 msleep(10);
1144 sh_hdmi_configure(hdmi);
1145 /* Switched to another (d) power-save mode */
1146 msleep(10);
1147
0d7fa180 1148 if (!info)
6de9edd5 1149 goto out;
6011bdea 1150
0d7fa180 1151 ch = info->par;
6011bdea
GL		 1152
1153 acquire_console_sem();
1154
1155 /* HDMI plug in */
afe417c0 1156 if (!sh_hdmi_must_reconfigure(hdmi) &&
0d7fa180 1157 info->state == FBINFO_STATE_RUNNING) {
afe417c0
GL		 1158 /*
1159 * First activation with the default monitor - just turn
1160 * on, if we run a resume here, the logo disappears
1161 */
0d7fa180 1162 if (lock_fb_info(info)) {
8c1ac08b
GL		 1163 info->var.width = hdmi->var.width;
1164 info->var.height = hdmi->var.height;
1165 sh_hdmi_display_on(hdmi, info);
1166 unlock_fb_info(info);
6de9edd5 1167 }
afe417c0
GL		 1168 } else {
1169 /* New monitor or have to wake up */
0d7fa180 1170 fb_set_suspend(info, 0);
6de9edd5 1171 }
6011bdea
GL		 1172
1173 release_console_sem();
1174 } else {
afe417c0 1175 ret = 0;
6011bdea 1176 if (!hdmi->info)
6de9edd5 1177 goto out;
6011bdea 1178
91d63f8a
GL		 1179 hdmi->monspec.modedb_len = 0;
1180 fb_destroy_modedb(hdmi->monspec.modedb);
1181 hdmi->monspec.modedb = NULL;
1182
6011bdea
GL		 1183 acquire_console_sem();
1184
1185 /* HDMI disconnect */
1186 fb_set_suspend(hdmi->info, 1);
1187
1188 release_console_sem();
1189 pm_runtime_put(hdmi->dev);
1190 }
1191
6de9edd5 1192out:
4232f607 1193 if (ret < 0 && ret != -EAGAIN)
afe417c0 1194 hdmi->hp_state = HDMI_HOTPLUG_DISCONNECTED;
6de9edd5
GL		 1195 mutex_unlock(&hdmi->mutex);
1196
6aa966e6 1197 dev_dbg(hdmi->dev, "%s(%p): end\n", __func__, pdata->lcd_dev);
6011bdea
GL		 1198}
1199
6de9edd5
GL		 1200static int sh_hdmi_notify(struct notifier_block *nb,
1201 unsigned long action, void *data)
1202{
1203 struct fb_event *event = data;
1204 struct fb_info *info = event->info;
1205 struct sh_mobile_lcdc_chan *ch = info->par;
1206 struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
1207 struct sh_hdmi *hdmi = board_cfg->board_data;
1208
eb0778bd 1209 if (!hdmi || nb != &hdmi->notifier || hdmi->info != info)
6de9edd5
GL		 1210 return NOTIFY_DONE;
1211
1212 switch(action) {
1213 case FB_EVENT_FB_REGISTERED:
6aa966e6 1214 /* Unneeded, activation taken care by sh_hdmi_display_on() */
6de9edd5
GL		 1215 break;
1216 case FB_EVENT_FB_UNREGISTERED:
1217 /*
1218 * We are called from unregister_framebuffer() with the
1219 * info->lock held. This is bad for us, because we can race with
1220 * the scheduled work, which has to call fb_set_suspend(), which
6aa966e6
GL		 1221 * takes info->lock internally, so, sh_hdmi_edid_work_fn()
1222 * cannot take and hold info->lock for the whole function
1223 * duration. Using an additional lock creates a classical AB-BA
1224 * lock up. Therefore, we have to release the info->lock
1225 * temporarily, synchronise with the work queue and re-acquire
1226 * the info->lock.
6de9edd5 1227 */
eb0778bd 1228 unlock_fb_info(info);
6de9edd5
GL		 1229 mutex_lock(&hdmi->mutex);
1230 hdmi->info = NULL;
1231 mutex_unlock(&hdmi->mutex);
eb0778bd 1232 lock_fb_info(info);
6de9edd5
GL		 1233 return NOTIFY_OK;
1234 }
1235 return NOTIFY_DONE;
6011bdea
GL		 1236}
1237
1238static int __init sh_hdmi_probe(struct platform_device *pdev)
1239{
1240 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1241 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6de9edd5 1242 struct sh_mobile_lcdc_board_cfg *board_cfg;
6011bdea
GL		 1243 int irq = platform_get_irq(pdev, 0), ret;
1244 struct sh_hdmi *hdmi;
1245 long rate;
1246
1247 if (!res || !pdata || irq < 0)
1248 return -ENODEV;
1249
1250 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
1251 if (!hdmi) {
1252 dev_err(&pdev->dev, "Cannot allocate device data\n");
1253 return -ENOMEM;
1254 }
1255
6de9edd5 1256 mutex_init(&hdmi->mutex);
1d6be338 1257
6011bdea
GL		 1258 hdmi->dev = &pdev->dev;
1259
1260 hdmi->hdmi_clk = clk_get(&pdev->dev, "ick");
1261 if (IS_ERR(hdmi->hdmi_clk)) {
1262 ret = PTR_ERR(hdmi->hdmi_clk);
1263 dev_err(&pdev->dev, "Unable to get clock: %d\n", ret);
1264 goto egetclk;
1265 }
1266
c36940e6
GL		 1267 /* An arbitrary relaxed pixclock just to get things started: from standard 480p */
1268 rate = clk_round_rate(hdmi->hdmi_clk, PICOS2KHZ(37037));
1269 if (rate > 0)
1270 rate = sh_hdmi_clk_configure(hdmi, rate, 0);
1271
6011bdea
GL		 1272 if (rate < 0) {
1273 ret = rate;
6011bdea
GL		 1274 goto erate;
1275 }
1276
c36940e6
GL		 1277 ret = clk_enable(hdmi->hdmi_clk);
1278 if (ret < 0) {
1279 dev_err(hdmi->dev, "Cannot enable clock: %d\n", ret);
1280 goto erate;
1281 }
1282
afe417c0 1283 dev_dbg(&pdev->dev, "Enabled HDMI clock at %luHz\n", rate);
6011bdea
GL		 1284
1285 if (!request_mem_region(res->start, resource_size(res), dev_name(&pdev->dev))) {
1286 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1287 ret = -EBUSY;
1288 goto ereqreg;
1289 }
1290
1291 hdmi->base = ioremap(res->start, resource_size(res));
1292 if (!hdmi->base) {
1293 dev_err(&pdev->dev, "HDMI register region already claimed\n");
1294 ret = -ENOMEM;
1295 goto emap;
1296 }
1297
1298 platform_set_drvdata(pdev, hdmi);
1299
6011bdea 1300 /* Set up LCDC callbacks */
6de9edd5
GL		 1301 board_cfg = &pdata->lcd_chan->board_cfg;
1302 board_cfg->owner = THIS_MODULE;
1303 board_cfg->board_data = hdmi;
6aa966e6
GL		 1304 board_cfg->display_on = sh_hdmi_display_on;
1305 board_cfg->display_off = sh_hdmi_display_off;
6011bdea 1306
6aa966e6 1307 INIT_DELAYED_WORK(&hdmi->edid_work, sh_hdmi_edid_work_fn);
6011bdea
GL		 1308
1309 pm_runtime_enable(&pdev->dev);
1310 pm_runtime_resume(&pdev->dev);
1311
c36940e6
GL		 1312 /* Product and revision IDs are 0 in sh-mobile version */
1313 dev_info(&pdev->dev, "Detected HDMI controller 0x%x:0x%x\n",
1314 hdmi_read(hdmi, HDMI_PRODUCT_ID), hdmi_read(hdmi, HDMI_REVISION_ID));
1315
6011bdea
GL		 1316 ret = request_irq(irq, sh_hdmi_hotplug, 0,
1317 dev_name(&pdev->dev), hdmi);
1318 if (ret < 0) {
1319 dev_err(&pdev->dev, "Unable to request irq: %d\n", ret);
1320 goto ereqirq;
1321 }
1322
b3773301
RK		 1323 ret = snd_soc_register_codec(&pdev->dev,
1324 &soc_codec_dev_sh_hdmi, &sh_hdmi_dai, 1);
1325 if (ret < 0) {
1326 dev_err(&pdev->dev, "codec registration failed\n");
1327 goto ecodec;
1328 }
1329
eb0778bd
GL		 1330 hdmi->notifier.notifier_call = sh_hdmi_notify;
1331 fb_register_client(&hdmi->notifier);
1332
6011bdea
GL		 1333 return 0;
1334
b3773301
RK		 1335ecodec:
1336 free_irq(irq, hdmi);
6011bdea
GL		 1337ereqirq:
1338 pm_runtime_disable(&pdev->dev);
1339 iounmap(hdmi->base);
1340emap:
1341 release_mem_region(res->start, resource_size(res));
1342ereqreg:
1343 clk_disable(hdmi->hdmi_clk);
6011bdea
GL		 1344erate:
1345 clk_put(hdmi->hdmi_clk);
1346egetclk:
6de9edd5 1347 mutex_destroy(&hdmi->mutex);
6011bdea
GL		 1348 kfree(hdmi);
1349
1350 return ret;
1351}
1352
1353static int __exit sh_hdmi_remove(struct platform_device *pdev)
1354{
1355 struct sh_mobile_hdmi_info *pdata = pdev->dev.platform_data;
1356 struct sh_hdmi *hdmi = platform_get_drvdata(pdev);
1357 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6de9edd5 1358 struct sh_mobile_lcdc_board_cfg *board_cfg = &pdata->lcd_chan->board_cfg;
6011bdea
GL		 1359 int irq = platform_get_irq(pdev, 0);
1360
1d6be338
KM		 1361 snd_soc_unregister_codec(&pdev->dev);
1362
eb0778bd
GL		 1363 fb_unregister_client(&hdmi->notifier);
1364
6de9edd5
GL		 1365 board_cfg->display_on = NULL;
1366 board_cfg->display_off = NULL;
1367 board_cfg->board_data = NULL;
1368 board_cfg->owner = NULL;
6011bdea 1369
6de9edd5 1370 /* No new work will be scheduled, wait for running ISR */
6011bdea 1371 free_irq(irq, hdmi);
6de9edd5 1372 /* Wait for already scheduled work */
6011bdea 1373 cancel_delayed_work_sync(&hdmi->edid_work);
6de9edd5 1374 pm_runtime_disable(&pdev->dev);
6011bdea
GL		 1375 clk_disable(hdmi->hdmi_clk);
1376 clk_put(hdmi->hdmi_clk);
1377 iounmap(hdmi->base);
1378 release_mem_region(res->start, resource_size(res));
6de9edd5 1379 mutex_destroy(&hdmi->mutex);
6011bdea
GL		 1380 kfree(hdmi);
1381
1382 return 0;
1383}
1384
1385static struct platform_driver sh_hdmi_driver = {
1386 .remove = __exit_p(sh_hdmi_remove),
1387 .driver = {
1388 .name = "sh-mobile-hdmi",
1389 },
1390};
1391
1392static int __init sh_hdmi_init(void)
1393{
1394 return platform_driver_probe(&sh_hdmi_driver, sh_hdmi_probe);
1395}
1396module_init(sh_hdmi_init);
1397
1398static void __exit sh_hdmi_exit(void)
1399{
1400 platform_driver_unregister(&sh_hdmi_driver);
1401}
1402module_exit(sh_hdmi_exit);
1403
1404MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
1405MODULE_DESCRIPTION("SuperH / ARM-shmobile HDMI driver");
1406MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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