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const: constify remaining dev_pm_ops
[deliverable/linux.git] / drivers / video / sh_mobile_lcdcfb.c
CommitLineData
cfb4f5d1
MD		 1/*
2 * SuperH Mobile LCDC Framebuffer
3 *
4 * Copyright (c) 2008 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
15#include <linux/fb.h>
16#include <linux/clk.h>
0246c471 17#include <linux/pm_runtime.h>
cfb4f5d1
MD		 18#include <linux/platform_device.h>
19#include <linux/dma-mapping.h>
8564557a 20#include <linux/interrupt.h>
1c6a307a 21#include <linux/vmalloc.h>
225c9a8d 22#include <video/sh_mobile_lcdc.h>
8564557a 23#include <asm/atomic.h>
cfb4f5d1
MD		 24
25#define PALETTE_NR 16
a6f15ade
PE		 26#define SIDE_B_OFFSET 0x1000
27#define MIRROR_OFFSET 0x2000
cfb4f5d1 28
cfb4f5d1
MD		 29/* shared registers */
30#define _LDDCKR 0x410
31#define _LDDCKSTPR 0x414
32#define _LDINTR 0x468
33#define _LDSR 0x46c
34#define _LDCNT1R 0x470
35#define _LDCNT2R 0x474
9dd38819 36#define _LDRCNTR 0x478
cfb4f5d1
MD		 37#define _LDDDSR 0x47c
38#define _LDDWD0R 0x800
39#define _LDDRDR 0x840
40#define _LDDWAR 0x900
41#define _LDDRAR 0x904
42
0246c471
MD		 43/* shared registers and their order for context save/restore */
44static int lcdc_shared_regs[] = {
45 _LDDCKR,
46 _LDDCKSTPR,
47 _LDINTR,
48 _LDDDSR,
49 _LDCNT1R,
50 _LDCNT2R,
51};
52#define NR_SHARED_REGS ARRAY_SIZE(lcdc_shared_regs)
53
cfb4f5d1
MD		 54/* per-channel registers */
55enum { LDDCKPAT1R, LDDCKPAT2R, LDMT1R, LDMT2R, LDMT3R, LDDFR, LDSM1R,
0246c471
MD		 56 LDSM2R, LDSA1R, LDMLSR, LDHCNR, LDHSYNR, LDVLNR, LDVSYNR, LDPMR,
57 NR_CH_REGS };
cfb4f5d1 58
0246c471 59static unsigned long lcdc_offs_mainlcd[NR_CH_REGS] = {
cfb4f5d1
MD		 60 [LDDCKPAT1R] = 0x400,
61 [LDDCKPAT2R] = 0x404,
62 [LDMT1R] = 0x418,
63 [LDMT2R] = 0x41c,
64 [LDMT3R] = 0x420,
65 [LDDFR] = 0x424,
66 [LDSM1R] = 0x428,
8564557a 67 [LDSM2R] = 0x42c,
cfb4f5d1
MD		 68 [LDSA1R] = 0x430,
69 [LDMLSR] = 0x438,
70 [LDHCNR] = 0x448,
71 [LDHSYNR] = 0x44c,
72 [LDVLNR] = 0x450,
73 [LDVSYNR] = 0x454,
74 [LDPMR] = 0x460,
75};
76
0246c471 77static unsigned long lcdc_offs_sublcd[NR_CH_REGS] = {
cfb4f5d1
MD		 78 [LDDCKPAT1R] = 0x408,
79 [LDDCKPAT2R] = 0x40c,
80 [LDMT1R] = 0x600,
81 [LDMT2R] = 0x604,
82 [LDMT3R] = 0x608,
83 [LDDFR] = 0x60c,
84 [LDSM1R] = 0x610,
8564557a 85 [LDSM2R] = 0x614,
cfb4f5d1
MD		 86 [LDSA1R] = 0x618,
87 [LDMLSR] = 0x620,
88 [LDHCNR] = 0x624,
89 [LDHSYNR] = 0x628,
90 [LDVLNR] = 0x62c,
91 [LDVSYNR] = 0x630,
92 [LDPMR] = 0x63c,
93};
94
95#define START_LCDC 0x00000001
96#define LCDC_RESET 0x00000100
97#define DISPLAY_BEU 0x00000008
98#define LCDC_ENABLE 0x00000001
8564557a 99#define LDINTR_FE 0x00000400
9dd38819
PE		 100#define LDINTR_VSE 0x00000200
101#define LDINTR_VEE 0x00000100
8564557a 102#define LDINTR_FS 0x00000004
9dd38819
PE		 103#define LDINTR_VSS 0x00000002
104#define LDINTR_VES 0x00000001
a6f15ade
PE		 105#define LDRCNTR_SRS 0x00020000
106#define LDRCNTR_SRC 0x00010000
107#define LDRCNTR_MRS 0x00000002
108#define LDRCNTR_MRC 0x00000001
cfb4f5d1 109
0246c471
MD		 110struct sh_mobile_lcdc_priv;
111struct sh_mobile_lcdc_chan {
112 struct sh_mobile_lcdc_priv *lcdc;
113 unsigned long *reg_offs;
114 unsigned long ldmt1r_value;
115 unsigned long enabled; /* ME and SE in LDCNT2R */
116 struct sh_mobile_lcdc_chan_cfg cfg;
117 u32 pseudo_palette[PALETTE_NR];
118 unsigned long saved_ch_regs[NR_CH_REGS];
119 struct fb_info *info;
120 dma_addr_t dma_handle;
121 struct fb_deferred_io defio;
122 struct scatterlist *sglist;
123 unsigned long frame_end;
9dd38819
PE		 124 unsigned long pan_offset;
125 unsigned long new_pan_offset;
0246c471
MD		 126 wait_queue_head_t frame_end_wait;
127};
128
129struct sh_mobile_lcdc_priv {
130 void __iomem *base;
131 int irq;
132 atomic_t hw_usecnt;
133 struct device *dev;
134 struct clk *dot_clk;
135 unsigned long lddckr;
136 struct sh_mobile_lcdc_chan ch[2];
137 unsigned long saved_shared_regs[NR_SHARED_REGS];
138 int started;
139};
140
a6f15ade
PE		 141static bool banked(int reg_nr)
142{
143 switch (reg_nr) {
144 case LDMT1R:
145 case LDMT2R:
146 case LDMT3R:
147 case LDDFR:
148 case LDSM1R:
149 case LDSA1R:
150 case LDMLSR:
151 case LDHCNR:
152 case LDHSYNR:
153 case LDVLNR:
154 case LDVSYNR:
155 return true;
156 }
157 return false;
158}
159
cfb4f5d1
MD		 160static void lcdc_write_chan(struct sh_mobile_lcdc_chan *chan,
161 int reg_nr, unsigned long data)
162{
163 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr]);
a6f15ade
PE		 164 if (banked(reg_nr))
165 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
166 SIDE_B_OFFSET);
167}
168
169static void lcdc_write_chan_mirror(struct sh_mobile_lcdc_chan *chan,
170 int reg_nr, unsigned long data)
171{
172 iowrite32(data, chan->lcdc->base + chan->reg_offs[reg_nr] +
173 MIRROR_OFFSET);
cfb4f5d1
MD		 174}
175
176static unsigned long lcdc_read_chan(struct sh_mobile_lcdc_chan *chan,
177 int reg_nr)
178{
179 return ioread32(chan->lcdc->base + chan->reg_offs[reg_nr]);
180}
181
182static void lcdc_write(struct sh_mobile_lcdc_priv *priv,
183 unsigned long reg_offs, unsigned long data)
184{
185 iowrite32(data, priv->base + reg_offs);
186}
187
188static unsigned long lcdc_read(struct sh_mobile_lcdc_priv *priv,
189 unsigned long reg_offs)
190{
191 return ioread32(priv->base + reg_offs);
192}
193
194static void lcdc_wait_bit(struct sh_mobile_lcdc_priv *priv,
195 unsigned long reg_offs,
196 unsigned long mask, unsigned long until)
197{
198 while ((lcdc_read(priv, reg_offs) & mask) != until)
199 cpu_relax();
200}
201
202static int lcdc_chan_is_sublcd(struct sh_mobile_lcdc_chan *chan)
203{
204 return chan->cfg.chan == LCDC_CHAN_SUBLCD;
205}
206
207static void lcdc_sys_write_index(void *handle, unsigned long data)
208{
209 struct sh_mobile_lcdc_chan *ch = handle;
210
211 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x10000000);
212 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
213 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 214 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 215}
216
217static void lcdc_sys_write_data(void *handle, unsigned long data)
218{
219 struct sh_mobile_lcdc_chan *ch = handle;
220
221 lcdc_write(ch->lcdc, _LDDWD0R, data | 0x11000000);
222 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
223 lcdc_write(ch->lcdc, _LDDWAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
909f10de 224 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1
MD		 225}
226
227static unsigned long lcdc_sys_read_data(void *handle)
228{
229 struct sh_mobile_lcdc_chan *ch = handle;
230
231 lcdc_write(ch->lcdc, _LDDRDR, 0x01000000);
232 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
233 lcdc_write(ch->lcdc, _LDDRAR, 1 | (lcdc_chan_is_sublcd(ch) ? 2 : 0));
234 udelay(1);
909f10de 235 lcdc_wait_bit(ch->lcdc, _LDSR, 2, 0);
cfb4f5d1 236
ec56b66f 237 return lcdc_read(ch->lcdc, _LDDRDR) & 0x3ffff;
cfb4f5d1
MD		 238}
239
240struct sh_mobile_lcdc_sys_bus_ops sh_mobile_lcdc_sys_bus_ops = {
241 lcdc_sys_write_index,
242 lcdc_sys_write_data,
243 lcdc_sys_read_data,
244};
245
8564557a
MD		 246static void sh_mobile_lcdc_clk_on(struct sh_mobile_lcdc_priv *priv)
247{
0246c471
MD		 248 if (atomic_inc_and_test(&priv->hw_usecnt)) {
249 pm_runtime_get_sync(priv->dev);
8564557a
MD		 250 if (priv->dot_clk)
251 clk_enable(priv->dot_clk);
252 }
253}
254
255static void sh_mobile_lcdc_clk_off(struct sh_mobile_lcdc_priv *priv)
256{
0246c471 257 if (atomic_sub_return(1, &priv->hw_usecnt) == -1) {
8564557a
MD		 258 if (priv->dot_clk)
259 clk_disable(priv->dot_clk);
0246c471 260 pm_runtime_put(priv->dev);
8564557a
MD		 261 }
262}
8564557a 263
1c6a307a
PM		 264static int sh_mobile_lcdc_sginit(struct fb_info *info,
265 struct list_head *pagelist)
266{
267 struct sh_mobile_lcdc_chan *ch = info->par;
268 unsigned int nr_pages_max = info->fix.smem_len >> PAGE_SHIFT;
269 struct page *page;
270 int nr_pages = 0;
271
272 sg_init_table(ch->sglist, nr_pages_max);
273
274 list_for_each_entry(page, pagelist, lru)
275 sg_set_page(&ch->sglist[nr_pages++], page, PAGE_SIZE, 0);
276
277 return nr_pages;
278}
279
8564557a
MD		 280static void sh_mobile_lcdc_deferred_io(struct fb_info *info,
281 struct list_head *pagelist)
282{
283 struct sh_mobile_lcdc_chan *ch = info->par;
284
285 /* enable clocks before accessing hardware */
286 sh_mobile_lcdc_clk_on(ch->lcdc);
287
5c1a56b5
PM		 288 /*
289 * It's possible to get here without anything on the pagelist via
290 * sh_mobile_lcdc_deferred_io_touch() or via a userspace fsync()
291 * invocation. In the former case, the acceleration routines are
292 * stepped in to when using the framebuffer console causing the
293 * workqueue to be scheduled without any dirty pages on the list.
294 *
295 * Despite this, a panel update is still needed given that the
296 * acceleration routines have their own methods for writing in
297 * that still need to be updated.
298 *
299 * The fsync() and empty pagelist case could be optimized for,
300 * but we don't bother, as any application exhibiting such
301 * behaviour is fundamentally broken anyways.
302 */
303 if (!list_empty(pagelist)) {
304 unsigned int nr_pages = sh_mobile_lcdc_sginit(info, pagelist);
305
306 /* trigger panel update */
307 dma_map_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
308 lcdc_write_chan(ch, LDSM2R, 1);
309 dma_unmap_sg(info->dev, ch->sglist, nr_pages, DMA_TO_DEVICE);
310 } else
311 lcdc_write_chan(ch, LDSM2R, 1);
8564557a
MD		 312}
313
314static void sh_mobile_lcdc_deferred_io_touch(struct fb_info *info)
315{
316 struct fb_deferred_io *fbdefio = info->fbdefio;
317
318 if (fbdefio)
319 schedule_delayed_work(&info->deferred_work, fbdefio->delay);
320}
321
322static irqreturn_t sh_mobile_lcdc_irq(int irq, void *data)
323{
324 struct sh_mobile_lcdc_priv *priv = data;
2feb075a 325 struct sh_mobile_lcdc_chan *ch;
8564557a 326 unsigned long tmp;
9dd38819 327 unsigned long ldintr;
2feb075a
MD		 328 int is_sub;
329 int k;
8564557a
MD		 330
331 /* acknowledge interrupt */
9dd38819
PE		 332 ldintr = tmp = lcdc_read(priv, _LDINTR);
333 /*
334 * disable further VSYNC End IRQs, preserve all other enabled IRQs,
335 * write 0 to bits 0-6 to ack all triggered IRQs.
336 */
337 tmp &= 0xffffff00 & ~LDINTR_VEE;
8564557a
MD		 338 lcdc_write(priv, _LDINTR, tmp);
339
2feb075a
MD		 340 /* figure out if this interrupt is for main or sub lcd */
341 is_sub = (lcdc_read(priv, _LDSR) & (1 << 10)) ? 1 : 0;
342
9dd38819 343 /* wake up channel and disable clocks */
2feb075a
MD		 344 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
345 ch = &priv->ch[k];
346
347 if (!ch->enabled)
348 continue;
349
9dd38819
PE		 350 /* Frame Start */
351 if (ldintr & LDINTR_FS) {
352 if (is_sub == lcdc_chan_is_sublcd(ch)) {
353 ch->frame_end = 1;
354 wake_up(&ch->frame_end_wait);
2feb075a 355
9dd38819
PE		 356 sh_mobile_lcdc_clk_off(priv);
357 }
358 }
359
360 /* VSYNC End */
361 if (ldintr & LDINTR_VES) {
a6f15ade 362 unsigned long ldrcntr = lcdc_read(priv, _LDRCNTR);
9dd38819 363 /* Set the source address for the next refresh */
a6f15ade
PE		 364 lcdc_write_chan_mirror(ch, LDSA1R, ch->dma_handle +
365 ch->new_pan_offset);
366 if (lcdc_chan_is_sublcd(ch))
367 lcdc_write(ch->lcdc, _LDRCNTR,
368 ldrcntr ^ LDRCNTR_SRS);
369 else
370 lcdc_write(ch->lcdc, _LDRCNTR,
371 ldrcntr ^ LDRCNTR_MRS);
9dd38819 372 ch->pan_offset = ch->new_pan_offset;
2feb075a
MD		 373 }
374 }
375
8564557a
MD		 376 return IRQ_HANDLED;
377}
378
cfb4f5d1
MD		 379static void sh_mobile_lcdc_start_stop(struct sh_mobile_lcdc_priv *priv,
380 int start)
381{
382 unsigned long tmp = lcdc_read(priv, _LDCNT2R);
383 int k;
384
385 /* start or stop the lcdc */
386 if (start)
387 lcdc_write(priv, _LDCNT2R, tmp | START_LCDC);
388 else
389 lcdc_write(priv, _LDCNT2R, tmp & ~START_LCDC);
390
391 /* wait until power is applied/stopped on all channels */
392 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
393 if (lcdc_read(priv, _LDCNT2R) & priv->ch[k].enabled)
394 while (1) {
395 tmp = lcdc_read_chan(&priv->ch[k], LDPMR) & 3;
396 if (start && tmp == 3)
397 break;
398 if (!start && tmp == 0)
399 break;
400 cpu_relax();
401 }
402
403 if (!start)
404 lcdc_write(priv, _LDDCKSTPR, 1); /* stop dotclock */
405}
406
407static int sh_mobile_lcdc_start(struct sh_mobile_lcdc_priv *priv)
408{
409 struct sh_mobile_lcdc_chan *ch;
410 struct fb_videomode *lcd_cfg;
411 struct sh_mobile_lcdc_board_cfg *board_cfg;
412 unsigned long tmp;
413 int k, m;
414 int ret = 0;
415
8564557a
MD		 416 /* enable clocks before accessing the hardware */
417 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
418 if (priv->ch[k].enabled)
419 sh_mobile_lcdc_clk_on(priv);
420
cfb4f5d1
MD		 421 /* reset */
422 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) | LCDC_RESET);
423 lcdc_wait_bit(priv, _LDCNT2R, LCDC_RESET, 0);
424
425 /* enable LCDC channels */
426 tmp = lcdc_read(priv, _LDCNT2R);
427 tmp |= priv->ch[0].enabled;
428 tmp |= priv->ch[1].enabled;
429 lcdc_write(priv, _LDCNT2R, tmp);
430
431 /* read data from external memory, avoid using the BEU for now */
432 lcdc_write(priv, _LDCNT2R, lcdc_read(priv, _LDCNT2R) & ~DISPLAY_BEU);
433
434 /* stop the lcdc first */
435 sh_mobile_lcdc_start_stop(priv, 0);
436
437 /* configure clocks */
438 tmp = priv->lddckr;
439 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
440 ch = &priv->ch[k];
441
442 if (!priv->ch[k].enabled)
443 continue;
444
445 m = ch->cfg.clock_divider;
446 if (!m)
447 continue;
448
449 if (m == 1)
450 m = 1 << 6;
451 tmp |= m << (lcdc_chan_is_sublcd(ch) ? 8 : 0);
452
453 lcdc_write_chan(ch, LDDCKPAT1R, 0x00000000);
454 lcdc_write_chan(ch, LDDCKPAT2R, (1 << (m/2)) - 1);
455 }
456
457 lcdc_write(priv, _LDDCKR, tmp);
458
459 /* start dotclock again */
460 lcdc_write(priv, _LDDCKSTPR, 0);
461 lcdc_wait_bit(priv, _LDDCKSTPR, ~0, 0);
462
8564557a 463 /* interrupts are disabled to begin with */
cfb4f5d1
MD		 464 lcdc_write(priv, _LDINTR, 0);
465
466 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
467 ch = &priv->ch[k];
468 lcd_cfg = &ch->cfg.lcd_cfg;
469
470 if (!ch->enabled)
471 continue;
472
473 tmp = ch->ldmt1r_value;
474 tmp |= (lcd_cfg->sync & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1 << 28;
475 tmp |= (lcd_cfg->sync & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1 << 27;
f400f510
MD		 476 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWPOL) ? 1 << 26 : 0;
477 tmp |= (ch->cfg.flags & LCDC_FLAGS_DIPOL) ? 1 << 25 : 0;
478 tmp |= (ch->cfg.flags & LCDC_FLAGS_DAPOL) ? 1 << 24 : 0;
479 tmp |= (ch->cfg.flags & LCDC_FLAGS_HSCNT) ? 1 << 17 : 0;
480 tmp |= (ch->cfg.flags & LCDC_FLAGS_DWCNT) ? 1 << 16 : 0;
cfb4f5d1
MD		 481 lcdc_write_chan(ch, LDMT1R, tmp);
482
483 /* setup SYS bus */
484 lcdc_write_chan(ch, LDMT2R, ch->cfg.sys_bus_cfg.ldmt2r);
485 lcdc_write_chan(ch, LDMT3R, ch->cfg.sys_bus_cfg.ldmt3r);
486
487 /* horizontal configuration */
488 tmp = lcd_cfg->xres + lcd_cfg->hsync_len;
489 tmp += lcd_cfg->left_margin;
490 tmp += lcd_cfg->right_margin;
491 tmp /= 8; /* HTCN */
492 tmp |= (lcd_cfg->xres / 8) << 16; /* HDCN */
493 lcdc_write_chan(ch, LDHCNR, tmp);
494
495 tmp = lcd_cfg->xres;
496 tmp += lcd_cfg->right_margin;
497 tmp /= 8; /* HSYNP */
498 tmp |= (lcd_cfg->hsync_len / 8) << 16; /* HSYNW */
499 lcdc_write_chan(ch, LDHSYNR, tmp);
500
501 /* power supply */
502 lcdc_write_chan(ch, LDPMR, 0);
503
504 /* vertical configuration */
505 tmp = lcd_cfg->yres + lcd_cfg->vsync_len;
506 tmp += lcd_cfg->upper_margin;
507 tmp += lcd_cfg->lower_margin; /* VTLN */
508 tmp |= lcd_cfg->yres << 16; /* VDLN */
509 lcdc_write_chan(ch, LDVLNR, tmp);
510
511 tmp = lcd_cfg->yres;
512 tmp += lcd_cfg->lower_margin; /* VSYNP */
513 tmp |= lcd_cfg->vsync_len << 16; /* VSYNW */
514 lcdc_write_chan(ch, LDVSYNR, tmp);
515
516 board_cfg = &ch->cfg.board_cfg;
517 if (board_cfg->setup_sys)
518 ret = board_cfg->setup_sys(board_cfg->board_data, ch,
519 &sh_mobile_lcdc_sys_bus_ops);
520 if (ret)
521 return ret;
522 }
523
cfb4f5d1
MD		 524 /* word and long word swap */
525 lcdc_write(priv, _LDDDSR, lcdc_read(priv, _LDDDSR) | 6);
526
527 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
528 ch = &priv->ch[k];
529
530 if (!priv->ch[k].enabled)
531 continue;
532
533 /* set bpp format in PKF[4:0] */
534 tmp = lcdc_read_chan(ch, LDDFR);
535 tmp &= ~(0x0001001f);
e33afddc 536 tmp |= (ch->info->var.bits_per_pixel == 16) ? 3 : 0;
cfb4f5d1
MD		 537 lcdc_write_chan(ch, LDDFR, tmp);
538
539 /* point out our frame buffer */
e33afddc 540 lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
cfb4f5d1
MD		 541
542 /* set line size */
e33afddc 543 lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
cfb4f5d1 544
8564557a
MD		 545 /* setup deferred io if SYS bus */
546 tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
547 if (ch->ldmt1r_value & (1 << 12) && tmp) {
548 ch->defio.deferred_io = sh_mobile_lcdc_deferred_io;
549 ch->defio.delay = msecs_to_jiffies(tmp);
e33afddc
PM		 550 ch->info->fbdefio = &ch->defio;
551 fb_deferred_io_init(ch->info);
8564557a
MD		 552
553 /* one-shot mode */
554 lcdc_write_chan(ch, LDSM1R, 1);
555
556 /* enable "Frame End Interrupt Enable" bit */
557 lcdc_write(priv, _LDINTR, LDINTR_FE);
558
559 } else {
560 /* continuous read mode */
561 lcdc_write_chan(ch, LDSM1R, 0);
562 }
cfb4f5d1
MD		 563 }
564
565 /* display output */
566 lcdc_write(priv, _LDCNT1R, LCDC_ENABLE);
567
568 /* start the lcdc */
569 sh_mobile_lcdc_start_stop(priv, 1);
8e9bb19e 570 priv->started = 1;
cfb4f5d1
MD		 571
572 /* tell the board code to enable the panel */
573 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
574 ch = &priv->ch[k];
21bc1f02
MD		 575 if (!ch->enabled)
576 continue;
577
cfb4f5d1
MD		 578 board_cfg = &ch->cfg.board_cfg;
579 if (board_cfg->display_on)
580 board_cfg->display_on(board_cfg->board_data);
581 }
582
583 return 0;
584}
585
586static void sh_mobile_lcdc_stop(struct sh_mobile_lcdc_priv *priv)
587{
588 struct sh_mobile_lcdc_chan *ch;
589 struct sh_mobile_lcdc_board_cfg *board_cfg;
590 int k;
591
2feb075a 592 /* clean up deferred io and ask board code to disable panel */
cfb4f5d1
MD		 593 for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
594 ch = &priv->ch[k];
21bc1f02
MD		 595 if (!ch->enabled)
596 continue;
8564557a 597
2feb075a
MD		 598 /* deferred io mode:
599 * flush frame, and wait for frame end interrupt
600 * clean up deferred io and enable clock
601 */
e33afddc 602 if (ch->info->fbdefio) {
2feb075a 603 ch->frame_end = 0;
e33afddc 604 schedule_delayed_work(&ch->info->deferred_work, 0);
2feb075a 605 wait_event(ch->frame_end_wait, ch->frame_end);
e33afddc
PM		 606 fb_deferred_io_cleanup(ch->info);
607 ch->info->fbdefio = NULL;
2feb075a 608 sh_mobile_lcdc_clk_on(priv);
8564557a 609 }
2feb075a
MD		 610
611 board_cfg = &ch->cfg.board_cfg;
612 if (board_cfg->display_off)
613 board_cfg->display_off(board_cfg->board_data);
cfb4f5d1
MD		 614 }
615
616 /* stop the lcdc */
8e9bb19e
MD		 617 if (priv->started) {
618 sh_mobile_lcdc_start_stop(priv, 0);
619 priv->started = 0;
620 }
b51339ff 621
8564557a
MD		 622 /* stop clocks */
623 for (k = 0; k < ARRAY_SIZE(priv->ch); k++)
624 if (priv->ch[k].enabled)
625 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 626}
627
628static int sh_mobile_lcdc_check_interface(struct sh_mobile_lcdc_chan *ch)
629{
630 int ifm, miftyp;
631
632 switch (ch->cfg.interface_type) {
633 case RGB8: ifm = 0; miftyp = 0; break;
634 case RGB9: ifm = 0; miftyp = 4; break;
635 case RGB12A: ifm = 0; miftyp = 5; break;
636 case RGB12B: ifm = 0; miftyp = 6; break;
637 case RGB16: ifm = 0; miftyp = 7; break;
638 case RGB18: ifm = 0; miftyp = 10; break;
639 case RGB24: ifm = 0; miftyp = 11; break;
640 case SYS8A: ifm = 1; miftyp = 0; break;
641 case SYS8B: ifm = 1; miftyp = 1; break;
642 case SYS8C: ifm = 1; miftyp = 2; break;
643 case SYS8D: ifm = 1; miftyp = 3; break;
644 case SYS9: ifm = 1; miftyp = 4; break;
645 case SYS12: ifm = 1; miftyp = 5; break;
646 case SYS16A: ifm = 1; miftyp = 7; break;
647 case SYS16B: ifm = 1; miftyp = 8; break;
648 case SYS16C: ifm = 1; miftyp = 9; break;
649 case SYS18: ifm = 1; miftyp = 10; break;
650 case SYS24: ifm = 1; miftyp = 11; break;
651 default: goto bad;
652 }
653
654 /* SUBLCD only supports SYS interface */
655 if (lcdc_chan_is_sublcd(ch)) {
656 if (ifm == 0)
657 goto bad;
658 else
659 ifm = 0;
660 }
661
662 ch->ldmt1r_value = (ifm << 12) | miftyp;
663 return 0;
664 bad:
665 return -EINVAL;
666}
667
b51339ff
MD		 668static int sh_mobile_lcdc_setup_clocks(struct platform_device *pdev,
669 int clock_source,
cfb4f5d1
MD		 670 struct sh_mobile_lcdc_priv *priv)
671{
672 char *str;
673 int icksel;
674
675 switch (clock_source) {
676 case LCDC_CLK_BUS: str = "bus_clk"; icksel = 0; break;
677 case LCDC_CLK_PERIPHERAL: str = "peripheral_clk"; icksel = 1; break;
678 case LCDC_CLK_EXTERNAL: str = NULL; icksel = 2; break;
679 default:
680 return -EINVAL;
681 }
682
683 priv->lddckr = icksel << 16;
684
685 if (str) {
b51339ff
MD		 686 priv->dot_clk = clk_get(&pdev->dev, str);
687 if (IS_ERR(priv->dot_clk)) {
688 dev_err(&pdev->dev, "cannot get dot clock %s\n", str);
b51339ff 689 return PTR_ERR(priv->dot_clk);
cfb4f5d1 690 }
cfb4f5d1 691 }
0246c471
MD		 692 atomic_set(&priv->hw_usecnt, -1);
693
694 /* Runtime PM support involves two step for this driver:
695 * 1) Enable Runtime PM
696 * 2) Force Runtime PM Resume since hardware is accessed from probe()
697 */
698 pm_runtime_enable(priv->dev);
699 pm_runtime_resume(priv->dev);
cfb4f5d1
MD		 700 return 0;
701}
702
703static int sh_mobile_lcdc_setcolreg(u_int regno,
704 u_int red, u_int green, u_int blue,
705 u_int transp, struct fb_info *info)
706{
707 u32 *palette = info->pseudo_palette;
708
709 if (regno >= PALETTE_NR)
710 return -EINVAL;
711
712 /* only FB_VISUAL_TRUECOLOR supported */
713
714 red >>= 16 - info->var.red.length;
715 green >>= 16 - info->var.green.length;
716 blue >>= 16 - info->var.blue.length;
717 transp >>= 16 - info->var.transp.length;
718
719 palette[regno] = (red << info->var.red.offset) |
720 (green << info->var.green.offset) |
721 (blue << info->var.blue.offset) |
722 (transp << info->var.transp.offset);
723
724 return 0;
725}
726
727static struct fb_fix_screeninfo sh_mobile_lcdc_fix = {
728 .id = "SH Mobile LCDC",
729 .type = FB_TYPE_PACKED_PIXELS,
730 .visual = FB_VISUAL_TRUECOLOR,
731 .accel = FB_ACCEL_NONE,
9dd38819
PE		 732 .xpanstep = 0,
733 .ypanstep = 1,
734 .ywrapstep = 0,
cfb4f5d1
MD		 735};
736
8564557a
MD		 737static void sh_mobile_lcdc_fillrect(struct fb_info *info,
738 const struct fb_fillrect *rect)
739{
740 sys_fillrect(info, rect);
741 sh_mobile_lcdc_deferred_io_touch(info);
742}
743
744static void sh_mobile_lcdc_copyarea(struct fb_info *info,
745 const struct fb_copyarea *area)
746{
747 sys_copyarea(info, area);
748 sh_mobile_lcdc_deferred_io_touch(info);
749}
750
751static void sh_mobile_lcdc_imageblit(struct fb_info *info,
752 const struct fb_image *image)
753{
754 sys_imageblit(info, image);
755 sh_mobile_lcdc_deferred_io_touch(info);
756}
757
9dd38819
PE		 758static int sh_mobile_fb_pan_display(struct fb_var_screeninfo *var,
759 struct fb_info *info)
760{
761 struct sh_mobile_lcdc_chan *ch = info->par;
762
763 if (info->var.xoffset == var->xoffset &&
764 info->var.yoffset == var->yoffset)
765 return 0; /* No change, do nothing */
766
767 ch->new_pan_offset = (var->yoffset * info->fix.line_length) +
768 (var->xoffset * (info->var.bits_per_pixel / 8));
769
770 if (ch->new_pan_offset != ch->pan_offset) {
771 unsigned long ldintr;
772 ldintr = lcdc_read(ch->lcdc, _LDINTR);
773 ldintr |= LDINTR_VEE;
774 lcdc_write(ch->lcdc, _LDINTR, ldintr);
775 sh_mobile_lcdc_deferred_io_touch(info);
776 }
777
778 return 0;
779}
780
cfb4f5d1 781static struct fb_ops sh_mobile_lcdc_ops = {
9dd38819 782 .owner = THIS_MODULE,
cfb4f5d1 783 .fb_setcolreg = sh_mobile_lcdc_setcolreg,
2540c111
MD		 784 .fb_read = fb_sys_read,
785 .fb_write = fb_sys_write,
8564557a
MD		 786 .fb_fillrect = sh_mobile_lcdc_fillrect,
787 .fb_copyarea = sh_mobile_lcdc_copyarea,
788 .fb_imageblit = sh_mobile_lcdc_imageblit,
9dd38819 789 .fb_pan_display = sh_mobile_fb_pan_display,
cfb4f5d1
MD		 790};
791
792static int sh_mobile_lcdc_set_bpp(struct fb_var_screeninfo *var, int bpp)
793{
794 switch (bpp) {
795 case 16: /* PKF[4:0] = 00011 - RGB 565 */
796 var->red.offset = 11;
797 var->red.length = 5;
798 var->green.offset = 5;
799 var->green.length = 6;
800 var->blue.offset = 0;
801 var->blue.length = 5;
802 var->transp.offset = 0;
803 var->transp.length = 0;
804 break;
805
806 case 32: /* PKF[4:0] = 00000 - RGB 888
807 * sh7722 pdf says 00RRGGBB but reality is GGBB00RR
808 * this may be because LDDDSR has word swap enabled..
809 */
810 var->red.offset = 0;
811 var->red.length = 8;
812 var->green.offset = 24;
813 var->green.length = 8;
814 var->blue.offset = 16;
815 var->blue.length = 8;
816 var->transp.offset = 0;
817 var->transp.length = 0;
818 break;
819 default:
820 return -EINVAL;
821 }
822 var->bits_per_pixel = bpp;
823 var->red.msb_right = 0;
824 var->green.msb_right = 0;
825 var->blue.msb_right = 0;
826 var->transp.msb_right = 0;
827 return 0;
828}
829
2feb075a
MD		 830static int sh_mobile_lcdc_suspend(struct device *dev)
831{
832 struct platform_device *pdev = to_platform_device(dev);
833
834 sh_mobile_lcdc_stop(platform_get_drvdata(pdev));
835 return 0;
836}
837
838static int sh_mobile_lcdc_resume(struct device *dev)
839{
840 struct platform_device *pdev = to_platform_device(dev);
841
842 return sh_mobile_lcdc_start(platform_get_drvdata(pdev));
843}
844
0246c471
MD		 845static int sh_mobile_lcdc_runtime_suspend(struct device *dev)
846{
847 struct platform_device *pdev = to_platform_device(dev);
848 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
849 struct sh_mobile_lcdc_chan *ch;
850 int k, n;
851
852 /* save per-channel registers */
853 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
854 ch = &p->ch[k];
855 if (!ch->enabled)
856 continue;
857 for (n = 0; n < NR_CH_REGS; n++)
858 ch->saved_ch_regs[n] = lcdc_read_chan(ch, n);
859 }
860
861 /* save shared registers */
862 for (n = 0; n < NR_SHARED_REGS; n++)
863 p->saved_shared_regs[n] = lcdc_read(p, lcdc_shared_regs[n]);
864
865 /* turn off LCDC hardware */
866 lcdc_write(p, _LDCNT1R, 0);
867 return 0;
868}
869
870static int sh_mobile_lcdc_runtime_resume(struct device *dev)
871{
872 struct platform_device *pdev = to_platform_device(dev);
873 struct sh_mobile_lcdc_priv *p = platform_get_drvdata(pdev);
874 struct sh_mobile_lcdc_chan *ch;
875 int k, n;
876
877 /* restore per-channel registers */
878 for (k = 0; k < ARRAY_SIZE(p->ch); k++) {
879 ch = &p->ch[k];
880 if (!ch->enabled)
881 continue;
882 for (n = 0; n < NR_CH_REGS; n++)
883 lcdc_write_chan(ch, n, ch->saved_ch_regs[n]);
884 }
885
886 /* restore shared registers */
887 for (n = 0; n < NR_SHARED_REGS; n++)
888 lcdc_write(p, lcdc_shared_regs[n], p->saved_shared_regs[n]);
889
890 return 0;
891}
892
47145210 893static const struct dev_pm_ops sh_mobile_lcdc_dev_pm_ops = {
2feb075a
MD		 894 .suspend = sh_mobile_lcdc_suspend,
895 .resume = sh_mobile_lcdc_resume,
0246c471
MD		 896 .runtime_suspend = sh_mobile_lcdc_runtime_suspend,
897 .runtime_resume = sh_mobile_lcdc_runtime_resume,
2feb075a
MD		 898};
899
cfb4f5d1
MD		 900static int sh_mobile_lcdc_remove(struct platform_device *pdev);
901
902static int __init sh_mobile_lcdc_probe(struct platform_device *pdev)
903{
904 struct fb_info *info;
905 struct sh_mobile_lcdc_priv *priv;
906 struct sh_mobile_lcdc_info *pdata;
907 struct sh_mobile_lcdc_chan_cfg *cfg;
908 struct resource *res;
909 int error;
910 void *buf;
911 int i, j;
912
913 if (!pdev->dev.platform_data) {
914 dev_err(&pdev->dev, "no platform data defined\n");
915 error = -EINVAL;
916 goto err0;
917 }
918
919 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8564557a
MD		 920 i = platform_get_irq(pdev, 0);
921 if (!res || i < 0) {
922 dev_err(&pdev->dev, "cannot get platform resources\n");
cfb4f5d1
MD		 923 error = -ENOENT;
924 goto err0;
925 }
926
927 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
928 if (!priv) {
929 dev_err(&pdev->dev, "cannot allocate device data\n");
930 error = -ENOMEM;
931 goto err0;
932 }
933
8564557a 934 error = request_irq(i, sh_mobile_lcdc_irq, IRQF_DISABLED,
7ad33e74 935 dev_name(&pdev->dev), priv);
8564557a
MD		 936 if (error) {
937 dev_err(&pdev->dev, "unable to request irq\n");
938 goto err1;
939 }
940
941 priv->irq = i;
0246c471 942 priv->dev = &pdev->dev;
cfb4f5d1
MD		 943 platform_set_drvdata(pdev, priv);
944 pdata = pdev->dev.platform_data;
945
946 j = 0;
947 for (i = 0; i < ARRAY_SIZE(pdata->ch); i++) {
948 priv->ch[j].lcdc = priv;
949 memcpy(&priv->ch[j].cfg, &pdata->ch[i], sizeof(pdata->ch[i]));
950
951 error = sh_mobile_lcdc_check_interface(&priv->ch[i]);
952 if (error) {
953 dev_err(&pdev->dev, "unsupported interface type\n");
954 goto err1;
955 }
2feb075a 956 init_waitqueue_head(&priv->ch[i].frame_end_wait);
9dd38819
PE		 957 priv->ch[j].pan_offset = 0;
958 priv->ch[j].new_pan_offset = 0;
cfb4f5d1
MD		 959
960 switch (pdata->ch[i].chan) {
961 case LCDC_CHAN_MAINLCD:
962 priv->ch[j].enabled = 1 << 1;
963 priv->ch[j].reg_offs = lcdc_offs_mainlcd;
964 j++;
965 break;
966 case LCDC_CHAN_SUBLCD:
967 priv->ch[j].enabled = 1 << 2;
968 priv->ch[j].reg_offs = lcdc_offs_sublcd;
969 j++;
970 break;
971 }
972 }
973
974 if (!j) {
975 dev_err(&pdev->dev, "no channels defined\n");
976 error = -EINVAL;
977 goto err1;
978 }
979
b51339ff 980 error = sh_mobile_lcdc_setup_clocks(pdev, pdata->clock_source, priv);
cfb4f5d1
MD		 981 if (error) {
982 dev_err(&pdev->dev, "unable to setup clocks\n");
983 goto err1;
984 }
985
cfb4f5d1
MD		 986 priv->base = ioremap_nocache(res->start, (res->end - res->start) + 1);
987
988 for (i = 0; i < j; i++) {
cfb4f5d1
MD		 989 cfg = &priv->ch[i].cfg;
990
e33afddc
PM		 991 priv->ch[i].info = framebuffer_alloc(0, &pdev->dev);
992 if (!priv->ch[i].info) {
993 dev_err(&pdev->dev, "unable to allocate fb_info\n");
994 error = -ENOMEM;
995 break;
996 }
997
998 info = priv->ch[i].info;
cfb4f5d1
MD		 999 info->fbops = &sh_mobile_lcdc_ops;
1000 info->var.xres = info->var.xres_virtual = cfg->lcd_cfg.xres;
9dd38819
PE		 1001 info->var.yres = cfg->lcd_cfg.yres;
1002 /* Default Y virtual resolution is 2x panel size */
1003 info->var.yres_virtual = info->var.yres * 2;
ce9c008c
MD		 1004 info->var.width = cfg->lcd_size_cfg.width;
1005 info->var.height = cfg->lcd_size_cfg.height;
cfb4f5d1
MD		 1006 info->var.activate = FB_ACTIVATE_NOW;
1007 error = sh_mobile_lcdc_set_bpp(&info->var, cfg->bpp);
1008 if (error)
1009 break;
1010
1011 info->fix = sh_mobile_lcdc_fix;
1012 info->fix.line_length = cfg->lcd_cfg.xres * (cfg->bpp / 8);
9dd38819
PE		 1013 info->fix.smem_len = info->fix.line_length *
1014 info->var.yres_virtual;
cfb4f5d1
MD		 1015
1016 buf = dma_alloc_coherent(&pdev->dev, info->fix.smem_len,
1017 &priv->ch[i].dma_handle, GFP_KERNEL);
1018 if (!buf) {
1019 dev_err(&pdev->dev, "unable to allocate buffer\n");
1020 error = -ENOMEM;
1021 break;
1022 }
1023
1024 info->pseudo_palette = &priv->ch[i].pseudo_palette;
1025 info->flags = FBINFO_FLAG_DEFAULT;
1026
1027 error = fb_alloc_cmap(&info->cmap, PALETTE_NR, 0);
1028 if (error < 0) {
1029 dev_err(&pdev->dev, "unable to allocate cmap\n");
1030 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1031 buf, priv->ch[i].dma_handle);
1032 break;
1033 }
1034
1035 memset(buf, 0, info->fix.smem_len);
1036 info->fix.smem_start = priv->ch[i].dma_handle;
1037 info->screen_base = buf;
1038 info->device = &pdev->dev;
8564557a 1039 info->par = &priv->ch[i];
cfb4f5d1
MD		 1040 }
1041
1042 if (error)
1043 goto err1;
1044
1045 error = sh_mobile_lcdc_start(priv);
1046 if (error) {
1047 dev_err(&pdev->dev, "unable to start hardware\n");
1048 goto err1;
1049 }
1050
1051 for (i = 0; i < j; i++) {
1c6a307a
PM		 1052 struct sh_mobile_lcdc_chan *ch = priv->ch + i;
1053
e33afddc 1054 info = ch->info;
1c6a307a
PM		 1055
1056 if (info->fbdefio) {
1057 priv->ch->sglist = vmalloc(sizeof(struct scatterlist) *
1058 info->fix.smem_len >> PAGE_SHIFT);
1059 if (!priv->ch->sglist) {
1060 dev_err(&pdev->dev, "cannot allocate sglist\n");
1061 goto err1;
1062 }
1063 }
1064
1065 error = register_framebuffer(info);
cfb4f5d1
MD		 1066 if (error < 0)
1067 goto err1;
cfb4f5d1 1068
cfb4f5d1
MD		 1069 dev_info(info->dev,
1070 "registered %s/%s as %dx%d %dbpp.\n",
1071 pdev->name,
1c6a307a 1072 (ch->cfg.chan == LCDC_CHAN_MAINLCD) ?
cfb4f5d1 1073 "mainlcd" : "sublcd",
1c6a307a
PM		 1074 (int) ch->cfg.lcd_cfg.xres,
1075 (int) ch->cfg.lcd_cfg.yres,
1076 ch->cfg.bpp);
8564557a
MD		 1077
1078 /* deferred io mode: disable clock to save power */
1079 if (info->fbdefio)
1080 sh_mobile_lcdc_clk_off(priv);
cfb4f5d1
MD		 1081 }
1082
1083 return 0;
1084 err1:
1085 sh_mobile_lcdc_remove(pdev);
1086 err0:
1087 return error;
1088}
1089
1090static int sh_mobile_lcdc_remove(struct platform_device *pdev)
1091{
1092 struct sh_mobile_lcdc_priv *priv = platform_get_drvdata(pdev);
1093 struct fb_info *info;
1094 int i;
1095
1096 for (i = 0; i < ARRAY_SIZE(priv->ch); i++)
e33afddc
PM		 1097 if (priv->ch[i].info->dev)
1098 unregister_framebuffer(priv->ch[i].info);
cfb4f5d1
MD		 1099
1100 sh_mobile_lcdc_stop(priv);
1101
1102 for (i = 0; i < ARRAY_SIZE(priv->ch); i++) {
e33afddc 1103 info = priv->ch[i].info;
cfb4f5d1 1104
e33afddc 1105 if (!info || !info->device)
cfb4f5d1
MD		 1106 continue;
1107
1c6a307a
PM		 1108 if (priv->ch[i].sglist)
1109 vfree(priv->ch[i].sglist);
1110
cfb4f5d1
MD		 1111 dma_free_coherent(&pdev->dev, info->fix.smem_len,
1112 info->screen_base, priv->ch[i].dma_handle);
1113 fb_dealloc_cmap(&info->cmap);
e33afddc 1114 framebuffer_release(info);
cfb4f5d1
MD		 1115 }
1116
b51339ff
MD		 1117 if (priv->dot_clk)
1118 clk_put(priv->dot_clk);
0246c471
MD		 1119
1120 pm_runtime_disable(priv->dev);
cfb4f5d1
MD		 1121
1122 if (priv->base)
1123 iounmap(priv->base);
1124
8564557a
MD		 1125 if (priv->irq)
1126 free_irq(priv->irq, priv);
cfb4f5d1
MD		 1127 kfree(priv);
1128 return 0;
1129}
1130
1131static struct platform_driver sh_mobile_lcdc_driver = {
1132 .driver = {
1133 .name = "sh_mobile_lcdc_fb",
1134 .owner = THIS_MODULE,
2feb075a 1135 .pm = &sh_mobile_lcdc_dev_pm_ops,
cfb4f5d1
MD		 1136 },
1137 .probe = sh_mobile_lcdc_probe,
1138 .remove = sh_mobile_lcdc_remove,
1139};
1140
1141static int __init sh_mobile_lcdc_init(void)
1142{
1143 return platform_driver_register(&sh_mobile_lcdc_driver);
1144}
1145
1146static void __exit sh_mobile_lcdc_exit(void)
1147{
1148 platform_driver_unregister(&sh_mobile_lcdc_driver);
1149}
1150
1151module_init(sh_mobile_lcdc_init);
1152module_exit(sh_mobile_lcdc_exit);
1153
1154MODULE_DESCRIPTION("SuperH Mobile LCDC Framebuffer driver");
1155MODULE_AUTHOR("Magnus Damm <damm@opensource.se>");
1156MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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