Commit | Line | Data |
---|---|---|
7caa4342 D |
1 | /* |
2 | * SuperH Mobile MERAM Driver for SuperH Mobile LCDC Driver | |
3 | * | |
4 | * Copyright (c) 2011 Damian Hobson-Garcia <dhobsong@igel.co.jp> | |
5 | * Takanari Hayama <taki@igel.co.jp> | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | ||
7554340c | 12 | #include <linux/device.h> |
48110050 | 13 | #include <linux/err.h> |
6e729b41 | 14 | #include <linux/export.h> |
974d250b | 15 | #include <linux/genalloc.h> |
7554340c | 16 | #include <linux/io.h> |
7caa4342 D |
17 | #include <linux/kernel.h> |
18 | #include <linux/module.h> | |
7554340c | 19 | #include <linux/platform_device.h> |
17673778 | 20 | #include <linux/pm_runtime.h> |
7caa4342 | 21 | #include <linux/slab.h> |
7554340c | 22 | |
8a20974f | 23 | #include <video/sh_mobile_meram.h> |
7caa4342 | 24 | |
7554340c LP |
25 | /* ----------------------------------------------------------------------------- |
26 | * MERAM registers | |
27 | */ | |
28 | ||
f0a260fe LP |
29 | #define MEVCR1 0x4 |
30 | #define MEVCR1_RST (1 << 31) | |
31 | #define MEVCR1_WD (1 << 30) | |
32 | #define MEVCR1_AMD1 (1 << 29) | |
33 | #define MEVCR1_AMD0 (1 << 28) | |
34 | #define MEQSEL1 0x40 | |
35 | #define MEQSEL2 0x44 | |
36 | ||
37 | #define MExxCTL 0x400 | |
38 | #define MExxCTL_BV (1 << 31) | |
39 | #define MExxCTL_BSZ_SHIFT 28 | |
40 | #define MExxCTL_MSAR_MASK (0x7ff << MExxCTL_MSAR_SHIFT) | |
41 | #define MExxCTL_MSAR_SHIFT 16 | |
42 | #define MExxCTL_NXT_MASK (0x1f << MExxCTL_NXT_SHIFT) | |
43 | #define MExxCTL_NXT_SHIFT 11 | |
44 | #define MExxCTL_WD1 (1 << 10) | |
45 | #define MExxCTL_WD0 (1 << 9) | |
46 | #define MExxCTL_WS (1 << 8) | |
47 | #define MExxCTL_CB (1 << 7) | |
48 | #define MExxCTL_WBF (1 << 6) | |
49 | #define MExxCTL_WF (1 << 5) | |
50 | #define MExxCTL_RF (1 << 4) | |
51 | #define MExxCTL_CM (1 << 3) | |
52 | #define MExxCTL_MD_READ (1 << 0) | |
53 | #define MExxCTL_MD_WRITE (2 << 0) | |
54 | #define MExxCTL_MD_ICB_WB (3 << 0) | |
55 | #define MExxCTL_MD_ICB (4 << 0) | |
56 | #define MExxCTL_MD_FB (7 << 0) | |
57 | #define MExxCTL_MD_MASK (7 << 0) | |
58 | #define MExxBSIZE 0x404 | |
59 | #define MExxBSIZE_RCNT_SHIFT 28 | |
60 | #define MExxBSIZE_YSZM1_SHIFT 16 | |
61 | #define MExxBSIZE_XSZM1_SHIFT 0 | |
62 | #define MExxMNCF 0x408 | |
63 | #define MExxMNCF_KWBNM_SHIFT 28 | |
64 | #define MExxMNCF_KRBNM_SHIFT 24 | |
65 | #define MExxMNCF_BNM_SHIFT 16 | |
66 | #define MExxMNCF_XBV (1 << 15) | |
67 | #define MExxMNCF_CPL_YCBCR444 (1 << 12) | |
68 | #define MExxMNCF_CPL_YCBCR420 (2 << 12) | |
69 | #define MExxMNCF_CPL_YCBCR422 (3 << 12) | |
70 | #define MExxMNCF_CPL_MSK (3 << 12) | |
71 | #define MExxMNCF_BL (1 << 2) | |
72 | #define MExxMNCF_LNM_SHIFT 0 | |
73 | #define MExxSARA 0x410 | |
74 | #define MExxSARB 0x414 | |
75 | #define MExxSBSIZE 0x418 | |
76 | #define MExxSBSIZE_HDV (1 << 31) | |
77 | #define MExxSBSIZE_HSZ16 (0 << 28) | |
78 | #define MExxSBSIZE_HSZ32 (1 << 28) | |
79 | #define MExxSBSIZE_HSZ64 (2 << 28) | |
80 | #define MExxSBSIZE_HSZ128 (3 << 28) | |
81 | #define MExxSBSIZE_SBSIZZ_SHIFT 0 | |
82 | ||
83 | #define MERAM_MExxCTL_VAL(next, addr) \ | |
84 | ((((next) << MExxCTL_NXT_SHIFT) & MExxCTL_NXT_MASK) | \ | |
85 | (((addr) << MExxCTL_MSAR_SHIFT) & MExxCTL_MSAR_MASK)) | |
86 | #define MERAM_MExxBSIZE_VAL(rcnt, yszm1, xszm1) \ | |
87 | (((rcnt) << MExxBSIZE_RCNT_SHIFT) | \ | |
88 | ((yszm1) << MExxBSIZE_YSZM1_SHIFT) | \ | |
89 | ((xszm1) << MExxBSIZE_XSZM1_SHIFT)) | |
7caa4342 | 90 | |
762f7cc9 | 91 | static const unsigned long common_regs[] = { |
0b3bb77c DHG |
92 | MEVCR1, |
93 | MEQSEL1, | |
94 | MEQSEL2, | |
95 | }; | |
7554340c | 96 | #define MERAM_REGS_SIZE ARRAY_SIZE(common_regs) |
0b3bb77c | 97 | |
762f7cc9 | 98 | static const unsigned long icb_regs[] = { |
0b3bb77c DHG |
99 | MExxCTL, |
100 | MExxBSIZE, | |
101 | MExxMNCF, | |
102 | MExxSARA, | |
103 | MExxSARB, | |
104 | MExxSBSIZE, | |
105 | }; | |
106 | #define ICB_REGS_SIZE ARRAY_SIZE(icb_regs) | |
107 | ||
2a618e03 LP |
108 | /* |
109 | * sh_mobile_meram_icb - MERAM ICB information | |
110 | * @regs: Registers cache | |
48110050 | 111 | * @index: ICB index |
974d250b | 112 | * @offset: MERAM block offset |
48110050 | 113 | * @size: MERAM block size in KiB |
2a618e03 LP |
114 | * @cache_unit: Bytes to cache per ICB |
115 | * @pixelformat: Video pixel format of the data stored in the ICB | |
116 | * @current_reg: Which of Start Address Register A (0) or B (1) is in use | |
117 | */ | |
118 | struct sh_mobile_meram_icb { | |
119 | unsigned long regs[ICB_REGS_SIZE]; | |
48110050 | 120 | unsigned int index; |
974d250b LP |
121 | unsigned long offset; |
122 | unsigned int size; | |
2a618e03 | 123 | |
2a618e03 LP |
124 | unsigned int cache_unit; |
125 | unsigned int pixelformat; | |
126 | unsigned int current_reg; | |
127 | }; | |
128 | ||
7554340c LP |
129 | #define MERAM_ICB_NUM 32 |
130 | ||
48110050 LP |
131 | struct sh_mobile_meram_fb_plane { |
132 | struct sh_mobile_meram_icb *marker; | |
133 | struct sh_mobile_meram_icb *cache; | |
134 | }; | |
135 | ||
136 | struct sh_mobile_meram_fb_cache { | |
137 | unsigned int nplanes; | |
138 | struct sh_mobile_meram_fb_plane planes[2]; | |
139 | }; | |
140 | ||
2a618e03 LP |
141 | /* |
142 | * sh_mobile_meram_priv - MERAM device | |
143 | * @base: Registers base address | |
974d250b | 144 | * @meram: MERAM physical address |
2a618e03 LP |
145 | * @regs: Registers cache |
146 | * @lock: Protects used_icb and icbs | |
147 | * @used_icb: Bitmask of used ICBs | |
148 | * @icbs: ICBs | |
974d250b | 149 | * @pool: Allocation pool to manage the MERAM |
2a618e03 | 150 | */ |
0aa492be | 151 | struct sh_mobile_meram_priv { |
2a618e03 | 152 | void __iomem *base; |
974d250b | 153 | unsigned long meram; |
7554340c | 154 | unsigned long regs[MERAM_REGS_SIZE]; |
2a618e03 LP |
155 | |
156 | struct mutex lock; | |
157 | unsigned long used_icb; | |
7554340c | 158 | struct sh_mobile_meram_icb icbs[MERAM_ICB_NUM]; |
974d250b LP |
159 | |
160 | struct gen_pool *pool; | |
0aa492be DHG |
161 | }; |
162 | ||
7caa4342 | 163 | /* settings */ |
974d250b | 164 | #define MERAM_GRANULARITY 1024 |
7554340c LP |
165 | #define MERAM_SEC_LINE 15 |
166 | #define MERAM_LINE_WIDTH 2048 | |
7caa4342 | 167 | |
7554340c LP |
168 | /* ----------------------------------------------------------------------------- |
169 | * Registers access | |
7caa4342 D |
170 | */ |
171 | ||
f0a260fe | 172 | #define MERAM_ICB_OFFSET(base, idx, off) ((base) + (off) + (idx) * 0x20) |
7caa4342 | 173 | |
05432837 LP |
174 | static inline void meram_write_icb(void __iomem *base, unsigned int idx, |
175 | unsigned int off, unsigned long val) | |
7caa4342 D |
176 | { |
177 | iowrite32(val, MERAM_ICB_OFFSET(base, idx, off)); | |
178 | } | |
179 | ||
05432837 LP |
180 | static inline unsigned long meram_read_icb(void __iomem *base, unsigned int idx, |
181 | unsigned int off) | |
7caa4342 D |
182 | { |
183 | return ioread32(MERAM_ICB_OFFSET(base, idx, off)); | |
184 | } | |
185 | ||
05432837 LP |
186 | static inline void meram_write_reg(void __iomem *base, unsigned int off, |
187 | unsigned long val) | |
7caa4342 D |
188 | { |
189 | iowrite32(val, base + off); | |
190 | } | |
191 | ||
05432837 | 192 | static inline unsigned long meram_read_reg(void __iomem *base, unsigned int off) |
7caa4342 D |
193 | { |
194 | return ioread32(base + off); | |
195 | } | |
196 | ||
239921ec LP |
197 | /* ----------------------------------------------------------------------------- |
198 | * MERAM allocation and free | |
199 | */ | |
200 | ||
201 | static unsigned long meram_alloc(struct sh_mobile_meram_priv *priv, size_t size) | |
202 | { | |
203 | return gen_pool_alloc(priv->pool, size); | |
204 | } | |
205 | ||
206 | static void meram_free(struct sh_mobile_meram_priv *priv, unsigned long mem, | |
207 | size_t size) | |
208 | { | |
209 | gen_pool_free(priv->pool, mem, size); | |
210 | } | |
211 | ||
7554340c | 212 | /* ----------------------------------------------------------------------------- |
4a237177 | 213 | * LCDC cache planes allocation, init, cleanup and free |
7caa4342 D |
214 | */ |
215 | ||
48110050 | 216 | /* Allocate ICBs and MERAM for a plane. */ |
4a237177 LP |
217 | static int meram_plane_alloc(struct sh_mobile_meram_priv *priv, |
218 | struct sh_mobile_meram_fb_plane *plane, | |
219 | size_t size) | |
7caa4342 | 220 | { |
48110050 LP |
221 | unsigned long mem; |
222 | unsigned long idx; | |
7caa4342 | 223 | |
48110050 LP |
224 | idx = find_first_zero_bit(&priv->used_icb, 28); |
225 | if (idx == 28) | |
226 | return -ENOMEM; | |
227 | plane->cache = &priv->icbs[idx]; | |
7caa4342 | 228 | |
48110050 LP |
229 | idx = find_next_zero_bit(&priv->used_icb, 32, 28); |
230 | if (idx == 32) | |
231 | return -ENOMEM; | |
232 | plane->marker = &priv->icbs[idx]; | |
974d250b | 233 | |
239921ec | 234 | mem = meram_alloc(priv, size * 1024); |
974d250b LP |
235 | if (mem == 0) |
236 | return -ENOMEM; | |
237 | ||
48110050 LP |
238 | __set_bit(plane->marker->index, &priv->used_icb); |
239 | __set_bit(plane->cache->index, &priv->used_icb); | |
7caa4342 | 240 | |
48110050 LP |
241 | plane->marker->offset = mem - priv->meram; |
242 | plane->marker->size = size; | |
974d250b LP |
243 | |
244 | return 0; | |
7caa4342 D |
245 | } |
246 | ||
48110050 | 247 | /* Free ICBs and MERAM for a plane. */ |
4a237177 LP |
248 | static void meram_plane_free(struct sh_mobile_meram_priv *priv, |
249 | struct sh_mobile_meram_fb_plane *plane) | |
7caa4342 | 250 | { |
239921ec LP |
251 | meram_free(priv, priv->meram + plane->marker->offset, |
252 | plane->marker->size * 1024); | |
974d250b | 253 | |
48110050 LP |
254 | __clear_bit(plane->marker->index, &priv->used_icb); |
255 | __clear_bit(plane->cache->index, &priv->used_icb); | |
7caa4342 D |
256 | } |
257 | ||
7554340c | 258 | /* Is this a YCbCr(NV12, NV16 or NV24) colorspace? */ |
762f7cc9 | 259 | static int is_nvcolor(int cspace) |
3fedd2ac D |
260 | { |
261 | if (cspace == SH_MOBILE_MERAM_PF_NV || | |
2a618e03 | 262 | cspace == SH_MOBILE_MERAM_PF_NV24) |
3fedd2ac D |
263 | return 1; |
264 | return 0; | |
265 | } | |
7caa4342 | 266 | |
7554340c | 267 | /* Set the next address to fetch. */ |
762f7cc9 | 268 | static void meram_set_next_addr(struct sh_mobile_meram_priv *priv, |
48110050 | 269 | struct sh_mobile_meram_fb_cache *cache, |
762f7cc9 LP |
270 | unsigned long base_addr_y, |
271 | unsigned long base_addr_c) | |
7caa4342 | 272 | { |
48110050 | 273 | struct sh_mobile_meram_icb *icb = cache->planes[0].marker; |
7caa4342 D |
274 | unsigned long target; |
275 | ||
2a618e03 LP |
276 | icb->current_reg ^= 1; |
277 | target = icb->current_reg ? MExxSARB : MExxSARA; | |
7caa4342 D |
278 | |
279 | /* set the next address to fetch */ | |
48110050 | 280 | meram_write_icb(priv->base, cache->planes[0].cache->index, target, |
7caa4342 | 281 | base_addr_y); |
48110050 LP |
282 | meram_write_icb(priv->base, cache->planes[0].marker->index, target, |
283 | base_addr_y + cache->planes[0].marker->cache_unit); | |
284 | ||
285 | if (cache->nplanes == 2) { | |
286 | meram_write_icb(priv->base, cache->planes[1].cache->index, | |
287 | target, base_addr_c); | |
288 | meram_write_icb(priv->base, cache->planes[1].marker->index, | |
289 | target, base_addr_c + | |
290 | cache->planes[1].marker->cache_unit); | |
7caa4342 D |
291 | } |
292 | } | |
293 | ||
7554340c | 294 | /* Get the next ICB address. */ |
762f7cc9 | 295 | static void |
2a618e03 | 296 | meram_get_next_icb_addr(struct sh_mobile_meram_info *pdata, |
48110050 | 297 | struct sh_mobile_meram_fb_cache *cache, |
2a618e03 | 298 | unsigned long *icb_addr_y, unsigned long *icb_addr_c) |
7caa4342 | 299 | { |
48110050 | 300 | struct sh_mobile_meram_icb *icb = cache->planes[0].marker; |
7caa4342 D |
301 | unsigned long icb_offset; |
302 | ||
303 | if (pdata->addr_mode == SH_MOBILE_MERAM_MODE0) | |
2a618e03 | 304 | icb_offset = 0x80000000 | (icb->current_reg << 29); |
7caa4342 | 305 | else |
2a618e03 | 306 | icb_offset = 0xc0000000 | (icb->current_reg << 23); |
7caa4342 | 307 | |
48110050 LP |
308 | *icb_addr_y = icb_offset | (cache->planes[0].marker->index << 24); |
309 | if (cache->nplanes == 2) | |
310 | *icb_addr_c = icb_offset | |
311 | | (cache->planes[1].marker->index << 24); | |
7caa4342 D |
312 | } |
313 | ||
314 | #define MERAM_CALC_BYTECOUNT(x, y) \ | |
315 | (((x) * (y) + (MERAM_LINE_WIDTH - 1)) & ~(MERAM_LINE_WIDTH - 1)) | |
316 | ||
7554340c | 317 | /* Initialize MERAM. */ |
4a237177 LP |
318 | static int meram_plane_init(struct sh_mobile_meram_priv *priv, |
319 | struct sh_mobile_meram_fb_plane *plane, | |
320 | unsigned int xres, unsigned int yres, | |
321 | unsigned int *out_pitch) | |
7caa4342 | 322 | { |
48110050 | 323 | struct sh_mobile_meram_icb *marker = plane->marker; |
7caa4342 D |
324 | unsigned long total_byte_count = MERAM_CALC_BYTECOUNT(xres, yres); |
325 | unsigned long bnm; | |
05432837 LP |
326 | unsigned int lcdc_pitch; |
327 | unsigned int xpitch; | |
328 | unsigned int line_cnt; | |
329 | unsigned int save_lines; | |
7caa4342 D |
330 | |
331 | /* adjust pitch to 1024, 2048, 4096 or 8192 */ | |
332 | lcdc_pitch = (xres - 1) | 1023; | |
333 | lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 1); | |
334 | lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 2); | |
335 | lcdc_pitch += 1; | |
336 | ||
337 | /* derive settings */ | |
338 | if (lcdc_pitch == 8192 && yres >= 1024) { | |
339 | lcdc_pitch = xpitch = MERAM_LINE_WIDTH; | |
340 | line_cnt = total_byte_count >> 11; | |
341 | *out_pitch = xres; | |
48110050 | 342 | save_lines = plane->marker->size / 16 / MERAM_SEC_LINE; |
7caa4342 D |
343 | save_lines *= MERAM_SEC_LINE; |
344 | } else { | |
345 | xpitch = xres; | |
346 | line_cnt = yres; | |
347 | *out_pitch = lcdc_pitch; | |
48110050 | 348 | save_lines = plane->marker->size / (lcdc_pitch >> 10) / 2; |
7caa4342 D |
349 | save_lines &= 0xff; |
350 | } | |
351 | bnm = (save_lines - 1) << 16; | |
352 | ||
353 | /* TODO: we better to check if we have enough MERAM buffer size */ | |
354 | ||
355 | /* set up ICB */ | |
48110050 | 356 | meram_write_icb(priv->base, plane->cache->index, MExxBSIZE, |
7caa4342 | 357 | MERAM_MExxBSIZE_VAL(0x0, line_cnt - 1, xpitch - 1)); |
48110050 | 358 | meram_write_icb(priv->base, plane->marker->index, MExxBSIZE, |
7caa4342 D |
359 | MERAM_MExxBSIZE_VAL(0xf, line_cnt - 1, xpitch - 1)); |
360 | ||
48110050 LP |
361 | meram_write_icb(priv->base, plane->cache->index, MExxMNCF, bnm); |
362 | meram_write_icb(priv->base, plane->marker->index, MExxMNCF, bnm); | |
7caa4342 | 363 | |
48110050 LP |
364 | meram_write_icb(priv->base, plane->cache->index, MExxSBSIZE, xpitch); |
365 | meram_write_icb(priv->base, plane->marker->index, MExxSBSIZE, xpitch); | |
7caa4342 D |
366 | |
367 | /* save a cache unit size */ | |
48110050 LP |
368 | plane->cache->cache_unit = xres * save_lines; |
369 | plane->marker->cache_unit = xres * save_lines; | |
7caa4342 D |
370 | |
371 | /* | |
372 | * Set MERAM for framebuffer | |
373 | * | |
7caa4342 D |
374 | * we also chain the cache_icb and the marker_icb. |
375 | * we also split the allocated MERAM buffer between two ICBs. | |
376 | */ | |
48110050 LP |
377 | meram_write_icb(priv->base, plane->cache->index, MExxCTL, |
378 | MERAM_MExxCTL_VAL(plane->marker->index, marker->offset) | |
379 | | MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM | | |
f0a260fe | 380 | MExxCTL_MD_FB); |
48110050 LP |
381 | meram_write_icb(priv->base, plane->marker->index, MExxCTL, |
382 | MERAM_MExxCTL_VAL(plane->cache->index, marker->offset + | |
383 | plane->marker->size / 2) | | |
f0a260fe LP |
384 | MExxCTL_WD1 | MExxCTL_WD0 | MExxCTL_WS | MExxCTL_CM | |
385 | MExxCTL_MD_FB); | |
7caa4342 D |
386 | |
387 | return 0; | |
388 | } | |
389 | ||
4a237177 LP |
390 | static void meram_plane_cleanup(struct sh_mobile_meram_priv *priv, |
391 | struct sh_mobile_meram_fb_plane *plane) | |
7caa4342 D |
392 | { |
393 | /* disable ICB */ | |
48110050 | 394 | meram_write_icb(priv->base, plane->cache->index, MExxCTL, |
da6cf512 | 395 | MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF); |
48110050 | 396 | meram_write_icb(priv->base, plane->marker->index, MExxCTL, |
da6cf512 | 397 | MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF); |
2a618e03 | 398 | |
48110050 LP |
399 | plane->cache->cache_unit = 0; |
400 | plane->marker->cache_unit = 0; | |
7caa4342 D |
401 | } |
402 | ||
7554340c | 403 | /* ----------------------------------------------------------------------------- |
239921ec | 404 | * MERAM operations |
7caa4342 D |
405 | */ |
406 | ||
239921ec LP |
407 | unsigned long sh_mobile_meram_alloc(struct sh_mobile_meram_info *pdata, |
408 | size_t size) | |
409 | { | |
410 | struct sh_mobile_meram_priv *priv = pdata->priv; | |
411 | ||
412 | return meram_alloc(priv, size); | |
413 | } | |
414 | EXPORT_SYMBOL_GPL(sh_mobile_meram_alloc); | |
415 | ||
416 | void sh_mobile_meram_free(struct sh_mobile_meram_info *pdata, unsigned long mem, | |
417 | size_t size) | |
418 | { | |
419 | struct sh_mobile_meram_priv *priv = pdata->priv; | |
420 | ||
421 | meram_free(priv, mem, size); | |
422 | } | |
423 | EXPORT_SYMBOL_GPL(sh_mobile_meram_free); | |
424 | ||
4a237177 LP |
425 | /* Allocate memory for the ICBs and mark them as used. */ |
426 | static struct sh_mobile_meram_fb_cache * | |
427 | meram_cache_alloc(struct sh_mobile_meram_priv *priv, | |
428 | const struct sh_mobile_meram_cfg *cfg, | |
429 | int pixelformat) | |
430 | { | |
431 | unsigned int nplanes = is_nvcolor(pixelformat) ? 2 : 1; | |
432 | struct sh_mobile_meram_fb_cache *cache; | |
433 | int ret; | |
434 | ||
435 | cache = kzalloc(sizeof(*cache), GFP_KERNEL); | |
436 | if (cache == NULL) | |
437 | return ERR_PTR(-ENOMEM); | |
438 | ||
439 | cache->nplanes = nplanes; | |
440 | ||
441 | ret = meram_plane_alloc(priv, &cache->planes[0], | |
442 | cfg->icb[0].meram_size); | |
443 | if (ret < 0) | |
444 | goto error; | |
445 | ||
446 | cache->planes[0].marker->current_reg = 1; | |
447 | cache->planes[0].marker->pixelformat = pixelformat; | |
448 | ||
449 | if (cache->nplanes == 1) | |
450 | return cache; | |
451 | ||
452 | ret = meram_plane_alloc(priv, &cache->planes[1], | |
453 | cfg->icb[1].meram_size); | |
454 | if (ret < 0) { | |
455 | meram_plane_free(priv, &cache->planes[0]); | |
456 | goto error; | |
457 | } | |
458 | ||
459 | return cache; | |
460 | ||
461 | error: | |
462 | kfree(cache); | |
463 | return ERR_PTR(-ENOMEM); | |
464 | } | |
465 | ||
6e729b41 LP |
466 | void *sh_mobile_meram_cache_alloc(struct sh_mobile_meram_info *pdata, |
467 | const struct sh_mobile_meram_cfg *cfg, | |
468 | unsigned int xres, unsigned int yres, | |
469 | unsigned int pixelformat, unsigned int *pitch) | |
7caa4342 | 470 | { |
48110050 | 471 | struct sh_mobile_meram_fb_cache *cache; |
cdf88b90 LP |
472 | struct sh_mobile_meram_priv *priv = pdata->priv; |
473 | struct platform_device *pdev = pdata->pdev; | |
4a237177 | 474 | unsigned int nplanes = is_nvcolor(pixelformat) ? 2 : 1; |
05432837 | 475 | unsigned int out_pitch; |
7caa4342 | 476 | |
6e729b41 LP |
477 | if (priv == NULL) |
478 | return ERR_PTR(-ENODEV); | |
479 | ||
7caa4342 | 480 | if (pixelformat != SH_MOBILE_MERAM_PF_NV && |
3fedd2ac | 481 | pixelformat != SH_MOBILE_MERAM_PF_NV24 && |
7caa4342 | 482 | pixelformat != SH_MOBILE_MERAM_PF_RGB) |
48110050 | 483 | return ERR_PTR(-EINVAL); |
7caa4342 | 484 | |
97d16fe6 LP |
485 | dev_dbg(&pdev->dev, "registering %dx%d (%s)", xres, yres, |
486 | !pixelformat ? "yuv" : "rgb"); | |
7caa4342 | 487 | |
7caa4342 D |
488 | /* we can't handle wider than 8192px */ |
489 | if (xres > 8192) { | |
490 | dev_err(&pdev->dev, "width exceeding the limit (> 8192)."); | |
48110050 | 491 | return ERR_PTR(-EINVAL); |
7963e21e LP |
492 | } |
493 | ||
4a237177 LP |
494 | if (cfg->icb[0].meram_size == 0) |
495 | return ERR_PTR(-EINVAL); | |
496 | ||
497 | if (nplanes == 2 && cfg->icb[1].meram_size == 0) | |
498 | return ERR_PTR(-EINVAL); | |
499 | ||
7963e21e LP |
500 | mutex_lock(&priv->lock); |
501 | ||
974d250b | 502 | /* We now register the ICBs and allocate the MERAM regions. */ |
4a237177 | 503 | cache = meram_cache_alloc(priv, cfg, pixelformat); |
48110050 LP |
504 | if (IS_ERR(cache)) { |
505 | dev_err(&pdev->dev, "MERAM allocation failed (%ld).", | |
506 | PTR_ERR(cache)); | |
974d250b | 507 | goto err; |
974d250b | 508 | } |
7caa4342 D |
509 | |
510 | /* initialize MERAM */ | |
4a237177 | 511 | meram_plane_init(priv, &cache->planes[0], xres, yres, &out_pitch); |
7caa4342 D |
512 | *pitch = out_pitch; |
513 | if (pixelformat == SH_MOBILE_MERAM_PF_NV) | |
4a237177 LP |
514 | meram_plane_init(priv, &cache->planes[1], |
515 | xres, (yres + 1) / 2, &out_pitch); | |
3fedd2ac | 516 | else if (pixelformat == SH_MOBILE_MERAM_PF_NV24) |
4a237177 LP |
517 | meram_plane_init(priv, &cache->planes[1], |
518 | 2 * xres, (yres + 1) / 2, &out_pitch); | |
7caa4342 | 519 | |
7caa4342 D |
520 | err: |
521 | mutex_unlock(&priv->lock); | |
48110050 | 522 | return cache; |
7caa4342 | 523 | } |
6e729b41 | 524 | EXPORT_SYMBOL_GPL(sh_mobile_meram_cache_alloc); |
7caa4342 | 525 | |
6e729b41 LP |
526 | void |
527 | sh_mobile_meram_cache_free(struct sh_mobile_meram_info *pdata, void *data) | |
7caa4342 | 528 | { |
48110050 | 529 | struct sh_mobile_meram_fb_cache *cache = data; |
cdf88b90 | 530 | struct sh_mobile_meram_priv *priv = pdata->priv; |
7caa4342 D |
531 | |
532 | mutex_lock(&priv->lock); | |
533 | ||
4a237177 LP |
534 | /* Cleanup and free. */ |
535 | meram_plane_cleanup(priv, &cache->planes[0]); | |
536 | meram_plane_free(priv, &cache->planes[0]); | |
48110050 | 537 | |
4a237177 LP |
538 | if (cache->nplanes == 2) { |
539 | meram_plane_cleanup(priv, &cache->planes[1]); | |
540 | meram_plane_free(priv, &cache->planes[1]); | |
541 | } | |
542 | ||
543 | kfree(cache); | |
7caa4342 D |
544 | |
545 | mutex_unlock(&priv->lock); | |
7caa4342 | 546 | } |
6e729b41 LP |
547 | EXPORT_SYMBOL_GPL(sh_mobile_meram_cache_free); |
548 | ||
549 | void | |
550 | sh_mobile_meram_cache_update(struct sh_mobile_meram_info *pdata, void *data, | |
551 | unsigned long base_addr_y, | |
552 | unsigned long base_addr_c, | |
553 | unsigned long *icb_addr_y, | |
554 | unsigned long *icb_addr_c) | |
7caa4342 | 555 | { |
48110050 | 556 | struct sh_mobile_meram_fb_cache *cache = data; |
cdf88b90 | 557 | struct sh_mobile_meram_priv *priv = pdata->priv; |
7caa4342 D |
558 | |
559 | mutex_lock(&priv->lock); | |
560 | ||
48110050 LP |
561 | meram_set_next_addr(priv, cache, base_addr_y, base_addr_c); |
562 | meram_get_next_icb_addr(pdata, cache, icb_addr_y, icb_addr_c); | |
7caa4342 D |
563 | |
564 | mutex_unlock(&priv->lock); | |
7caa4342 | 565 | } |
6e729b41 | 566 | EXPORT_SYMBOL_GPL(sh_mobile_meram_cache_update); |
7554340c LP |
567 | |
568 | /* ----------------------------------------------------------------------------- | |
569 | * Power management | |
570 | */ | |
571 | ||
af89956b | 572 | static int sh_mobile_meram_suspend(struct device *dev) |
0b3bb77c DHG |
573 | { |
574 | struct platform_device *pdev = to_platform_device(dev); | |
575 | struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev); | |
05432837 | 576 | unsigned int i, j; |
0b3bb77c | 577 | |
7554340c | 578 | for (i = 0; i < MERAM_REGS_SIZE; i++) |
2a618e03 | 579 | priv->regs[i] = meram_read_reg(priv->base, common_regs[i]); |
0b3bb77c | 580 | |
05432837 LP |
581 | for (i = 0; i < 32; i++) { |
582 | if (!test_bit(i, &priv->used_icb)) | |
0b3bb77c | 583 | continue; |
05432837 | 584 | for (j = 0; j < ICB_REGS_SIZE; j++) { |
2a618e03 | 585 | priv->icbs[i].regs[j] = |
05432837 | 586 | meram_read_icb(priv->base, i, icb_regs[j]); |
0b3bb77c | 587 | /* Reset ICB on resume */ |
05432837 | 588 | if (icb_regs[j] == MExxCTL) |
2a618e03 | 589 | priv->icbs[i].regs[j] |= |
f0a260fe | 590 | MExxCTL_WBF | MExxCTL_WF | MExxCTL_RF; |
0b3bb77c DHG |
591 | } |
592 | } | |
593 | return 0; | |
594 | } | |
595 | ||
af89956b | 596 | static int sh_mobile_meram_resume(struct device *dev) |
0b3bb77c DHG |
597 | { |
598 | struct platform_device *pdev = to_platform_device(dev); | |
599 | struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev); | |
05432837 | 600 | unsigned int i, j; |
0b3bb77c | 601 | |
05432837 LP |
602 | for (i = 0; i < 32; i++) { |
603 | if (!test_bit(i, &priv->used_icb)) | |
0b3bb77c | 604 | continue; |
2a618e03 | 605 | for (j = 0; j < ICB_REGS_SIZE; j++) |
05432837 | 606 | meram_write_icb(priv->base, i, icb_regs[j], |
2a618e03 | 607 | priv->icbs[i].regs[j]); |
0b3bb77c DHG |
608 | } |
609 | ||
7554340c | 610 | for (i = 0; i < MERAM_REGS_SIZE; i++) |
2a618e03 | 611 | meram_write_reg(priv->base, common_regs[i], priv->regs[i]); |
0b3bb77c DHG |
612 | return 0; |
613 | } | |
614 | ||
af89956b LP |
615 | static UNIVERSAL_DEV_PM_OPS(sh_mobile_meram_dev_pm_ops, |
616 | sh_mobile_meram_suspend, | |
617 | sh_mobile_meram_resume, NULL); | |
0b3bb77c | 618 | |
7554340c LP |
619 | /* ----------------------------------------------------------------------------- |
620 | * Probe/remove and driver init/exit | |
7caa4342 D |
621 | */ |
622 | ||
48c68c4f | 623 | static int sh_mobile_meram_probe(struct platform_device *pdev) |
7caa4342 D |
624 | { |
625 | struct sh_mobile_meram_priv *priv; | |
626 | struct sh_mobile_meram_info *pdata = pdev->dev.platform_data; | |
e1d1144e LP |
627 | struct resource *regs; |
628 | struct resource *meram; | |
48110050 | 629 | unsigned int i; |
7caa4342 D |
630 | int error; |
631 | ||
632 | if (!pdata) { | |
633 | dev_err(&pdev->dev, "no platform data defined\n"); | |
634 | return -EINVAL; | |
635 | } | |
636 | ||
e1d1144e LP |
637 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
638 | meram = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
639 | if (regs == NULL || meram == NULL) { | |
7caa4342 D |
640 | dev_err(&pdev->dev, "cannot get platform resources\n"); |
641 | return -ENOENT; | |
642 | } | |
643 | ||
644 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); | |
645 | if (!priv) { | |
646 | dev_err(&pdev->dev, "cannot allocate device data\n"); | |
647 | return -ENOMEM; | |
648 | } | |
649 | ||
48110050 | 650 | /* Initialize private data. */ |
7caa4342 | 651 | mutex_init(&priv->lock); |
48110050 LP |
652 | priv->used_icb = pdata->reserved_icbs; |
653 | ||
654 | for (i = 0; i < MERAM_ICB_NUM; ++i) | |
655 | priv->icbs[i].index = i; | |
656 | ||
e1d1144e LP |
657 | pdata->priv = priv; |
658 | pdata->pdev = pdev; | |
659 | ||
974d250b | 660 | /* Request memory regions and remap the registers. */ |
e1d1144e LP |
661 | if (!request_mem_region(regs->start, resource_size(regs), pdev->name)) { |
662 | dev_err(&pdev->dev, "MERAM registers region already claimed\n"); | |
663 | error = -EBUSY; | |
664 | goto err_req_regs; | |
665 | } | |
666 | ||
667 | if (!request_mem_region(meram->start, resource_size(meram), | |
668 | pdev->name)) { | |
669 | dev_err(&pdev->dev, "MERAM memory region already claimed\n"); | |
670 | error = -EBUSY; | |
671 | goto err_req_meram; | |
672 | } | |
673 | ||
674 | priv->base = ioremap_nocache(regs->start, resource_size(regs)); | |
7caa4342 D |
675 | if (!priv->base) { |
676 | dev_err(&pdev->dev, "ioremap failed\n"); | |
677 | error = -EFAULT; | |
e1d1144e | 678 | goto err_ioremap; |
7caa4342 | 679 | } |
7caa4342 | 680 | |
974d250b LP |
681 | priv->meram = meram->start; |
682 | ||
683 | /* Create and initialize the MERAM memory pool. */ | |
684 | priv->pool = gen_pool_create(ilog2(MERAM_GRANULARITY), -1); | |
685 | if (priv->pool == NULL) { | |
686 | error = -ENOMEM; | |
687 | goto err_genpool; | |
688 | } | |
689 | ||
690 | error = gen_pool_add(priv->pool, meram->start, resource_size(meram), | |
691 | -1); | |
692 | if (error < 0) | |
693 | goto err_genpool; | |
694 | ||
7caa4342 D |
695 | /* initialize ICB addressing mode */ |
696 | if (pdata->addr_mode == SH_MOBILE_MERAM_MODE1) | |
f0a260fe | 697 | meram_write_reg(priv->base, MEVCR1, MEVCR1_AMD1); |
7caa4342 | 698 | |
e1d1144e | 699 | platform_set_drvdata(pdev, priv); |
17673778 DHG |
700 | pm_runtime_enable(&pdev->dev); |
701 | ||
7caa4342 D |
702 | dev_info(&pdev->dev, "sh_mobile_meram initialized."); |
703 | ||
704 | return 0; | |
705 | ||
974d250b LP |
706 | err_genpool: |
707 | if (priv->pool) | |
708 | gen_pool_destroy(priv->pool); | |
709 | iounmap(priv->base); | |
e1d1144e LP |
710 | err_ioremap: |
711 | release_mem_region(meram->start, resource_size(meram)); | |
712 | err_req_meram: | |
713 | release_mem_region(regs->start, resource_size(regs)); | |
714 | err_req_regs: | |
715 | mutex_destroy(&priv->lock); | |
716 | kfree(priv); | |
7caa4342 D |
717 | |
718 | return error; | |
719 | } | |
720 | ||
721 | ||
722 | static int sh_mobile_meram_remove(struct platform_device *pdev) | |
723 | { | |
724 | struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev); | |
e1d1144e LP |
725 | struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
726 | struct resource *meram = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
7caa4342 | 727 | |
17673778 DHG |
728 | pm_runtime_disable(&pdev->dev); |
729 | ||
974d250b LP |
730 | gen_pool_destroy(priv->pool); |
731 | ||
e1d1144e LP |
732 | iounmap(priv->base); |
733 | release_mem_region(meram->start, resource_size(meram)); | |
734 | release_mem_region(regs->start, resource_size(regs)); | |
7caa4342 D |
735 | |
736 | mutex_destroy(&priv->lock); | |
737 | ||
738 | kfree(priv); | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
743 | static struct platform_driver sh_mobile_meram_driver = { | |
744 | .driver = { | |
745 | .name = "sh_mobile_meram", | |
746 | .owner = THIS_MODULE, | |
0b3bb77c | 747 | .pm = &sh_mobile_meram_dev_pm_ops, |
7caa4342 D |
748 | }, |
749 | .probe = sh_mobile_meram_probe, | |
750 | .remove = sh_mobile_meram_remove, | |
751 | }; | |
752 | ||
4277f2c4 | 753 | module_platform_driver(sh_mobile_meram_driver); |
7caa4342 D |
754 | |
755 | MODULE_DESCRIPTION("SuperH Mobile MERAM driver"); | |
756 | MODULE_AUTHOR("Damian Hobson-Garcia / Takanari Hayama"); | |
757 | MODULE_LICENSE("GPL v2"); |