[deliverable/linux.git] / drivers / video / sis / sis.h

/*
 * SiS 300/540/630[S]/730[S],
 * SiS 315[E|PRO]/550/[M]65x/[M]661[F|M]X/740/[M]741[GX]/330/[M]76x[GX],
 * XGI V3XT/V5/V8, Z7
 * frame buffer driver for Linux kernels >=2.4.14 and >=2.6.3
 *
 * Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the named License,
 * or any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
 */

#ifndef _SIS_H_
#define _SIS_H_

#include "osdef.h"
#include <video/sisfb.h>

#include "vgatypes.h"
#include "vstruct.h"

#define VER_MAJOR		1
#define VER_MINOR		8
#define VER_LEVEL		9

#include <linux/spinlock.h>

#ifdef CONFIG_COMPAT
#define SIS_NEW_CONFIG_COMPAT
#endif	/* CONFIG_COMPAT */

#undef SISFBDEBUG

#ifdef SISFBDEBUG
#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
#define TWDEBUG(x) printk(KERN_INFO x "\n");
#else
#define DPRINTK(fmt, args...)
#define TWDEBUG(x)
#endif

#define SISFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0)

/* To be included in pci_ids.h */
#ifndef PCI_DEVICE_ID_SI_650_VGA
#define PCI_DEVICE_ID_SI_650_VGA	0x6325
#endif
#ifndef PCI_DEVICE_ID_SI_650
#define PCI_DEVICE_ID_SI_650		0x0650
#endif
#ifndef PCI_DEVICE_ID_SI_651
#define PCI_DEVICE_ID_SI_651		0x0651
#endif
#ifndef PCI_DEVICE_ID_SI_740
#define PCI_DEVICE_ID_SI_740		0x0740
#endif
#ifndef PCI_DEVICE_ID_SI_330
#define PCI_DEVICE_ID_SI_330		0x0330
#endif
#ifndef PCI_DEVICE_ID_SI_660_VGA
#define PCI_DEVICE_ID_SI_660_VGA	0x6330
#endif
#ifndef PCI_DEVICE_ID_SI_661
#define PCI_DEVICE_ID_SI_661		0x0661
#endif
#ifndef PCI_DEVICE_ID_SI_741
#define PCI_DEVICE_ID_SI_741		0x0741
#endif
#ifndef PCI_DEVICE_ID_SI_660
#define PCI_DEVICE_ID_SI_660		0x0660
#endif
#ifndef PCI_DEVICE_ID_SI_760
#define PCI_DEVICE_ID_SI_760		0x0760
#endif
#ifndef PCI_DEVICE_ID_SI_761
#define PCI_DEVICE_ID_SI_761		0x0761
#endif

#ifndef PCI_VENDOR_ID_XGI
#define PCI_VENDOR_ID_XGI		0x18ca
#endif

#ifndef PCI_DEVICE_ID_XGI_20
#define PCI_DEVICE_ID_XGI_20		0x0020
#endif

#ifndef PCI_DEVICE_ID_XGI_40
#define PCI_DEVICE_ID_XGI_40		0x0040
#endif

/* To be included in fb.h */
#ifndef FB_ACCEL_SIS_GLAMOUR_2
#define FB_ACCEL_SIS_GLAMOUR_2	40	/* SiS 315, 65x, 740, 661, 741  */
#endif
#ifndef FB_ACCEL_SIS_XABRE
#define FB_ACCEL_SIS_XABRE	41	/* SiS 330 ("Xabre"), 76x 	*/
#endif
#ifndef FB_ACCEL_XGI_VOLARI_V
#define FB_ACCEL_XGI_VOLARI_V	47	/* XGI Volari Vx (V3XT, V5, V8)	*/
#endif
#ifndef FB_ACCEL_XGI_VOLARI_Z
#define FB_ACCEL_XGI_VOLARI_Z	48	/* XGI Volari Z7		*/
#endif

/* ivideo->caps */
#define HW_CURSOR_CAP		0x80
#define TURBO_QUEUE_CAP		0x40
#define AGP_CMD_QUEUE_CAP	0x20
#define VM_CMD_QUEUE_CAP	0x10
#define MMIO_CMD_QUEUE_CAP	0x08

/* For 300 series */
#define TURBO_QUEUE_AREA_SIZE	(512 * 1024)	/* 512K */
#define HW_CURSOR_AREA_SIZE_300	4096		/* 4K */

/* For 315/Xabre series */
#define COMMAND_QUEUE_AREA_SIZE	(512 * 1024)	/* 512K */
#define COMMAND_QUEUE_AREA_SIZE_Z7 (128 * 1024)	/* 128k for XGI Z7 */
#define HW_CURSOR_AREA_SIZE_315	16384		/* 16K */
#define COMMAND_QUEUE_THRESHOLD	0x1F

#define SIS_OH_ALLOC_SIZE	4000
#define SENTINEL		0x7fffffff

#define SEQ_ADR			0x14
#define SEQ_DATA		0x15
#define DAC_ADR			0x18
#define DAC_DATA		0x19
#define CRTC_ADR		0x24
#define CRTC_DATA		0x25
#define DAC2_ADR		(0x16-0x30)
#define DAC2_DATA		(0x17-0x30)
#define VB_PART1_ADR		(0x04-0x30)
#define VB_PART1_DATA		(0x05-0x30)
#define VB_PART2_ADR		(0x10-0x30)
#define VB_PART2_DATA		(0x11-0x30)
#define VB_PART3_ADR		(0x12-0x30)
#define VB_PART3_DATA		(0x13-0x30)
#define VB_PART4_ADR		(0x14-0x30)
#define VB_PART4_DATA		(0x15-0x30)

#define SISSR			ivideo->SiS_Pr.SiS_P3c4
#define SISCR			ivideo->SiS_Pr.SiS_P3d4
#define SISDACA			ivideo->SiS_Pr.SiS_P3c8
#define SISDACD			ivideo->SiS_Pr.SiS_P3c9
#define SISPART1		ivideo->SiS_Pr.SiS_Part1Port
#define SISPART2		ivideo->SiS_Pr.SiS_Part2Port
#define SISPART3		ivideo->SiS_Pr.SiS_Part3Port
#define SISPART4		ivideo->SiS_Pr.SiS_Part4Port
#define SISPART5		ivideo->SiS_Pr.SiS_Part5Port
#define SISDAC2A		SISPART5
#define SISDAC2D		(SISPART5 + 1)
#define SISMISCR		(ivideo->SiS_Pr.RelIO + 0x1c)
#define SISMISCW		ivideo->SiS_Pr.SiS_P3c2
#define SISINPSTAT		(ivideo->SiS_Pr.RelIO + 0x2a)
#define SISPEL			ivideo->SiS_Pr.SiS_P3c6
#define SISVGAENABLE		(ivideo->SiS_Pr.RelIO + 0x13)
#define SISVID			(ivideo->SiS_Pr.RelIO + 0x02 - 0x30)
#define SISCAP			(ivideo->SiS_Pr.RelIO + 0x00 - 0x30)

#define IND_SIS_PASSWORD		0x05  /* SRs */
#define IND_SIS_COLOR_MODE		0x06
#define IND_SIS_RAMDAC_CONTROL		0x07
#define IND_SIS_DRAM_SIZE		0x14
#define IND_SIS_MODULE_ENABLE		0x1E
#define IND_SIS_PCI_ADDRESS_SET		0x20
#define IND_SIS_TURBOQUEUE_ADR		0x26
#define IND_SIS_TURBOQUEUE_SET		0x27
#define IND_SIS_POWER_ON_TRAP		0x38
#define IND_SIS_POWER_ON_TRAP2		0x39
#define IND_SIS_CMDQUEUE_SET		0x26
#define IND_SIS_CMDQUEUE_THRESHOLD	0x27

#define IND_SIS_AGP_IO_PAD	0x48

#define SIS_CRT2_WENABLE_300	0x24  /* Part1 */
#define SIS_CRT2_WENABLE_315	0x2F

#define SIS_PASSWORD		0x86  /* SR05 */

#define SIS_INTERLACED_MODE	0x20  /* SR06 */
#define SIS_8BPP_COLOR_MODE	0x0
#define SIS_15BPP_COLOR_MODE	0x1
#define SIS_16BPP_COLOR_MODE	0x2
#define SIS_32BPP_COLOR_MODE	0x4

#define SIS_ENABLE_2D		0x40  /* SR1E */

#define SIS_MEM_MAP_IO_ENABLE	0x01  /* SR20 */
#define SIS_PCI_ADDR_ENABLE	0x80

#define SIS_AGP_CMDQUEUE_ENABLE		0x80  /* 315/330/340 series SR26 */
#define SIS_VRAM_CMDQUEUE_ENABLE	0x40
#define SIS_MMIO_CMD_ENABLE		0x20
#define SIS_CMD_QUEUE_SIZE_512k		0x00
#define SIS_CMD_QUEUE_SIZE_1M		0x04
#define SIS_CMD_QUEUE_SIZE_2M		0x08
#define SIS_CMD_QUEUE_SIZE_4M		0x0C
#define SIS_CMD_QUEUE_RESET		0x01
#define SIS_CMD_AUTO_CORR		0x02

#define SIS_CMD_QUEUE_SIZE_Z7_64k	0x00 /* XGI Z7 */
#define SIS_CMD_QUEUE_SIZE_Z7_128k	0x04

#define SIS_SIMULTANEOUS_VIEW_ENABLE	0x01  /* CR30 */
#define SIS_MODE_SELECT_CRT2		0x02
#define SIS_VB_OUTPUT_COMPOSITE		0x04
#define SIS_VB_OUTPUT_SVIDEO		0x08
#define SIS_VB_OUTPUT_SCART		0x10
#define SIS_VB_OUTPUT_LCD		0x20
#define SIS_VB_OUTPUT_CRT2		0x40
#define SIS_VB_OUTPUT_HIVISION		0x80

#define SIS_VB_OUTPUT_DISABLE	0x20  /* CR31 */
#define SIS_DRIVER_MODE		0x40

#define SIS_VB_COMPOSITE	0x01  /* CR32 */
#define SIS_VB_SVIDEO		0x02
#define SIS_VB_SCART		0x04
#define SIS_VB_LCD		0x08
#define SIS_VB_CRT2		0x10
#define SIS_CRT1		0x20
#define SIS_VB_HIVISION		0x40
#define SIS_VB_YPBPR		0x80
#define SIS_VB_TV		(SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \
				SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR)

#define SIS_EXTERNAL_CHIP_MASK			0x0E  /* CR37 (< SiS 660) */
#define SIS_EXTERNAL_CHIP_SIS301		0x01  /* in CR37 << 1 ! */
#define SIS_EXTERNAL_CHIP_LVDS			0x02
#define SIS_EXTERNAL_CHIP_TRUMPION		0x03
#define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL		0x04
#define SIS_EXTERNAL_CHIP_CHRONTEL		0x05
#define SIS310_EXTERNAL_CHIP_LVDS		0x02
#define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL	0x03

#define SIS_AGP_2X		0x20  /* CR48 */

/* vbflags, private entries (others in sisfb.h) */
#define VB_CONEXANT		0x00000800	/* 661 series only */
#define VB_TRUMPION		VB_CONEXANT	/* 300 series only */
#define VB_302ELV		0x00004000
#define VB_301			0x00100000	/* Video bridge type */
#define VB_301B			0x00200000
#define VB_302B			0x00400000
#define VB_30xBDH		0x00800000	/* 30xB DH version (w/o LCD support) */
#define VB_LVDS			0x01000000
#define VB_CHRONTEL		0x02000000
#define VB_301LV		0x04000000
#define VB_302LV		0x08000000
#define VB_301C			0x10000000

#define VB_SISBRIDGE		(VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV|VB_302ELV)
#define VB_VIDEOBRIDGE		(VB_SISBRIDGE | VB_LVDS | VB_CHRONTEL | VB_CONEXANT)

/* vbflags2 (static stuff only!) */
#define VB2_SISUMC		0x00000001
#define VB2_301			0x00000002	/* Video bridge type */
#define VB2_301B		0x00000004
#define VB2_301C		0x00000008
#define VB2_307T		0x00000010
#define VB2_302B		0x00000800
#define VB2_301LV		0x00001000
#define VB2_302LV		0x00002000
#define VB2_302ELV		0x00004000
#define VB2_307LV		0x00008000
#define VB2_30xBDH		0x08000000      /* 30xB DH version (w/o LCD support) */
#define VB2_CONEXANT		0x10000000
#define VB2_TRUMPION		0x20000000
#define VB2_LVDS		0x40000000
#define VB2_CHRONTEL		0x80000000

#define VB2_SISLVDSBRIDGE	(VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV)
#define VB2_SISTMDSBRIDGE	(VB2_301   | VB2_301B  | VB2_301C   | VB2_302B | VB2_307T)
#define VB2_SISBRIDGE		(VB2_SISLVDSBRIDGE | VB2_SISTMDSBRIDGE)

#define VB2_SISTMDSLCDABRIDGE	(VB2_301C | VB2_307T)
#define VB2_SISLCDABRIDGE	(VB2_SISTMDSLCDABRIDGE | VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV)

#define VB2_SISHIVISIONBRIDGE	(VB2_301  | VB2_301B | VB2_302B)
#define VB2_SISYPBPRBRIDGE	(VB2_301C | VB2_307T | VB2_SISLVDSBRIDGE)
#define VB2_SISYPBPRARBRIDGE	(VB2_301C | VB2_307T | VB2_307LV)
#define VB2_SISTAP4SCALER	(VB2_301C | VB2_307T | VB2_302ELV | VB2_307LV)
#define VB2_SISTVBRIDGE		(VB2_SISHIVISIONBRIDGE | VB2_SISYPBPRBRIDGE)

#define VB2_SISVGA2BRIDGE	(VB2_301 | VB2_301B | VB2_301C | VB2_302B | VB2_307T)

#define VB2_VIDEOBRIDGE		(VB2_SISBRIDGE | VB2_LVDS | VB2_CHRONTEL | VB2_CONEXANT)

#define VB2_30xB		(VB2_301B  | VB2_301C   | VB2_302B  | VB2_307T)
#define VB2_30xBLV		(VB2_30xB  | VB2_SISLVDSBRIDGE)
#define VB2_30xC		(VB2_301C  | VB2_307T)
#define VB2_30xCLV		(VB2_301C  | VB2_307T   | VB2_302ELV| VB2_307LV)
#define VB2_SISEMIBRIDGE	(VB2_302LV | VB2_302ELV | VB2_307LV)
#define VB2_LCD162MHZBRIDGE	(VB2_301C  | VB2_307T)
#define VB2_LCDOVER1280BRIDGE	(VB2_301C  | VB2_307T   | VB2_302LV | VB2_302ELV | VB2_307LV)
#define VB2_LCDOVER1600BRIDGE	(VB2_307T  | VB2_307LV)
#define VB2_RAMDAC202MHZBRIDGE	(VB2_301C  | VB2_307T)

/* I/O port access macros */
#define inSISREG(base)		inb(base)

#define outSISREG(base,val)	outb(val,base)

#define orSISREG(base,val)      			\
		do {					\
			u8 __Temp = inSISREG(base); 	\
			outSISREG(base, __Temp | (val));\
		} while (0)

#define andSISREG(base,val)     			\
		do {					\
			u8 __Temp = inSISREG(base); 	\
			outSISREG(base, __Temp & (val));\
		} while (0)

#define inSISIDXREG(base,idx,var)			\
		do {					\
			outSISREG(base, idx); 		\
			var = inSISREG((base)+1);	\
		} while (0)

#define outSISIDXREG(base,idx,val)			\
		do {					\
			outSISREG(base, idx);		\
			outSISREG((base)+1, val);	\
		} while (0)

#define orSISIDXREG(base,idx,val)				\
		do {						\
			u8 __Temp; 				\
			outSISREG(base, idx);   		\
			__Temp = inSISREG((base)+1) | (val); 	\
			outSISREG((base)+1, __Temp);		\
		} while (0)

#define andSISIDXREG(base,idx,and)				\
		do {						\
			u8 __Temp; 				\
			outSISREG(base, idx);   		\
			__Temp = inSISREG((base)+1) & (and); 	\
			outSISREG((base)+1, __Temp);		\
		} while (0)

#define setSISIDXREG(base,idx,and,or)   				\
		do {							\
			u8 __Temp; 					\
			outSISREG(base, idx);				\
			__Temp = (inSISREG((base)+1) & (and)) | (or); 	\
			outSISREG((base)+1, __Temp);			\
		} while (0)

/* MMIO access macros */
#define MMIO_IN8(base, offset)  readb((base+offset))
#define MMIO_IN16(base, offset) readw((base+offset))
#define MMIO_IN32(base, offset) readl((base+offset))

#define MMIO_OUT8(base, offset, val)  writeb(((u8)(val)), (base+offset))
#define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset))
#define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset))

/* Queue control MMIO registers */
#define Q_BASE_ADDR		0x85C0  /* Base address of software queue */
#define Q_WRITE_PTR		0x85C4  /* Current write pointer */
#define Q_READ_PTR		0x85C8  /* Current read pointer */
#define Q_STATUS		0x85CC  /* queue status */

#define MMIO_QUEUE_PHYBASE      Q_BASE_ADDR
#define MMIO_QUEUE_WRITEPORT    Q_WRITE_PTR
#define MMIO_QUEUE_READPORT     Q_READ_PTR

#ifndef FB_BLANK_UNBLANK
#define FB_BLANK_UNBLANK	0
#endif
#ifndef FB_BLANK_NORMAL
#define FB_BLANK_NORMAL		1
#endif
#ifndef FB_BLANK_VSYNC_SUSPEND
#define FB_BLANK_VSYNC_SUSPEND	2
#endif
#ifndef FB_BLANK_HSYNC_SUSPEND
#define FB_BLANK_HSYNC_SUSPEND	3
#endif
#ifndef FB_BLANK_POWERDOWN
#define FB_BLANK_POWERDOWN	4
#endif

enum _SIS_LCD_TYPE {
    LCD_INVALID = 0,
    LCD_800x600,
    LCD_1024x768,
    LCD_1280x1024,
    LCD_1280x960,
    LCD_640x480,
    LCD_1600x1200,
    LCD_1920x1440,
    LCD_2048x1536,
    LCD_320x240,	/* FSTN */
    LCD_1400x1050,
    LCD_1152x864,
    LCD_1152x768,
    LCD_1280x768,
    LCD_1024x600,
    LCD_320x240_2,	/* DSTN */
    LCD_320x240_3,	/* DSTN */
    LCD_848x480,
    LCD_1280x800,
    LCD_1680x1050,
    LCD_1280x720,
    LCD_1280x854,
    LCD_CUSTOM,
    LCD_UNKNOWN
};

enum _SIS_CMDTYPE {
    MMIO_CMD = 0,
    AGP_CMD_QUEUE,
    VM_CMD_QUEUE,
};

struct SIS_OH {
	struct SIS_OH *poh_next;
	struct SIS_OH *poh_prev;
	u32            offset;
	u32            size;
};

struct SIS_OHALLOC {
	struct SIS_OHALLOC *poha_next;
	struct SIS_OH aoh[1];
};

struct SIS_HEAP {
	struct SIS_OH	oh_free;
	struct SIS_OH	oh_used;
	struct SIS_OH	*poh_freelist;
	struct SIS_OHALLOC *poha_chain;
	u32		max_freesize;
	struct sis_video_info *vinfo;
};

/* Our "par" */
struct sis_video_info {
	int		cardnumber;
	struct fb_info  *memyselfandi;

	struct SiS_Private SiS_Pr;

	struct sisfb_info sisfbinfo;	/* For ioctl SISFB_GET_INFO */

	struct fb_var_screeninfo default_var;

	struct fb_fix_screeninfo sisfb_fix;
	u32		pseudo_palette[16];

	struct sisfb_monitor {
		u16 hmin;
		u16 hmax;
		u16 vmin;
		u16 vmax;
		u32 dclockmax;
		u8  feature;
		bool datavalid;
	}		sisfb_thismonitor;

	unsigned short	chip_id;	/* PCI ID of chip */
	unsigned short	chip_vendor;	/* PCI ID of vendor */
	char		myid[40];

	struct pci_dev  *nbridge;
	struct pci_dev  *lpcdev;

	int		mni;	/* Mode number index */

	unsigned long	video_size;
	unsigned long	video_base;
	unsigned long	mmio_size;
	unsigned long	mmio_base;
	unsigned long	vga_base;

	unsigned long	video_offset;

	unsigned long	UMAsize, LFBsize;

	void __iomem	*video_vbase;
	void __iomem	*mmio_vbase;

	unsigned char	*bios_abase;

	int		mtrr;

	u32		sisfb_mem;

	u32		sisfb_parm_mem;
	int		sisfb_accel;
	int		sisfb_ypan;
	int		sisfb_max;
	int		sisfb_userom;
	int		sisfb_useoem;
	int		sisfb_mode_idx;
	int		sisfb_parm_rate;
	int		sisfb_crt1off;
	int		sisfb_forcecrt1;
	int		sisfb_crt2type;
	int		sisfb_crt2flags;
	int		sisfb_dstn;
	int		sisfb_fstn;
	int		sisfb_tvplug;
	int		sisfb_tvstd;
	int		sisfb_nocrt2rate;

	u32		heapstart;		/* offset  */
	void __iomem	*sisfb_heap_start;	/* address */
	void __iomem	*sisfb_heap_end;	/* address */
	u32		sisfb_heap_size;
	int		havenoheap;

	struct SIS_HEAP	sisfb_heap;		/* This card's vram heap */

	int		video_bpp;
	int		video_cmap_len;
	int		video_width;
	int		video_height;
	unsigned int	refresh_rate;

	unsigned int	chip;
	u8		revision_id;
	int		sisvga_enabled;		/* PCI device was enabled */

	int		video_linelength;	/* real pitch */
	int		scrnpitchCRT1;		/* pitch regarding interlace */

	u16		DstColor;		/* For 2d acceleration */
	u32		SiS310_AccelDepth;
	u32		CommandReg;
	int		cmdqueuelength;		/* Current (for accel) */
	u32		cmdQueueSize;		/* Total size in KB */

	spinlock_t	lockaccel;		/* Do not use outside of kernel! */

	unsigned int	pcibus;
	unsigned int	pcislot;
	unsigned int	pcifunc;

	int		accel;
	int		engineok;

	u16		subsysvendor;
	u16		subsysdevice;

	u32		vbflags;		/* Replacing deprecated stuff from above */
	u32		currentvbflags;
	u32		vbflags2;

	int		lcdxres, lcdyres;
	int		lcddefmodeidx, tvdefmodeidx, defmodeidx;
	u32		CRT2LCDType;		/* defined in "SIS_LCD_TYPE" */
	u32		curFSTN, curDSTN;

	int		current_bpp;
	int		current_width;
	int		current_height;
	int		current_htotal;
	int		current_vtotal;
	int		current_linelength;
	__u32		current_pixclock;
	int		current_refresh_rate;

	unsigned int	current_base;

	u8		mode_no;
	u8		rate_idx;
	int		modechanged;
	unsigned char	modeprechange;

	u8		sisfb_lastrates[128];

	int		newrom;
	int		haveXGIROM;
	int		registered;
	int		warncount;

	int		sisvga_engine;
	int		hwcursor_size;
	int		CRT2_write_enable;
	u8		caps;

	u8		detectedpdc;
	u8		detectedpdca;
	u8		detectedlcda;

	void __iomem	*hwcursor_vbase;

	int		chronteltype;
	int		tvxpos, tvypos;
	u8		p2_1f,p2_20,p2_2b,p2_42,p2_43,p2_01,p2_02;
	int		tvx, tvy;

	u8		sisfblocked;

	struct sisfb_info sisfb_infoblock;

	struct sisfb_cmd sisfb_command;

	u32		sisfb_id;

	u8		sisfb_can_post;
	u8		sisfb_card_posted;
	u8		sisfb_was_boot_device;

	struct sis_video_info *next;
};

#endif
Commit	Line	Data
1da177e4	1	/*
544393fe TW	2	* SiS 300/540/630[S]/730[S],
	3	* SiS 315[E\|PRO]/550/[M]65x/[M]661[F\|M]X/740/[M]741[GX]/330/[M]76x[GX],
	4	* XGI V3XT/V5/V8, Z7
1da177e4 LT	5	* frame buffer driver for Linux kernels >=2.4.14 and >=2.6.3
1da177e4 LT	6	*
544393fe	7	* Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
1da177e4 LT	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the named License,
	12	* or any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
	22	*/
	23
544393fe TW	24	#ifndef _SIS_H_
544393fe TW	25	#define _SIS_H_
1da177e4	26
1da177e4	27	#include "osdef.h"
1da177e4	28	#include <video/sisfb.h>
1da177e4 LT	29
	30	#include "vgatypes.h"
	31	#include "vstruct.h"
	32
544393fe TW	33	#define VER_MAJOR 1
	34	#define VER_MINOR 8
	35	#define VER_LEVEL 9
1da177e4	36
1da177e4	37	#include <linux/spinlock.h>
0959f0ca	38
1da177e4	39	#ifdef CONFIG_COMPAT
544393fe	40	#define SIS_NEW_CONFIG_COMPAT
544393fe	41	#endif /* CONFIG_COMPAT */
0959f0ca	42
1da177e4 LT	43	#undef SISFBDEBUG
	44
	45	#ifdef SISFBDEBUG
5ae12170	46	#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__ , ## args)
1da177e4 LT	47	#define TWDEBUG(x) printk(KERN_INFO x "\n");
	48	#else
	49	#define DPRINTK(fmt, args...)
	50	#define TWDEBUG(x)
	51	#endif
	52
	53	#define SISFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0)
	54
	55	/* To be included in pci_ids.h */
	56	#ifndef PCI_DEVICE_ID_SI_650_VGA
544393fe	57	#define PCI_DEVICE_ID_SI_650_VGA 0x6325
1da177e4 LT	58	#endif
1da177e4 LT	59	#ifndef PCI_DEVICE_ID_SI_650
544393fe	60	#define PCI_DEVICE_ID_SI_650 0x0650
1da177e4 LT	61	#endif
1da177e4 LT	62	#ifndef PCI_DEVICE_ID_SI_651
544393fe	63	#define PCI_DEVICE_ID_SI_651 0x0651
1da177e4 LT	64	#endif
1da177e4 LT	65	#ifndef PCI_DEVICE_ID_SI_740
544393fe	66	#define PCI_DEVICE_ID_SI_740 0x0740
1da177e4 LT	67	#endif
1da177e4 LT	68	#ifndef PCI_DEVICE_ID_SI_330
544393fe	69	#define PCI_DEVICE_ID_SI_330 0x0330
1da177e4 LT	70	#endif
1da177e4 LT	71	#ifndef PCI_DEVICE_ID_SI_660_VGA
544393fe	72	#define PCI_DEVICE_ID_SI_660_VGA 0x6330
1da177e4 LT	73	#endif
1da177e4 LT	74	#ifndef PCI_DEVICE_ID_SI_661
544393fe	75	#define PCI_DEVICE_ID_SI_661 0x0661
1da177e4 LT	76	#endif
1da177e4 LT	77	#ifndef PCI_DEVICE_ID_SI_741
544393fe	78	#define PCI_DEVICE_ID_SI_741 0x0741
1da177e4 LT	79	#endif
1da177e4 LT	80	#ifndef PCI_DEVICE_ID_SI_660
544393fe	81	#define PCI_DEVICE_ID_SI_660 0x0660
1da177e4 LT	82	#endif
1da177e4 LT	83	#ifndef PCI_DEVICE_ID_SI_760
544393fe TW	84	#define PCI_DEVICE_ID_SI_760 0x0760
	85	#endif
	86	#ifndef PCI_DEVICE_ID_SI_761
	87	#define PCI_DEVICE_ID_SI_761 0x0761
	88	#endif
	89
	90	#ifndef PCI_VENDOR_ID_XGI
	91	#define PCI_VENDOR_ID_XGI 0x18ca
	92	#endif
	93
	94	#ifndef PCI_DEVICE_ID_XGI_20
	95	#define PCI_DEVICE_ID_XGI_20 0x0020
	96	#endif
	97
	98	#ifndef PCI_DEVICE_ID_XGI_40
	99	#define PCI_DEVICE_ID_XGI_40 0x0040
1da177e4 LT	100	#endif
	101
	102	/* To be included in fb.h */
	103	#ifndef FB_ACCEL_SIS_GLAMOUR_2
544393fe	104	#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 65x, 740, 661, 741 */
1da177e4 LT	105	#endif
1da177e4 LT	106	#ifndef FB_ACCEL_SIS_XABRE
544393fe TW	107	#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre"), 76x */
	108	#endif
	109	#ifndef FB_ACCEL_XGI_VOLARI_V
	110	#define FB_ACCEL_XGI_VOLARI_V 47 /* XGI Volari Vx (V3XT, V5, V8) */
	111	#endif
	112	#ifndef FB_ACCEL_XGI_VOLARI_Z
	113	#define FB_ACCEL_XGI_VOLARI_Z 48 /* XGI Volari Z7 */
1da177e4	114	#endif
1da177e4 LT	115
1da177e4 LT	116	/* ivideo->caps */
544393fe TW	117	#define HW_CURSOR_CAP 0x80
	118	#define TURBO_QUEUE_CAP 0x40
	119	#define AGP_CMD_QUEUE_CAP 0x20
	120	#define VM_CMD_QUEUE_CAP 0x10
	121	#define MMIO_CMD_QUEUE_CAP 0x08
1da177e4 LT	122
1da177e4 LT	123	/* For 300 series */
544393fe TW	124	#define TURBO_QUEUE_AREA_SIZE (512 * 1024) /* 512K */
544393fe TW	125	#define HW_CURSOR_AREA_SIZE_300 4096 /* 4K */
1da177e4 LT	126
1da177e4 LT	127	/* For 315/Xabre series */
544393fe TW	128	#define COMMAND_QUEUE_AREA_SIZE (512 * 1024) /* 512K */
	129	#define COMMAND_QUEUE_AREA_SIZE_Z7 (128 * 1024) /* 128k for XGI Z7 */
	130	#define HW_CURSOR_AREA_SIZE_315 16384 /* 16K */
	131	#define COMMAND_QUEUE_THRESHOLD 0x1F
	132
	133	#define SIS_OH_ALLOC_SIZE 4000
	134	#define SENTINEL 0x7fffffff
	135
	136	#define SEQ_ADR 0x14
	137	#define SEQ_DATA 0x15
	138	#define DAC_ADR 0x18
	139	#define DAC_DATA 0x19
	140	#define CRTC_ADR 0x24
	141	#define CRTC_DATA 0x25
	142	#define DAC2_ADR (0x16-0x30)
	143	#define DAC2_DATA (0x17-0x30)
	144	#define VB_PART1_ADR (0x04-0x30)
	145	#define VB_PART1_DATA (0x05-0x30)
	146	#define VB_PART2_ADR (0x10-0x30)
	147	#define VB_PART2_DATA (0x11-0x30)
	148	#define VB_PART3_ADR (0x12-0x30)
	149	#define VB_PART3_DATA (0x13-0x30)
	150	#define VB_PART4_ADR (0x14-0x30)
	151	#define VB_PART4_DATA (0x15-0x30)
	152
	153	#define SISSR ivideo->SiS_Pr.SiS_P3c4
	154	#define SISCR ivideo->SiS_Pr.SiS_P3d4
	155	#define SISDACA ivideo->SiS_Pr.SiS_P3c8
	156	#define SISDACD ivideo->SiS_Pr.SiS_P3c9
	157	#define SISPART1 ivideo->SiS_Pr.SiS_Part1Port
	158	#define SISPART2 ivideo->SiS_Pr.SiS_Part2Port
	159	#define SISPART3 ivideo->SiS_Pr.SiS_Part3Port
	160	#define SISPART4 ivideo->SiS_Pr.SiS_Part4Port
	161	#define SISPART5 ivideo->SiS_Pr.SiS_Part5Port
	162	#define SISDAC2A SISPART5
	163	#define SISDAC2D (SISPART5 + 1)
	164	#define SISMISCR (ivideo->SiS_Pr.RelIO + 0x1c)
	165	#define SISMISCW ivideo->SiS_Pr.SiS_P3c2
	166	#define SISINPSTAT (ivideo->SiS_Pr.RelIO + 0x2a)
	167	#define SISPEL ivideo->SiS_Pr.SiS_P3c6
	168	#define SISVGAENABLE (ivideo->SiS_Pr.RelIO + 0x13)
	169	#define SISVID (ivideo->SiS_Pr.RelIO + 0x02 - 0x30)
	170	#define SISCAP (ivideo->SiS_Pr.RelIO + 0x00 - 0x30)
	171
	172	#define IND_SIS_PASSWORD 0x05 /* SRs */
	173	#define IND_SIS_COLOR_MODE 0x06
	174	#define IND_SIS_RAMDAC_CONTROL 0x07
	175	#define IND_SIS_DRAM_SIZE 0x14
	176	#define IND_SIS_MODULE_ENABLE 0x1E
	177	#define IND_SIS_PCI_ADDRESS_SET 0x20
	178	#define IND_SIS_TURBOQUEUE_ADR 0x26
	179	#define IND_SIS_TURBOQUEUE_SET 0x27
	180	#define IND_SIS_POWER_ON_TRAP 0x38
	181	#define IND_SIS_POWER_ON_TRAP2 0x39
	182	#define IND_SIS_CMDQUEUE_SET 0x26
	183	#define IND_SIS_CMDQUEUE_THRESHOLD 0x27
	184
	185	#define IND_SIS_AGP_IO_PAD 0x48
	186
	187	#define SIS_CRT2_WENABLE_300 0x24 /* Part1 */
	188	#define SIS_CRT2_WENABLE_315 0x2F
	189
	190	#define SIS_PASSWORD 0x86 /* SR05 */
	191
192	#define SIS_INTERLACED_MODE 0x20 /* SR06 */
193	#define SIS_8BPP_COLOR_MODE 0x0
194	#define SIS_15BPP_COLOR_MODE 0x1
195	#define SIS_16BPP_COLOR_MODE 0x2
196	#define SIS_32BPP_COLOR_MODE 0x4
197
198	#define SIS_ENABLE_2D 0x40 /* SR1E */
199
200	#define SIS_MEM_MAP_IO_ENABLE 0x01 /* SR20 */
201	#define SIS_PCI_ADDR_ENABLE 0x80
202
203	#define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315/330/340 series SR26 */
204	#define SIS_VRAM_CMDQUEUE_ENABLE 0x40
205	#define SIS_MMIO_CMD_ENABLE 0x20
206	#define SIS_CMD_QUEUE_SIZE_512k 0x00
207	#define SIS_CMD_QUEUE_SIZE_1M 0x04
208	#define SIS_CMD_QUEUE_SIZE_2M 0x08
209	#define SIS_CMD_QUEUE_SIZE_4M 0x0C
210	#define SIS_CMD_QUEUE_RESET 0x01
211	#define SIS_CMD_AUTO_CORR 0x02
212
213	#define SIS_CMD_QUEUE_SIZE_Z7_64k 0x00 /* XGI Z7 */
214	#define SIS_CMD_QUEUE_SIZE_Z7_128k 0x04
215
216	#define SIS_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */
217	#define SIS_MODE_SELECT_CRT2 0x02
218	#define SIS_VB_OUTPUT_COMPOSITE 0x04
219	#define SIS_VB_OUTPUT_SVIDEO 0x08
220	#define SIS_VB_OUTPUT_SCART 0x10
221	#define SIS_VB_OUTPUT_LCD 0x20
222	#define SIS_VB_OUTPUT_CRT2 0x40
223	#define SIS_VB_OUTPUT_HIVISION 0x80
224
225	#define SIS_VB_OUTPUT_DISABLE 0x20 /* CR31 */
226	#define SIS_DRIVER_MODE 0x40
227
228	#define SIS_VB_COMPOSITE 0x01 /* CR32 */
229	#define SIS_VB_SVIDEO 0x02
230	#define SIS_VB_SCART 0x04
231	#define SIS_VB_LCD 0x08
232	#define SIS_VB_CRT2 0x10
233	#define SIS_CRT1 0x20
234	#define SIS_VB_HIVISION 0x40
235	#define SIS_VB_YPBPR 0x80
236	#define SIS_VB_TV (SIS_VB_COMPOSITE \| SIS_VB_SVIDEO \| \
237	SIS_VB_SCART \| SIS_VB_HIVISION \| SIS_VB_YPBPR)
238
239	#define SIS_EXTERNAL_CHIP_MASK 0x0E /* CR37 (< SiS 660) */
240	#define SIS_EXTERNAL_CHIP_SIS301 0x01 /* in CR37 << 1 ! */
241	#define SIS_EXTERNAL_CHIP_LVDS 0x02
242	#define SIS_EXTERNAL_CHIP_TRUMPION 0x03
243	#define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04
244	#define SIS_EXTERNAL_CHIP_CHRONTEL 0x05
245	#define SIS310_EXTERNAL_CHIP_LVDS 0x02
246	#define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03
247
248	#define SIS_AGP_2X 0x20 /* CR48 */
249
250	/* vbflags, private entries (others in sisfb.h) */
251	#define VB_CONEXANT 0x00000800 /* 661 series only */
252	#define VB_TRUMPION VB_CONEXANT /* 300 series only */
253	#define VB_302ELV 0x00004000
254	#define VB_301 0x00100000 /* Video bridge type */
255	#define VB_301B 0x00200000
256	#define VB_302B 0x00400000
257	#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */
258	#define VB_LVDS 0x01000000
259	#define VB_CHRONTEL 0x02000000
260	#define VB_301LV 0x04000000
261	#define VB_302LV 0x08000000
262	#define VB_301C 0x10000000
263
264	#define VB_SISBRIDGE (VB_301\|VB_301B\|VB_301C\|VB_302B\|VB_301LV\|VB_302LV\|VB_302ELV)
265	#define VB_VIDEOBRIDGE (VB_SISBRIDGE \| VB_LVDS \| VB_CHRONTEL \| VB_CONEXANT)
266
267	/* vbflags2 (static stuff only!) */
268	#define VB2_SISUMC 0x00000001
269	#define VB2_301 0x00000002 /* Video bridge type */
270	#define VB2_301B 0x00000004
271	#define VB2_301C 0x00000008
272	#define VB2_307T 0x00000010
273	#define VB2_302B 0x00000800
274	#define VB2_301LV 0x00001000
275	#define VB2_302LV 0x00002000
276	#define VB2_302ELV 0x00004000
277	#define VB2_307LV 0x00008000
278	#define VB2_30xBDH 0x08000000 /* 30xB DH version (w/o LCD support) */
279	#define VB2_CONEXANT 0x10000000
280	#define VB2_TRUMPION 0x20000000
281	#define VB2_LVDS 0x40000000
282	#define VB2_CHRONTEL 0x80000000
283
284	#define VB2_SISLVDSBRIDGE (VB2_301LV \| VB2_302LV \| VB2_302ELV \| VB2_307LV)
285	#define VB2_SISTMDSBRIDGE (VB2_301 \| VB2_301B \| VB2_301C \| VB2_302B \| VB2_307T)
286	#define VB2_SISBRIDGE (VB2_SISLVDSBRIDGE \| VB2_SISTMDSBRIDGE)
287
288	#define VB2_SISTMDSLCDABRIDGE (VB2_301C \| VB2_307T)
289	#define VB2_SISLCDABRIDGE (VB2_SISTMDSLCDABRIDGE \| VB2_301LV \| VB2_302LV \| VB2_302ELV \| VB2_307LV)
290
291	#define VB2_SISHIVISIONBRIDGE (VB2_301 \| VB2_301B \| VB2_302B)
292	#define VB2_SISYPBPRBRIDGE (VB2_301C \| VB2_307T \| VB2_SISLVDSBRIDGE)
293	#define VB2_SISYPBPRARBRIDGE (VB2_301C \| VB2_307T \| VB2_307LV)
294	#define VB2_SISTAP4SCALER (VB2_301C \| VB2_307T \| VB2_302ELV \| VB2_307LV)
295	#define VB2_SISTVBRIDGE (VB2_SISHIVISIONBRIDGE \| VB2_SISYPBPRBRIDGE)
296
297	#define VB2_SISVGA2BRIDGE (VB2_301 \| VB2_301B \| VB2_301C \| VB2_302B \| VB2_307T)
298
299	#define VB2_VIDEOBRIDGE (VB2_SISBRIDGE \| VB2_LVDS \| VB2_CHRONTEL \| VB2_CONEXANT)
300
301	#define VB2_30xB (VB2_301B \| VB2_301C \| VB2_302B \| VB2_307T)
302	#define VB2_30xBLV (VB2_30xB \| VB2_SISLVDSBRIDGE)
303	#define VB2_30xC (VB2_301C \| VB2_307T)
304	#define VB2_30xCLV (VB2_301C \| VB2_307T \| VB2_302ELV\| VB2_307LV)
305	#define VB2_SISEMIBRIDGE (VB2_302LV \| VB2_302ELV \| VB2_307LV)
306	#define VB2_LCD162MHZBRIDGE (VB2_301C \| VB2_307T)
307	#define VB2_LCDOVER1280BRIDGE (VB2_301C \| VB2_307T \| VB2_302LV \| VB2_302ELV \| VB2_307LV)
308	#define VB2_LCDOVER1600BRIDGE (VB2_307T \| VB2_307LV)
309	#define VB2_RAMDAC202MHZBRIDGE (VB2_301C \| VB2_307T)
1da177e4 LT	310
1da177e4 LT	311	/* I/O port access macros */
544393fe	312	#define inSISREG(base) inb(base)
1da177e4	313
544393fe	314	#define outSISREG(base,val) outb(val,base)
1da177e4 LT	315
1da177e4 LT	316	#define orSISREG(base,val) \
544393fe TW	317	do { \
	318	u8 __Temp = inSISREG(base); \
	319	outSISREG(base, __Temp \| (val));\
	320	} while (0)
1da177e4 LT	321
1da177e4 LT	322	#define andSISREG(base,val) \
544393fe TW	323	do { \
	324	u8 __Temp = inSISREG(base); \
	325	outSISREG(base, __Temp & (val));\
	326	} while (0)
	327
	328	#define inSISIDXREG(base,idx,var) \
	329	do { \
	330	outSISREG(base, idx); \
	331	var = inSISREG((base)+1); \
	332	} while (0)
	333
	334	#define outSISIDXREG(base,idx,val) \
	335	do { \
	336	outSISREG(base, idx); \
	337	outSISREG((base)+1, val); \
	338	} while (0)
	339
	340	#define orSISIDXREG(base,idx,val) \
	341	do { \
	342	u8 __Temp; \
	343	outSISREG(base, idx); \
	344	__Temp = inSISREG((base)+1) \| (val); \
	345	outSISREG((base)+1, __Temp); \
	346	} while (0)
	347
	348	#define andSISIDXREG(base,idx,and) \
	349	do { \
	350	u8 __Temp; \
	351	outSISREG(base, idx); \
	352	__Temp = inSISREG((base)+1) & (and); \
	353	outSISREG((base)+1, __Temp); \
	354	} while (0)
	355
	356	#define setSISIDXREG(base,idx,and,or) \
	357	do { \
	358	u8 __Temp; \
	359	outSISREG(base, idx); \
	360	__Temp = (inSISREG((base)+1) & (and)) \| (or); \
	361	outSISREG((base)+1, __Temp); \
	362	} while (0)
1da177e4 LT	363
	364	/* MMIO access macros */
	365	#define MMIO_IN8(base, offset) readb((base+offset))
	366	#define MMIO_IN16(base, offset) readw((base+offset))
	367	#define MMIO_IN32(base, offset) readl((base+offset))
	368
	369	#define MMIO_OUT8(base, offset, val) writeb(((u8)(val)), (base+offset))
	370	#define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset))
	371	#define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset))
	372
	373	/* Queue control MMIO registers */
	374	#define Q_BASE_ADDR 0x85C0 /* Base address of software queue */
	375	#define Q_WRITE_PTR 0x85C4 /* Current write pointer */
	376	#define Q_READ_PTR 0x85C8 /* Current read pointer */
	377	#define Q_STATUS 0x85CC /* queue status */
	378
	379	#define MMIO_QUEUE_PHYBASE Q_BASE_ADDR
	380	#define MMIO_QUEUE_WRITEPORT Q_WRITE_PTR
	381	#define MMIO_QUEUE_READPORT Q_READ_PTR
	382
	383	#ifndef FB_BLANK_UNBLANK
544393fe	384	#define FB_BLANK_UNBLANK 0
1da177e4 LT	385	#endif
1da177e4 LT	386	#ifndef FB_BLANK_NORMAL
544393fe	387	#define FB_BLANK_NORMAL 1
1da177e4 LT	388	#endif
1da177e4 LT	389	#ifndef FB_BLANK_VSYNC_SUSPEND
544393fe	390	#define FB_BLANK_VSYNC_SUSPEND 2
1da177e4 LT	391	#endif
1da177e4 LT	392	#ifndef FB_BLANK_HSYNC_SUSPEND
544393fe	393	#define FB_BLANK_HSYNC_SUSPEND 3
1da177e4 LT	394	#endif
1da177e4 LT	395	#ifndef FB_BLANK_POWERDOWN
544393fe	396	#define FB_BLANK_POWERDOWN 4
1da177e4 LT	397	#endif
	398
	399	enum _SIS_LCD_TYPE {
	400	LCD_INVALID = 0,
	401	LCD_800x600,
	402	LCD_1024x768,
	403	LCD_1280x1024,
	404	LCD_1280x960,
	405	LCD_640x480,
	406	LCD_1600x1200,
	407	LCD_1920x1440,
	408	LCD_2048x1536,
544393fe	409	LCD_320x240, /* FSTN */
1da177e4 LT	410	LCD_1400x1050,
	411	LCD_1152x864,
	412	LCD_1152x768,
	413	LCD_1280x768,
	414	LCD_1024x600,
544393fe TW	415	LCD_320x240_2, /* DSTN */
544393fe TW	416	LCD_320x240_3, /* DSTN */
1da177e4 LT	417	LCD_848x480,
	418	LCD_1280x800,
	419	LCD_1680x1050,
	420	LCD_1280x720,
544393fe	421	LCD_1280x854,
1da177e4 LT	422	LCD_CUSTOM,
	423	LCD_UNKNOWN
	424	};
	425
	426	enum _SIS_CMDTYPE {
	427	MMIO_CMD = 0,
	428	AGP_CMD_QUEUE,
	429	VM_CMD_QUEUE,
	430	};
544393fe TW	431
	432	struct SIS_OH {
	433	struct SIS_OH *poh_next;
	434	struct SIS_OH *poh_prev;
	435	u32 offset;
	436	u32 size;
	437	};
	438
	439	struct SIS_OHALLOC {
	440	struct SIS_OHALLOC *poha_next;
	441	struct SIS_OH aoh[1];
	442	};
	443
	444	struct SIS_HEAP {
	445	struct SIS_OH oh_free;
	446	struct SIS_OH oh_used;
	447	struct SIS_OH *poh_freelist;
	448	struct SIS_OHALLOC *poha_chain;
	449	u32 max_freesize;
	450	struct sis_video_info *vinfo;
	451	};
1da177e4 LT	452
	453	/* Our "par" */
	454	struct sis_video_info {
	455	int cardnumber;
	456	struct fb_info *memyselfandi;
	457
544393fe	458	struct SiS_Private SiS_Pr;
1da177e4	459
544393fe	460	struct sisfb_info sisfbinfo; /* For ioctl SISFB_GET_INFO */
1da177e4 LT	461
	462	struct fb_var_screeninfo default_var;
	463
1da177e4	464	struct fb_fix_screeninfo sisfb_fix;
000d5335	465	u32 pseudo_palette[16];
1da177e4	466
544393fe	467	struct sisfb_monitor {
1da177e4 LT	468	u16 hmin;
	469	u16 hmax;
	470	u16 vmin;
	471	u16 vmax;
	472	u32 dclockmax;
	473	u8 feature;
c30660ea	474	bool datavalid;
544393fe	475	} sisfb_thismonitor;
1da177e4	476
544393fe TW	477	unsigned short chip_id; /* PCI ID of chip */
544393fe TW	478	unsigned short chip_vendor; /* PCI ID of vendor */
1da177e4 LT	479	char myid[40];
	480
	481	struct pci_dev *nbridge;
544393fe	482	struct pci_dev *lpcdev;
1da177e4 LT	483
	484	int mni; /* Mode number index */
	485
1da177e4	486	unsigned long video_size;
544393fe	487	unsigned long video_base;
1da177e4	488	unsigned long mmio_size;
544393fe TW	489	unsigned long mmio_base;
	490	unsigned long vga_base;
	491
	492	unsigned long video_offset;
1da177e4	493
544393fe	494	unsigned long UMAsize, LFBsize;
1da177e4	495
14aefd1b AB	496	void __iomem *video_vbase;
14aefd1b AB	497	void __iomem *mmio_vbase;
1da177e4	498
544393fe TW	499	unsigned char *bios_abase;
	500
	501	int mtrr;
1da177e4 LT	502
	503	u32 sisfb_mem;
	504
544393fe TW	505	u32 sisfb_parm_mem;
	506	int sisfb_accel;
	507	int sisfb_ypan;
	508	int sisfb_max;
	509	int sisfb_userom;
	510	int sisfb_useoem;
1da177e4 LT	511	int sisfb_mode_idx;
	512	int sisfb_parm_rate;
	513	int sisfb_crt1off;
	514	int sisfb_forcecrt1;
	515	int sisfb_crt2type;
	516	int sisfb_crt2flags;
544393fe TW	517	int sisfb_dstn;
544393fe TW	518	int sisfb_fstn;
1da177e4 LT	519	int sisfb_tvplug;
1da177e4 LT	520	int sisfb_tvstd;
1da177e4	521	int sisfb_nocrt2rate;
1da177e4	522
544393fe	523	u32 heapstart; /* offset */
14aefd1b AB	524	void __iomem sisfb_heap_start; / address */
14aefd1b AB	525	void __iomem sisfb_heap_end; / address */
544393fe	526	u32 sisfb_heap_size;
1da177e4	527	int havenoheap;
1da177e4	528
544393fe	529	struct SIS_HEAP sisfb_heap; /* This card's vram heap */
1da177e4	530
544393fe TW	531	int video_bpp;
	532	int video_cmap_len;
	533	int video_width;
	534	int video_height;
	535	unsigned int refresh_rate;
1da177e4	536
544393fe TW	537	unsigned int chip;
	538	u8 revision_id;
	539	int sisvga_enabled; /* PCI device was enabled */
1da177e4	540
544393fe	541	int video_linelength; /* real pitch */
1da177e4 LT	542	int scrnpitchCRT1; /* pitch regarding interlace */
1da177e4 LT	543
544393fe TW	544	u16 DstColor; /* For 2d acceleration */
	545	u32 SiS310_AccelDepth;
	546	u32 CommandReg;
	547	int cmdqueuelength; /* Current (for accel) */
	548	u32 cmdQueueSize; /* Total size in KB */
1da177e4	549
544393fe	550	spinlock_t lockaccel; /* Do not use outside of kernel! */
1da177e4	551
544393fe TW	552	unsigned int pcibus;
	553	unsigned int pcislot;
	554	unsigned int pcifunc;
1da177e4	555
544393fe TW	556	int accel;
544393fe TW	557	int engineok;
1da177e4	558
544393fe TW	559	u16 subsysvendor;
544393fe TW	560	u16 subsysdevice;
1da177e4	561
544393fe TW	562	u32 vbflags; /* Replacing deprecated stuff from above */
	563	u32 currentvbflags;
	564	u32 vbflags2;
1da177e4 LT	565
	566	int lcdxres, lcdyres;
	567	int lcddefmodeidx, tvdefmodeidx, defmodeidx;
544393fe TW	568	u32 CRT2LCDType; /* defined in "SIS_LCD_TYPE" */
	569	u32 curFSTN, curDSTN;
	570
	571	int current_bpp;
	572	int current_width;
	573	int current_height;
	574	int current_htotal;
	575	int current_vtotal;
1da177e4	576	int current_linelength;
544393fe TW	577	__u32 current_pixclock;
	578	int current_refresh_rate;
	579
	580	unsigned int current_base;
1da177e4	581
544393fe TW	582	u8 mode_no;
	583	u8 rate_idx;
	584	int modechanged;
	585	unsigned char modeprechange;
1da177e4	586
544393fe	587	u8 sisfb_lastrates[128];
1da177e4	588
544393fe TW	589	int newrom;
	590	int haveXGIROM;
	591	int registered;
1da177e4 LT	592	int warncount;
1da177e4 LT	593
544393fe TW	594	int sisvga_engine;
	595	int hwcursor_size;
	596	int CRT2_write_enable;
	597	u8 caps;
1da177e4	598
544393fe TW	599	u8 detectedpdc;
	600	u8 detectedpdca;
	601	u8 detectedlcda;
1da177e4	602
14aefd1b	603	void __iomem *hwcursor_vbase;
1da177e4	604
544393fe TW	605	int chronteltype;
	606	int tvxpos, tvypos;
	607	u8 p2_1f,p2_20,p2_2b,p2_42,p2_43,p2_01,p2_02;
1da177e4 LT	608	int tvx, tvy;
1da177e4 LT	609
544393fe TW	610	u8 sisfblocked;
	611
	612	struct sisfb_info sisfb_infoblock;
	613
	614	struct sisfb_cmd sisfb_command;
	615
	616	u32 sisfb_id;
	617
	618	u8 sisfb_can_post;
	619	u8 sisfb_card_posted;
	620	u8 sisfb_was_boot_device;
1da177e4 LT	621
	622	struct sis_video_info *next;
	623	};
	624
1da177e4	625	#endif