Commit | Line | Data |
---|---|---|
d61e0bf3 JC |
1 | /* |
2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
4 | ||
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public | |
7 | * License as published by the Free Software Foundation; | |
8 | * either version 2, or (at your option) any later version. | |
9 | ||
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
14 | * for more details. | |
15 | ||
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
ec66841e JC |
21 | |
22 | #include <linux/via-core.h> | |
d61e0bf3 JC |
23 | #include "global.h" |
24 | ||
d61e0bf3 | 25 | static struct pll_map pll_value[] = { |
1f844350 FTS |
26 | {25175000, |
27 | {99, 7, 3}, | |
28 | {85, 3, 4}, /* ignoring bit difference: 0x00008000 */ | |
29 | {141, 5, 4}, | |
30 | {141, 5, 4} }, | |
31 | {29581000, | |
32 | {33, 4, 2}, | |
33 | {66, 2, 4}, /* ignoring bit difference: 0x00808000 */ | |
34 | {166, 5, 4}, /* ignoring bit difference: 0x00008000 */ | |
35 | {165, 5, 4} }, | |
36 | {26880000, | |
37 | {15, 4, 1}, | |
38 | {30, 2, 3}, /* ignoring bit difference: 0x00808000 */ | |
39 | {150, 5, 4}, | |
40 | {150, 5, 4} }, | |
41 | {31500000, | |
42 | {53, 3, 3}, /* ignoring bit difference: 0x00008000 */ | |
43 | {141, 4, 4}, /* ignoring bit difference: 0x00008000 */ | |
44 | {176, 5, 4}, | |
45 | {176, 5, 4} }, | |
46 | {31728000, | |
47 | {31, 7, 1}, | |
48 | {177, 5, 4}, /* ignoring bit difference: 0x00008000 */ | |
49 | {177, 5, 4}, | |
50 | {142, 4, 4} }, | |
51 | {32688000, | |
52 | {73, 4, 3}, | |
53 | {146, 4, 4}, /* ignoring bit difference: 0x00008000 */ | |
54 | {183, 5, 4}, | |
55 | {146, 4, 4} }, | |
56 | {36000000, | |
57 | {101, 5, 3}, /* ignoring bit difference: 0x00008000 */ | |
58 | {161, 4, 4}, /* ignoring bit difference: 0x00008000 */ | |
59 | {202, 5, 4}, | |
60 | {161, 4, 4} }, | |
61 | {40000000, | |
62 | {89, 4, 3}, | |
63 | {89, 4, 3}, /* ignoring bit difference: 0x00008000 */ | |
64 | {112, 5, 3}, | |
65 | {112, 5, 3} }, | |
66 | {41291000, | |
67 | {23, 4, 1}, | |
68 | {69, 3, 3}, /* ignoring bit difference: 0x00008000 */ | |
69 | {115, 5, 3}, | |
70 | {115, 5, 3} }, | |
71 | {43163000, | |
72 | {121, 5, 3}, | |
73 | {121, 5, 3}, /* ignoring bit difference: 0x00008000 */ | |
74 | {121, 5, 3}, | |
75 | {121, 5, 3} }, | |
76 | {45250000, | |
77 | {127, 5, 3}, | |
78 | {127, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
79 | {127, 5, 3}, | |
80 | {127, 5, 3} }, | |
81 | {46000000, | |
82 | {90, 7, 2}, | |
83 | {103, 4, 3}, /* ignoring bit difference: 0x00008000 */ | |
84 | {129, 5, 3}, | |
85 | {103, 4, 3} }, | |
86 | {46996000, | |
87 | {105, 4, 3}, /* ignoring bit difference: 0x00008000 */ | |
88 | {131, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
89 | {131, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
90 | {105, 4, 3} }, | |
91 | {48000000, | |
92 | {67, 20, 0}, | |
93 | {134, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
94 | {134, 5, 3}, | |
95 | {134, 5, 3} }, | |
96 | {48875000, | |
97 | {99, 29, 0}, | |
98 | {82, 3, 3}, /* ignoring bit difference: 0x00808000 */ | |
99 | {82, 3, 3}, /* ignoring bit difference: 0x00808000 */ | |
100 | {137, 5, 3} }, | |
101 | {49500000, | |
102 | {83, 6, 2}, | |
103 | {83, 3, 3}, /* ignoring bit difference: 0x00008000 */ | |
104 | {138, 5, 3}, | |
105 | {83, 3, 3} }, | |
106 | {52406000, | |
107 | {117, 4, 3}, | |
108 | {117, 4, 3}, /* ignoring bit difference: 0x00008000 */ | |
109 | {117, 4, 3}, | |
110 | {88, 3, 3} }, | |
111 | {52977000, | |
112 | {37, 5, 1}, | |
113 | {148, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
114 | {148, 5, 3}, | |
115 | {148, 5, 3} }, | |
116 | {56250000, | |
117 | {55, 7, 1}, /* ignoring bit difference: 0x00008000 */ | |
118 | {126, 4, 3}, /* ignoring bit difference: 0x00008000 */ | |
119 | {157, 5, 3}, | |
120 | {157, 5, 3} }, | |
121 | {57275000, | |
122 | {0, 0, 0}, | |
123 | {2, 2, 0}, | |
124 | {2, 2, 0}, | |
125 | {157, 5, 3} }, /* ignoring bit difference: 0x00808000 */ | |
126 | {60466000, | |
127 | {76, 9, 1}, | |
128 | {169, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
129 | {169, 5, 3}, /* FIXED: old = {72, 2, 3} */ | |
130 | {169, 5, 3} }, | |
131 | {61500000, | |
132 | {86, 20, 0}, | |
133 | {172, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
134 | {172, 5, 3}, | |
135 | {172, 5, 3} }, | |
136 | {65000000, | |
137 | {109, 6, 2}, /* ignoring bit difference: 0x00008000 */ | |
138 | {109, 3, 3}, /* ignoring bit difference: 0x00008000 */ | |
139 | {109, 3, 3}, | |
140 | {109, 3, 3} }, | |
141 | {65178000, | |
142 | {91, 5, 2}, | |
143 | {182, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
144 | {109, 3, 3}, | |
145 | {182, 5, 3} }, | |
146 | {66750000, | |
147 | {75, 4, 2}, | |
148 | {150, 4, 3}, /* ignoring bit difference: 0x00808000 */ | |
149 | {150, 4, 3}, | |
150 | {112, 3, 3} }, | |
151 | {68179000, | |
152 | {19, 4, 0}, | |
153 | {114, 3, 3}, /* ignoring bit difference: 0x00008000 */ | |
154 | {190, 5, 3}, | |
155 | {191, 5, 3} }, | |
156 | {69924000, | |
157 | {83, 17, 0}, | |
158 | {195, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
159 | {195, 5, 3}, | |
160 | {195, 5, 3} }, | |
161 | {70159000, | |
162 | {98, 20, 0}, | |
163 | {196, 5, 3}, /* ignoring bit difference: 0x00808000 */ | |
164 | {196, 5, 3}, | |
165 | {195, 5, 3} }, | |
166 | {72000000, | |
167 | {121, 24, 0}, | |
168 | {161, 4, 3}, /* ignoring bit difference: 0x00808000 */ | |
169 | {161, 4, 3}, | |
170 | {161, 4, 3} }, | |
171 | {78750000, | |
172 | {33, 3, 1}, | |
173 | {66, 3, 2}, /* ignoring bit difference: 0x00008000 */ | |
174 | {110, 5, 2}, | |
175 | {110, 5, 2} }, | |
176 | {80136000, | |
177 | {28, 5, 0}, | |
178 | {68, 3, 2}, /* ignoring bit difference: 0x00008000 */ | |
179 | {112, 5, 2}, | |
180 | {112, 5, 2} }, | |
181 | {83375000, | |
182 | {93, 2, 3}, | |
183 | {93, 4, 2}, /* ignoring bit difference: 0x00800000 */ | |
184 | {93, 4, 2}, /* ignoring bit difference: 0x00800000 */ | |
185 | {117, 5, 2} }, | |
186 | {83950000, | |
187 | {41, 7, 0}, | |
188 | {117, 5, 2}, /* ignoring bit difference: 0x00008000 */ | |
189 | {117, 5, 2}, | |
190 | {117, 5, 2} }, | |
191 | {84750000, | |
192 | {118, 5, 2}, | |
193 | {118, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
194 | {118, 5, 2}, | |
195 | {118, 5, 2} }, | |
196 | {85860000, | |
197 | {84, 7, 1}, | |
198 | {120, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
199 | {120, 5, 2}, | |
200 | {118, 5, 2} }, | |
201 | {88750000, | |
202 | {31, 5, 0}, | |
203 | {124, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
204 | {174, 7, 2}, /* ignoring bit difference: 0x00808000 */ | |
205 | {124, 5, 2} }, | |
206 | {94500000, | |
207 | {33, 5, 0}, | |
208 | {132, 5, 2}, /* ignoring bit difference: 0x00008000 */ | |
209 | {132, 5, 2}, | |
210 | {132, 5, 2} }, | |
211 | {97750000, | |
212 | {82, 6, 1}, | |
213 | {137, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
214 | {137, 5, 2}, | |
215 | {137, 5, 2} }, | |
216 | {101000000, | |
217 | {127, 9, 1}, | |
218 | {141, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
219 | {141, 5, 2}, | |
220 | {141, 5, 2} }, | |
221 | {106500000, | |
222 | {119, 4, 2}, | |
223 | {119, 4, 2}, /* ignoring bit difference: 0x00808000 */ | |
224 | {119, 4, 2}, | |
225 | {149, 5, 2} }, | |
226 | {108000000, | |
227 | {121, 4, 2}, | |
228 | {121, 4, 2}, /* ignoring bit difference: 0x00808000 */ | |
229 | {151, 5, 2}, | |
230 | {151, 5, 2} }, | |
231 | {113309000, | |
232 | {95, 12, 0}, | |
233 | {95, 3, 2}, /* ignoring bit difference: 0x00808000 */ | |
234 | {95, 3, 2}, | |
235 | {159, 5, 2} }, | |
236 | {118840000, | |
237 | {83, 5, 1}, | |
238 | {166, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
239 | {166, 5, 2}, | |
240 | {166, 5, 2} }, | |
241 | {119000000, | |
242 | {108, 13, 0}, | |
243 | {133, 4, 2}, /* ignoring bit difference: 0x00808000 */ | |
244 | {133, 4, 2}, | |
245 | {167, 5, 2} }, | |
246 | {121750000, | |
247 | {85, 5, 1}, | |
248 | {170, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
249 | {68, 2, 2}, | |
250 | {0, 0, 0} }, | |
251 | {125104000, | |
252 | {53, 6, 0}, /* ignoring bit difference: 0x00008000 */ | |
253 | {106, 3, 2}, /* ignoring bit difference: 0x00008000 */ | |
254 | {175, 5, 2}, | |
255 | {0, 0, 0} }, | |
256 | {135000000, | |
257 | {94, 5, 1}, | |
258 | {28, 3, 0}, /* ignoring bit difference: 0x00804000 */ | |
259 | {151, 4, 2}, | |
260 | {189, 5, 2} }, | |
261 | {136700000, | |
262 | {115, 12, 0}, | |
263 | {191, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
264 | {191, 5, 2}, | |
265 | {191, 5, 2} }, | |
266 | {138400000, | |
267 | {87, 9, 0}, | |
268 | {116, 3, 2}, /* ignoring bit difference: 0x00808000 */ | |
269 | {116, 3, 2}, | |
270 | {194, 5, 2} }, | |
271 | {146760000, | |
272 | {103, 5, 1}, | |
273 | {206, 5, 2}, /* ignoring bit difference: 0x00808000 */ | |
274 | {206, 5, 2}, | |
275 | {206, 5, 2} }, | |
276 | {153920000, | |
277 | {86, 8, 0}, | |
278 | {86, 4, 1}, /* ignoring bit difference: 0x00808000 */ | |
279 | {86, 4, 1}, | |
280 | {86, 4, 1} }, /* FIXED: old = {84, 2, 1} */ | |
281 | {156000000, | |
282 | {109, 5, 1}, | |
283 | {109, 5, 1}, /* ignoring bit difference: 0x00808000 */ | |
284 | {109, 5, 1}, | |
285 | {108, 5, 1} }, | |
286 | {157500000, | |
287 | {55, 5, 0}, /* ignoring bit difference: 0x00008000 */ | |
288 | {22, 2, 0}, /* ignoring bit difference: 0x00802000 */ | |
289 | {110, 5, 1}, | |
290 | {110, 5, 1} }, | |
291 | {162000000, | |
292 | {113, 5, 1}, | |
293 | {113, 5, 1}, /* ignoring bit difference: 0x00808000 */ | |
294 | {113, 5, 1}, | |
295 | {113, 5, 1} }, | |
296 | {187000000, | |
297 | {118, 9, 0}, | |
298 | {131, 5, 1}, /* ignoring bit difference: 0x00808000 */ | |
299 | {131, 5, 1}, | |
300 | {131, 5, 1} }, | |
301 | {193295000, | |
302 | {108, 8, 0}, | |
303 | {81, 3, 1}, /* ignoring bit difference: 0x00808000 */ | |
304 | {135, 5, 1}, | |
305 | {135, 5, 1} }, | |
306 | {202500000, | |
307 | {99, 7, 0}, | |
308 | {85, 3, 1}, /* ignoring bit difference: 0x00808000 */ | |
309 | {142, 5, 1}, | |
310 | {142, 5, 1} }, | |
311 | {204000000, | |
312 | {100, 7, 0}, | |
313 | {143, 5, 1}, /* ignoring bit difference: 0x00808000 */ | |
314 | {143, 5, 1}, | |
315 | {143, 5, 1} }, | |
316 | {218500000, | |
317 | {92, 6, 0}, | |
318 | {153, 5, 1}, /* ignoring bit difference: 0x00808000 */ | |
319 | {153, 5, 1}, | |
320 | {153, 5, 1} }, | |
321 | {234000000, | |
322 | {98, 6, 0}, | |
323 | {98, 3, 1}, /* ignoring bit difference: 0x00008000 */ | |
324 | {98, 3, 1}, | |
325 | {164, 5, 1} }, | |
326 | {267250000, | |
327 | {112, 6, 0}, | |
328 | {112, 3, 1}, /* ignoring bit difference: 0x00808000 */ | |
329 | {187, 5, 1}, | |
330 | {187, 5, 1} }, | |
331 | {297500000, | |
332 | {102, 5, 0}, /* ignoring bit difference: 0x00008000 */ | |
333 | {166, 4, 1}, /* ignoring bit difference: 0x00008000 */ | |
334 | {208, 5, 1}, | |
335 | {208, 5, 1} }, | |
336 | {74481000, | |
337 | {26, 5, 0}, | |
338 | {125, 3, 3}, /* ignoring bit difference: 0x00808000 */ | |
339 | {208, 5, 3}, | |
340 | {209, 5, 3} }, | |
341 | {172798000, | |
342 | {121, 5, 1}, | |
343 | {121, 5, 1}, /* ignoring bit difference: 0x00808000 */ | |
344 | {121, 5, 1}, | |
345 | {121, 5, 1} }, | |
346 | {122614000, | |
347 | {60, 7, 0}, | |
348 | {137, 4, 2}, /* ignoring bit difference: 0x00808000 */ | |
349 | {137, 4, 2}, | |
350 | {172, 5, 2} }, | |
351 | {74270000, | |
352 | {83, 8, 1}, | |
353 | {208, 5, 3}, | |
354 | {208, 5, 3}, | |
355 | {0, 0, 0} }, | |
356 | {148500000, | |
357 | {83, 8, 0}, | |
358 | {208, 5, 2}, | |
359 | {166, 4, 2}, | |
360 | {208, 5, 2} } | |
d61e0bf3 JC |
361 | }; |
362 | ||
363 | static struct fifo_depth_select display_fifo_depth_reg = { | |
364 | /* IGA1 FIFO Depth_Select */ | |
365 | {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } }, | |
366 | /* IGA2 FIFO Depth_Select */ | |
367 | {IGA2_FIFO_DEPTH_SELECT_REG_NUM, | |
368 | {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } } | |
369 | }; | |
370 | ||
371 | static struct fifo_threshold_select fifo_threshold_select_reg = { | |
372 | /* IGA1 FIFO Threshold Select */ | |
373 | {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } }, | |
374 | /* IGA2 FIFO Threshold Select */ | |
375 | {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } } | |
376 | }; | |
377 | ||
378 | static struct fifo_high_threshold_select fifo_high_threshold_select_reg = { | |
379 | /* IGA1 FIFO High Threshold Select */ | |
380 | {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } }, | |
381 | /* IGA2 FIFO High Threshold Select */ | |
382 | {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } } | |
383 | }; | |
384 | ||
385 | static struct display_queue_expire_num display_queue_expire_num_reg = { | |
386 | /* IGA1 Display Queue Expire Num */ | |
387 | {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } }, | |
388 | /* IGA2 Display Queue Expire Num */ | |
389 | {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } } | |
390 | }; | |
391 | ||
392 | /* Definition Fetch Count Registers*/ | |
393 | static struct fetch_count fetch_count_reg = { | |
394 | /* IGA1 Fetch Count Register */ | |
395 | {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } }, | |
396 | /* IGA2 Fetch Count Register */ | |
397 | {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } } | |
398 | }; | |
399 | ||
400 | static struct iga1_crtc_timing iga1_crtc_reg = { | |
401 | /* IGA1 Horizontal Total */ | |
402 | {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } }, | |
403 | /* IGA1 Horizontal Addressable Video */ | |
404 | {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } }, | |
405 | /* IGA1 Horizontal Blank Start */ | |
406 | {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } }, | |
407 | /* IGA1 Horizontal Blank End */ | |
408 | {IGA1_HOR_BLANK_END_REG_NUM, | |
409 | {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } }, | |
410 | /* IGA1 Horizontal Sync Start */ | |
411 | {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } }, | |
412 | /* IGA1 Horizontal Sync End */ | |
413 | {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } }, | |
414 | /* IGA1 Vertical Total */ | |
415 | {IGA1_VER_TOTAL_REG_NUM, | |
416 | {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } }, | |
417 | /* IGA1 Vertical Addressable Video */ | |
418 | {IGA1_VER_ADDR_REG_NUM, | |
419 | {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } }, | |
420 | /* IGA1 Vertical Blank Start */ | |
421 | {IGA1_VER_BLANK_START_REG_NUM, | |
422 | {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } }, | |
423 | /* IGA1 Vertical Blank End */ | |
424 | {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } }, | |
425 | /* IGA1 Vertical Sync Start */ | |
426 | {IGA1_VER_SYNC_START_REG_NUM, | |
427 | {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } }, | |
428 | /* IGA1 Vertical Sync End */ | |
429 | {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } } | |
430 | }; | |
431 | ||
432 | static struct iga2_crtc_timing iga2_crtc_reg = { | |
433 | /* IGA2 Horizontal Total */ | |
434 | {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } }, | |
435 | /* IGA2 Horizontal Addressable Video */ | |
436 | {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } }, | |
437 | /* IGA2 Horizontal Blank Start */ | |
438 | {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } }, | |
439 | /* IGA2 Horizontal Blank End */ | |
440 | {IGA2_HOR_BLANK_END_REG_NUM, | |
441 | {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } }, | |
442 | /* IGA2 Horizontal Sync Start */ | |
443 | {IGA2_HOR_SYNC_START_REG_NUM, | |
444 | {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } }, | |
445 | /* IGA2 Horizontal Sync End */ | |
446 | {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } }, | |
447 | /* IGA2 Vertical Total */ | |
448 | {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } }, | |
449 | /* IGA2 Vertical Addressable Video */ | |
450 | {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } }, | |
451 | /* IGA2 Vertical Blank Start */ | |
452 | {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } }, | |
453 | /* IGA2 Vertical Blank End */ | |
454 | {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } }, | |
455 | /* IGA2 Vertical Sync Start */ | |
456 | {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } }, | |
457 | /* IGA2 Vertical Sync End */ | |
458 | {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } } | |
459 | }; | |
460 | ||
461 | static struct rgbLUT palLUT_table[] = { | |
462 | /* {R,G,B} */ | |
463 | /* Index 0x00~0x03 */ | |
464 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00, | |
465 | 0x2A, | |
466 | 0x2A}, | |
467 | /* Index 0x04~0x07 */ | |
468 | {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A, | |
469 | 0x2A, | |
470 | 0x2A}, | |
471 | /* Index 0x08~0x0B */ | |
472 | {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15, | |
473 | 0x3F, | |
474 | 0x3F}, | |
475 | /* Index 0x0C~0x0F */ | |
476 | {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F, | |
477 | 0x3F, | |
478 | 0x3F}, | |
479 | /* Index 0x10~0x13 */ | |
480 | {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B, | |
481 | 0x0B, | |
482 | 0x0B}, | |
483 | /* Index 0x14~0x17 */ | |
484 | {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18, | |
485 | 0x18, | |
486 | 0x18}, | |
487 | /* Index 0x18~0x1B */ | |
488 | {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28, | |
489 | 0x28, | |
490 | 0x28}, | |
491 | /* Index 0x1C~0x1F */ | |
492 | {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F, | |
493 | 0x3F, | |
494 | 0x3F}, | |
495 | /* Index 0x20~0x23 */ | |
496 | {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F, | |
497 | 0x00, | |
498 | 0x3F}, | |
499 | /* Index 0x24~0x27 */ | |
500 | {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F, | |
501 | 0x00, | |
502 | 0x10}, | |
503 | /* Index 0x28~0x2B */ | |
504 | {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F, | |
505 | 0x2F, | |
506 | 0x00}, | |
507 | /* Index 0x2C~0x2F */ | |
508 | {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10, | |
509 | 0x3F, | |
510 | 0x00}, | |
511 | /* Index 0x30~0x33 */ | |
512 | {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00, | |
513 | 0x3F, | |
514 | 0x2F}, | |
515 | /* Index 0x34~0x37 */ | |
516 | {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00, | |
517 | 0x10, | |
518 | 0x3F}, | |
519 | /* Index 0x38~0x3B */ | |
520 | {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37, | |
521 | 0x1F, | |
522 | 0x3F}, | |
523 | /* Index 0x3C~0x3F */ | |
524 | {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F, | |
525 | 0x1F, | |
526 | 0x27}, | |
527 | /* Index 0x40~0x43 */ | |
528 | {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F, | |
529 | 0x3F, | |
530 | 0x1F}, | |
531 | /* Index 0x44~0x47 */ | |
532 | {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27, | |
533 | 0x3F, | |
534 | 0x1F}, | |
535 | /* Index 0x48~0x4B */ | |
536 | {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F, | |
537 | 0x3F, | |
538 | 0x37}, | |
539 | /* Index 0x4C~0x4F */ | |
540 | {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F, | |
541 | 0x27, | |
542 | 0x3F}, | |
543 | /* Index 0x50~0x53 */ | |
544 | {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A, | |
545 | 0x2D, | |
546 | 0x3F}, | |
547 | /* Index 0x54~0x57 */ | |
548 | {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F, | |
549 | 0x2D, | |
550 | 0x31}, | |
551 | /* Index 0x58~0x5B */ | |
552 | {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F, | |
553 | 0x3A, | |
554 | 0x2D}, | |
555 | /* Index 0x5C~0x5F */ | |
556 | {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31, | |
557 | 0x3F, | |
558 | 0x2D}, | |
559 | /* Index 0x60~0x63 */ | |
560 | {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D, | |
561 | 0x3F, | |
562 | 0x3A}, | |
563 | /* Index 0x64~0x67 */ | |
564 | {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D, | |
565 | 0x31, | |
566 | 0x3F}, | |
567 | /* Index 0x68~0x6B */ | |
568 | {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15, | |
569 | 0x00, | |
570 | 0x1C}, | |
571 | /* Index 0x6C~0x6F */ | |
572 | {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C, | |
573 | 0x00, | |
574 | 0x07}, | |
575 | /* Index 0x70~0x73 */ | |
576 | {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C, | |
577 | 0x15, | |
578 | 0x00}, | |
579 | /* Index 0x74~0x77 */ | |
580 | {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07, | |
581 | 0x1C, | |
582 | 0x00}, | |
583 | /* Index 0x78~0x7B */ | |
584 | {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00, | |
585 | 0x1C, | |
586 | 0x15}, | |
587 | /* Index 0x7C~0x7F */ | |
588 | {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00, | |
589 | 0x07, | |
590 | 0x1C}, | |
591 | /* Index 0x80~0x83 */ | |
592 | {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18, | |
593 | 0x0E, | |
594 | 0x1C}, | |
595 | /* Index 0x84~0x87 */ | |
596 | {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C, | |
597 | 0x0E, | |
598 | 0x11}, | |
599 | /* Index 0x88~0x8B */ | |
600 | {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C, | |
601 | 0x18, | |
602 | 0x0E}, | |
603 | /* Index 0x8C~0x8F */ | |
604 | {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11, | |
605 | 0x1C, | |
606 | 0x0E}, | |
607 | /* Index 0x90~0x93 */ | |
608 | {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E, | |
609 | 0x1C, | |
610 | 0x18}, | |
611 | /* Index 0x94~0x97 */ | |
612 | {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E, | |
613 | 0x11, | |
614 | 0x1C}, | |
615 | /* Index 0x98~0x9B */ | |
616 | {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A, | |
617 | 0x14, | |
618 | 0x1C}, | |
619 | /* Index 0x9C~0x9F */ | |
620 | {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C, | |
621 | 0x14, | |
622 | 0x16}, | |
623 | /* Index 0xA0~0xA3 */ | |
624 | {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C, | |
625 | 0x1A, | |
626 | 0x14}, | |
627 | /* Index 0xA4~0xA7 */ | |
628 | {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16, | |
629 | 0x1C, | |
630 | 0x14}, | |
631 | /* Index 0xA8~0xAB */ | |
632 | {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14, | |
633 | 0x1C, | |
634 | 0x1A}, | |
635 | /* Index 0xAC~0xAF */ | |
636 | {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14, | |
637 | 0x16, | |
638 | 0x1C}, | |
639 | /* Index 0xB0~0xB3 */ | |
640 | {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C, | |
641 | 0x00, | |
642 | 0x10}, | |
643 | /* Index 0xB4~0xB7 */ | |
644 | {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10, | |
645 | 0x00, | |
646 | 0x04}, | |
647 | /* Index 0xB8~0xBB */ | |
648 | {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10, | |
649 | 0x0C, | |
650 | 0x00}, | |
651 | /* Index 0xBC~0xBF */ | |
652 | {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04, | |
653 | 0x10, | |
654 | 0x00}, | |
655 | /* Index 0xC0~0xC3 */ | |
656 | {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00, | |
657 | 0x10, | |
658 | 0x0C}, | |
659 | /* Index 0xC4~0xC7 */ | |
660 | {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00, | |
661 | 0x04, | |
662 | 0x10}, | |
663 | /* Index 0xC8~0xCB */ | |
664 | {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E, | |
665 | 0x08, | |
666 | 0x10}, | |
667 | /* Index 0xCC~0xCF */ | |
668 | {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10, | |
669 | 0x08, | |
670 | 0x0A}, | |
671 | /* Index 0xD0~0xD3 */ | |
672 | {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10, | |
673 | 0x0E, | |
674 | 0x08}, | |
675 | /* Index 0xD4~0xD7 */ | |
676 | {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A, | |
677 | 0x10, | |
678 | 0x08}, | |
679 | /* Index 0xD8~0xDB */ | |
680 | {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08, | |
681 | 0x10, | |
682 | 0x0E}, | |
683 | /* Index 0xDC~0xDF */ | |
684 | {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08, | |
685 | 0x0A, | |
686 | 0x10}, | |
687 | /* Index 0xE0~0xE3 */ | |
688 | {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F, | |
689 | 0x0B, | |
690 | 0x10}, | |
691 | /* Index 0xE4~0xE7 */ | |
692 | {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10, | |
693 | 0x0B, | |
694 | 0x0C}, | |
695 | /* Index 0xE8~0xEB */ | |
696 | {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10, | |
697 | 0x0F, | |
698 | 0x0B}, | |
699 | /* Index 0xEC~0xEF */ | |
700 | {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C, | |
701 | 0x10, | |
702 | 0x0B}, | |
703 | /* Index 0xF0~0xF3 */ | |
704 | {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B, | |
705 | 0x10, | |
706 | 0x0F}, | |
707 | /* Index 0xF4~0xF7 */ | |
708 | {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B, | |
709 | 0x0C, | |
710 | 0x10}, | |
711 | /* Index 0xF8~0xFB */ | |
712 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, | |
713 | 0x00, | |
714 | 0x00}, | |
715 | /* Index 0xFC~0xFF */ | |
716 | {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, | |
717 | 0x00, | |
718 | 0x00} | |
719 | }; | |
720 | ||
2a918392 | 721 | static struct via_device_mapping device_mapping[] = { |
a2aa9f9f FTS |
722 | {VIA_LDVP0, "LDVP0"}, |
723 | {VIA_LDVP1, "LDVP1"}, | |
724 | {VIA_DVP0, "DVP0"}, | |
2a918392 FTS |
725 | {VIA_CRT, "CRT"}, |
726 | {VIA_DVP1, "DVP1"}, | |
727 | {VIA_LVDS1, "LVDS1"}, | |
728 | {VIA_LVDS2, "LVDS2"} | |
729 | }; | |
730 | ||
d61e0bf3 | 731 | static void load_fix_bit_crtc_reg(void); |
f4ab2f7a FTS |
732 | static void __devinit init_gfx_chip_info(int chip_type); |
733 | static void __devinit init_tmds_chip_info(void); | |
734 | static void __devinit init_lvds_chip_info(void); | |
d61e0bf3 JC |
735 | static void device_screen_off(void); |
736 | static void device_screen_on(void); | |
737 | static void set_display_channel(void); | |
738 | static void device_off(void); | |
739 | static void device_on(void); | |
740 | static void enable_second_display_channel(void); | |
bc684887 | 741 | static void disable_second_display_channel(void); |
d61e0bf3 | 742 | |
d61e0bf3 JC |
743 | void viafb_lock_crt(void) |
744 | { | |
745 | viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); | |
746 | } | |
747 | ||
748 | void viafb_unlock_crt(void) | |
749 | { | |
750 | viafb_write_reg_mask(CR11, VIACR, 0, BIT7); | |
751 | viafb_write_reg_mask(CR47, VIACR, 0, BIT0); | |
752 | } | |
753 | ||
d61e0bf3 JC |
754 | void write_dac_reg(u8 index, u8 r, u8 g, u8 b) |
755 | { | |
756 | outb(index, LUT_INDEX_WRITE); | |
757 | outb(r, LUT_DATA); | |
758 | outb(g, LUT_DATA); | |
759 | outb(b, LUT_DATA); | |
760 | } | |
761 | ||
18d9dc08 FTS |
762 | static u32 get_dvi_devices(int output_interface) |
763 | { | |
764 | switch (output_interface) { | |
765 | case INTERFACE_DVP0: | |
a2aa9f9f | 766 | return VIA_DVP0 | VIA_LDVP0; |
18d9dc08 FTS |
767 | |
768 | case INTERFACE_DVP1: | |
769 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) | |
a2aa9f9f | 770 | return VIA_LDVP1; |
18d9dc08 FTS |
771 | else |
772 | return VIA_DVP1; | |
773 | ||
774 | case INTERFACE_DFP_HIGH: | |
775 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) | |
776 | return 0; | |
777 | else | |
a2aa9f9f | 778 | return VIA_LVDS2 | VIA_DVP0; |
18d9dc08 FTS |
779 | |
780 | case INTERFACE_DFP_LOW: | |
781 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) | |
782 | return 0; | |
783 | else | |
784 | return VIA_DVP1 | VIA_LVDS1; | |
785 | ||
786 | case INTERFACE_TMDS: | |
787 | return VIA_LVDS1; | |
788 | } | |
789 | ||
790 | return 0; | |
791 | } | |
792 | ||
793 | static u32 get_lcd_devices(int output_interface) | |
794 | { | |
795 | switch (output_interface) { | |
796 | case INTERFACE_DVP0: | |
a2aa9f9f | 797 | return VIA_DVP0; |
18d9dc08 FTS |
798 | |
799 | case INTERFACE_DVP1: | |
800 | return VIA_DVP1; | |
801 | ||
802 | case INTERFACE_DFP_HIGH: | |
a2aa9f9f | 803 | return VIA_LVDS2 | VIA_DVP0; |
18d9dc08 FTS |
804 | |
805 | case INTERFACE_DFP_LOW: | |
806 | return VIA_LVDS1 | VIA_DVP1; | |
807 | ||
808 | case INTERFACE_DFP: | |
809 | return VIA_LVDS1 | VIA_LVDS2; | |
810 | ||
811 | case INTERFACE_LVDS0: | |
812 | case INTERFACE_LVDS0LVDS1: | |
813 | return VIA_LVDS1; | |
814 | ||
815 | case INTERFACE_LVDS1: | |
816 | return VIA_LVDS2; | |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
d61e0bf3 JC |
822 | /*Set IGA path for each device*/ |
823 | void viafb_set_iga_path(void) | |
824 | { | |
825 | ||
826 | if (viafb_SAMM_ON == 1) { | |
827 | if (viafb_CRT_ON) { | |
828 | if (viafb_primary_dev == CRT_Device) | |
829 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
830 | else | |
831 | viaparinfo->crt_setting_info->iga_path = IGA2; | |
832 | } | |
833 | ||
834 | if (viafb_DVI_ON) { | |
835 | if (viafb_primary_dev == DVI_Device) | |
836 | viaparinfo->tmds_setting_info->iga_path = IGA1; | |
837 | else | |
838 | viaparinfo->tmds_setting_info->iga_path = IGA2; | |
839 | } | |
840 | ||
841 | if (viafb_LCD_ON) { | |
842 | if (viafb_primary_dev == LCD_Device) { | |
843 | if (viafb_dual_fb && | |
844 | (viaparinfo->chip_info->gfx_chip_name == | |
845 | UNICHROME_CLE266)) { | |
846 | viaparinfo-> | |
847 | lvds_setting_info->iga_path = IGA2; | |
848 | viaparinfo-> | |
849 | crt_setting_info->iga_path = IGA1; | |
850 | viaparinfo-> | |
851 | tmds_setting_info->iga_path = IGA1; | |
852 | } else | |
853 | viaparinfo-> | |
854 | lvds_setting_info->iga_path = IGA1; | |
855 | } else { | |
856 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
857 | } | |
858 | } | |
859 | if (viafb_LCD2_ON) { | |
860 | if (LCD2_Device == viafb_primary_dev) | |
861 | viaparinfo->lvds_setting_info2->iga_path = IGA1; | |
862 | else | |
863 | viaparinfo->lvds_setting_info2->iga_path = IGA2; | |
864 | } | |
865 | } else { | |
866 | viafb_SAMM_ON = 0; | |
867 | ||
868 | if (viafb_CRT_ON && viafb_LCD_ON) { | |
869 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
870 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
871 | } else if (viafb_CRT_ON && viafb_DVI_ON) { | |
872 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
873 | viaparinfo->tmds_setting_info->iga_path = IGA2; | |
874 | } else if (viafb_LCD_ON && viafb_DVI_ON) { | |
875 | viaparinfo->tmds_setting_info->iga_path = IGA1; | |
876 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
877 | } else if (viafb_LCD_ON && viafb_LCD2_ON) { | |
878 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
879 | viaparinfo->lvds_setting_info2->iga_path = IGA2; | |
880 | } else if (viafb_CRT_ON) { | |
881 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
882 | } else if (viafb_LCD_ON) { | |
883 | viaparinfo->lvds_setting_info->iga_path = IGA2; | |
884 | } else if (viafb_DVI_ON) { | |
885 | viaparinfo->tmds_setting_info->iga_path = IGA1; | |
886 | } | |
887 | } | |
18d9dc08 FTS |
888 | |
889 | viaparinfo->shared->iga1_devices = 0; | |
890 | viaparinfo->shared->iga2_devices = 0; | |
891 | if (viafb_CRT_ON) { | |
892 | if (viaparinfo->crt_setting_info->iga_path == IGA1) | |
893 | viaparinfo->shared->iga1_devices |= VIA_CRT; | |
894 | else | |
895 | viaparinfo->shared->iga2_devices |= VIA_CRT; | |
896 | } | |
897 | ||
898 | if (viafb_DVI_ON) { | |
899 | if (viaparinfo->tmds_setting_info->iga_path == IGA1) | |
900 | viaparinfo->shared->iga1_devices |= get_dvi_devices( | |
901 | viaparinfo->chip_info-> | |
902 | tmds_chip_info.output_interface); | |
903 | else | |
904 | viaparinfo->shared->iga2_devices |= get_dvi_devices( | |
905 | viaparinfo->chip_info-> | |
906 | tmds_chip_info.output_interface); | |
907 | } | |
908 | ||
909 | if (viafb_LCD_ON) { | |
910 | if (viaparinfo->lvds_setting_info->iga_path == IGA1) | |
911 | viaparinfo->shared->iga1_devices |= get_lcd_devices( | |
912 | viaparinfo->chip_info-> | |
913 | lvds_chip_info.output_interface); | |
914 | else | |
915 | viaparinfo->shared->iga2_devices |= get_lcd_devices( | |
916 | viaparinfo->chip_info-> | |
917 | lvds_chip_info.output_interface); | |
918 | } | |
919 | ||
920 | if (viafb_LCD2_ON) { | |
921 | if (viaparinfo->lvds_setting_info2->iga_path == IGA1) | |
922 | viaparinfo->shared->iga1_devices |= get_lcd_devices( | |
923 | viaparinfo->chip_info-> | |
924 | lvds_chip_info2.output_interface); | |
925 | else | |
926 | viaparinfo->shared->iga2_devices |= get_lcd_devices( | |
927 | viaparinfo->chip_info-> | |
928 | lvds_chip_info2.output_interface); | |
929 | } | |
d61e0bf3 JC |
930 | } |
931 | ||
415559fb FTS |
932 | static void set_color_register(u8 index, u8 red, u8 green, u8 blue) |
933 | { | |
934 | outb(0xFF, 0x3C6); /* bit mask of palette */ | |
935 | outb(index, 0x3C8); | |
936 | outb(red, 0x3C9); | |
937 | outb(green, 0x3C9); | |
938 | outb(blue, 0x3C9); | |
939 | } | |
940 | ||
941 | void viafb_set_primary_color_register(u8 index, u8 red, u8 green, u8 blue) | |
942 | { | |
943 | viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); | |
944 | set_color_register(index, red, green, blue); | |
945 | } | |
946 | ||
947 | void viafb_set_secondary_color_register(u8 index, u8 red, u8 green, u8 blue) | |
948 | { | |
949 | viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); | |
950 | set_color_register(index, red, green, blue); | |
951 | } | |
952 | ||
a54be174 | 953 | static void set_source_common(u8 index, u8 offset, u8 iga) |
d61e0bf3 | 954 | { |
a54be174 FTS |
955 | u8 value, mask = 1 << offset; |
956 | ||
957 | switch (iga) { | |
958 | case IGA1: | |
959 | value = 0x00; | |
960 | break; | |
961 | case IGA2: | |
962 | value = mask; | |
963 | break; | |
964 | default: | |
965 | printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga); | |
966 | return; | |
967 | } | |
968 | ||
969 | via_write_reg_mask(VIACR, index, value, mask); | |
970 | } | |
971 | ||
972 | static void set_crt_source(u8 iga) | |
973 | { | |
974 | u8 value; | |
d61e0bf3 | 975 | |
a54be174 | 976 | switch (iga) { |
d61e0bf3 | 977 | case IGA1: |
a54be174 | 978 | value = 0x00; |
d61e0bf3 JC |
979 | break; |
980 | case IGA2: | |
a54be174 | 981 | value = 0x40; |
d61e0bf3 | 982 | break; |
a54be174 FTS |
983 | default: |
984 | printk(KERN_WARNING "viafb: Unsupported source: %d\n", iga); | |
985 | return; | |
d61e0bf3 | 986 | } |
a54be174 FTS |
987 | |
988 | via_write_reg_mask(VIASR, 0x16, value, 0x40); | |
989 | } | |
990 | ||
a2aa9f9f | 991 | static inline void set_ldvp0_source(u8 iga) |
a54be174 FTS |
992 | { |
993 | set_source_common(0x6C, 7, iga); | |
994 | } | |
995 | ||
a2aa9f9f | 996 | static inline void set_ldvp1_source(u8 iga) |
a54be174 FTS |
997 | { |
998 | set_source_common(0x93, 7, iga); | |
999 | } | |
1000 | ||
a2aa9f9f | 1001 | static inline void set_dvp0_source(u8 iga) |
a54be174 FTS |
1002 | { |
1003 | set_source_common(0x96, 4, iga); | |
1004 | } | |
1005 | ||
1006 | static inline void set_dvp1_source(u8 iga) | |
1007 | { | |
1008 | set_source_common(0x9B, 4, iga); | |
1009 | } | |
1010 | ||
1011 | static inline void set_lvds1_source(u8 iga) | |
1012 | { | |
1013 | set_source_common(0x99, 4, iga); | |
1014 | } | |
1015 | ||
1016 | static inline void set_lvds2_source(u8 iga) | |
1017 | { | |
1018 | set_source_common(0x97, 4, iga); | |
1019 | } | |
1020 | ||
bc684887 | 1021 | void via_set_source(u32 devices, u8 iga) |
a54be174 | 1022 | { |
a2aa9f9f FTS |
1023 | if (devices & VIA_LDVP0) |
1024 | set_ldvp0_source(iga); | |
1025 | if (devices & VIA_LDVP1) | |
1026 | set_ldvp1_source(iga); | |
1027 | if (devices & VIA_DVP0) | |
1028 | set_dvp0_source(iga); | |
bc684887 FTS |
1029 | if (devices & VIA_CRT) |
1030 | set_crt_source(iga); | |
1031 | if (devices & VIA_DVP1) | |
1032 | set_dvp1_source(iga); | |
1033 | if (devices & VIA_LVDS1) | |
1034 | set_lvds1_source(iga); | |
1035 | if (devices & VIA_LVDS2) | |
1036 | set_lvds2_source(iga); | |
d61e0bf3 JC |
1037 | } |
1038 | ||
6f9422d4 FTS |
1039 | static void set_crt_state(u8 state) |
1040 | { | |
1041 | u8 value; | |
1042 | ||
1043 | switch (state) { | |
1044 | case VIA_STATE_ON: | |
1045 | value = 0x00; | |
1046 | break; | |
1047 | case VIA_STATE_STANDBY: | |
1048 | value = 0x10; | |
1049 | break; | |
1050 | case VIA_STATE_SUSPEND: | |
1051 | value = 0x20; | |
1052 | break; | |
1053 | case VIA_STATE_OFF: | |
1054 | value = 0x30; | |
1055 | break; | |
1056 | default: | |
1057 | return; | |
1058 | } | |
1059 | ||
1060 | via_write_reg_mask(VIACR, 0x36, value, 0x30); | |
1061 | } | |
1062 | ||
a2aa9f9f | 1063 | static void set_dvp0_state(u8 state) |
6f9422d4 FTS |
1064 | { |
1065 | u8 value; | |
1066 | ||
1067 | switch (state) { | |
1068 | case VIA_STATE_ON: | |
1069 | value = 0xC0; | |
1070 | break; | |
1071 | case VIA_STATE_OFF: | |
1072 | value = 0x00; | |
1073 | break; | |
1074 | default: | |
1075 | return; | |
1076 | } | |
1077 | ||
1078 | via_write_reg_mask(VIASR, 0x1E, value, 0xC0); | |
1079 | } | |
1080 | ||
1081 | static void set_dvp1_state(u8 state) | |
1082 | { | |
1083 | u8 value; | |
1084 | ||
1085 | switch (state) { | |
1086 | case VIA_STATE_ON: | |
1087 | value = 0x30; | |
1088 | break; | |
1089 | case VIA_STATE_OFF: | |
1090 | value = 0x00; | |
1091 | break; | |
1092 | default: | |
1093 | return; | |
1094 | } | |
1095 | ||
1096 | via_write_reg_mask(VIASR, 0x1E, value, 0x30); | |
1097 | } | |
1098 | ||
1099 | static void set_lvds1_state(u8 state) | |
1100 | { | |
1101 | u8 value; | |
1102 | ||
1103 | switch (state) { | |
1104 | case VIA_STATE_ON: | |
1105 | value = 0x03; | |
1106 | break; | |
1107 | case VIA_STATE_OFF: | |
1108 | value = 0x00; | |
1109 | break; | |
1110 | default: | |
1111 | return; | |
1112 | } | |
1113 | ||
1114 | via_write_reg_mask(VIASR, 0x2A, value, 0x03); | |
1115 | } | |
1116 | ||
1117 | static void set_lvds2_state(u8 state) | |
1118 | { | |
1119 | u8 value; | |
1120 | ||
1121 | switch (state) { | |
1122 | case VIA_STATE_ON: | |
1123 | value = 0x0C; | |
1124 | break; | |
1125 | case VIA_STATE_OFF: | |
1126 | value = 0x00; | |
1127 | break; | |
1128 | default: | |
1129 | return; | |
1130 | } | |
1131 | ||
1132 | via_write_reg_mask(VIASR, 0x2A, value, 0x0C); | |
1133 | } | |
1134 | ||
1135 | void via_set_state(u32 devices, u8 state) | |
1136 | { | |
1137 | /* | |
1138 | TODO: Can we enable/disable these devices? How? | |
a2aa9f9f FTS |
1139 | if (devices & VIA_LDVP0) |
1140 | if (devices & VIA_LDVP1) | |
6f9422d4 | 1141 | */ |
a2aa9f9f FTS |
1142 | if (devices & VIA_DVP0) |
1143 | set_dvp0_state(state); | |
6f9422d4 FTS |
1144 | if (devices & VIA_CRT) |
1145 | set_crt_state(state); | |
1146 | if (devices & VIA_DVP1) | |
1147 | set_dvp1_state(state); | |
1148 | if (devices & VIA_LVDS1) | |
1149 | set_lvds1_state(state); | |
1150 | if (devices & VIA_LVDS2) | |
1151 | set_lvds2_state(state); | |
1152 | } | |
1153 | ||
7f0e153e FTS |
1154 | void via_set_sync_polarity(u32 devices, u8 polarity) |
1155 | { | |
1156 | if (polarity & ~(VIA_HSYNC_NEGATIVE | VIA_VSYNC_NEGATIVE)) { | |
1157 | printk(KERN_WARNING "viafb: Unsupported polarity: %d\n", | |
1158 | polarity); | |
1159 | return; | |
1160 | } | |
1161 | ||
1162 | if (devices & VIA_CRT) | |
1163 | via_write_misc_reg_mask(polarity << 6, 0xC0); | |
1164 | if (devices & VIA_DVP1) | |
1165 | via_write_reg_mask(VIACR, 0x9B, polarity << 5, 0x60); | |
1166 | if (devices & VIA_LVDS1) | |
1167 | via_write_reg_mask(VIACR, 0x99, polarity << 5, 0x60); | |
1168 | if (devices & VIA_LVDS2) | |
1169 | via_write_reg_mask(VIACR, 0x97, polarity << 5, 0x60); | |
1170 | } | |
1171 | ||
2a918392 FTS |
1172 | u32 via_parse_odev(char *input, char **end) |
1173 | { | |
1174 | char *ptr = input; | |
1175 | u32 odev = 0; | |
1176 | bool next = true; | |
1177 | int i, len; | |
1178 | ||
1179 | while (next) { | |
1180 | next = false; | |
1181 | for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { | |
1182 | len = strlen(device_mapping[i].name); | |
1183 | if (!strncmp(ptr, device_mapping[i].name, len)) { | |
1184 | odev |= device_mapping[i].device; | |
1185 | ptr += len; | |
1186 | if (*ptr == ',') { | |
1187 | ptr++; | |
1188 | next = true; | |
1189 | } | |
1190 | } | |
1191 | } | |
1192 | } | |
1193 | ||
1194 | *end = ptr; | |
1195 | return odev; | |
1196 | } | |
1197 | ||
1198 | void via_odev_to_seq(struct seq_file *m, u32 odev) | |
1199 | { | |
1200 | int i, count = 0; | |
1201 | ||
1202 | for (i = 0; i < ARRAY_SIZE(device_mapping); i++) { | |
1203 | if (odev & device_mapping[i].device) { | |
1204 | if (count > 0) | |
1205 | seq_putc(m, ','); | |
1206 | ||
1207 | seq_puts(m, device_mapping[i].name); | |
1208 | count++; | |
1209 | } | |
1210 | } | |
1211 | ||
1212 | seq_putc(m, '\n'); | |
1213 | } | |
1214 | ||
d61e0bf3 JC |
1215 | static void load_fix_bit_crtc_reg(void) |
1216 | { | |
1217 | /* always set to 1 */ | |
1218 | viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); | |
1219 | /* line compare should set all bits = 1 (extend modes) */ | |
1220 | viafb_write_reg(CR18, VIACR, 0xff); | |
1221 | /* line compare should set all bits = 1 (extend modes) */ | |
1222 | viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4); | |
1223 | /* line compare should set all bits = 1 (extend modes) */ | |
1224 | viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6); | |
1225 | /* line compare should set all bits = 1 (extend modes) */ | |
1226 | viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); | |
1227 | /* line compare should set all bits = 1 (extend modes) */ | |
1228 | viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); | |
1229 | /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */ | |
1230 | /* extend mode always set to e3h */ | |
1231 | viafb_write_reg(CR17, VIACR, 0xe3); | |
1232 | /* extend mode always set to 0h */ | |
1233 | viafb_write_reg(CR08, VIACR, 0x00); | |
1234 | /* extend mode always set to 0h */ | |
1235 | viafb_write_reg(CR14, VIACR, 0x00); | |
1236 | ||
1237 | /* If K8M800, enable Prefetch Mode. */ | |
1238 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) | |
1239 | || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890)) | |
1240 | viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3); | |
1241 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) | |
1242 | && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX)) | |
1243 | viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); | |
1244 | ||
1245 | } | |
1246 | ||
1247 | void viafb_load_reg(int timing_value, int viafb_load_reg_num, | |
1248 | struct io_register *reg, | |
1249 | int io_type) | |
1250 | { | |
1251 | int reg_mask; | |
1252 | int bit_num = 0; | |
1253 | int data; | |
1254 | int i, j; | |
1255 | int shift_next_reg; | |
1256 | int start_index, end_index, cr_index; | |
1257 | u16 get_bit; | |
1258 | ||
1259 | for (i = 0; i < viafb_load_reg_num; i++) { | |
1260 | reg_mask = 0; | |
1261 | data = 0; | |
1262 | start_index = reg[i].start_bit; | |
1263 | end_index = reg[i].end_bit; | |
1264 | cr_index = reg[i].io_addr; | |
1265 | ||
1266 | shift_next_reg = bit_num; | |
1267 | for (j = start_index; j <= end_index; j++) { | |
1268 | /*if (bit_num==8) timing_value = timing_value >>8; */ | |
1269 | reg_mask = reg_mask | (BIT0 << j); | |
1270 | get_bit = (timing_value & (BIT0 << bit_num)); | |
1271 | data = | |
1272 | data | ((get_bit >> shift_next_reg) << start_index); | |
1273 | bit_num++; | |
1274 | } | |
1275 | if (io_type == VIACR) | |
1276 | viafb_write_reg_mask(cr_index, VIACR, data, reg_mask); | |
1277 | else | |
1278 | viafb_write_reg_mask(cr_index, VIASR, data, reg_mask); | |
1279 | } | |
1280 | ||
1281 | } | |
1282 | ||
1283 | /* Write Registers */ | |
1284 | void viafb_write_regx(struct io_reg RegTable[], int ItemNum) | |
1285 | { | |
1286 | int i; | |
d61e0bf3 JC |
1287 | |
1288 | /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */ | |
1289 | ||
384c3041 FTS |
1290 | for (i = 0; i < ItemNum; i++) |
1291 | via_write_reg_mask(RegTable[i].port, RegTable[i].index, | |
1292 | RegTable[i].value, RegTable[i].mask); | |
d61e0bf3 JC |
1293 | } |
1294 | ||
d61e0bf3 JC |
1295 | void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga) |
1296 | { | |
1297 | int reg_value; | |
1298 | int viafb_load_reg_num; | |
1299 | struct io_register *reg = NULL; | |
1300 | ||
1301 | switch (set_iga) { | |
d61e0bf3 JC |
1302 | case IGA1: |
1303 | reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte); | |
1304 | viafb_load_reg_num = fetch_count_reg. | |
1305 | iga1_fetch_count_reg.reg_num; | |
1306 | reg = fetch_count_reg.iga1_fetch_count_reg.reg; | |
1307 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
4bbac05f | 1308 | break; |
d61e0bf3 JC |
1309 | case IGA2: |
1310 | reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte); | |
1311 | viafb_load_reg_num = fetch_count_reg. | |
1312 | iga2_fetch_count_reg.reg_num; | |
1313 | reg = fetch_count_reg.iga2_fetch_count_reg.reg; | |
1314 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1315 | break; | |
1316 | } | |
1317 | ||
1318 | } | |
1319 | ||
1320 | void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active) | |
1321 | { | |
1322 | int reg_value; | |
1323 | int viafb_load_reg_num; | |
1324 | struct io_register *reg = NULL; | |
1325 | int iga1_fifo_max_depth = 0, iga1_fifo_threshold = | |
1326 | 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0; | |
1327 | int iga2_fifo_max_depth = 0, iga2_fifo_threshold = | |
1328 | 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0; | |
1329 | ||
1330 | if (set_iga == IGA1) { | |
1331 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { | |
1332 | iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH; | |
1333 | iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD; | |
1334 | iga1_fifo_high_threshold = | |
1335 | K800_IGA1_FIFO_HIGH_THRESHOLD; | |
1336 | /* If resolution > 1280x1024, expire length = 64, else | |
1337 | expire length = 128 */ | |
1338 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1339 | iga1_display_queue_expire_num = 16; | |
1340 | else | |
1341 | iga1_display_queue_expire_num = | |
1342 | K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1343 | ||
1344 | } | |
1345 | ||
1346 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) { | |
1347 | iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH; | |
1348 | iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD; | |
1349 | iga1_fifo_high_threshold = | |
1350 | P880_IGA1_FIFO_HIGH_THRESHOLD; | |
1351 | iga1_display_queue_expire_num = | |
1352 | P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1353 | ||
1354 | /* If resolution > 1280x1024, expire length = 64, else | |
1355 | expire length = 128 */ | |
1356 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1357 | iga1_display_queue_expire_num = 16; | |
1358 | else | |
1359 | iga1_display_queue_expire_num = | |
1360 | P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1361 | } | |
1362 | ||
1363 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) { | |
1364 | iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH; | |
1365 | iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD; | |
1366 | iga1_fifo_high_threshold = | |
1367 | CN700_IGA1_FIFO_HIGH_THRESHOLD; | |
1368 | ||
1369 | /* If resolution > 1280x1024, expire length = 64, | |
1370 | else expire length = 128 */ | |
1371 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1372 | iga1_display_queue_expire_num = 16; | |
1373 | else | |
1374 | iga1_display_queue_expire_num = | |
1375 | CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1376 | } | |
1377 | ||
1378 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { | |
1379 | iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH; | |
1380 | iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD; | |
1381 | iga1_fifo_high_threshold = | |
1382 | CX700_IGA1_FIFO_HIGH_THRESHOLD; | |
1383 | iga1_display_queue_expire_num = | |
1384 | CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1385 | } | |
1386 | ||
1387 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) { | |
1388 | iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH; | |
1389 | iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD; | |
1390 | iga1_fifo_high_threshold = | |
1391 | K8M890_IGA1_FIFO_HIGH_THRESHOLD; | |
1392 | iga1_display_queue_expire_num = | |
1393 | K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1394 | } | |
1395 | ||
1396 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) { | |
1397 | iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH; | |
1398 | iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD; | |
1399 | iga1_fifo_high_threshold = | |
1400 | P4M890_IGA1_FIFO_HIGH_THRESHOLD; | |
1401 | iga1_display_queue_expire_num = | |
1402 | P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1403 | } | |
1404 | ||
1405 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) { | |
1406 | iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH; | |
1407 | iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD; | |
1408 | iga1_fifo_high_threshold = | |
1409 | P4M900_IGA1_FIFO_HIGH_THRESHOLD; | |
1410 | iga1_display_queue_expire_num = | |
1411 | P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1412 | } | |
1413 | ||
1414 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) { | |
1415 | iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH; | |
1416 | iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD; | |
1417 | iga1_fifo_high_threshold = | |
1418 | VX800_IGA1_FIFO_HIGH_THRESHOLD; | |
1419 | iga1_display_queue_expire_num = | |
1420 | VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1421 | } | |
1422 | ||
0306ab11 HW |
1423 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) { |
1424 | iga1_fifo_max_depth = VX855_IGA1_FIFO_MAX_DEPTH; | |
1425 | iga1_fifo_threshold = VX855_IGA1_FIFO_THRESHOLD; | |
1426 | iga1_fifo_high_threshold = | |
1427 | VX855_IGA1_FIFO_HIGH_THRESHOLD; | |
1428 | iga1_display_queue_expire_num = | |
1429 | VX855_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1430 | } | |
1431 | ||
51f4332b FTS |
1432 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) { |
1433 | iga1_fifo_max_depth = VX900_IGA1_FIFO_MAX_DEPTH; | |
1434 | iga1_fifo_threshold = VX900_IGA1_FIFO_THRESHOLD; | |
1435 | iga1_fifo_high_threshold = | |
1436 | VX900_IGA1_FIFO_HIGH_THRESHOLD; | |
1437 | iga1_display_queue_expire_num = | |
1438 | VX900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM; | |
1439 | } | |
1440 | ||
d61e0bf3 JC |
1441 | /* Set Display FIFO Depath Select */ |
1442 | reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth); | |
1443 | viafb_load_reg_num = | |
1444 | display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num; | |
1445 | reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg; | |
1446 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
1447 | ||
1448 | /* Set Display FIFO Threshold Select */ | |
1449 | reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold); | |
1450 | viafb_load_reg_num = | |
1451 | fifo_threshold_select_reg. | |
1452 | iga1_fifo_threshold_select_reg.reg_num; | |
1453 | reg = | |
1454 | fifo_threshold_select_reg. | |
1455 | iga1_fifo_threshold_select_reg.reg; | |
1456 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
1457 | ||
1458 | /* Set FIFO High Threshold Select */ | |
1459 | reg_value = | |
1460 | IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold); | |
1461 | viafb_load_reg_num = | |
1462 | fifo_high_threshold_select_reg. | |
1463 | iga1_fifo_high_threshold_select_reg.reg_num; | |
1464 | reg = | |
1465 | fifo_high_threshold_select_reg. | |
1466 | iga1_fifo_high_threshold_select_reg.reg; | |
1467 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
1468 | ||
1469 | /* Set Display Queue Expire Num */ | |
1470 | reg_value = | |
1471 | IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA | |
1472 | (iga1_display_queue_expire_num); | |
1473 | viafb_load_reg_num = | |
1474 | display_queue_expire_num_reg. | |
1475 | iga1_display_queue_expire_num_reg.reg_num; | |
1476 | reg = | |
1477 | display_queue_expire_num_reg. | |
1478 | iga1_display_queue_expire_num_reg.reg; | |
1479 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR); | |
1480 | ||
1481 | } else { | |
1482 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { | |
1483 | iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH; | |
1484 | iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD; | |
1485 | iga2_fifo_high_threshold = | |
1486 | K800_IGA2_FIFO_HIGH_THRESHOLD; | |
1487 | ||
1488 | /* If resolution > 1280x1024, expire length = 64, | |
1489 | else expire length = 128 */ | |
1490 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1491 | iga2_display_queue_expire_num = 16; | |
1492 | else | |
1493 | iga2_display_queue_expire_num = | |
1494 | K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1495 | } | |
1496 | ||
1497 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) { | |
1498 | iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH; | |
1499 | iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD; | |
1500 | iga2_fifo_high_threshold = | |
1501 | P880_IGA2_FIFO_HIGH_THRESHOLD; | |
1502 | ||
1503 | /* If resolution > 1280x1024, expire length = 64, | |
1504 | else expire length = 128 */ | |
1505 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1506 | iga2_display_queue_expire_num = 16; | |
1507 | else | |
1508 | iga2_display_queue_expire_num = | |
1509 | P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1510 | } | |
1511 | ||
1512 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) { | |
1513 | iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH; | |
1514 | iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD; | |
1515 | iga2_fifo_high_threshold = | |
1516 | CN700_IGA2_FIFO_HIGH_THRESHOLD; | |
1517 | ||
1518 | /* If resolution > 1280x1024, expire length = 64, | |
1519 | else expire length = 128 */ | |
1520 | if ((hor_active > 1280) && (ver_active > 1024)) | |
1521 | iga2_display_queue_expire_num = 16; | |
1522 | else | |
1523 | iga2_display_queue_expire_num = | |
1524 | CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1525 | } | |
1526 | ||
1527 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { | |
1528 | iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH; | |
1529 | iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD; | |
1530 | iga2_fifo_high_threshold = | |
1531 | CX700_IGA2_FIFO_HIGH_THRESHOLD; | |
1532 | iga2_display_queue_expire_num = | |
1533 | CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1534 | } | |
1535 | ||
1536 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) { | |
1537 | iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH; | |
1538 | iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD; | |
1539 | iga2_fifo_high_threshold = | |
1540 | K8M890_IGA2_FIFO_HIGH_THRESHOLD; | |
1541 | iga2_display_queue_expire_num = | |
1542 | K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1543 | } | |
1544 | ||
1545 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) { | |
1546 | iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH; | |
1547 | iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD; | |
1548 | iga2_fifo_high_threshold = | |
1549 | P4M890_IGA2_FIFO_HIGH_THRESHOLD; | |
1550 | iga2_display_queue_expire_num = | |
1551 | P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1552 | } | |
1553 | ||
1554 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) { | |
1555 | iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH; | |
1556 | iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD; | |
1557 | iga2_fifo_high_threshold = | |
1558 | P4M900_IGA2_FIFO_HIGH_THRESHOLD; | |
1559 | iga2_display_queue_expire_num = | |
1560 | P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1561 | } | |
1562 | ||
1563 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) { | |
1564 | iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH; | |
1565 | iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD; | |
1566 | iga2_fifo_high_threshold = | |
1567 | VX800_IGA2_FIFO_HIGH_THRESHOLD; | |
1568 | iga2_display_queue_expire_num = | |
1569 | VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1570 | } | |
1571 | ||
0306ab11 HW |
1572 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX855) { |
1573 | iga2_fifo_max_depth = VX855_IGA2_FIFO_MAX_DEPTH; | |
1574 | iga2_fifo_threshold = VX855_IGA2_FIFO_THRESHOLD; | |
1575 | iga2_fifo_high_threshold = | |
1576 | VX855_IGA2_FIFO_HIGH_THRESHOLD; | |
1577 | iga2_display_queue_expire_num = | |
1578 | VX855_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1579 | } | |
1580 | ||
51f4332b FTS |
1581 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX900) { |
1582 | iga2_fifo_max_depth = VX900_IGA2_FIFO_MAX_DEPTH; | |
1583 | iga2_fifo_threshold = VX900_IGA2_FIFO_THRESHOLD; | |
1584 | iga2_fifo_high_threshold = | |
1585 | VX900_IGA2_FIFO_HIGH_THRESHOLD; | |
1586 | iga2_display_queue_expire_num = | |
1587 | VX900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM; | |
1588 | } | |
1589 | ||
d61e0bf3 JC |
1590 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) { |
1591 | /* Set Display FIFO Depath Select */ | |
1592 | reg_value = | |
1593 | IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth) | |
1594 | - 1; | |
1595 | /* Patch LCD in IGA2 case */ | |
1596 | viafb_load_reg_num = | |
1597 | display_fifo_depth_reg. | |
1598 | iga2_fifo_depth_select_reg.reg_num; | |
1599 | reg = | |
1600 | display_fifo_depth_reg. | |
1601 | iga2_fifo_depth_select_reg.reg; | |
1602 | viafb_load_reg(reg_value, | |
1603 | viafb_load_reg_num, reg, VIACR); | |
1604 | } else { | |
1605 | ||
1606 | /* Set Display FIFO Depath Select */ | |
1607 | reg_value = | |
1608 | IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth); | |
1609 | viafb_load_reg_num = | |
1610 | display_fifo_depth_reg. | |
1611 | iga2_fifo_depth_select_reg.reg_num; | |
1612 | reg = | |
1613 | display_fifo_depth_reg. | |
1614 | iga2_fifo_depth_select_reg.reg; | |
1615 | viafb_load_reg(reg_value, | |
1616 | viafb_load_reg_num, reg, VIACR); | |
1617 | } | |
1618 | ||
1619 | /* Set Display FIFO Threshold Select */ | |
1620 | reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold); | |
1621 | viafb_load_reg_num = | |
1622 | fifo_threshold_select_reg. | |
1623 | iga2_fifo_threshold_select_reg.reg_num; | |
1624 | reg = | |
1625 | fifo_threshold_select_reg. | |
1626 | iga2_fifo_threshold_select_reg.reg; | |
1627 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1628 | ||
1629 | /* Set FIFO High Threshold Select */ | |
1630 | reg_value = | |
1631 | IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold); | |
1632 | viafb_load_reg_num = | |
1633 | fifo_high_threshold_select_reg. | |
1634 | iga2_fifo_high_threshold_select_reg.reg_num; | |
1635 | reg = | |
1636 | fifo_high_threshold_select_reg. | |
1637 | iga2_fifo_high_threshold_select_reg.reg; | |
1638 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1639 | ||
1640 | /* Set Display Queue Expire Num */ | |
1641 | reg_value = | |
1642 | IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA | |
1643 | (iga2_display_queue_expire_num); | |
1644 | viafb_load_reg_num = | |
1645 | display_queue_expire_num_reg. | |
1646 | iga2_display_queue_expire_num_reg.reg_num; | |
1647 | reg = | |
1648 | display_queue_expire_num_reg. | |
1649 | iga2_display_queue_expire_num_reg.reg; | |
1650 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
1651 | ||
1652 | } | |
1653 | ||
1654 | } | |
1655 | ||
1f844350 FTS |
1656 | static u32 cle266_encode_pll(struct pll_config pll) |
1657 | { | |
1658 | return (pll.multiplier << 8) | |
1659 | | (pll.rshift << 6) | |
1660 | | pll.divisor; | |
1661 | } | |
1662 | ||
1663 | static u32 k800_encode_pll(struct pll_config pll) | |
1664 | { | |
1665 | return ((pll.divisor - 2) << 16) | |
1666 | | (pll.rshift << 10) | |
1667 | | (pll.multiplier - 2); | |
1668 | } | |
1669 | ||
1670 | static u32 vx855_encode_pll(struct pll_config pll) | |
1671 | { | |
1672 | return (pll.divisor << 16) | |
1673 | | (pll.rshift << 10) | |
1674 | | pll.multiplier; | |
1675 | } | |
1676 | ||
d61e0bf3 JC |
1677 | u32 viafb_get_clk_value(int clk) |
1678 | { | |
1f844350 FTS |
1679 | u32 value = 0; |
1680 | int i = 0; | |
d61e0bf3 | 1681 | |
1f844350 FTS |
1682 | while (i < NUM_TOTAL_PLL_TABLE && clk != pll_value[i].clk) |
1683 | i++; | |
1684 | ||
1685 | if (i == NUM_TOTAL_PLL_TABLE) { | |
1686 | printk(KERN_WARNING "viafb_get_clk_value: PLL lookup failed!"); | |
1687 | } else { | |
1688 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
1689 | case UNICHROME_CLE266: | |
1690 | case UNICHROME_K400: | |
1691 | value = cle266_encode_pll(pll_value[i].cle266_pll); | |
1692 | break; | |
1693 | ||
1694 | case UNICHROME_K800: | |
1695 | case UNICHROME_PM800: | |
1696 | case UNICHROME_CN700: | |
1697 | value = k800_encode_pll(pll_value[i].k800_pll); | |
1698 | break; | |
1699 | ||
1700 | case UNICHROME_CX700: | |
1701 | case UNICHROME_CN750: | |
1702 | case UNICHROME_K8M890: | |
1703 | case UNICHROME_P4M890: | |
1704 | case UNICHROME_P4M900: | |
1705 | case UNICHROME_VX800: | |
1706 | value = k800_encode_pll(pll_value[i].cx700_pll); | |
1707 | break; | |
1708 | ||
1709 | case UNICHROME_VX855: | |
51f4332b | 1710 | case UNICHROME_VX900: |
1f844350 FTS |
1711 | value = vx855_encode_pll(pll_value[i].vx855_pll); |
1712 | break; | |
d61e0bf3 JC |
1713 | } |
1714 | } | |
1715 | ||
1f844350 | 1716 | return value; |
d61e0bf3 JC |
1717 | } |
1718 | ||
1719 | /* Set VCLK*/ | |
1f844350 | 1720 | void viafb_set_vclock(u32 clk, int set_iga) |
d61e0bf3 | 1721 | { |
d61e0bf3 JC |
1722 | /* H.W. Reset : ON */ |
1723 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); | |
1724 | ||
4bbac05f | 1725 | if (set_iga == IGA1) { |
d61e0bf3 JC |
1726 | /* Change D,N FOR VCLK */ |
1727 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
1728 | case UNICHROME_CLE266: | |
1729 | case UNICHROME_K400: | |
1f844350 FTS |
1730 | via_write_reg(VIASR, SR46, (clk & 0x00FF)); |
1731 | via_write_reg(VIASR, SR47, (clk & 0xFF00) >> 8); | |
d61e0bf3 JC |
1732 | break; |
1733 | ||
1734 | case UNICHROME_K800: | |
1735 | case UNICHROME_PM800: | |
1736 | case UNICHROME_CN700: | |
1737 | case UNICHROME_CX700: | |
1f844350 | 1738 | case UNICHROME_CN750: |
d61e0bf3 JC |
1739 | case UNICHROME_K8M890: |
1740 | case UNICHROME_P4M890: | |
1741 | case UNICHROME_P4M900: | |
1742 | case UNICHROME_VX800: | |
0306ab11 | 1743 | case UNICHROME_VX855: |
51f4332b | 1744 | case UNICHROME_VX900: |
1f844350 FTS |
1745 | via_write_reg(VIASR, SR44, (clk & 0x0000FF)); |
1746 | via_write_reg(VIASR, SR45, (clk & 0x00FF00) >> 8); | |
1747 | via_write_reg(VIASR, SR46, (clk & 0xFF0000) >> 16); | |
d61e0bf3 JC |
1748 | break; |
1749 | } | |
1750 | } | |
1751 | ||
4bbac05f | 1752 | if (set_iga == IGA2) { |
d61e0bf3 JC |
1753 | /* Change D,N FOR LCK */ |
1754 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
1755 | case UNICHROME_CLE266: | |
1756 | case UNICHROME_K400: | |
1f844350 FTS |
1757 | via_write_reg(VIASR, SR44, (clk & 0x00FF)); |
1758 | via_write_reg(VIASR, SR45, (clk & 0xFF00) >> 8); | |
d61e0bf3 JC |
1759 | break; |
1760 | ||
1761 | case UNICHROME_K800: | |
1762 | case UNICHROME_PM800: | |
1763 | case UNICHROME_CN700: | |
1764 | case UNICHROME_CX700: | |
1f844350 | 1765 | case UNICHROME_CN750: |
d61e0bf3 JC |
1766 | case UNICHROME_K8M890: |
1767 | case UNICHROME_P4M890: | |
1768 | case UNICHROME_P4M900: | |
1769 | case UNICHROME_VX800: | |
0306ab11 | 1770 | case UNICHROME_VX855: |
51f4332b | 1771 | case UNICHROME_VX900: |
1f844350 FTS |
1772 | via_write_reg(VIASR, SR4A, (clk & 0x0000FF)); |
1773 | via_write_reg(VIASR, SR4B, (clk & 0x00FF00) >> 8); | |
1774 | via_write_reg(VIASR, SR4C, (clk & 0xFF0000) >> 16); | |
d61e0bf3 JC |
1775 | break; |
1776 | } | |
1777 | } | |
1778 | ||
1779 | /* H.W. Reset : OFF */ | |
1780 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); | |
1781 | ||
1782 | /* Reset PLL */ | |
4bbac05f | 1783 | if (set_iga == IGA1) { |
d61e0bf3 JC |
1784 | viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1); |
1785 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1); | |
1786 | } | |
1787 | ||
4bbac05f | 1788 | if (set_iga == IGA2) { |
e3812ce4 FTS |
1789 | viafb_write_reg_mask(SR40, VIASR, 0x04, BIT2); |
1790 | viafb_write_reg_mask(SR40, VIASR, 0x00, BIT2); | |
d61e0bf3 JC |
1791 | } |
1792 | ||
1793 | /* Fire! */ | |
162fc8c0 | 1794 | via_write_misc_reg_mask(0x0C, 0x0C); /* select external clock */ |
d61e0bf3 JC |
1795 | } |
1796 | ||
1797 | void viafb_load_crtc_timing(struct display_timing device_timing, | |
1798 | int set_iga) | |
1799 | { | |
1800 | int i; | |
1801 | int viafb_load_reg_num = 0; | |
1802 | int reg_value = 0; | |
1803 | struct io_register *reg = NULL; | |
1804 | ||
1805 | viafb_unlock_crt(); | |
1806 | ||
1807 | for (i = 0; i < 12; i++) { | |
1808 | if (set_iga == IGA1) { | |
1809 | switch (i) { | |
1810 | case H_TOTAL_INDEX: | |
1811 | reg_value = | |
1812 | IGA1_HOR_TOTAL_FORMULA(device_timing. | |
1813 | hor_total); | |
1814 | viafb_load_reg_num = | |
1815 | iga1_crtc_reg.hor_total.reg_num; | |
1816 | reg = iga1_crtc_reg.hor_total.reg; | |
1817 | break; | |
1818 | case H_ADDR_INDEX: | |
1819 | reg_value = | |
1820 | IGA1_HOR_ADDR_FORMULA(device_timing. | |
1821 | hor_addr); | |
1822 | viafb_load_reg_num = | |
1823 | iga1_crtc_reg.hor_addr.reg_num; | |
1824 | reg = iga1_crtc_reg.hor_addr.reg; | |
1825 | break; | |
1826 | case H_BLANK_START_INDEX: | |
1827 | reg_value = | |
1828 | IGA1_HOR_BLANK_START_FORMULA | |
1829 | (device_timing.hor_blank_start); | |
1830 | viafb_load_reg_num = | |
1831 | iga1_crtc_reg.hor_blank_start.reg_num; | |
1832 | reg = iga1_crtc_reg.hor_blank_start.reg; | |
1833 | break; | |
1834 | case H_BLANK_END_INDEX: | |
1835 | reg_value = | |
1836 | IGA1_HOR_BLANK_END_FORMULA | |
1837 | (device_timing.hor_blank_start, | |
1838 | device_timing.hor_blank_end); | |
1839 | viafb_load_reg_num = | |
1840 | iga1_crtc_reg.hor_blank_end.reg_num; | |
1841 | reg = iga1_crtc_reg.hor_blank_end.reg; | |
1842 | break; | |
1843 | case H_SYNC_START_INDEX: | |
1844 | reg_value = | |
1845 | IGA1_HOR_SYNC_START_FORMULA | |
1846 | (device_timing.hor_sync_start); | |
1847 | viafb_load_reg_num = | |
1848 | iga1_crtc_reg.hor_sync_start.reg_num; | |
1849 | reg = iga1_crtc_reg.hor_sync_start.reg; | |
1850 | break; | |
1851 | case H_SYNC_END_INDEX: | |
1852 | reg_value = | |
1853 | IGA1_HOR_SYNC_END_FORMULA | |
1854 | (device_timing.hor_sync_start, | |
1855 | device_timing.hor_sync_end); | |
1856 | viafb_load_reg_num = | |
1857 | iga1_crtc_reg.hor_sync_end.reg_num; | |
1858 | reg = iga1_crtc_reg.hor_sync_end.reg; | |
1859 | break; | |
1860 | case V_TOTAL_INDEX: | |
1861 | reg_value = | |
1862 | IGA1_VER_TOTAL_FORMULA(device_timing. | |
1863 | ver_total); | |
1864 | viafb_load_reg_num = | |
1865 | iga1_crtc_reg.ver_total.reg_num; | |
1866 | reg = iga1_crtc_reg.ver_total.reg; | |
1867 | break; | |
1868 | case V_ADDR_INDEX: | |
1869 | reg_value = | |
1870 | IGA1_VER_ADDR_FORMULA(device_timing. | |
1871 | ver_addr); | |
1872 | viafb_load_reg_num = | |
1873 | iga1_crtc_reg.ver_addr.reg_num; | |
1874 | reg = iga1_crtc_reg.ver_addr.reg; | |
1875 | break; | |
1876 | case V_BLANK_START_INDEX: | |
1877 | reg_value = | |
1878 | IGA1_VER_BLANK_START_FORMULA | |
1879 | (device_timing.ver_blank_start); | |
1880 | viafb_load_reg_num = | |
1881 | iga1_crtc_reg.ver_blank_start.reg_num; | |
1882 | reg = iga1_crtc_reg.ver_blank_start.reg; | |
1883 | break; | |
1884 | case V_BLANK_END_INDEX: | |
1885 | reg_value = | |
1886 | IGA1_VER_BLANK_END_FORMULA | |
1887 | (device_timing.ver_blank_start, | |
1888 | device_timing.ver_blank_end); | |
1889 | viafb_load_reg_num = | |
1890 | iga1_crtc_reg.ver_blank_end.reg_num; | |
1891 | reg = iga1_crtc_reg.ver_blank_end.reg; | |
1892 | break; | |
1893 | case V_SYNC_START_INDEX: | |
1894 | reg_value = | |
1895 | IGA1_VER_SYNC_START_FORMULA | |
1896 | (device_timing.ver_sync_start); | |
1897 | viafb_load_reg_num = | |
1898 | iga1_crtc_reg.ver_sync_start.reg_num; | |
1899 | reg = iga1_crtc_reg.ver_sync_start.reg; | |
1900 | break; | |
1901 | case V_SYNC_END_INDEX: | |
1902 | reg_value = | |
1903 | IGA1_VER_SYNC_END_FORMULA | |
1904 | (device_timing.ver_sync_start, | |
1905 | device_timing.ver_sync_end); | |
1906 | viafb_load_reg_num = | |
1907 | iga1_crtc_reg.ver_sync_end.reg_num; | |
1908 | reg = iga1_crtc_reg.ver_sync_end.reg; | |
1909 | break; | |
1910 | ||
1911 | } | |
1912 | } | |
1913 | ||
1914 | if (set_iga == IGA2) { | |
1915 | switch (i) { | |
1916 | case H_TOTAL_INDEX: | |
1917 | reg_value = | |
1918 | IGA2_HOR_TOTAL_FORMULA(device_timing. | |
1919 | hor_total); | |
1920 | viafb_load_reg_num = | |
1921 | iga2_crtc_reg.hor_total.reg_num; | |
1922 | reg = iga2_crtc_reg.hor_total.reg; | |
1923 | break; | |
1924 | case H_ADDR_INDEX: | |
1925 | reg_value = | |
1926 | IGA2_HOR_ADDR_FORMULA(device_timing. | |
1927 | hor_addr); | |
1928 | viafb_load_reg_num = | |
1929 | iga2_crtc_reg.hor_addr.reg_num; | |
1930 | reg = iga2_crtc_reg.hor_addr.reg; | |
1931 | break; | |
1932 | case H_BLANK_START_INDEX: | |
1933 | reg_value = | |
1934 | IGA2_HOR_BLANK_START_FORMULA | |
1935 | (device_timing.hor_blank_start); | |
1936 | viafb_load_reg_num = | |
1937 | iga2_crtc_reg.hor_blank_start.reg_num; | |
1938 | reg = iga2_crtc_reg.hor_blank_start.reg; | |
1939 | break; | |
1940 | case H_BLANK_END_INDEX: | |
1941 | reg_value = | |
1942 | IGA2_HOR_BLANK_END_FORMULA | |
1943 | (device_timing.hor_blank_start, | |
1944 | device_timing.hor_blank_end); | |
1945 | viafb_load_reg_num = | |
1946 | iga2_crtc_reg.hor_blank_end.reg_num; | |
1947 | reg = iga2_crtc_reg.hor_blank_end.reg; | |
1948 | break; | |
1949 | case H_SYNC_START_INDEX: | |
1950 | reg_value = | |
1951 | IGA2_HOR_SYNC_START_FORMULA | |
1952 | (device_timing.hor_sync_start); | |
1953 | if (UNICHROME_CN700 <= | |
1954 | viaparinfo->chip_info->gfx_chip_name) | |
1955 | viafb_load_reg_num = | |
1956 | iga2_crtc_reg.hor_sync_start. | |
1957 | reg_num; | |
1958 | else | |
1959 | viafb_load_reg_num = 3; | |
1960 | reg = iga2_crtc_reg.hor_sync_start.reg; | |
1961 | break; | |
1962 | case H_SYNC_END_INDEX: | |
1963 | reg_value = | |
1964 | IGA2_HOR_SYNC_END_FORMULA | |
1965 | (device_timing.hor_sync_start, | |
1966 | device_timing.hor_sync_end); | |
1967 | viafb_load_reg_num = | |
1968 | iga2_crtc_reg.hor_sync_end.reg_num; | |
1969 | reg = iga2_crtc_reg.hor_sync_end.reg; | |
1970 | break; | |
1971 | case V_TOTAL_INDEX: | |
1972 | reg_value = | |
1973 | IGA2_VER_TOTAL_FORMULA(device_timing. | |
1974 | ver_total); | |
1975 | viafb_load_reg_num = | |
1976 | iga2_crtc_reg.ver_total.reg_num; | |
1977 | reg = iga2_crtc_reg.ver_total.reg; | |
1978 | break; | |
1979 | case V_ADDR_INDEX: | |
1980 | reg_value = | |
1981 | IGA2_VER_ADDR_FORMULA(device_timing. | |
1982 | ver_addr); | |
1983 | viafb_load_reg_num = | |
1984 | iga2_crtc_reg.ver_addr.reg_num; | |
1985 | reg = iga2_crtc_reg.ver_addr.reg; | |
1986 | break; | |
1987 | case V_BLANK_START_INDEX: | |
1988 | reg_value = | |
1989 | IGA2_VER_BLANK_START_FORMULA | |
1990 | (device_timing.ver_blank_start); | |
1991 | viafb_load_reg_num = | |
1992 | iga2_crtc_reg.ver_blank_start.reg_num; | |
1993 | reg = iga2_crtc_reg.ver_blank_start.reg; | |
1994 | break; | |
1995 | case V_BLANK_END_INDEX: | |
1996 | reg_value = | |
1997 | IGA2_VER_BLANK_END_FORMULA | |
1998 | (device_timing.ver_blank_start, | |
1999 | device_timing.ver_blank_end); | |
2000 | viafb_load_reg_num = | |
2001 | iga2_crtc_reg.ver_blank_end.reg_num; | |
2002 | reg = iga2_crtc_reg.ver_blank_end.reg; | |
2003 | break; | |
2004 | case V_SYNC_START_INDEX: | |
2005 | reg_value = | |
2006 | IGA2_VER_SYNC_START_FORMULA | |
2007 | (device_timing.ver_sync_start); | |
2008 | viafb_load_reg_num = | |
2009 | iga2_crtc_reg.ver_sync_start.reg_num; | |
2010 | reg = iga2_crtc_reg.ver_sync_start.reg; | |
2011 | break; | |
2012 | case V_SYNC_END_INDEX: | |
2013 | reg_value = | |
2014 | IGA2_VER_SYNC_END_FORMULA | |
2015 | (device_timing.ver_sync_start, | |
2016 | device_timing.ver_sync_end); | |
2017 | viafb_load_reg_num = | |
2018 | iga2_crtc_reg.ver_sync_end.reg_num; | |
2019 | reg = iga2_crtc_reg.ver_sync_end.reg; | |
2020 | break; | |
2021 | ||
2022 | } | |
2023 | } | |
2024 | viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR); | |
2025 | } | |
2026 | ||
2027 | viafb_lock_crt(); | |
2028 | } | |
2029 | ||
d61e0bf3 | 2030 | void viafb_fill_crtc_timing(struct crt_mode_table *crt_table, |
dd73d686 | 2031 | struct VideoModeTable *video_mode, int bpp_byte, int set_iga) |
d61e0bf3 | 2032 | { |
d61e0bf3 JC |
2033 | struct display_timing crt_reg; |
2034 | int i; | |
2035 | int index = 0; | |
2036 | int h_addr, v_addr; | |
2037 | u32 pll_D_N; | |
2038 | ||
d61e0bf3 JC |
2039 | for (i = 0; i < video_mode->mode_array; i++) { |
2040 | index = i; | |
2041 | ||
2042 | if (crt_table[i].refresh_rate == viaparinfo-> | |
2043 | crt_setting_info->refresh_rate) | |
2044 | break; | |
2045 | } | |
2046 | ||
2047 | crt_reg = crt_table[index].crtc; | |
2048 | ||
2049 | /* Mode 640x480 has border, but LCD/DFP didn't have border. */ | |
2050 | /* So we would delete border. */ | |
dd73d686 FTS |
2051 | if ((viafb_LCD_ON | viafb_DVI_ON) |
2052 | && video_mode->crtc[0].crtc.hor_addr == 640 | |
2053 | && video_mode->crtc[0].crtc.ver_addr == 480 | |
2054 | && viaparinfo->crt_setting_info->refresh_rate == 60) { | |
d61e0bf3 JC |
2055 | /* The border is 8 pixels. */ |
2056 | crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8; | |
2057 | ||
2058 | /* Blanking time should add left and right borders. */ | |
2059 | crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16; | |
2060 | } | |
2061 | ||
2062 | h_addr = crt_reg.hor_addr; | |
2063 | v_addr = crt_reg.ver_addr; | |
d61e0bf3 JC |
2064 | if (set_iga == IGA1) { |
2065 | viafb_unlock_crt(); | |
2066 | viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */ | |
2067 | viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6); | |
2068 | viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7); | |
2069 | } | |
2070 | ||
2071 | switch (set_iga) { | |
2072 | case IGA1: | |
2073 | viafb_load_crtc_timing(crt_reg, IGA1); | |
2074 | break; | |
2075 | case IGA2: | |
2076 | viafb_load_crtc_timing(crt_reg, IGA2); | |
2077 | break; | |
2078 | } | |
2079 | ||
2080 | load_fix_bit_crtc_reg(); | |
2081 | viafb_lock_crt(); | |
2082 | viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7); | |
d61e0bf3 JC |
2083 | viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga); |
2084 | ||
2085 | /* load FIFO */ | |
2086 | if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) | |
2087 | && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400)) | |
2088 | viafb_load_FIFO_reg(set_iga, h_addr, v_addr); | |
2089 | ||
d61e0bf3 JC |
2090 | pll_D_N = viafb_get_clk_value(crt_table[index].clk); |
2091 | DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N); | |
2092 | viafb_set_vclock(pll_D_N, set_iga); | |
2093 | ||
2094 | } | |
2095 | ||
f4ab2f7a | 2096 | void __devinit viafb_init_chip_info(int chip_type) |
d61e0bf3 | 2097 | { |
24b4d82e | 2098 | init_gfx_chip_info(chip_type); |
d61e0bf3 JC |
2099 | init_tmds_chip_info(); |
2100 | init_lvds_chip_info(); | |
2101 | ||
2102 | viaparinfo->crt_setting_info->iga_path = IGA1; | |
2103 | viaparinfo->crt_setting_info->refresh_rate = viafb_refresh; | |
2104 | ||
2105 | /*Set IGA path for each device */ | |
2106 | viafb_set_iga_path(); | |
2107 | ||
2108 | viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method; | |
d61e0bf3 JC |
2109 | viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode; |
2110 | viaparinfo->lvds_setting_info2->display_method = | |
2111 | viaparinfo->lvds_setting_info->display_method; | |
2112 | viaparinfo->lvds_setting_info2->lcd_mode = | |
2113 | viaparinfo->lvds_setting_info->lcd_mode; | |
2114 | } | |
2115 | ||
2116 | void viafb_update_device_setting(int hres, int vres, | |
2117 | int bpp, int vmode_refresh, int flag) | |
2118 | { | |
2119 | if (flag == 0) { | |
2120 | viaparinfo->crt_setting_info->h_active = hres; | |
2121 | viaparinfo->crt_setting_info->v_active = vres; | |
2122 | viaparinfo->crt_setting_info->bpp = bpp; | |
2123 | viaparinfo->crt_setting_info->refresh_rate = | |
2124 | vmode_refresh; | |
2125 | ||
2126 | viaparinfo->tmds_setting_info->h_active = hres; | |
2127 | viaparinfo->tmds_setting_info->v_active = vres; | |
d61e0bf3 JC |
2128 | |
2129 | viaparinfo->lvds_setting_info->h_active = hres; | |
2130 | viaparinfo->lvds_setting_info->v_active = vres; | |
2131 | viaparinfo->lvds_setting_info->bpp = bpp; | |
2132 | viaparinfo->lvds_setting_info->refresh_rate = | |
2133 | vmode_refresh; | |
2134 | viaparinfo->lvds_setting_info2->h_active = hres; | |
2135 | viaparinfo->lvds_setting_info2->v_active = vres; | |
2136 | viaparinfo->lvds_setting_info2->bpp = bpp; | |
2137 | viaparinfo->lvds_setting_info2->refresh_rate = | |
2138 | vmode_refresh; | |
2139 | } else { | |
2140 | ||
2141 | if (viaparinfo->tmds_setting_info->iga_path == IGA2) { | |
2142 | viaparinfo->tmds_setting_info->h_active = hres; | |
2143 | viaparinfo->tmds_setting_info->v_active = vres; | |
d61e0bf3 JC |
2144 | } |
2145 | ||
2146 | if (viaparinfo->lvds_setting_info->iga_path == IGA2) { | |
2147 | viaparinfo->lvds_setting_info->h_active = hres; | |
2148 | viaparinfo->lvds_setting_info->v_active = vres; | |
2149 | viaparinfo->lvds_setting_info->bpp = bpp; | |
2150 | viaparinfo->lvds_setting_info->refresh_rate = | |
2151 | vmode_refresh; | |
2152 | } | |
2153 | if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) { | |
2154 | viaparinfo->lvds_setting_info2->h_active = hres; | |
2155 | viaparinfo->lvds_setting_info2->v_active = vres; | |
2156 | viaparinfo->lvds_setting_info2->bpp = bpp; | |
2157 | viaparinfo->lvds_setting_info2->refresh_rate = | |
2158 | vmode_refresh; | |
2159 | } | |
2160 | } | |
2161 | } | |
2162 | ||
f4ab2f7a | 2163 | static void __devinit init_gfx_chip_info(int chip_type) |
d61e0bf3 | 2164 | { |
d61e0bf3 JC |
2165 | u8 tmp; |
2166 | ||
24b4d82e | 2167 | viaparinfo->chip_info->gfx_chip_name = chip_type; |
d61e0bf3 JC |
2168 | |
2169 | /* Check revision of CLE266 Chip */ | |
2170 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) { | |
2171 | /* CR4F only define in CLE266.CX chip */ | |
2172 | tmp = viafb_read_reg(VIACR, CR4F); | |
2173 | viafb_write_reg(CR4F, VIACR, 0x55); | |
2174 | if (viafb_read_reg(VIACR, CR4F) != 0x55) | |
2175 | viaparinfo->chip_info->gfx_chip_revision = | |
2176 | CLE266_REVISION_AX; | |
2177 | else | |
2178 | viaparinfo->chip_info->gfx_chip_revision = | |
2179 | CLE266_REVISION_CX; | |
2180 | /* restore orignal CR4F value */ | |
2181 | viafb_write_reg(CR4F, VIACR, tmp); | |
2182 | } | |
2183 | ||
2184 | if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) { | |
2185 | tmp = viafb_read_reg(VIASR, SR43); | |
2186 | DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp); | |
2187 | if (tmp & 0x02) { | |
2188 | viaparinfo->chip_info->gfx_chip_revision = | |
2189 | CX700_REVISION_700M2; | |
2190 | } else if (tmp & 0x40) { | |
2191 | viaparinfo->chip_info->gfx_chip_revision = | |
2192 | CX700_REVISION_700M; | |
2193 | } else { | |
2194 | viaparinfo->chip_info->gfx_chip_revision = | |
2195 | CX700_REVISION_700; | |
2196 | } | |
2197 | } | |
107ea34d HW |
2198 | |
2199 | /* Determine which 2D engine we have */ | |
2200 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
2201 | case UNICHROME_VX800: | |
2202 | case UNICHROME_VX855: | |
51f4332b | 2203 | case UNICHROME_VX900: |
107ea34d HW |
2204 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_M1; |
2205 | break; | |
2206 | case UNICHROME_K8M890: | |
2207 | case UNICHROME_P4M900: | |
2208 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H5; | |
2209 | break; | |
2210 | default: | |
2211 | viaparinfo->chip_info->twod_engine = VIA_2D_ENG_H2; | |
2212 | break; | |
2213 | } | |
d61e0bf3 JC |
2214 | } |
2215 | ||
f4ab2f7a | 2216 | static void __devinit init_tmds_chip_info(void) |
d61e0bf3 JC |
2217 | { |
2218 | viafb_tmds_trasmitter_identify(); | |
2219 | ||
2220 | if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info. | |
2221 | output_interface) { | |
2222 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
2223 | case UNICHROME_CX700: | |
2224 | { | |
2225 | /* we should check support by hardware layout.*/ | |
2226 | if ((viafb_display_hardware_layout == | |
2227 | HW_LAYOUT_DVI_ONLY) | |
2228 | || (viafb_display_hardware_layout == | |
2229 | HW_LAYOUT_LCD_DVI)) { | |
2230 | viaparinfo->chip_info->tmds_chip_info. | |
2231 | output_interface = INTERFACE_TMDS; | |
2232 | } else { | |
2233 | viaparinfo->chip_info->tmds_chip_info. | |
2234 | output_interface = | |
2235 | INTERFACE_NONE; | |
2236 | } | |
2237 | break; | |
2238 | } | |
2239 | case UNICHROME_K8M890: | |
2240 | case UNICHROME_P4M900: | |
2241 | case UNICHROME_P4M890: | |
2242 | /* TMDS on PCIE, we set DFPLOW as default. */ | |
2243 | viaparinfo->chip_info->tmds_chip_info.output_interface = | |
2244 | INTERFACE_DFP_LOW; | |
2245 | break; | |
2246 | default: | |
2247 | { | |
2248 | /* set DVP1 default for DVI */ | |
2249 | viaparinfo->chip_info->tmds_chip_info | |
2250 | .output_interface = INTERFACE_DVP1; | |
2251 | } | |
2252 | } | |
2253 | } | |
2254 | ||
2255 | DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n", | |
2256 | viaparinfo->chip_info->tmds_chip_info.tmds_chip_name); | |
c5f06f5c FTS |
2257 | viafb_init_dvi_size(&viaparinfo->shared->chip_info.tmds_chip_info, |
2258 | &viaparinfo->shared->tmds_setting_info); | |
d61e0bf3 JC |
2259 | } |
2260 | ||
f4ab2f7a | 2261 | static void __devinit init_lvds_chip_info(void) |
d61e0bf3 | 2262 | { |
d61e0bf3 JC |
2263 | viafb_lvds_trasmitter_identify(); |
2264 | viafb_init_lcd_size(); | |
2265 | viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info, | |
2266 | viaparinfo->lvds_setting_info); | |
2267 | if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) { | |
2268 | viafb_init_lvds_output_interface(&viaparinfo->chip_info-> | |
2269 | lvds_chip_info2, viaparinfo->lvds_setting_info2); | |
2270 | } | |
2271 | /*If CX700,two singel LCD, we need to reassign | |
2272 | LCD interface to different LVDS port */ | |
2273 | if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name) | |
2274 | && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) { | |
2275 | if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info. | |
2276 | lvds_chip_name) && (INTEGRATED_LVDS == | |
2277 | viaparinfo->chip_info-> | |
2278 | lvds_chip_info2.lvds_chip_name)) { | |
2279 | viaparinfo->chip_info->lvds_chip_info.output_interface = | |
2280 | INTERFACE_LVDS0; | |
2281 | viaparinfo->chip_info->lvds_chip_info2. | |
2282 | output_interface = | |
2283 | INTERFACE_LVDS1; | |
2284 | } | |
2285 | } | |
2286 | ||
2287 | DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n", | |
2288 | viaparinfo->chip_info->lvds_chip_info.lvds_chip_name); | |
2289 | DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n", | |
2290 | viaparinfo->chip_info->lvds_chip_info.output_interface); | |
2291 | DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n", | |
2292 | viaparinfo->chip_info->lvds_chip_info.output_interface); | |
2293 | } | |
2294 | ||
f4ab2f7a | 2295 | void __devinit viafb_init_dac(int set_iga) |
d61e0bf3 JC |
2296 | { |
2297 | int i; | |
2298 | u8 tmp; | |
2299 | ||
2300 | if (set_iga == IGA1) { | |
2301 | /* access Primary Display's LUT */ | |
2302 | viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); | |
2303 | /* turn off LCK */ | |
2304 | viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); | |
2305 | for (i = 0; i < 256; i++) { | |
2306 | write_dac_reg(i, palLUT_table[i].red, | |
2307 | palLUT_table[i].green, | |
2308 | palLUT_table[i].blue); | |
2309 | } | |
2310 | /* turn on LCK */ | |
2311 | viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); | |
2312 | } else { | |
2313 | tmp = viafb_read_reg(VIACR, CR6A); | |
2314 | /* access Secondary Display's LUT */ | |
2315 | viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6); | |
2316 | viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); | |
2317 | for (i = 0; i < 256; i++) { | |
2318 | write_dac_reg(i, palLUT_table[i].red, | |
2319 | palLUT_table[i].green, | |
2320 | palLUT_table[i].blue); | |
2321 | } | |
2322 | /* set IGA1 DAC for default */ | |
2323 | viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); | |
2324 | viafb_write_reg(CR6A, VIACR, tmp); | |
2325 | } | |
2326 | } | |
2327 | ||
2328 | static void device_screen_off(void) | |
2329 | { | |
2330 | /* turn off CRT screen (IGA1) */ | |
2331 | viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5); | |
2332 | } | |
2333 | ||
2334 | static void device_screen_on(void) | |
2335 | { | |
2336 | /* turn on CRT screen (IGA1) */ | |
2337 | viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5); | |
2338 | } | |
2339 | ||
2340 | static void set_display_channel(void) | |
2341 | { | |
2342 | /*If viafb_LCD2_ON, on cx700, internal lvds's information | |
2343 | is keeped on lvds_setting_info2 */ | |
2344 | if (viafb_LCD2_ON && | |
2345 | viaparinfo->lvds_setting_info2->device_lcd_dualedge) { | |
2346 | /* For dual channel LCD: */ | |
2347 | /* Set to Dual LVDS channel. */ | |
2348 | viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); | |
2349 | } else if (viafb_LCD_ON && viafb_DVI_ON) { | |
2350 | /* For LCD+DFP: */ | |
2351 | /* Set to LVDS1 + TMDS channel. */ | |
2352 | viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5); | |
2353 | } else if (viafb_DVI_ON) { | |
2354 | /* Set to single TMDS channel. */ | |
2355 | viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5); | |
2356 | } else if (viafb_LCD_ON) { | |
2357 | if (viaparinfo->lvds_setting_info->device_lcd_dualedge) { | |
2358 | /* For dual channel LCD: */ | |
2359 | /* Set to Dual LVDS channel. */ | |
2360 | viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5); | |
2361 | } else { | |
2362 | /* Set to LVDS0 + LVDS1 channel. */ | |
2363 | viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5); | |
2364 | } | |
2365 | } | |
2366 | } | |
2367 | ||
2e1abbdd FTS |
2368 | static u8 get_sync(struct fb_info *info) |
2369 | { | |
2370 | u8 polarity = 0; | |
2371 | ||
2372 | if (!(info->var.sync & FB_SYNC_HOR_HIGH_ACT)) | |
2373 | polarity |= VIA_HSYNC_NEGATIVE; | |
2374 | if (!(info->var.sync & FB_SYNC_VERT_HIGH_ACT)) | |
2375 | polarity |= VIA_VSYNC_NEGATIVE; | |
2376 | return polarity; | |
2377 | } | |
2378 | ||
dd73d686 FTS |
2379 | int viafb_setmode(struct VideoModeTable *vmode_tbl, int video_bpp, |
2380 | struct VideoModeTable *vmode_tbl1, int video_bpp1) | |
d61e0bf3 JC |
2381 | { |
2382 | int i, j; | |
2383 | int port; | |
6f9422d4 FTS |
2384 | u32 devices = viaparinfo->shared->iga1_devices |
2385 | | viaparinfo->shared->iga2_devices; | |
d61e0bf3 | 2386 | u8 value, index, mask; |
d61e0bf3 | 2387 | struct crt_mode_table *crt_timing; |
d61e0bf3 JC |
2388 | struct crt_mode_table *crt_timing1 = NULL; |
2389 | ||
d61e0bf3 | 2390 | device_screen_off(); |
d61e0bf3 JC |
2391 | crt_timing = vmode_tbl->crtc; |
2392 | ||
2393 | if (viafb_SAMM_ON == 1) { | |
d61e0bf3 JC |
2394 | crt_timing1 = vmode_tbl1->crtc; |
2395 | } | |
2396 | ||
2397 | inb(VIAStatus); | |
2398 | outb(0x00, VIAAR); | |
2399 | ||
2400 | /* Write Common Setting for Video Mode */ | |
2401 | switch (viaparinfo->chip_info->gfx_chip_name) { | |
2402 | case UNICHROME_CLE266: | |
2403 | viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs); | |
2404 | break; | |
2405 | ||
2406 | case UNICHROME_K400: | |
2407 | viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs); | |
2408 | break; | |
2409 | ||
2410 | case UNICHROME_K800: | |
2411 | case UNICHROME_PM800: | |
2412 | viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs); | |
2413 | break; | |
2414 | ||
2415 | case UNICHROME_CN700: | |
2416 | case UNICHROME_K8M890: | |
2417 | case UNICHROME_P4M890: | |
2418 | case UNICHROME_P4M900: | |
2419 | viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs); | |
2420 | break; | |
2421 | ||
2422 | case UNICHROME_CX700: | |
d61e0bf3 | 2423 | case UNICHROME_VX800: |
0e3ca33a | 2424 | viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs); |
d61e0bf3 | 2425 | break; |
0306ab11 HW |
2426 | |
2427 | case UNICHROME_VX855: | |
51f4332b | 2428 | case UNICHROME_VX900: |
0306ab11 HW |
2429 | viafb_write_regx(VX855_ModeXregs, NUM_TOTAL_VX855_ModeXregs); |
2430 | break; | |
d61e0bf3 JC |
2431 | } |
2432 | ||
2433 | device_off(); | |
6f9422d4 | 2434 | via_set_state(devices, VIA_STATE_OFF); |
d61e0bf3 JC |
2435 | |
2436 | /* Fill VPIT Parameters */ | |
2437 | /* Write Misc Register */ | |
162fc8c0 | 2438 | outb(VPIT.Misc, VIA_MISC_REG_WRITE); |
d61e0bf3 JC |
2439 | |
2440 | /* Write Sequencer */ | |
384c3041 FTS |
2441 | for (i = 1; i <= StdSR; i++) |
2442 | via_write_reg(VIASR, i, VPIT.SR[i - 1]); | |
d61e0bf3 | 2443 | |
415559fb | 2444 | viafb_write_reg_mask(0x15, VIASR, 0xA2, 0xA2); |
d61e0bf3 JC |
2445 | |
2446 | /* Write CRTC */ | |
dd73d686 | 2447 | viafb_fill_crtc_timing(crt_timing, vmode_tbl, video_bpp / 8, IGA1); |
d61e0bf3 JC |
2448 | |
2449 | /* Write Graphic Controller */ | |
384c3041 FTS |
2450 | for (i = 0; i < StdGR; i++) |
2451 | via_write_reg(VIAGR, i, VPIT.GR[i]); | |
d61e0bf3 JC |
2452 | |
2453 | /* Write Attribute Controller */ | |
2454 | for (i = 0; i < StdAR; i++) { | |
2455 | inb(VIAStatus); | |
2456 | outb(i, VIAAR); | |
2457 | outb(VPIT.AR[i], VIAAR); | |
2458 | } | |
2459 | ||
2460 | inb(VIAStatus); | |
2461 | outb(0x20, VIAAR); | |
2462 | ||
2463 | /* Update Patch Register */ | |
2464 | ||
dd73d686 FTS |
2465 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266 |
2466 | || viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400) | |
2467 | && vmode_tbl->crtc[0].crtc.hor_addr == 1024 | |
2468 | && vmode_tbl->crtc[0].crtc.ver_addr == 768) { | |
2469 | for (j = 0; j < res_patch_table[0].table_length; j++) { | |
2470 | index = res_patch_table[0].io_reg_table[j].index; | |
2471 | port = res_patch_table[0].io_reg_table[j].port; | |
2472 | value = res_patch_table[0].io_reg_table[j].value; | |
2473 | mask = res_patch_table[0].io_reg_table[j].mask; | |
2474 | viafb_write_reg_mask(index, port, value, mask); | |
d61e0bf3 JC |
2475 | } |
2476 | } | |
2477 | ||
2749413d FTS |
2478 | via_set_primary_pitch(viafbinfo->fix.line_length); |
2479 | via_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length | |
2d6e8851 | 2480 | : viafbinfo->fix.line_length); |
2749413d FTS |
2481 | via_set_primary_color_depth(viaparinfo->depth); |
2482 | via_set_secondary_color_depth(viafb_dual_fb ? viaparinfo1->depth | |
daacccd1 | 2483 | : viaparinfo->depth); |
bc684887 FTS |
2484 | via_set_source(viaparinfo->shared->iga1_devices, IGA1); |
2485 | via_set_source(viaparinfo->shared->iga2_devices, IGA2); | |
2486 | if (viaparinfo->shared->iga2_devices) | |
2487 | enable_second_display_channel(); | |
2488 | else | |
2489 | disable_second_display_channel(); | |
2490 | ||
d61e0bf3 JC |
2491 | /* Update Refresh Rate Setting */ |
2492 | ||
2493 | /* Clear On Screen */ | |
2494 | ||
2495 | /* CRT set mode */ | |
2496 | if (viafb_CRT_ON) { | |
2497 | if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path == | |
2498 | IGA2)) { | |
dd73d686 | 2499 | viafb_fill_crtc_timing(crt_timing1, vmode_tbl1, |
d61e0bf3 JC |
2500 | video_bpp1 / 8, |
2501 | viaparinfo->crt_setting_info->iga_path); | |
2502 | } else { | |
dd73d686 | 2503 | viafb_fill_crtc_timing(crt_timing, vmode_tbl, |
d61e0bf3 JC |
2504 | video_bpp / 8, |
2505 | viaparinfo->crt_setting_info->iga_path); | |
2506 | } | |
2507 | ||
d61e0bf3 JC |
2508 | /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode |
2509 | to 8 alignment (1368),there is several pixels (2 pixels) | |
2510 | on right side of screen. */ | |
dd73d686 | 2511 | if (vmode_tbl->crtc[0].crtc.hor_addr % 8) { |
d61e0bf3 JC |
2512 | viafb_unlock_crt(); |
2513 | viafb_write_reg(CR02, VIACR, | |
2514 | viafb_read_reg(VIACR, CR02) - 1); | |
2515 | viafb_lock_crt(); | |
2516 | } | |
2517 | } | |
2518 | ||
2519 | if (viafb_DVI_ON) { | |
2520 | if (viafb_SAMM_ON && | |
2521 | (viaparinfo->tmds_setting_info->iga_path == IGA2)) { | |
dd73d686 | 2522 | viafb_dvi_set_mode(viafb_get_mode |
d61e0bf3 JC |
2523 | (viaparinfo->tmds_setting_info->h_active, |
2524 | viaparinfo->tmds_setting_info-> | |
52159444 | 2525 | v_active), |
d61e0bf3 JC |
2526 | video_bpp1, viaparinfo-> |
2527 | tmds_setting_info->iga_path); | |
2528 | } else { | |
dd73d686 | 2529 | viafb_dvi_set_mode(viafb_get_mode |
d61e0bf3 JC |
2530 | (viaparinfo->tmds_setting_info->h_active, |
2531 | viaparinfo-> | |
52159444 | 2532 | tmds_setting_info->v_active), |
d61e0bf3 JC |
2533 | video_bpp, viaparinfo-> |
2534 | tmds_setting_info->iga_path); | |
2535 | } | |
2536 | } | |
2537 | ||
2538 | if (viafb_LCD_ON) { | |
2539 | if (viafb_SAMM_ON && | |
2540 | (viaparinfo->lvds_setting_info->iga_path == IGA2)) { | |
2541 | viaparinfo->lvds_setting_info->bpp = video_bpp1; | |
2542 | viafb_lcd_set_mode(crt_timing1, viaparinfo-> | |
2543 | lvds_setting_info, | |
2544 | &viaparinfo->chip_info->lvds_chip_info); | |
2545 | } else { | |
2546 | /* IGA1 doesn't have LCD scaling, so set it center. */ | |
2547 | if (viaparinfo->lvds_setting_info->iga_path == IGA1) { | |
2548 | viaparinfo->lvds_setting_info->display_method = | |
2549 | LCD_CENTERING; | |
2550 | } | |
2551 | viaparinfo->lvds_setting_info->bpp = video_bpp; | |
2552 | viafb_lcd_set_mode(crt_timing, viaparinfo-> | |
2553 | lvds_setting_info, | |
2554 | &viaparinfo->chip_info->lvds_chip_info); | |
2555 | } | |
2556 | } | |
2557 | if (viafb_LCD2_ON) { | |
2558 | if (viafb_SAMM_ON && | |
2559 | (viaparinfo->lvds_setting_info2->iga_path == IGA2)) { | |
2560 | viaparinfo->lvds_setting_info2->bpp = video_bpp1; | |
2561 | viafb_lcd_set_mode(crt_timing1, viaparinfo-> | |
2562 | lvds_setting_info2, | |
2563 | &viaparinfo->chip_info->lvds_chip_info2); | |
2564 | } else { | |
2565 | /* IGA1 doesn't have LCD scaling, so set it center. */ | |
2566 | if (viaparinfo->lvds_setting_info2->iga_path == IGA1) { | |
2567 | viaparinfo->lvds_setting_info2->display_method = | |
2568 | LCD_CENTERING; | |
2569 | } | |
2570 | viaparinfo->lvds_setting_info2->bpp = video_bpp; | |
2571 | viafb_lcd_set_mode(crt_timing, viaparinfo-> | |
2572 | lvds_setting_info2, | |
2573 | &viaparinfo->chip_info->lvds_chip_info2); | |
2574 | } | |
2575 | } | |
2576 | ||
2577 | if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) | |
2578 | && (viafb_LCD_ON || viafb_DVI_ON)) | |
2579 | set_display_channel(); | |
2580 | ||
2581 | /* If set mode normally, save resolution information for hot-plug . */ | |
2582 | if (!viafb_hotplug) { | |
dd73d686 FTS |
2583 | viafb_hotplug_Xres = vmode_tbl->crtc[0].crtc.hor_addr; |
2584 | viafb_hotplug_Yres = vmode_tbl->crtc[0].crtc.ver_addr; | |
d61e0bf3 JC |
2585 | viafb_hotplug_bpp = video_bpp; |
2586 | viafb_hotplug_refresh = viafb_refresh; | |
2587 | ||
2588 | if (viafb_DVI_ON) | |
2589 | viafb_DeviceStatus = DVI_Device; | |
2590 | else | |
2591 | viafb_DeviceStatus = CRT_Device; | |
2592 | } | |
2593 | device_on(); | |
2e1abbdd FTS |
2594 | if (!viafb_dual_fb) |
2595 | via_set_sync_polarity(devices, get_sync(viafbinfo)); | |
2596 | else { | |
2597 | via_set_sync_polarity(viaparinfo->shared->iga1_devices, | |
2598 | get_sync(viafbinfo)); | |
2599 | via_set_sync_polarity(viaparinfo->shared->iga2_devices, | |
2600 | get_sync(viafbinfo1)); | |
2601 | } | |
2602 | ||
6f9422d4 | 2603 | via_set_state(devices, VIA_STATE_ON); |
d61e0bf3 JC |
2604 | device_screen_on(); |
2605 | return 1; | |
2606 | } | |
2607 | ||
2608 | int viafb_get_pixclock(int hres, int vres, int vmode_refresh) | |
2609 | { | |
2610 | int i; | |
2611 | ||
2612 | for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { | |
2613 | if ((hres == res_map_refresh_tbl[i].hres) | |
2614 | && (vres == res_map_refresh_tbl[i].vres) | |
2615 | && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh)) | |
2616 | return res_map_refresh_tbl[i].pixclock; | |
2617 | } | |
2618 | return RES_640X480_60HZ_PIXCLOCK; | |
2619 | ||
2620 | } | |
2621 | ||
2622 | int viafb_get_refresh(int hres, int vres, u32 long_refresh) | |
2623 | { | |
2624 | #define REFRESH_TOLERANCE 3 | |
2625 | int i, nearest = -1, diff = REFRESH_TOLERANCE; | |
2626 | for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) { | |
2627 | if ((hres == res_map_refresh_tbl[i].hres) | |
2628 | && (vres == res_map_refresh_tbl[i].vres) | |
2629 | && (diff > (abs(long_refresh - | |
2630 | res_map_refresh_tbl[i].vmode_refresh)))) { | |
2631 | diff = abs(long_refresh - res_map_refresh_tbl[i]. | |
2632 | vmode_refresh); | |
2633 | nearest = i; | |
2634 | } | |
2635 | } | |
2636 | #undef REFRESH_TOLERANCE | |
2637 | if (nearest > 0) | |
2638 | return res_map_refresh_tbl[nearest].vmode_refresh; | |
2639 | return 60; | |
2640 | } | |
2641 | ||
2642 | static void device_off(void) | |
2643 | { | |
d61e0bf3 JC |
2644 | viafb_dvi_disable(); |
2645 | viafb_lcd_disable(); | |
2646 | } | |
2647 | ||
2648 | static void device_on(void) | |
2649 | { | |
d61e0bf3 JC |
2650 | if (viafb_DVI_ON == 1) |
2651 | viafb_dvi_enable(); | |
2652 | if (viafb_LCD_ON == 1) | |
2653 | viafb_lcd_enable(); | |
2654 | } | |
2655 | ||
d61e0bf3 JC |
2656 | static void enable_second_display_channel(void) |
2657 | { | |
2658 | /* to enable second display channel. */ | |
2659 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); | |
2660 | viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7); | |
2661 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); | |
2662 | } | |
2663 | ||
bc684887 FTS |
2664 | static void disable_second_display_channel(void) |
2665 | { | |
2666 | /* to disable second display channel. */ | |
2667 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6); | |
2668 | viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); | |
2669 | viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6); | |
2670 | } | |
2671 | ||
d61e0bf3 JC |
2672 | void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\ |
2673 | *p_gfx_dpa_setting) | |
2674 | { | |
2675 | switch (output_interface) { | |
2676 | case INTERFACE_DVP0: | |
2677 | { | |
2678 | /* DVP0 Clock Polarity and Adjust: */ | |
2679 | viafb_write_reg_mask(CR96, VIACR, | |
2680 | p_gfx_dpa_setting->DVP0, 0x0F); | |
2681 | ||
2682 | /* DVP0 Clock and Data Pads Driving: */ | |
2683 | viafb_write_reg_mask(SR1E, VIASR, | |
2684 | p_gfx_dpa_setting->DVP0ClockDri_S, BIT2); | |
2685 | viafb_write_reg_mask(SR2A, VIASR, | |
2686 | p_gfx_dpa_setting->DVP0ClockDri_S1, | |
2687 | BIT4); | |
2688 | viafb_write_reg_mask(SR1B, VIASR, | |
2689 | p_gfx_dpa_setting->DVP0DataDri_S, BIT1); | |
2690 | viafb_write_reg_mask(SR2A, VIASR, | |
2691 | p_gfx_dpa_setting->DVP0DataDri_S1, BIT5); | |
2692 | break; | |
2693 | } | |
2694 | ||
2695 | case INTERFACE_DVP1: | |
2696 | { | |
2697 | /* DVP1 Clock Polarity and Adjust: */ | |
2698 | viafb_write_reg_mask(CR9B, VIACR, | |
2699 | p_gfx_dpa_setting->DVP1, 0x0F); | |
2700 | ||
2701 | /* DVP1 Clock and Data Pads Driving: */ | |
2702 | viafb_write_reg_mask(SR65, VIASR, | |
2703 | p_gfx_dpa_setting->DVP1Driving, 0x0F); | |
2704 | break; | |
2705 | } | |
2706 | ||
2707 | case INTERFACE_DFP_HIGH: | |
2708 | { | |
2709 | viafb_write_reg_mask(CR97, VIACR, | |
2710 | p_gfx_dpa_setting->DFPHigh, 0x0F); | |
2711 | break; | |
2712 | } | |
2713 | ||
2714 | case INTERFACE_DFP_LOW: | |
2715 | { | |
2716 | viafb_write_reg_mask(CR99, VIACR, | |
2717 | p_gfx_dpa_setting->DFPLow, 0x0F); | |
2718 | break; | |
2719 | } | |
2720 | ||
2721 | case INTERFACE_DFP: | |
2722 | { | |
2723 | viafb_write_reg_mask(CR97, VIACR, | |
2724 | p_gfx_dpa_setting->DFPHigh, 0x0F); | |
2725 | viafb_write_reg_mask(CR99, VIACR, | |
2726 | p_gfx_dpa_setting->DFPLow, 0x0F); | |
2727 | break; | |
2728 | } | |
2729 | } | |
2730 | } | |
2731 | ||
d61e0bf3 JC |
2732 | /*According var's xres, yres fill var's other timing information*/ |
2733 | void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh, | |
dd73d686 | 2734 | struct VideoModeTable *vmode_tbl) |
d61e0bf3 | 2735 | { |
d61e0bf3 JC |
2736 | struct crt_mode_table *crt_timing = NULL; |
2737 | struct display_timing crt_reg; | |
2738 | int i = 0, index = 0; | |
d61e0bf3 JC |
2739 | crt_timing = vmode_tbl->crtc; |
2740 | for (i = 0; i < vmode_tbl->mode_array; i++) { | |
2741 | index = i; | |
2742 | if (crt_timing[i].refresh_rate == refresh) | |
2743 | break; | |
2744 | } | |
2745 | ||
2746 | crt_reg = crt_timing[index].crtc; | |
d61e0bf3 JC |
2747 | var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh); |
2748 | var->left_margin = | |
2749 | crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end); | |
2750 | var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr; | |
2751 | var->hsync_len = crt_reg.hor_sync_end; | |
2752 | var->upper_margin = | |
2753 | crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end); | |
2754 | var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr; | |
2755 | var->vsync_len = crt_reg.ver_sync_end; | |
2e1abbdd FTS |
2756 | var->sync = 0; |
2757 | if (crt_timing[index].h_sync_polarity == POSITIVE) | |
2758 | var->sync |= FB_SYNC_HOR_HIGH_ACT; | |
2759 | if (crt_timing[index].v_sync_polarity == POSITIVE) | |
2760 | var->sync |= FB_SYNC_VERT_HIGH_ACT; | |
d61e0bf3 | 2761 | } |