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viafb: improve pitch handling
[deliverable/linux.git] / drivers / video / via / hw.c
CommitLineData
d61e0bf3
JC		 1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
21
22#include "global.h"
23
24static const struct pci_device_id_info pciidlist[] = {
25 {PCI_VIA_VENDOR_ID, UNICHROME_CLE266_DID, UNICHROME_CLE266},
26 {PCI_VIA_VENDOR_ID, UNICHROME_PM800_DID, UNICHROME_PM800},
27 {PCI_VIA_VENDOR_ID, UNICHROME_K400_DID, UNICHROME_K400},
28 {PCI_VIA_VENDOR_ID, UNICHROME_K800_DID, UNICHROME_K800},
29 {PCI_VIA_VENDOR_ID, UNICHROME_CN700_DID, UNICHROME_CN700},
30 {PCI_VIA_VENDOR_ID, UNICHROME_P4M890_DID, UNICHROME_P4M890},
31 {PCI_VIA_VENDOR_ID, UNICHROME_K8M890_DID, UNICHROME_K8M890},
32 {PCI_VIA_VENDOR_ID, UNICHROME_CX700_DID, UNICHROME_CX700},
33 {PCI_VIA_VENDOR_ID, UNICHROME_P4M900_DID, UNICHROME_P4M900},
34 {PCI_VIA_VENDOR_ID, UNICHROME_CN750_DID, UNICHROME_CN750},
35 {PCI_VIA_VENDOR_ID, UNICHROME_VX800_DID, UNICHROME_VX800},
36 {0, 0, 0}
37};
38
d61e0bf3
JC		 39static struct pll_map pll_value[] = {
40 {CLK_25_175M, CLE266_PLL_25_175M, K800_PLL_25_175M, CX700_25_175M},
41 {CLK_29_581M, CLE266_PLL_29_581M, K800_PLL_29_581M, CX700_29_581M},
42 {CLK_26_880M, CLE266_PLL_26_880M, K800_PLL_26_880M, CX700_26_880M},
43 {CLK_31_490M, CLE266_PLL_31_490M, K800_PLL_31_490M, CX700_31_490M},
44 {CLK_31_500M, CLE266_PLL_31_500M, K800_PLL_31_500M, CX700_31_500M},
45 {CLK_31_728M, CLE266_PLL_31_728M, K800_PLL_31_728M, CX700_31_728M},
46 {CLK_32_668M, CLE266_PLL_32_668M, K800_PLL_32_668M, CX700_32_668M},
47 {CLK_36_000M, CLE266_PLL_36_000M, K800_PLL_36_000M, CX700_36_000M},
48 {CLK_40_000M, CLE266_PLL_40_000M, K800_PLL_40_000M, CX700_40_000M},
49 {CLK_41_291M, CLE266_PLL_41_291M, K800_PLL_41_291M, CX700_41_291M},
50 {CLK_43_163M, CLE266_PLL_43_163M, K800_PLL_43_163M, CX700_43_163M},
51 {CLK_45_250M, CLE266_PLL_45_250M, K800_PLL_45_250M, CX700_45_250M},
52 {CLK_46_000M, CLE266_PLL_46_000M, K800_PLL_46_000M, CX700_46_000M},
53 {CLK_46_996M, CLE266_PLL_46_996M, K800_PLL_46_996M, CX700_46_996M},
54 {CLK_48_000M, CLE266_PLL_48_000M, K800_PLL_48_000M, CX700_48_000M},
55 {CLK_48_875M, CLE266_PLL_48_875M, K800_PLL_48_875M, CX700_48_875M},
56 {CLK_49_500M, CLE266_PLL_49_500M, K800_PLL_49_500M, CX700_49_500M},
57 {CLK_52_406M, CLE266_PLL_52_406M, K800_PLL_52_406M, CX700_52_406M},
58 {CLK_52_977M, CLE266_PLL_52_977M, K800_PLL_52_977M, CX700_52_977M},
59 {CLK_56_250M, CLE266_PLL_56_250M, K800_PLL_56_250M, CX700_56_250M},
60 {CLK_60_466M, CLE266_PLL_60_466M, K800_PLL_60_466M, CX700_60_466M},
61 {CLK_61_500M, CLE266_PLL_61_500M, K800_PLL_61_500M, CX700_61_500M},
62 {CLK_65_000M, CLE266_PLL_65_000M, K800_PLL_65_000M, CX700_65_000M},
63 {CLK_65_178M, CLE266_PLL_65_178M, K800_PLL_65_178M, CX700_65_178M},
64 {CLK_66_750M, CLE266_PLL_66_750M, K800_PLL_66_750M, CX700_66_750M},
65 {CLK_68_179M, CLE266_PLL_68_179M, K800_PLL_68_179M, CX700_68_179M},
66 {CLK_69_924M, CLE266_PLL_69_924M, K800_PLL_69_924M, CX700_69_924M},
67 {CLK_70_159M, CLE266_PLL_70_159M, K800_PLL_70_159M, CX700_70_159M},
68 {CLK_72_000M, CLE266_PLL_72_000M, K800_PLL_72_000M, CX700_72_000M},
69 {CLK_78_750M, CLE266_PLL_78_750M, K800_PLL_78_750M, CX700_78_750M},
70 {CLK_80_136M, CLE266_PLL_80_136M, K800_PLL_80_136M, CX700_80_136M},
71 {CLK_83_375M, CLE266_PLL_83_375M, K800_PLL_83_375M, CX700_83_375M},
72 {CLK_83_950M, CLE266_PLL_83_950M, K800_PLL_83_950M, CX700_83_950M},
73 {CLK_84_750M, CLE266_PLL_84_750M, K800_PLL_84_750M, CX700_84_750M},
74 {CLK_85_860M, CLE266_PLL_85_860M, K800_PLL_85_860M, CX700_85_860M},
75 {CLK_88_750M, CLE266_PLL_88_750M, K800_PLL_88_750M, CX700_88_750M},
76 {CLK_94_500M, CLE266_PLL_94_500M, K800_PLL_94_500M, CX700_94_500M},
77 {CLK_97_750M, CLE266_PLL_97_750M, K800_PLL_97_750M, CX700_97_750M},
78 {CLK_101_000M, CLE266_PLL_101_000M, K800_PLL_101_000M,
79 CX700_101_000M},
80 {CLK_106_500M, CLE266_PLL_106_500M, K800_PLL_106_500M,
81 CX700_106_500M},
82 {CLK_108_000M, CLE266_PLL_108_000M, K800_PLL_108_000M,
83 CX700_108_000M},
84 {CLK_113_309M, CLE266_PLL_113_309M, K800_PLL_113_309M,
85 CX700_113_309M},
86 {CLK_118_840M, CLE266_PLL_118_840M, K800_PLL_118_840M,
87 CX700_118_840M},
88 {CLK_119_000M, CLE266_PLL_119_000M, K800_PLL_119_000M,
89 CX700_119_000M},
90 {CLK_121_750M, CLE266_PLL_121_750M, K800_PLL_121_750M,
91 CX700_121_750M},
92 {CLK_125_104M, CLE266_PLL_125_104M, K800_PLL_125_104M,
93 CX700_125_104M},
94 {CLK_133_308M, CLE266_PLL_133_308M, K800_PLL_133_308M,
95 CX700_133_308M},
96 {CLK_135_000M, CLE266_PLL_135_000M, K800_PLL_135_000M,
97 CX700_135_000M},
98 {CLK_136_700M, CLE266_PLL_136_700M, K800_PLL_136_700M,
99 CX700_136_700M},
100 {CLK_138_400M, CLE266_PLL_138_400M, K800_PLL_138_400M,
101 CX700_138_400M},
102 {CLK_146_760M, CLE266_PLL_146_760M, K800_PLL_146_760M,
103 CX700_146_760M},
104 {CLK_153_920M, CLE266_PLL_153_920M, K800_PLL_153_920M,
105 CX700_153_920M},
106 {CLK_156_000M, CLE266_PLL_156_000M, K800_PLL_156_000M,
107 CX700_156_000M},
108 {CLK_157_500M, CLE266_PLL_157_500M, K800_PLL_157_500M,
109 CX700_157_500M},
110 {CLK_162_000M, CLE266_PLL_162_000M, K800_PLL_162_000M,
111 CX700_162_000M},
112 {CLK_187_000M, CLE266_PLL_187_000M, K800_PLL_187_000M,
113 CX700_187_000M},
114 {CLK_193_295M, CLE266_PLL_193_295M, K800_PLL_193_295M,
115 CX700_193_295M},
116 {CLK_202_500M, CLE266_PLL_202_500M, K800_PLL_202_500M,
117 CX700_202_500M},
118 {CLK_204_000M, CLE266_PLL_204_000M, K800_PLL_204_000M,
119 CX700_204_000M},
120 {CLK_218_500M, CLE266_PLL_218_500M, K800_PLL_218_500M,
121 CX700_218_500M},
122 {CLK_234_000M, CLE266_PLL_234_000M, K800_PLL_234_000M,
123 CX700_234_000M},
124 {CLK_267_250M, CLE266_PLL_267_250M, K800_PLL_267_250M,
125 CX700_267_250M},
126 {CLK_297_500M, CLE266_PLL_297_500M, K800_PLL_297_500M,
127 CX700_297_500M},
128 {CLK_74_481M, CLE266_PLL_74_481M, K800_PLL_74_481M, CX700_74_481M},
129 {CLK_172_798M, CLE266_PLL_172_798M, K800_PLL_172_798M,
130 CX700_172_798M},
131 {CLK_122_614M, CLE266_PLL_122_614M, K800_PLL_122_614M,
132 CX700_122_614M},
133 {CLK_74_270M, CLE266_PLL_74_270M, K800_PLL_74_270M, CX700_74_270M},
134 {CLK_148_500M, CLE266_PLL_148_500M, K800_PLL_148_500M,
135 CX700_148_500M}
136};
137
138static struct fifo_depth_select display_fifo_depth_reg = {
139 /* IGA1 FIFO Depth_Select */
140 {IGA1_FIFO_DEPTH_SELECT_REG_NUM, {{SR17, 0, 7} } },
141 /* IGA2 FIFO Depth_Select */
142 {IGA2_FIFO_DEPTH_SELECT_REG_NUM,
143 {{CR68, 4, 7}, {CR94, 7, 7}, {CR95, 7, 7} } }
144};
145
146static struct fifo_threshold_select fifo_threshold_select_reg = {
147 /* IGA1 FIFO Threshold Select */
148 {IGA1_FIFO_THRESHOLD_REG_NUM, {{SR16, 0, 5}, {SR16, 7, 7} } },
149 /* IGA2 FIFO Threshold Select */
150 {IGA2_FIFO_THRESHOLD_REG_NUM, {{CR68, 0, 3}, {CR95, 4, 6} } }
151};
152
153static struct fifo_high_threshold_select fifo_high_threshold_select_reg = {
154 /* IGA1 FIFO High Threshold Select */
155 {IGA1_FIFO_HIGH_THRESHOLD_REG_NUM, {{SR18, 0, 5}, {SR18, 7, 7} } },
156 /* IGA2 FIFO High Threshold Select */
157 {IGA2_FIFO_HIGH_THRESHOLD_REG_NUM, {{CR92, 0, 3}, {CR95, 0, 2} } }
158};
159
160static struct display_queue_expire_num display_queue_expire_num_reg = {
161 /* IGA1 Display Queue Expire Num */
162 {IGA1_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{SR22, 0, 4} } },
163 /* IGA2 Display Queue Expire Num */
164 {IGA2_DISPLAY_QUEUE_EXPIRE_NUM_REG_NUM, {{CR94, 0, 6} } }
165};
166
167/* Definition Fetch Count Registers*/
168static struct fetch_count fetch_count_reg = {
169 /* IGA1 Fetch Count Register */
170 {IGA1_FETCH_COUNT_REG_NUM, {{SR1C, 0, 7}, {SR1D, 0, 1} } },
171 /* IGA2 Fetch Count Register */
172 {IGA2_FETCH_COUNT_REG_NUM, {{CR65, 0, 7}, {CR67, 2, 3} } }
173};
174
175static struct iga1_crtc_timing iga1_crtc_reg = {
176 /* IGA1 Horizontal Total */
177 {IGA1_HOR_TOTAL_REG_NUM, {{CR00, 0, 7}, {CR36, 3, 3} } },
178 /* IGA1 Horizontal Addressable Video */
179 {IGA1_HOR_ADDR_REG_NUM, {{CR01, 0, 7} } },
180 /* IGA1 Horizontal Blank Start */
181 {IGA1_HOR_BLANK_START_REG_NUM, {{CR02, 0, 7} } },
182 /* IGA1 Horizontal Blank End */
183 {IGA1_HOR_BLANK_END_REG_NUM,
184 {{CR03, 0, 4}, {CR05, 7, 7}, {CR33, 5, 5} } },
185 /* IGA1 Horizontal Sync Start */
186 {IGA1_HOR_SYNC_START_REG_NUM, {{CR04, 0, 7}, {CR33, 4, 4} } },
187 /* IGA1 Horizontal Sync End */
188 {IGA1_HOR_SYNC_END_REG_NUM, {{CR05, 0, 4} } },
189 /* IGA1 Vertical Total */
190 {IGA1_VER_TOTAL_REG_NUM,
191 {{CR06, 0, 7}, {CR07, 0, 0}, {CR07, 5, 5}, {CR35, 0, 0} } },
192 /* IGA1 Vertical Addressable Video */
193 {IGA1_VER_ADDR_REG_NUM,
194 {{CR12, 0, 7}, {CR07, 1, 1}, {CR07, 6, 6}, {CR35, 2, 2} } },
195 /* IGA1 Vertical Blank Start */
196 {IGA1_VER_BLANK_START_REG_NUM,
197 {{CR15, 0, 7}, {CR07, 3, 3}, {CR09, 5, 5}, {CR35, 3, 3} } },
198 /* IGA1 Vertical Blank End */
199 {IGA1_VER_BLANK_END_REG_NUM, {{CR16, 0, 7} } },
200 /* IGA1 Vertical Sync Start */
201 {IGA1_VER_SYNC_START_REG_NUM,
202 {{CR10, 0, 7}, {CR07, 2, 2}, {CR07, 7, 7}, {CR35, 1, 1} } },
203 /* IGA1 Vertical Sync End */
204 {IGA1_VER_SYNC_END_REG_NUM, {{CR11, 0, 3} } }
205};
206
207static struct iga2_crtc_timing iga2_crtc_reg = {
208 /* IGA2 Horizontal Total */
209 {IGA2_HOR_TOTAL_REG_NUM, {{CR50, 0, 7}, {CR55, 0, 3} } },
210 /* IGA2 Horizontal Addressable Video */
211 {IGA2_HOR_ADDR_REG_NUM, {{CR51, 0, 7}, {CR55, 4, 6} } },
212 /* IGA2 Horizontal Blank Start */
213 {IGA2_HOR_BLANK_START_REG_NUM, {{CR52, 0, 7}, {CR54, 0, 2} } },
214 /* IGA2 Horizontal Blank End */
215 {IGA2_HOR_BLANK_END_REG_NUM,
216 {{CR53, 0, 7}, {CR54, 3, 5}, {CR5D, 6, 6} } },
217 /* IGA2 Horizontal Sync Start */
218 {IGA2_HOR_SYNC_START_REG_NUM,
219 {{CR56, 0, 7}, {CR54, 6, 7}, {CR5C, 7, 7}, {CR5D, 7, 7} } },
220 /* IGA2 Horizontal Sync End */
221 {IGA2_HOR_SYNC_END_REG_NUM, {{CR57, 0, 7}, {CR5C, 6, 6} } },
222 /* IGA2 Vertical Total */
223 {IGA2_VER_TOTAL_REG_NUM, {{CR58, 0, 7}, {CR5D, 0, 2} } },
224 /* IGA2 Vertical Addressable Video */
225 {IGA2_VER_ADDR_REG_NUM, {{CR59, 0, 7}, {CR5D, 3, 5} } },
226 /* IGA2 Vertical Blank Start */
227 {IGA2_VER_BLANK_START_REG_NUM, {{CR5A, 0, 7}, {CR5C, 0, 2} } },
228 /* IGA2 Vertical Blank End */
229 {IGA2_VER_BLANK_END_REG_NUM, {{CR5B, 0, 7}, {CR5C, 3, 5} } },
230 /* IGA2 Vertical Sync Start */
231 {IGA2_VER_SYNC_START_REG_NUM, {{CR5E, 0, 7}, {CR5F, 5, 7} } },
232 /* IGA2 Vertical Sync End */
233 {IGA2_VER_SYNC_END_REG_NUM, {{CR5F, 0, 4} } }
234};
235
236static struct rgbLUT palLUT_table[] = {
237 /* {R,G,B} */
238 /* Index 0x00~0x03 */
239 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x2A}, {0x00, 0x2A, 0x00}, {0x00,
240 0x2A,
241 0x2A},
242 /* Index 0x04~0x07 */
243 {0x2A, 0x00, 0x00}, {0x2A, 0x00, 0x2A}, {0x2A, 0x15, 0x00}, {0x2A,
244 0x2A,
245 0x2A},
246 /* Index 0x08~0x0B */
247 {0x15, 0x15, 0x15}, {0x15, 0x15, 0x3F}, {0x15, 0x3F, 0x15}, {0x15,
248 0x3F,
249 0x3F},
250 /* Index 0x0C~0x0F */
251 {0x3F, 0x15, 0x15}, {0x3F, 0x15, 0x3F}, {0x3F, 0x3F, 0x15}, {0x3F,
252 0x3F,
253 0x3F},
254 /* Index 0x10~0x13 */
255 {0x00, 0x00, 0x00}, {0x05, 0x05, 0x05}, {0x08, 0x08, 0x08}, {0x0B,
256 0x0B,
257 0x0B},
258 /* Index 0x14~0x17 */
259 {0x0E, 0x0E, 0x0E}, {0x11, 0x11, 0x11}, {0x14, 0x14, 0x14}, {0x18,
260 0x18,
261 0x18},
262 /* Index 0x18~0x1B */
263 {0x1C, 0x1C, 0x1C}, {0x20, 0x20, 0x20}, {0x24, 0x24, 0x24}, {0x28,
264 0x28,
265 0x28},
266 /* Index 0x1C~0x1F */
267 {0x2D, 0x2D, 0x2D}, {0x32, 0x32, 0x32}, {0x38, 0x38, 0x38}, {0x3F,
268 0x3F,
269 0x3F},
270 /* Index 0x20~0x23 */
271 {0x00, 0x00, 0x3F}, {0x10, 0x00, 0x3F}, {0x1F, 0x00, 0x3F}, {0x2F,
272 0x00,
273 0x3F},
274 /* Index 0x24~0x27 */
275 {0x3F, 0x00, 0x3F}, {0x3F, 0x00, 0x2F}, {0x3F, 0x00, 0x1F}, {0x3F,
276 0x00,
277 0x10},
278 /* Index 0x28~0x2B */
279 {0x3F, 0x00, 0x00}, {0x3F, 0x10, 0x00}, {0x3F, 0x1F, 0x00}, {0x3F,
280 0x2F,
281 0x00},
282 /* Index 0x2C~0x2F */
283 {0x3F, 0x3F, 0x00}, {0x2F, 0x3F, 0x00}, {0x1F, 0x3F, 0x00}, {0x10,
284 0x3F,
285 0x00},
286 /* Index 0x30~0x33 */
287 {0x00, 0x3F, 0x00}, {0x00, 0x3F, 0x10}, {0x00, 0x3F, 0x1F}, {0x00,
288 0x3F,
289 0x2F},
290 /* Index 0x34~0x37 */
291 {0x00, 0x3F, 0x3F}, {0x00, 0x2F, 0x3F}, {0x00, 0x1F, 0x3F}, {0x00,
292 0x10,
293 0x3F},
294 /* Index 0x38~0x3B */
295 {0x1F, 0x1F, 0x3F}, {0x27, 0x1F, 0x3F}, {0x2F, 0x1F, 0x3F}, {0x37,
296 0x1F,
297 0x3F},
298 /* Index 0x3C~0x3F */
299 {0x3F, 0x1F, 0x3F}, {0x3F, 0x1F, 0x37}, {0x3F, 0x1F, 0x2F}, {0x3F,
300 0x1F,
301 0x27},
302 /* Index 0x40~0x43 */
303 {0x3F, 0x1F, 0x1F}, {0x3F, 0x27, 0x1F}, {0x3F, 0x2F, 0x1F}, {0x3F,
304 0x3F,
305 0x1F},
306 /* Index 0x44~0x47 */
307 {0x3F, 0x3F, 0x1F}, {0x37, 0x3F, 0x1F}, {0x2F, 0x3F, 0x1F}, {0x27,
308 0x3F,
309 0x1F},
310 /* Index 0x48~0x4B */
311 {0x1F, 0x3F, 0x1F}, {0x1F, 0x3F, 0x27}, {0x1F, 0x3F, 0x2F}, {0x1F,
312 0x3F,
313 0x37},
314 /* Index 0x4C~0x4F */
315 {0x1F, 0x3F, 0x3F}, {0x1F, 0x37, 0x3F}, {0x1F, 0x2F, 0x3F}, {0x1F,
316 0x27,
317 0x3F},
318 /* Index 0x50~0x53 */
319 {0x2D, 0x2D, 0x3F}, {0x31, 0x2D, 0x3F}, {0x36, 0x2D, 0x3F}, {0x3A,
320 0x2D,
321 0x3F},
322 /* Index 0x54~0x57 */
323 {0x3F, 0x2D, 0x3F}, {0x3F, 0x2D, 0x3A}, {0x3F, 0x2D, 0x36}, {0x3F,
324 0x2D,
325 0x31},
326 /* Index 0x58~0x5B */
327 {0x3F, 0x2D, 0x2D}, {0x3F, 0x31, 0x2D}, {0x3F, 0x36, 0x2D}, {0x3F,
328 0x3A,
329 0x2D},
330 /* Index 0x5C~0x5F */
331 {0x3F, 0x3F, 0x2D}, {0x3A, 0x3F, 0x2D}, {0x36, 0x3F, 0x2D}, {0x31,
332 0x3F,
333 0x2D},
334 /* Index 0x60~0x63 */
335 {0x2D, 0x3F, 0x2D}, {0x2D, 0x3F, 0x31}, {0x2D, 0x3F, 0x36}, {0x2D,
336 0x3F,
337 0x3A},
338 /* Index 0x64~0x67 */
339 {0x2D, 0x3F, 0x3F}, {0x2D, 0x3A, 0x3F}, {0x2D, 0x36, 0x3F}, {0x2D,
340 0x31,
341 0x3F},
342 /* Index 0x68~0x6B */
343 {0x00, 0x00, 0x1C}, {0x07, 0x00, 0x1C}, {0x0E, 0x00, 0x1C}, {0x15,
344 0x00,
345 0x1C},
346 /* Index 0x6C~0x6F */
347 {0x1C, 0x00, 0x1C}, {0x1C, 0x00, 0x15}, {0x1C, 0x00, 0x0E}, {0x1C,
348 0x00,
349 0x07},
350 /* Index 0x70~0x73 */
351 {0x1C, 0x00, 0x00}, {0x1C, 0x07, 0x00}, {0x1C, 0x0E, 0x00}, {0x1C,
352 0x15,
353 0x00},
354 /* Index 0x74~0x77 */
355 {0x1C, 0x1C, 0x00}, {0x15, 0x1C, 0x00}, {0x0E, 0x1C, 0x00}, {0x07,
356 0x1C,
357 0x00},
358 /* Index 0x78~0x7B */
359 {0x00, 0x1C, 0x00}, {0x00, 0x1C, 0x07}, {0x00, 0x1C, 0x0E}, {0x00,
360 0x1C,
361 0x15},
362 /* Index 0x7C~0x7F */
363 {0x00, 0x1C, 0x1C}, {0x00, 0x15, 0x1C}, {0x00, 0x0E, 0x1C}, {0x00,
364 0x07,
365 0x1C},
366 /* Index 0x80~0x83 */
367 {0x0E, 0x0E, 0x1C}, {0x11, 0x0E, 0x1C}, {0x15, 0x0E, 0x1C}, {0x18,
368 0x0E,
369 0x1C},
370 /* Index 0x84~0x87 */
371 {0x1C, 0x0E, 0x1C}, {0x1C, 0x0E, 0x18}, {0x1C, 0x0E, 0x15}, {0x1C,
372 0x0E,
373 0x11},
374 /* Index 0x88~0x8B */
375 {0x1C, 0x0E, 0x0E}, {0x1C, 0x11, 0x0E}, {0x1C, 0x15, 0x0E}, {0x1C,
376 0x18,
377 0x0E},
378 /* Index 0x8C~0x8F */
379 {0x1C, 0x1C, 0x0E}, {0x18, 0x1C, 0x0E}, {0x15, 0x1C, 0x0E}, {0x11,
380 0x1C,
381 0x0E},
382 /* Index 0x90~0x93 */
383 {0x0E, 0x1C, 0x0E}, {0x0E, 0x1C, 0x11}, {0x0E, 0x1C, 0x15}, {0x0E,
384 0x1C,
385 0x18},
386 /* Index 0x94~0x97 */
387 {0x0E, 0x1C, 0x1C}, {0x0E, 0x18, 0x1C}, {0x0E, 0x15, 0x1C}, {0x0E,
388 0x11,
389 0x1C},
390 /* Index 0x98~0x9B */
391 {0x14, 0x14, 0x1C}, {0x16, 0x14, 0x1C}, {0x18, 0x14, 0x1C}, {0x1A,
392 0x14,
393 0x1C},
394 /* Index 0x9C~0x9F */
395 {0x1C, 0x14, 0x1C}, {0x1C, 0x14, 0x1A}, {0x1C, 0x14, 0x18}, {0x1C,
396 0x14,
397 0x16},
398 /* Index 0xA0~0xA3 */
399 {0x1C, 0x14, 0x14}, {0x1C, 0x16, 0x14}, {0x1C, 0x18, 0x14}, {0x1C,
400 0x1A,
401 0x14},
402 /* Index 0xA4~0xA7 */
403 {0x1C, 0x1C, 0x14}, {0x1A, 0x1C, 0x14}, {0x18, 0x1C, 0x14}, {0x16,
404 0x1C,
405 0x14},
406 /* Index 0xA8~0xAB */
407 {0x14, 0x1C, 0x14}, {0x14, 0x1C, 0x16}, {0x14, 0x1C, 0x18}, {0x14,
408 0x1C,
409 0x1A},
410 /* Index 0xAC~0xAF */
411 {0x14, 0x1C, 0x1C}, {0x14, 0x1A, 0x1C}, {0x14, 0x18, 0x1C}, {0x14,
412 0x16,
413 0x1C},
414 /* Index 0xB0~0xB3 */
415 {0x00, 0x00, 0x10}, {0x04, 0x00, 0x10}, {0x08, 0x00, 0x10}, {0x0C,
416 0x00,
417 0x10},
418 /* Index 0xB4~0xB7 */
419 {0x10, 0x00, 0x10}, {0x10, 0x00, 0x0C}, {0x10, 0x00, 0x08}, {0x10,
420 0x00,
421 0x04},
422 /* Index 0xB8~0xBB */
423 {0x10, 0x00, 0x00}, {0x10, 0x04, 0x00}, {0x10, 0x08, 0x00}, {0x10,
424 0x0C,
425 0x00},
426 /* Index 0xBC~0xBF */
427 {0x10, 0x10, 0x00}, {0x0C, 0x10, 0x00}, {0x08, 0x10, 0x00}, {0x04,
428 0x10,
429 0x00},
430 /* Index 0xC0~0xC3 */
431 {0x00, 0x10, 0x00}, {0x00, 0x10, 0x04}, {0x00, 0x10, 0x08}, {0x00,
432 0x10,
433 0x0C},
434 /* Index 0xC4~0xC7 */
435 {0x00, 0x10, 0x10}, {0x00, 0x0C, 0x10}, {0x00, 0x08, 0x10}, {0x00,
436 0x04,
437 0x10},
438 /* Index 0xC8~0xCB */
439 {0x08, 0x08, 0x10}, {0x0A, 0x08, 0x10}, {0x0C, 0x08, 0x10}, {0x0E,
440 0x08,
441 0x10},
442 /* Index 0xCC~0xCF */
443 {0x10, 0x08, 0x10}, {0x10, 0x08, 0x0E}, {0x10, 0x08, 0x0C}, {0x10,
444 0x08,
445 0x0A},
446 /* Index 0xD0~0xD3 */
447 {0x10, 0x08, 0x08}, {0x10, 0x0A, 0x08}, {0x10, 0x0C, 0x08}, {0x10,
448 0x0E,
449 0x08},
450 /* Index 0xD4~0xD7 */
451 {0x10, 0x10, 0x08}, {0x0E, 0x10, 0x08}, {0x0C, 0x10, 0x08}, {0x0A,
452 0x10,
453 0x08},
454 /* Index 0xD8~0xDB */
455 {0x08, 0x10, 0x08}, {0x08, 0x10, 0x0A}, {0x08, 0x10, 0x0C}, {0x08,
456 0x10,
457 0x0E},
458 /* Index 0xDC~0xDF */
459 {0x08, 0x10, 0x10}, {0x08, 0x0E, 0x10}, {0x08, 0x0C, 0x10}, {0x08,
460 0x0A,
461 0x10},
462 /* Index 0xE0~0xE3 */
463 {0x0B, 0x0B, 0x10}, {0x0C, 0x0B, 0x10}, {0x0D, 0x0B, 0x10}, {0x0F,
464 0x0B,
465 0x10},
466 /* Index 0xE4~0xE7 */
467 {0x10, 0x0B, 0x10}, {0x10, 0x0B, 0x0F}, {0x10, 0x0B, 0x0D}, {0x10,
468 0x0B,
469 0x0C},
470 /* Index 0xE8~0xEB */
471 {0x10, 0x0B, 0x0B}, {0x10, 0x0C, 0x0B}, {0x10, 0x0D, 0x0B}, {0x10,
472 0x0F,
473 0x0B},
474 /* Index 0xEC~0xEF */
475 {0x10, 0x10, 0x0B}, {0x0F, 0x10, 0x0B}, {0x0D, 0x10, 0x0B}, {0x0C,
476 0x10,
477 0x0B},
478 /* Index 0xF0~0xF3 */
479 {0x0B, 0x10, 0x0B}, {0x0B, 0x10, 0x0C}, {0x0B, 0x10, 0x0D}, {0x0B,
480 0x10,
481 0x0F},
482 /* Index 0xF4~0xF7 */
483 {0x0B, 0x10, 0x10}, {0x0B, 0x0F, 0x10}, {0x0B, 0x0D, 0x10}, {0x0B,
484 0x0C,
485 0x10},
486 /* Index 0xF8~0xFB */
487 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
488 0x00,
489 0x00},
490 /* Index 0xFC~0xFF */
491 {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00, 0x00, 0x00}, {0x00,
492 0x00,
493 0x00}
494};
495
496static void set_crt_output_path(int set_iga);
497static void dvi_patch_skew_dvp0(void);
498static void dvi_patch_skew_dvp1(void);
499static void dvi_patch_skew_dvp_low(void);
500static void set_dvi_output_path(int set_iga, int output_interface);
501static void set_lcd_output_path(int set_iga, int output_interface);
502static int search_mode_setting(int ModeInfoIndex);
503static void load_fix_bit_crtc_reg(void);
504static void init_gfx_chip_info(void);
505static void init_tmds_chip_info(void);
506static void init_lvds_chip_info(void);
507static void device_screen_off(void);
508static void device_screen_on(void);
509static void set_display_channel(void);
510static void device_off(void);
511static void device_on(void);
512static void enable_second_display_channel(void);
513static void disable_second_display_channel(void);
514static int get_fb_size_from_pci(void);
515
516void viafb_write_reg(u8 index, u16 io_port, u8 data)
517{
518 outb(index, io_port);
519 outb(data, io_port + 1);
520 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, data); */
521}
522u8 viafb_read_reg(int io_port, u8 index)
523{
524 outb(index, io_port);
525 return inb(io_port + 1);
526}
527
528void viafb_lock_crt(void)
529{
530 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
531}
532
533void viafb_unlock_crt(void)
534{
535 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
536 viafb_write_reg_mask(CR47, VIACR, 0, BIT0);
537}
538
539void viafb_write_reg_mask(u8 index, int io_port, u8 data, u8 mask)
540{
541 u8 tmp;
542
543 outb(index, io_port);
544 tmp = inb(io_port + 1);
545 outb((data & mask) | (tmp & (~mask)), io_port + 1);
546 /*DEBUG_MSG(KERN_INFO "\nIndex=%2d Value=%2d", index, tmp); */
547}
548
549void write_dac_reg(u8 index, u8 r, u8 g, u8 b)
550{
551 outb(index, LUT_INDEX_WRITE);
552 outb(r, LUT_DATA);
553 outb(g, LUT_DATA);
554 outb(b, LUT_DATA);
555}
556
557/*Set IGA path for each device*/
558void viafb_set_iga_path(void)
559{
560
561 if (viafb_SAMM_ON == 1) {
562 if (viafb_CRT_ON) {
563 if (viafb_primary_dev == CRT_Device)
564 viaparinfo->crt_setting_info->iga_path = IGA1;
565 else
566 viaparinfo->crt_setting_info->iga_path = IGA2;
567 }
568
569 if (viafb_DVI_ON) {
570 if (viafb_primary_dev == DVI_Device)
571 viaparinfo->tmds_setting_info->iga_path = IGA1;
572 else
573 viaparinfo->tmds_setting_info->iga_path = IGA2;
574 }
575
576 if (viafb_LCD_ON) {
577 if (viafb_primary_dev == LCD_Device) {
578 if (viafb_dual_fb &&
579 (viaparinfo->chip_info->gfx_chip_name ==
580 UNICHROME_CLE266)) {
581 viaparinfo->
582 lvds_setting_info->iga_path = IGA2;
583 viaparinfo->
584 crt_setting_info->iga_path = IGA1;
585 viaparinfo->
586 tmds_setting_info->iga_path = IGA1;
587 } else
588 viaparinfo->
589 lvds_setting_info->iga_path = IGA1;
590 } else {
591 viaparinfo->lvds_setting_info->iga_path = IGA2;
592 }
593 }
594 if (viafb_LCD2_ON) {
595 if (LCD2_Device == viafb_primary_dev)
596 viaparinfo->lvds_setting_info2->iga_path = IGA1;
597 else
598 viaparinfo->lvds_setting_info2->iga_path = IGA2;
599 }
600 } else {
601 viafb_SAMM_ON = 0;
602
603 if (viafb_CRT_ON && viafb_LCD_ON) {
604 viaparinfo->crt_setting_info->iga_path = IGA1;
605 viaparinfo->lvds_setting_info->iga_path = IGA2;
606 } else if (viafb_CRT_ON && viafb_DVI_ON) {
607 viaparinfo->crt_setting_info->iga_path = IGA1;
608 viaparinfo->tmds_setting_info->iga_path = IGA2;
609 } else if (viafb_LCD_ON && viafb_DVI_ON) {
610 viaparinfo->tmds_setting_info->iga_path = IGA1;
611 viaparinfo->lvds_setting_info->iga_path = IGA2;
612 } else if (viafb_LCD_ON && viafb_LCD2_ON) {
613 viaparinfo->lvds_setting_info->iga_path = IGA2;
614 viaparinfo->lvds_setting_info2->iga_path = IGA2;
615 } else if (viafb_CRT_ON) {
616 viaparinfo->crt_setting_info->iga_path = IGA1;
617 } else if (viafb_LCD_ON) {
618 viaparinfo->lvds_setting_info->iga_path = IGA2;
619 } else if (viafb_DVI_ON) {
620 viaparinfo->tmds_setting_info->iga_path = IGA1;
621 }
622 }
623}
624
09cf1180 625void viafb_set_primary_address(u32 addr)
d61e0bf3 626{
09cf1180
FTS		 627 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_address(0x%08X)\n", addr);
628 viafb_write_reg(CR0D, VIACR, addr & 0xFF);
629 viafb_write_reg(CR0C, VIACR, (addr >> 8) & 0xFF);
630 viafb_write_reg(CR34, VIACR, (addr >> 16) & 0xFF);
631 viafb_write_reg_mask(CR48, VIACR, (addr >> 24) & 0x1F, 0x1F);
632}
d61e0bf3 633
09cf1180
FTS		 634void viafb_set_secondary_address(u32 addr)
635{
636 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_address(0x%08X)\n", addr);
637 /* secondary display supports only quadword aligned memory */
638 viafb_write_reg_mask(CR62, VIACR, (addr >> 2) & 0xFE, 0xFE);
639 viafb_write_reg(CR63, VIACR, (addr >> 10) & 0xFF);
640 viafb_write_reg(CR64, VIACR, (addr >> 18) & 0xFF);
641 viafb_write_reg_mask(CRA3, VIACR, (addr >> 26) & 0x07, 0x07);
d61e0bf3
JC		 642}
643
2d6e8851
FTS		 644void viafb_set_primary_pitch(u32 pitch)
645{
646 DEBUG_MSG(KERN_DEBUG "viafb_set_primary_pitch(0x%08X)\n", pitch);
647 /* spec does not say that first adapter skips 3 bits but old
648 * code did it and seems to be reasonable in analogy to 2nd adapter
649 */
650 pitch = pitch >> 3;
651 viafb_write_reg(0x13, VIACR, pitch & 0xFF);
652 viafb_write_reg_mask(0x35, VIACR, (pitch >> (8 - 5)) & 0xE0, 0xE0);
653}
654
655void viafb_set_secondary_pitch(u32 pitch)
656{
657 DEBUG_MSG(KERN_DEBUG "viafb_set_secondary_pitch(0x%08X)\n", pitch);
658 pitch = pitch >> 3;
659 viafb_write_reg(0x66, VIACR, pitch & 0xFF);
660 viafb_write_reg_mask(0x67, VIACR, (pitch >> 8) & 0x03, 0x03);
661 viafb_write_reg_mask(0x71, VIACR, (pitch >> (10 - 7)) & 0x80, 0x80);
662}
663
d61e0bf3
JC		 664void viafb_set_output_path(int device, int set_iga, int output_interface)
665{
666 switch (device) {
667 case DEVICE_CRT:
668 set_crt_output_path(set_iga);
669 break;
670 case DEVICE_DVI:
671 set_dvi_output_path(set_iga, output_interface);
672 break;
673 case DEVICE_LCD:
674 set_lcd_output_path(set_iga, output_interface);
675 break;
676 }
677}
678
679static void set_crt_output_path(int set_iga)
680{
681 viafb_write_reg_mask(CR36, VIACR, 0x00, BIT4 + BIT5);
682
683 switch (set_iga) {
684 case IGA1:
685 viafb_write_reg_mask(SR16, VIASR, 0x00, BIT6);
686 break;
687 case IGA2:
688 case IGA1_IGA2:
689 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
690 viafb_write_reg_mask(SR16, VIASR, 0x40, BIT6);
691 if (set_iga == IGA1_IGA2)
692 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
693 break;
694 }
695}
696
697static void dvi_patch_skew_dvp0(void)
698{
699 /* Reset data driving first: */
700 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
701 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
702
703 switch (viaparinfo->chip_info->gfx_chip_name) {
704 case UNICHROME_P4M890:
705 {
706 if ((viaparinfo->tmds_setting_info->h_active == 1600) &&
707 (viaparinfo->tmds_setting_info->v_active ==
708 1200))
709 viafb_write_reg_mask(CR96, VIACR, 0x03,
710 BIT0 + BIT1 + BIT2);
711 else
712 viafb_write_reg_mask(CR96, VIACR, 0x07,
713 BIT0 + BIT1 + BIT2);
714 break;
715 }
716
717 case UNICHROME_P4M900:
718 {
719 viafb_write_reg_mask(CR96, VIACR, 0x07,
720 BIT0 + BIT1 + BIT2 + BIT3);
721 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
722 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
723 break;
724 }
725
726 default:
727 {
728 break;
729 }
730 }
731}
732
733static void dvi_patch_skew_dvp1(void)
734{
735 switch (viaparinfo->chip_info->gfx_chip_name) {
736 case UNICHROME_CX700:
737 {
738 break;
739 }
740
741 default:
742 {
743 break;
744 }
745 }
746}
747
748static void dvi_patch_skew_dvp_low(void)
749{
750 switch (viaparinfo->chip_info->gfx_chip_name) {
751 case UNICHROME_K8M890:
752 {
753 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
754 break;
755 }
756
757 case UNICHROME_P4M900:
758 {
759 viafb_write_reg_mask(CR99, VIACR, 0x08,
760 BIT0 + BIT1 + BIT2 + BIT3);
761 break;
762 }
763
764 case UNICHROME_P4M890:
765 {
766 viafb_write_reg_mask(CR99, VIACR, 0x0F,
767 BIT0 + BIT1 + BIT2 + BIT3);
768 break;
769 }
770
771 default:
772 {
773 break;
774 }
775 }
776}
777
778static void set_dvi_output_path(int set_iga, int output_interface)
779{
780 switch (output_interface) {
781 case INTERFACE_DVP0:
782 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
783
784 if (set_iga == IGA1) {
785 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
786 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 +
787 BIT5 + BIT7);
788 } else {
789 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
790 viafb_write_reg_mask(CR6C, VIACR, 0xA1, BIT0 +
791 BIT5 + BIT7);
792 }
793
794 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT7 + BIT6);
795
796 dvi_patch_skew_dvp0();
797 break;
798
799 case INTERFACE_DVP1:
800 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
801 if (set_iga == IGA1)
802 viafb_write_reg_mask(CR93, VIACR, 0x21,
803 BIT0 + BIT5 + BIT7);
804 else
805 viafb_write_reg_mask(CR93, VIACR, 0xA1,
806 BIT0 + BIT5 + BIT7);
807 } else {
808 if (set_iga == IGA1)
809 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
810 else
811 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
812 }
813
814 viafb_write_reg_mask(SR1E, VIASR, 0x30, BIT4 + BIT5);
815 dvi_patch_skew_dvp1();
816 break;
817 case INTERFACE_DFP_HIGH:
818 if (viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266) {
819 if (set_iga == IGA1) {
820 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
821 viafb_write_reg_mask(CR97, VIACR, 0x03,
822 BIT0 + BIT1 + BIT4);
823 } else {
824 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
825 viafb_write_reg_mask(CR97, VIACR, 0x13,
826 BIT0 + BIT1 + BIT4);
827 }
828 }
829 viafb_write_reg_mask(SR2A, VIASR, 0x0C, BIT2 + BIT3);
830 break;
831
832 case INTERFACE_DFP_LOW:
833 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
834 break;
835
836 if (set_iga == IGA1) {
837 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
838 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
839 } else {
840 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
841 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
842 }
843
844 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
845 dvi_patch_skew_dvp_low();
846 break;
847
848 case INTERFACE_TMDS:
849 if (set_iga == IGA1)
850 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
851 else
852 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
853 break;
854 }
855
856 if (set_iga == IGA2) {
857 enable_second_display_channel();
858 /* Disable LCD Scaling */
859 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0);
860 }
861}
862
863static void set_lcd_output_path(int set_iga, int output_interface)
864{
865 DEBUG_MSG(KERN_INFO
866 "set_lcd_output_path, iga:%d,out_interface:%d\n",
867 set_iga, output_interface);
868 switch (set_iga) {
869 case IGA1:
870 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
871 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
872
873 disable_second_display_channel();
874 break;
875
876 case IGA2:
877 viafb_write_reg_mask(CR6B, VIACR, 0x00, BIT3);
878 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
879
880 enable_second_display_channel();
881 break;
882
883 case IGA1_IGA2:
884 viafb_write_reg_mask(CR6B, VIACR, 0x08, BIT3);
885 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
886
887 disable_second_display_channel();
888 break;
889 }
890
891 switch (output_interface) {
892 case INTERFACE_DVP0:
893 if (set_iga == IGA1) {
894 viafb_write_reg_mask(CR96, VIACR, 0x00, BIT4);
895 } else {
896 viafb_write_reg(CR91, VIACR, 0x00);
897 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
898 }
899 break;
900
901 case INTERFACE_DVP1:
902 if (set_iga == IGA1)
903 viafb_write_reg_mask(CR9B, VIACR, 0x00, BIT4);
904 else {
905 viafb_write_reg(CR91, VIACR, 0x00);
906 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
907 }
908 break;
909
910 case INTERFACE_DFP_HIGH:
911 if (set_iga == IGA1)
912 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
913 else {
914 viafb_write_reg(CR91, VIACR, 0x00);
915 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
916 viafb_write_reg_mask(CR96, VIACR, 0x10, BIT4);
917 }
918 break;
919
920 case INTERFACE_DFP_LOW:
921 if (set_iga == IGA1)
922 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
923 else {
924 viafb_write_reg(CR91, VIACR, 0x00);
925 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
926 viafb_write_reg_mask(CR9B, VIACR, 0x10, BIT4);
927 }
928
929 break;
930
931 case INTERFACE_DFP:
932 if ((UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name)
933 || (UNICHROME_P4M890 ==
934 viaparinfo->chip_info->gfx_chip_name))
935 viafb_write_reg_mask(CR97, VIACR, 0x84,
936 BIT7 + BIT2 + BIT1 + BIT0);
937 if (set_iga == IGA1) {
938 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
939 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
940 } else {
941 viafb_write_reg(CR91, VIACR, 0x00);
942 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
943 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
944 }
945 break;
946
947 case INTERFACE_LVDS0:
948 case INTERFACE_LVDS0LVDS1:
949 if (set_iga == IGA1)
950 viafb_write_reg_mask(CR99, VIACR, 0x00, BIT4);
951 else
952 viafb_write_reg_mask(CR99, VIACR, 0x10, BIT4);
953
954 break;
955
956 case INTERFACE_LVDS1:
957 if (set_iga == IGA1)
958 viafb_write_reg_mask(CR97, VIACR, 0x00, BIT4);
959 else
960 viafb_write_reg_mask(CR97, VIACR, 0x10, BIT4);
961 break;
962 }
963}
964
965/* Search Mode Index */
966static int search_mode_setting(int ModeInfoIndex)
967{
968 int i = 0;
969
970 while ((i < NUM_TOTAL_MODETABLE) &&
971 (ModeInfoIndex != CLE266Modes[i].ModeIndex))
972 i++;
973 if (i >= NUM_TOTAL_MODETABLE)
974 i = 0;
975 return i;
976
977}
978
979struct VideoModeTable *viafb_get_modetbl_pointer(int Index)
980{
981 struct VideoModeTable *TmpTbl = NULL;
982 TmpTbl = &CLE266Modes[search_mode_setting(Index)];
983 return TmpTbl;
984}
985
986struct VideoModeTable *viafb_get_cea_mode_tbl_pointer(int Index)
987{
988 struct VideoModeTable *TmpTbl = NULL;
989 int i = 0;
990 while ((i < NUM_TOTAL_CEA_MODES) &&
991 (Index != CEA_HDMI_Modes[i].ModeIndex))
992 i++;
993 if ((i < NUM_TOTAL_CEA_MODES))
994 TmpTbl = &CEA_HDMI_Modes[i];
995 else {
996 /*Still use general timing if don't find CEA timing */
997 i = 0;
998 while ((i < NUM_TOTAL_MODETABLE) &&
999 (Index != CLE266Modes[i].ModeIndex))
1000 i++;
1001 if (i >= NUM_TOTAL_MODETABLE)
1002 i = 0;
1003 TmpTbl = &CLE266Modes[i];
1004 }
1005 return TmpTbl;
1006}
1007
1008static void load_fix_bit_crtc_reg(void)
1009{
1010 /* always set to 1 */
1011 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1012 /* line compare should set all bits = 1 (extend modes) */
1013 viafb_write_reg(CR18, VIACR, 0xff);
1014 /* line compare should set all bits = 1 (extend modes) */
1015 viafb_write_reg_mask(CR07, VIACR, 0x10, BIT4);
1016 /* line compare should set all bits = 1 (extend modes) */
1017 viafb_write_reg_mask(CR09, VIACR, 0x40, BIT6);
1018 /* line compare should set all bits = 1 (extend modes) */
1019 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1020 /* line compare should set all bits = 1 (extend modes) */
1021 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2);
1022 /*viafb_write_reg_mask(CR32, VIACR, 0x01, BIT0); */
1023 /* extend mode always set to e3h */
1024 viafb_write_reg(CR17, VIACR, 0xe3);
1025 /* extend mode always set to 0h */
1026 viafb_write_reg(CR08, VIACR, 0x00);
1027 /* extend mode always set to 0h */
1028 viafb_write_reg(CR14, VIACR, 0x00);
1029
1030 /* If K8M800, enable Prefetch Mode. */
1031 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
1032 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890))
1033 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3);
1034 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
1035 && (viaparinfo->chip_info->gfx_chip_revision == CLE266_REVISION_AX))
1036 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1);
1037
1038}
1039
1040void viafb_load_reg(int timing_value, int viafb_load_reg_num,
1041 struct io_register *reg,
1042 int io_type)
1043{
1044 int reg_mask;
1045 int bit_num = 0;
1046 int data;
1047 int i, j;
1048 int shift_next_reg;
1049 int start_index, end_index, cr_index;
1050 u16 get_bit;
1051
1052 for (i = 0; i < viafb_load_reg_num; i++) {
1053 reg_mask = 0;
1054 data = 0;
1055 start_index = reg[i].start_bit;
1056 end_index = reg[i].end_bit;
1057 cr_index = reg[i].io_addr;
1058
1059 shift_next_reg = bit_num;
1060 for (j = start_index; j <= end_index; j++) {
1061 /*if (bit_num==8) timing_value = timing_value >>8; */
1062 reg_mask = reg_mask | (BIT0 << j);
1063 get_bit = (timing_value & (BIT0 << bit_num));
1064 data =
1065 data | ((get_bit >> shift_next_reg) << start_index);
1066 bit_num++;
1067 }
1068 if (io_type == VIACR)
1069 viafb_write_reg_mask(cr_index, VIACR, data, reg_mask);
1070 else
1071 viafb_write_reg_mask(cr_index, VIASR, data, reg_mask);
1072 }
1073
1074}
1075
1076/* Write Registers */
1077void viafb_write_regx(struct io_reg RegTable[], int ItemNum)
1078{
1079 int i;
1080 unsigned char RegTemp;
1081
1082 /*DEBUG_MSG(KERN_INFO "Table Size : %x!!\n",ItemNum ); */
1083
1084 for (i = 0; i < ItemNum; i++) {
1085 outb(RegTable[i].index, RegTable[i].port);
1086 RegTemp = inb(RegTable[i].port + 1);
1087 RegTemp = (RegTemp & (~RegTable[i].mask)) | RegTable[i].value;
1088 outb(RegTemp, RegTable[i].port + 1);
1089 }
1090}
1091
d61e0bf3
JC		 1092void viafb_load_fetch_count_reg(int h_addr, int bpp_byte, int set_iga)
1093{
1094 int reg_value;
1095 int viafb_load_reg_num;
1096 struct io_register *reg = NULL;
1097
1098 switch (set_iga) {
1099 case IGA1_IGA2:
1100 case IGA1:
1101 reg_value = IGA1_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1102 viafb_load_reg_num = fetch_count_reg.
1103 iga1_fetch_count_reg.reg_num;
1104 reg = fetch_count_reg.iga1_fetch_count_reg.reg;
1105 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1106 if (set_iga == IGA1)
1107 break;
1108 case IGA2:
1109 reg_value = IGA2_FETCH_COUNT_FORMULA(h_addr, bpp_byte);
1110 viafb_load_reg_num = fetch_count_reg.
1111 iga2_fetch_count_reg.reg_num;
1112 reg = fetch_count_reg.iga2_fetch_count_reg.reg;
1113 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1114 break;
1115 }
1116
1117}
1118
1119void viafb_load_FIFO_reg(int set_iga, int hor_active, int ver_active)
1120{
1121 int reg_value;
1122 int viafb_load_reg_num;
1123 struct io_register *reg = NULL;
1124 int iga1_fifo_max_depth = 0, iga1_fifo_threshold =
1125 0, iga1_fifo_high_threshold = 0, iga1_display_queue_expire_num = 0;
1126 int iga2_fifo_max_depth = 0, iga2_fifo_threshold =
1127 0, iga2_fifo_high_threshold = 0, iga2_display_queue_expire_num = 0;
1128
1129 if (set_iga == IGA1) {
1130 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1131 iga1_fifo_max_depth = K800_IGA1_FIFO_MAX_DEPTH;
1132 iga1_fifo_threshold = K800_IGA1_FIFO_THRESHOLD;
1133 iga1_fifo_high_threshold =
1134 K800_IGA1_FIFO_HIGH_THRESHOLD;
1135 /* If resolution > 1280x1024, expire length = 64, else
1136 expire length = 128 */
1137 if ((hor_active > 1280) && (ver_active > 1024))
1138 iga1_display_queue_expire_num = 16;
1139 else
1140 iga1_display_queue_expire_num =
1141 K800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1142
1143 }
1144
1145 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1146 iga1_fifo_max_depth = P880_IGA1_FIFO_MAX_DEPTH;
1147 iga1_fifo_threshold = P880_IGA1_FIFO_THRESHOLD;
1148 iga1_fifo_high_threshold =
1149 P880_IGA1_FIFO_HIGH_THRESHOLD;
1150 iga1_display_queue_expire_num =
1151 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1152
1153 /* If resolution > 1280x1024, expire length = 64, else
1154 expire length = 128 */
1155 if ((hor_active > 1280) && (ver_active > 1024))
1156 iga1_display_queue_expire_num = 16;
1157 else
1158 iga1_display_queue_expire_num =
1159 P880_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1160 }
1161
1162 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1163 iga1_fifo_max_depth = CN700_IGA1_FIFO_MAX_DEPTH;
1164 iga1_fifo_threshold = CN700_IGA1_FIFO_THRESHOLD;
1165 iga1_fifo_high_threshold =
1166 CN700_IGA1_FIFO_HIGH_THRESHOLD;
1167
1168 /* If resolution > 1280x1024, expire length = 64,
1169 else expire length = 128 */
1170 if ((hor_active > 1280) && (ver_active > 1024))
1171 iga1_display_queue_expire_num = 16;
1172 else
1173 iga1_display_queue_expire_num =
1174 CN700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1175 }
1176
1177 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1178 iga1_fifo_max_depth = CX700_IGA1_FIFO_MAX_DEPTH;
1179 iga1_fifo_threshold = CX700_IGA1_FIFO_THRESHOLD;
1180 iga1_fifo_high_threshold =
1181 CX700_IGA1_FIFO_HIGH_THRESHOLD;
1182 iga1_display_queue_expire_num =
1183 CX700_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1184 }
1185
1186 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1187 iga1_fifo_max_depth = K8M890_IGA1_FIFO_MAX_DEPTH;
1188 iga1_fifo_threshold = K8M890_IGA1_FIFO_THRESHOLD;
1189 iga1_fifo_high_threshold =
1190 K8M890_IGA1_FIFO_HIGH_THRESHOLD;
1191 iga1_display_queue_expire_num =
1192 K8M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1193 }
1194
1195 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1196 iga1_fifo_max_depth = P4M890_IGA1_FIFO_MAX_DEPTH;
1197 iga1_fifo_threshold = P4M890_IGA1_FIFO_THRESHOLD;
1198 iga1_fifo_high_threshold =
1199 P4M890_IGA1_FIFO_HIGH_THRESHOLD;
1200 iga1_display_queue_expire_num =
1201 P4M890_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1202 }
1203
1204 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1205 iga1_fifo_max_depth = P4M900_IGA1_FIFO_MAX_DEPTH;
1206 iga1_fifo_threshold = P4M900_IGA1_FIFO_THRESHOLD;
1207 iga1_fifo_high_threshold =
1208 P4M900_IGA1_FIFO_HIGH_THRESHOLD;
1209 iga1_display_queue_expire_num =
1210 P4M900_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1211 }
1212
1213 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1214 iga1_fifo_max_depth = VX800_IGA1_FIFO_MAX_DEPTH;
1215 iga1_fifo_threshold = VX800_IGA1_FIFO_THRESHOLD;
1216 iga1_fifo_high_threshold =
1217 VX800_IGA1_FIFO_HIGH_THRESHOLD;
1218 iga1_display_queue_expire_num =
1219 VX800_IGA1_DISPLAY_QUEUE_EXPIRE_NUM;
1220 }
1221
1222 /* Set Display FIFO Depath Select */
1223 reg_value = IGA1_FIFO_DEPTH_SELECT_FORMULA(iga1_fifo_max_depth);
1224 viafb_load_reg_num =
1225 display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg_num;
1226 reg = display_fifo_depth_reg.iga1_fifo_depth_select_reg.reg;
1227 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1228
1229 /* Set Display FIFO Threshold Select */
1230 reg_value = IGA1_FIFO_THRESHOLD_FORMULA(iga1_fifo_threshold);
1231 viafb_load_reg_num =
1232 fifo_threshold_select_reg.
1233 iga1_fifo_threshold_select_reg.reg_num;
1234 reg =
1235 fifo_threshold_select_reg.
1236 iga1_fifo_threshold_select_reg.reg;
1237 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1238
1239 /* Set FIFO High Threshold Select */
1240 reg_value =
1241 IGA1_FIFO_HIGH_THRESHOLD_FORMULA(iga1_fifo_high_threshold);
1242 viafb_load_reg_num =
1243 fifo_high_threshold_select_reg.
1244 iga1_fifo_high_threshold_select_reg.reg_num;
1245 reg =
1246 fifo_high_threshold_select_reg.
1247 iga1_fifo_high_threshold_select_reg.reg;
1248 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1249
1250 /* Set Display Queue Expire Num */
1251 reg_value =
1252 IGA1_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1253 (iga1_display_queue_expire_num);
1254 viafb_load_reg_num =
1255 display_queue_expire_num_reg.
1256 iga1_display_queue_expire_num_reg.reg_num;
1257 reg =
1258 display_queue_expire_num_reg.
1259 iga1_display_queue_expire_num_reg.reg;
1260 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIASR);
1261
1262 } else {
1263 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1264 iga2_fifo_max_depth = K800_IGA2_FIFO_MAX_DEPTH;
1265 iga2_fifo_threshold = K800_IGA2_FIFO_THRESHOLD;
1266 iga2_fifo_high_threshold =
1267 K800_IGA2_FIFO_HIGH_THRESHOLD;
1268
1269 /* If resolution > 1280x1024, expire length = 64,
1270 else expire length = 128 */
1271 if ((hor_active > 1280) && (ver_active > 1024))
1272 iga2_display_queue_expire_num = 16;
1273 else
1274 iga2_display_queue_expire_num =
1275 K800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1276 }
1277
1278 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_PM800) {
1279 iga2_fifo_max_depth = P880_IGA2_FIFO_MAX_DEPTH;
1280 iga2_fifo_threshold = P880_IGA2_FIFO_THRESHOLD;
1281 iga2_fifo_high_threshold =
1282 P880_IGA2_FIFO_HIGH_THRESHOLD;
1283
1284 /* If resolution > 1280x1024, expire length = 64,
1285 else expire length = 128 */
1286 if ((hor_active > 1280) && (ver_active > 1024))
1287 iga2_display_queue_expire_num = 16;
1288 else
1289 iga2_display_queue_expire_num =
1290 P880_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1291 }
1292
1293 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CN700) {
1294 iga2_fifo_max_depth = CN700_IGA2_FIFO_MAX_DEPTH;
1295 iga2_fifo_threshold = CN700_IGA2_FIFO_THRESHOLD;
1296 iga2_fifo_high_threshold =
1297 CN700_IGA2_FIFO_HIGH_THRESHOLD;
1298
1299 /* If resolution > 1280x1024, expire length = 64,
1300 else expire length = 128 */
1301 if ((hor_active > 1280) && (ver_active > 1024))
1302 iga2_display_queue_expire_num = 16;
1303 else
1304 iga2_display_queue_expire_num =
1305 CN700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1306 }
1307
1308 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1309 iga2_fifo_max_depth = CX700_IGA2_FIFO_MAX_DEPTH;
1310 iga2_fifo_threshold = CX700_IGA2_FIFO_THRESHOLD;
1311 iga2_fifo_high_threshold =
1312 CX700_IGA2_FIFO_HIGH_THRESHOLD;
1313 iga2_display_queue_expire_num =
1314 CX700_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1315 }
1316
1317 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K8M890) {
1318 iga2_fifo_max_depth = K8M890_IGA2_FIFO_MAX_DEPTH;
1319 iga2_fifo_threshold = K8M890_IGA2_FIFO_THRESHOLD;
1320 iga2_fifo_high_threshold =
1321 K8M890_IGA2_FIFO_HIGH_THRESHOLD;
1322 iga2_display_queue_expire_num =
1323 K8M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1324 }
1325
1326 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M890) {
1327 iga2_fifo_max_depth = P4M890_IGA2_FIFO_MAX_DEPTH;
1328 iga2_fifo_threshold = P4M890_IGA2_FIFO_THRESHOLD;
1329 iga2_fifo_high_threshold =
1330 P4M890_IGA2_FIFO_HIGH_THRESHOLD;
1331 iga2_display_queue_expire_num =
1332 P4M890_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1333 }
1334
1335 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_P4M900) {
1336 iga2_fifo_max_depth = P4M900_IGA2_FIFO_MAX_DEPTH;
1337 iga2_fifo_threshold = P4M900_IGA2_FIFO_THRESHOLD;
1338 iga2_fifo_high_threshold =
1339 P4M900_IGA2_FIFO_HIGH_THRESHOLD;
1340 iga2_display_queue_expire_num =
1341 P4M900_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1342 }
1343
1344 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_VX800) {
1345 iga2_fifo_max_depth = VX800_IGA2_FIFO_MAX_DEPTH;
1346 iga2_fifo_threshold = VX800_IGA2_FIFO_THRESHOLD;
1347 iga2_fifo_high_threshold =
1348 VX800_IGA2_FIFO_HIGH_THRESHOLD;
1349 iga2_display_queue_expire_num =
1350 VX800_IGA2_DISPLAY_QUEUE_EXPIRE_NUM;
1351 }
1352
1353 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800) {
1354 /* Set Display FIFO Depath Select */
1355 reg_value =
1356 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth)
1357 - 1;
1358 /* Patch LCD in IGA2 case */
1359 viafb_load_reg_num =
1360 display_fifo_depth_reg.
1361 iga2_fifo_depth_select_reg.reg_num;
1362 reg =
1363 display_fifo_depth_reg.
1364 iga2_fifo_depth_select_reg.reg;
1365 viafb_load_reg(reg_value,
1366 viafb_load_reg_num, reg, VIACR);
1367 } else {
1368
1369 /* Set Display FIFO Depath Select */
1370 reg_value =
1371 IGA2_FIFO_DEPTH_SELECT_FORMULA(iga2_fifo_max_depth);
1372 viafb_load_reg_num =
1373 display_fifo_depth_reg.
1374 iga2_fifo_depth_select_reg.reg_num;
1375 reg =
1376 display_fifo_depth_reg.
1377 iga2_fifo_depth_select_reg.reg;
1378 viafb_load_reg(reg_value,
1379 viafb_load_reg_num, reg, VIACR);
1380 }
1381
1382 /* Set Display FIFO Threshold Select */
1383 reg_value = IGA2_FIFO_THRESHOLD_FORMULA(iga2_fifo_threshold);
1384 viafb_load_reg_num =
1385 fifo_threshold_select_reg.
1386 iga2_fifo_threshold_select_reg.reg_num;
1387 reg =
1388 fifo_threshold_select_reg.
1389 iga2_fifo_threshold_select_reg.reg;
1390 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1391
1392 /* Set FIFO High Threshold Select */
1393 reg_value =
1394 IGA2_FIFO_HIGH_THRESHOLD_FORMULA(iga2_fifo_high_threshold);
1395 viafb_load_reg_num =
1396 fifo_high_threshold_select_reg.
1397 iga2_fifo_high_threshold_select_reg.reg_num;
1398 reg =
1399 fifo_high_threshold_select_reg.
1400 iga2_fifo_high_threshold_select_reg.reg;
1401 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1402
1403 /* Set Display Queue Expire Num */
1404 reg_value =
1405 IGA2_DISPLAY_QUEUE_EXPIRE_NUM_FORMULA
1406 (iga2_display_queue_expire_num);
1407 viafb_load_reg_num =
1408 display_queue_expire_num_reg.
1409 iga2_display_queue_expire_num_reg.reg_num;
1410 reg =
1411 display_queue_expire_num_reg.
1412 iga2_display_queue_expire_num_reg.reg;
1413 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1414
1415 }
1416
1417}
1418
1419u32 viafb_get_clk_value(int clk)
1420{
1421 int i;
1422
1423 for (i = 0; i < NUM_TOTAL_PLL_TABLE; i++) {
1424 if (clk == pll_value[i].clk) {
1425 switch (viaparinfo->chip_info->gfx_chip_name) {
1426 case UNICHROME_CLE266:
1427 case UNICHROME_K400:
1428 return pll_value[i].cle266_pll;
1429
1430 case UNICHROME_K800:
1431 case UNICHROME_PM800:
1432 case UNICHROME_CN700:
1433 return pll_value[i].k800_pll;
1434
1435 case UNICHROME_CX700:
1436 case UNICHROME_K8M890:
1437 case UNICHROME_P4M890:
1438 case UNICHROME_P4M900:
1439 case UNICHROME_VX800:
1440 return pll_value[i].cx700_pll;
1441 }
1442 }
1443 }
1444
1445 DEBUG_MSG(KERN_INFO "Can't find match PLL value\n\n");
1446 return 0;
1447}
1448
1449/* Set VCLK*/
1450void viafb_set_vclock(u32 CLK, int set_iga)
1451{
1452 unsigned char RegTemp;
1453
1454 /* H.W. Reset : ON */
1455 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1456
1457 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1458 /* Change D,N FOR VCLK */
1459 switch (viaparinfo->chip_info->gfx_chip_name) {
1460 case UNICHROME_CLE266:
1461 case UNICHROME_K400:
1462 viafb_write_reg(SR46, VIASR, CLK / 0x100);
1463 viafb_write_reg(SR47, VIASR, CLK % 0x100);
1464 break;
1465
1466 case UNICHROME_K800:
1467 case UNICHROME_PM800:
1468 case UNICHROME_CN700:
1469 case UNICHROME_CX700:
1470 case UNICHROME_K8M890:
1471 case UNICHROME_P4M890:
1472 case UNICHROME_P4M900:
1473 case UNICHROME_VX800:
1474 viafb_write_reg(SR44, VIASR, CLK / 0x10000);
1475 DEBUG_MSG(KERN_INFO "\nSR44=%x", CLK / 0x10000);
1476 viafb_write_reg(SR45, VIASR, (CLK & 0xFFFF) / 0x100);
1477 DEBUG_MSG(KERN_INFO "\nSR45=%x",
1478 (CLK & 0xFFFF) / 0x100);
1479 viafb_write_reg(SR46, VIASR, CLK % 0x100);
1480 DEBUG_MSG(KERN_INFO "\nSR46=%x", CLK % 0x100);
1481 break;
1482 }
1483 }
1484
1485 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1486 /* Change D,N FOR LCK */
1487 switch (viaparinfo->chip_info->gfx_chip_name) {
1488 case UNICHROME_CLE266:
1489 case UNICHROME_K400:
1490 viafb_write_reg(SR44, VIASR, CLK / 0x100);
1491 viafb_write_reg(SR45, VIASR, CLK % 0x100);
1492 break;
1493
1494 case UNICHROME_K800:
1495 case UNICHROME_PM800:
1496 case UNICHROME_CN700:
1497 case UNICHROME_CX700:
1498 case UNICHROME_K8M890:
1499 case UNICHROME_P4M890:
1500 case UNICHROME_P4M900:
1501 case UNICHROME_VX800:
1502 viafb_write_reg(SR4A, VIASR, CLK / 0x10000);
1503 viafb_write_reg(SR4B, VIASR, (CLK & 0xFFFF) / 0x100);
1504 viafb_write_reg(SR4C, VIASR, CLK % 0x100);
1505 break;
1506 }
1507 }
1508
1509 /* H.W. Reset : OFF */
1510 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
1511
1512 /* Reset PLL */
1513 if ((set_iga == IGA1) || (set_iga == IGA1_IGA2)) {
1514 viafb_write_reg_mask(SR40, VIASR, 0x02, BIT1);
1515 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT1);
1516 }
1517
1518 if ((set_iga == IGA2) || (set_iga == IGA1_IGA2)) {
1519 viafb_write_reg_mask(SR40, VIASR, 0x01, BIT0);
1520 viafb_write_reg_mask(SR40, VIASR, 0x00, BIT0);
1521 }
1522
1523 /* Fire! */
1524 RegTemp = inb(VIARMisc);
1525 outb(RegTemp | (BIT2 + BIT3), VIAWMisc);
1526}
1527
1528void viafb_load_crtc_timing(struct display_timing device_timing,
1529 int set_iga)
1530{
1531 int i;
1532 int viafb_load_reg_num = 0;
1533 int reg_value = 0;
1534 struct io_register *reg = NULL;
1535
1536 viafb_unlock_crt();
1537
1538 for (i = 0; i < 12; i++) {
1539 if (set_iga == IGA1) {
1540 switch (i) {
1541 case H_TOTAL_INDEX:
1542 reg_value =
1543 IGA1_HOR_TOTAL_FORMULA(device_timing.
1544 hor_total);
1545 viafb_load_reg_num =
1546 iga1_crtc_reg.hor_total.reg_num;
1547 reg = iga1_crtc_reg.hor_total.reg;
1548 break;
1549 case H_ADDR_INDEX:
1550 reg_value =
1551 IGA1_HOR_ADDR_FORMULA(device_timing.
1552 hor_addr);
1553 viafb_load_reg_num =
1554 iga1_crtc_reg.hor_addr.reg_num;
1555 reg = iga1_crtc_reg.hor_addr.reg;
1556 break;
1557 case H_BLANK_START_INDEX:
1558 reg_value =
1559 IGA1_HOR_BLANK_START_FORMULA
1560 (device_timing.hor_blank_start);
1561 viafb_load_reg_num =
1562 iga1_crtc_reg.hor_blank_start.reg_num;
1563 reg = iga1_crtc_reg.hor_blank_start.reg;
1564 break;
1565 case H_BLANK_END_INDEX:
1566 reg_value =
1567 IGA1_HOR_BLANK_END_FORMULA
1568 (device_timing.hor_blank_start,
1569 device_timing.hor_blank_end);
1570 viafb_load_reg_num =
1571 iga1_crtc_reg.hor_blank_end.reg_num;
1572 reg = iga1_crtc_reg.hor_blank_end.reg;
1573 break;
1574 case H_SYNC_START_INDEX:
1575 reg_value =
1576 IGA1_HOR_SYNC_START_FORMULA
1577 (device_timing.hor_sync_start);
1578 viafb_load_reg_num =
1579 iga1_crtc_reg.hor_sync_start.reg_num;
1580 reg = iga1_crtc_reg.hor_sync_start.reg;
1581 break;
1582 case H_SYNC_END_INDEX:
1583 reg_value =
1584 IGA1_HOR_SYNC_END_FORMULA
1585 (device_timing.hor_sync_start,
1586 device_timing.hor_sync_end);
1587 viafb_load_reg_num =
1588 iga1_crtc_reg.hor_sync_end.reg_num;
1589 reg = iga1_crtc_reg.hor_sync_end.reg;
1590 break;
1591 case V_TOTAL_INDEX:
1592 reg_value =
1593 IGA1_VER_TOTAL_FORMULA(device_timing.
1594 ver_total);
1595 viafb_load_reg_num =
1596 iga1_crtc_reg.ver_total.reg_num;
1597 reg = iga1_crtc_reg.ver_total.reg;
1598 break;
1599 case V_ADDR_INDEX:
1600 reg_value =
1601 IGA1_VER_ADDR_FORMULA(device_timing.
1602 ver_addr);
1603 viafb_load_reg_num =
1604 iga1_crtc_reg.ver_addr.reg_num;
1605 reg = iga1_crtc_reg.ver_addr.reg;
1606 break;
1607 case V_BLANK_START_INDEX:
1608 reg_value =
1609 IGA1_VER_BLANK_START_FORMULA
1610 (device_timing.ver_blank_start);
1611 viafb_load_reg_num =
1612 iga1_crtc_reg.ver_blank_start.reg_num;
1613 reg = iga1_crtc_reg.ver_blank_start.reg;
1614 break;
1615 case V_BLANK_END_INDEX:
1616 reg_value =
1617 IGA1_VER_BLANK_END_FORMULA
1618 (device_timing.ver_blank_start,
1619 device_timing.ver_blank_end);
1620 viafb_load_reg_num =
1621 iga1_crtc_reg.ver_blank_end.reg_num;
1622 reg = iga1_crtc_reg.ver_blank_end.reg;
1623 break;
1624 case V_SYNC_START_INDEX:
1625 reg_value =
1626 IGA1_VER_SYNC_START_FORMULA
1627 (device_timing.ver_sync_start);
1628 viafb_load_reg_num =
1629 iga1_crtc_reg.ver_sync_start.reg_num;
1630 reg = iga1_crtc_reg.ver_sync_start.reg;
1631 break;
1632 case V_SYNC_END_INDEX:
1633 reg_value =
1634 IGA1_VER_SYNC_END_FORMULA
1635 (device_timing.ver_sync_start,
1636 device_timing.ver_sync_end);
1637 viafb_load_reg_num =
1638 iga1_crtc_reg.ver_sync_end.reg_num;
1639 reg = iga1_crtc_reg.ver_sync_end.reg;
1640 break;
1641
1642 }
1643 }
1644
1645 if (set_iga == IGA2) {
1646 switch (i) {
1647 case H_TOTAL_INDEX:
1648 reg_value =
1649 IGA2_HOR_TOTAL_FORMULA(device_timing.
1650 hor_total);
1651 viafb_load_reg_num =
1652 iga2_crtc_reg.hor_total.reg_num;
1653 reg = iga2_crtc_reg.hor_total.reg;
1654 break;
1655 case H_ADDR_INDEX:
1656 reg_value =
1657 IGA2_HOR_ADDR_FORMULA(device_timing.
1658 hor_addr);
1659 viafb_load_reg_num =
1660 iga2_crtc_reg.hor_addr.reg_num;
1661 reg = iga2_crtc_reg.hor_addr.reg;
1662 break;
1663 case H_BLANK_START_INDEX:
1664 reg_value =
1665 IGA2_HOR_BLANK_START_FORMULA
1666 (device_timing.hor_blank_start);
1667 viafb_load_reg_num =
1668 iga2_crtc_reg.hor_blank_start.reg_num;
1669 reg = iga2_crtc_reg.hor_blank_start.reg;
1670 break;
1671 case H_BLANK_END_INDEX:
1672 reg_value =
1673 IGA2_HOR_BLANK_END_FORMULA
1674 (device_timing.hor_blank_start,
1675 device_timing.hor_blank_end);
1676 viafb_load_reg_num =
1677 iga2_crtc_reg.hor_blank_end.reg_num;
1678 reg = iga2_crtc_reg.hor_blank_end.reg;
1679 break;
1680 case H_SYNC_START_INDEX:
1681 reg_value =
1682 IGA2_HOR_SYNC_START_FORMULA
1683 (device_timing.hor_sync_start);
1684 if (UNICHROME_CN700 <=
1685 viaparinfo->chip_info->gfx_chip_name)
1686 viafb_load_reg_num =
1687 iga2_crtc_reg.hor_sync_start.
1688 reg_num;
1689 else
1690 viafb_load_reg_num = 3;
1691 reg = iga2_crtc_reg.hor_sync_start.reg;
1692 break;
1693 case H_SYNC_END_INDEX:
1694 reg_value =
1695 IGA2_HOR_SYNC_END_FORMULA
1696 (device_timing.hor_sync_start,
1697 device_timing.hor_sync_end);
1698 viafb_load_reg_num =
1699 iga2_crtc_reg.hor_sync_end.reg_num;
1700 reg = iga2_crtc_reg.hor_sync_end.reg;
1701 break;
1702 case V_TOTAL_INDEX:
1703 reg_value =
1704 IGA2_VER_TOTAL_FORMULA(device_timing.
1705 ver_total);
1706 viafb_load_reg_num =
1707 iga2_crtc_reg.ver_total.reg_num;
1708 reg = iga2_crtc_reg.ver_total.reg;
1709 break;
1710 case V_ADDR_INDEX:
1711 reg_value =
1712 IGA2_VER_ADDR_FORMULA(device_timing.
1713 ver_addr);
1714 viafb_load_reg_num =
1715 iga2_crtc_reg.ver_addr.reg_num;
1716 reg = iga2_crtc_reg.ver_addr.reg;
1717 break;
1718 case V_BLANK_START_INDEX:
1719 reg_value =
1720 IGA2_VER_BLANK_START_FORMULA
1721 (device_timing.ver_blank_start);
1722 viafb_load_reg_num =
1723 iga2_crtc_reg.ver_blank_start.reg_num;
1724 reg = iga2_crtc_reg.ver_blank_start.reg;
1725 break;
1726 case V_BLANK_END_INDEX:
1727 reg_value =
1728 IGA2_VER_BLANK_END_FORMULA
1729 (device_timing.ver_blank_start,
1730 device_timing.ver_blank_end);
1731 viafb_load_reg_num =
1732 iga2_crtc_reg.ver_blank_end.reg_num;
1733 reg = iga2_crtc_reg.ver_blank_end.reg;
1734 break;
1735 case V_SYNC_START_INDEX:
1736 reg_value =
1737 IGA2_VER_SYNC_START_FORMULA
1738 (device_timing.ver_sync_start);
1739 viafb_load_reg_num =
1740 iga2_crtc_reg.ver_sync_start.reg_num;
1741 reg = iga2_crtc_reg.ver_sync_start.reg;
1742 break;
1743 case V_SYNC_END_INDEX:
1744 reg_value =
1745 IGA2_VER_SYNC_END_FORMULA
1746 (device_timing.ver_sync_start,
1747 device_timing.ver_sync_end);
1748 viafb_load_reg_num =
1749 iga2_crtc_reg.ver_sync_end.reg_num;
1750 reg = iga2_crtc_reg.ver_sync_end.reg;
1751 break;
1752
1753 }
1754 }
1755 viafb_load_reg(reg_value, viafb_load_reg_num, reg, VIACR);
1756 }
1757
1758 viafb_lock_crt();
1759}
1760
1761void viafb_set_color_depth(int bpp_byte, int set_iga)
1762{
1763 if (set_iga == IGA1) {
1764 switch (bpp_byte) {
1765 case MODE_8BPP:
1766 viafb_write_reg_mask(SR15, VIASR, 0x22, 0x7E);
1767 break;
1768 case MODE_16BPP:
1769 viafb_write_reg_mask(SR15, VIASR, 0xB6, 0xFE);
1770 break;
1771 case MODE_32BPP:
1772 viafb_write_reg_mask(SR15, VIASR, 0xAE, 0xFE);
1773 break;
1774 }
1775 } else {
1776 switch (bpp_byte) {
1777 case MODE_8BPP:
1778 viafb_write_reg_mask(CR67, VIACR, 0x00, BIT6 + BIT7);
1779 break;
1780 case MODE_16BPP:
1781 viafb_write_reg_mask(CR67, VIACR, 0x40, BIT6 + BIT7);
1782 break;
1783 case MODE_32BPP:
1784 viafb_write_reg_mask(CR67, VIACR, 0xC0, BIT6 + BIT7);
1785 break;
1786 }
1787 }
1788}
1789
1790void viafb_fill_crtc_timing(struct crt_mode_table *crt_table,
1791 int mode_index, int bpp_byte, int set_iga)
1792{
1793 struct VideoModeTable *video_mode;
1794 struct display_timing crt_reg;
1795 int i;
1796 int index = 0;
1797 int h_addr, v_addr;
1798 u32 pll_D_N;
1799
1800 video_mode = &CLE266Modes[search_mode_setting(mode_index)];
1801
1802 for (i = 0; i < video_mode->mode_array; i++) {
1803 index = i;
1804
1805 if (crt_table[i].refresh_rate == viaparinfo->
1806 crt_setting_info->refresh_rate)
1807 break;
1808 }
1809
1810 crt_reg = crt_table[index].crtc;
1811
1812 /* Mode 640x480 has border, but LCD/DFP didn't have border. */
1813 /* So we would delete border. */
1814 if ((viafb_LCD_ON | viafb_DVI_ON) && (mode_index == VIA_RES_640X480)
1815 && (viaparinfo->crt_setting_info->refresh_rate == 60)) {
1816 /* The border is 8 pixels. */
1817 crt_reg.hor_blank_start = crt_reg.hor_blank_start - 8;
1818
1819 /* Blanking time should add left and right borders. */
1820 crt_reg.hor_blank_end = crt_reg.hor_blank_end + 16;
1821 }
1822
1823 h_addr = crt_reg.hor_addr;
1824 v_addr = crt_reg.ver_addr;
1825
1826 /* update polarity for CRT timing */
1827 if (crt_table[index].h_sync_polarity == NEGATIVE) {
1828 if (crt_table[index].v_sync_polarity == NEGATIVE)
1829 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) |
1830 (BIT6 + BIT7), VIAWMisc);
1831 else
1832 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT6),
1833 VIAWMisc);
1834 } else {
1835 if (crt_table[index].v_sync_polarity == NEGATIVE)
1836 outb((inb(VIARMisc) & (~(BIT6 + BIT7))) | (BIT7),
1837 VIAWMisc);
1838 else
1839 outb((inb(VIARMisc) & (~(BIT6 + BIT7))), VIAWMisc);
1840 }
1841
1842 if (set_iga == IGA1) {
1843 viafb_unlock_crt();
1844 viafb_write_reg(CR09, VIACR, 0x00); /*initial CR09=0 */
1845 viafb_write_reg_mask(CR11, VIACR, 0x00, BIT4 + BIT5 + BIT6);
1846 viafb_write_reg_mask(CR17, VIACR, 0x00, BIT7);
1847 }
1848
1849 switch (set_iga) {
1850 case IGA1:
1851 viafb_load_crtc_timing(crt_reg, IGA1);
1852 break;
1853 case IGA2:
1854 viafb_load_crtc_timing(crt_reg, IGA2);
1855 break;
1856 }
1857
1858 load_fix_bit_crtc_reg();
1859 viafb_lock_crt();
1860 viafb_write_reg_mask(CR17, VIACR, 0x80, BIT7);
d61e0bf3
JC		 1861 viafb_load_fetch_count_reg(h_addr, bpp_byte, set_iga);
1862
1863 /* load FIFO */
1864 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
1865 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
1866 viafb_load_FIFO_reg(set_iga, h_addr, v_addr);
1867
1868 /* load SR Register About Memory and Color part */
1869 viafb_set_color_depth(bpp_byte, set_iga);
1870
1871 pll_D_N = viafb_get_clk_value(crt_table[index].clk);
1872 DEBUG_MSG(KERN_INFO "PLL=%x", pll_D_N);
1873 viafb_set_vclock(pll_D_N, set_iga);
1874
1875}
1876
1877void viafb_init_chip_info(void)
1878{
1879 init_gfx_chip_info();
1880 init_tmds_chip_info();
1881 init_lvds_chip_info();
1882
1883 viaparinfo->crt_setting_info->iga_path = IGA1;
1884 viaparinfo->crt_setting_info->refresh_rate = viafb_refresh;
1885
1886 /*Set IGA path for each device */
1887 viafb_set_iga_path();
1888
1889 viaparinfo->lvds_setting_info->display_method = viafb_lcd_dsp_method;
1890 viaparinfo->lvds_setting_info->get_lcd_size_method =
1891 GET_LCD_SIZE_BY_USER_SETTING;
1892 viaparinfo->lvds_setting_info->lcd_mode = viafb_lcd_mode;
1893 viaparinfo->lvds_setting_info2->display_method =
1894 viaparinfo->lvds_setting_info->display_method;
1895 viaparinfo->lvds_setting_info2->lcd_mode =
1896 viaparinfo->lvds_setting_info->lcd_mode;
1897}
1898
1899void viafb_update_device_setting(int hres, int vres,
1900 int bpp, int vmode_refresh, int flag)
1901{
1902 if (flag == 0) {
1903 viaparinfo->crt_setting_info->h_active = hres;
1904 viaparinfo->crt_setting_info->v_active = vres;
1905 viaparinfo->crt_setting_info->bpp = bpp;
1906 viaparinfo->crt_setting_info->refresh_rate =
1907 vmode_refresh;
1908
1909 viaparinfo->tmds_setting_info->h_active = hres;
1910 viaparinfo->tmds_setting_info->v_active = vres;
1911 viaparinfo->tmds_setting_info->bpp = bpp;
1912 viaparinfo->tmds_setting_info->refresh_rate =
1913 vmode_refresh;
1914
1915 viaparinfo->lvds_setting_info->h_active = hres;
1916 viaparinfo->lvds_setting_info->v_active = vres;
1917 viaparinfo->lvds_setting_info->bpp = bpp;
1918 viaparinfo->lvds_setting_info->refresh_rate =
1919 vmode_refresh;
1920 viaparinfo->lvds_setting_info2->h_active = hres;
1921 viaparinfo->lvds_setting_info2->v_active = vres;
1922 viaparinfo->lvds_setting_info2->bpp = bpp;
1923 viaparinfo->lvds_setting_info2->refresh_rate =
1924 vmode_refresh;
1925 } else {
1926
1927 if (viaparinfo->tmds_setting_info->iga_path == IGA2) {
1928 viaparinfo->tmds_setting_info->h_active = hres;
1929 viaparinfo->tmds_setting_info->v_active = vres;
1930 viaparinfo->tmds_setting_info->bpp = bpp;
1931 viaparinfo->tmds_setting_info->refresh_rate =
1932 vmode_refresh;
1933 }
1934
1935 if (viaparinfo->lvds_setting_info->iga_path == IGA2) {
1936 viaparinfo->lvds_setting_info->h_active = hres;
1937 viaparinfo->lvds_setting_info->v_active = vres;
1938 viaparinfo->lvds_setting_info->bpp = bpp;
1939 viaparinfo->lvds_setting_info->refresh_rate =
1940 vmode_refresh;
1941 }
1942 if (IGA2 == viaparinfo->lvds_setting_info2->iga_path) {
1943 viaparinfo->lvds_setting_info2->h_active = hres;
1944 viaparinfo->lvds_setting_info2->v_active = vres;
1945 viaparinfo->lvds_setting_info2->bpp = bpp;
1946 viaparinfo->lvds_setting_info2->refresh_rate =
1947 vmode_refresh;
1948 }
1949 }
1950}
1951
1952static void init_gfx_chip_info(void)
1953{
1954 struct pci_dev *pdev = NULL;
1955 u32 i;
1956 u8 tmp;
1957
1958 /* Indentify GFX Chip Name */
1959 for (i = 0; pciidlist[i].vendor != 0; i++) {
1960 pdev = pci_get_device(pciidlist[i].vendor,
1961 pciidlist[i].device, 0);
1962 if (pdev)
1963 break;
1964 }
1965
1966 if (!pciidlist[i].vendor)
1967 return ;
1968
1969 viaparinfo->chip_info->gfx_chip_name = pciidlist[i].chip_index;
1970
1971 /* Check revision of CLE266 Chip */
1972 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
1973 /* CR4F only define in CLE266.CX chip */
1974 tmp = viafb_read_reg(VIACR, CR4F);
1975 viafb_write_reg(CR4F, VIACR, 0x55);
1976 if (viafb_read_reg(VIACR, CR4F) != 0x55)
1977 viaparinfo->chip_info->gfx_chip_revision =
1978 CLE266_REVISION_AX;
1979 else
1980 viaparinfo->chip_info->gfx_chip_revision =
1981 CLE266_REVISION_CX;
1982 /* restore orignal CR4F value */
1983 viafb_write_reg(CR4F, VIACR, tmp);
1984 }
1985
1986 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
1987 tmp = viafb_read_reg(VIASR, SR43);
1988 DEBUG_MSG(KERN_INFO "SR43:%X\n", tmp);
1989 if (tmp & 0x02) {
1990 viaparinfo->chip_info->gfx_chip_revision =
1991 CX700_REVISION_700M2;
1992 } else if (tmp & 0x40) {
1993 viaparinfo->chip_info->gfx_chip_revision =
1994 CX700_REVISION_700M;
1995 } else {
1996 viaparinfo->chip_info->gfx_chip_revision =
1997 CX700_REVISION_700;
1998 }
1999 }
2000
2001 pci_dev_put(pdev);
2002}
2003
2004static void init_tmds_chip_info(void)
2005{
2006 viafb_tmds_trasmitter_identify();
2007
2008 if (INTERFACE_NONE == viaparinfo->chip_info->tmds_chip_info.
2009 output_interface) {
2010 switch (viaparinfo->chip_info->gfx_chip_name) {
2011 case UNICHROME_CX700:
2012 {
2013 /* we should check support by hardware layout.*/
2014 if ((viafb_display_hardware_layout ==
2015 HW_LAYOUT_DVI_ONLY)
2016 || (viafb_display_hardware_layout ==
2017 HW_LAYOUT_LCD_DVI)) {
2018 viaparinfo->chip_info->tmds_chip_info.
2019 output_interface = INTERFACE_TMDS;
2020 } else {
2021 viaparinfo->chip_info->tmds_chip_info.
2022 output_interface =
2023 INTERFACE_NONE;
2024 }
2025 break;
2026 }
2027 case UNICHROME_K8M890:
2028 case UNICHROME_P4M900:
2029 case UNICHROME_P4M890:
2030 /* TMDS on PCIE, we set DFPLOW as default. */
2031 viaparinfo->chip_info->tmds_chip_info.output_interface =
2032 INTERFACE_DFP_LOW;
2033 break;
2034 default:
2035 {
2036 /* set DVP1 default for DVI */
2037 viaparinfo->chip_info->tmds_chip_info
2038 .output_interface = INTERFACE_DVP1;
2039 }
2040 }
2041 }
2042
2043 DEBUG_MSG(KERN_INFO "TMDS Chip = %d\n",
2044 viaparinfo->chip_info->tmds_chip_info.tmds_chip_name);
2045 viaparinfo->tmds_setting_info->get_dvi_size_method =
2046 GET_DVI_SIZE_BY_VGA_BIOS;
2047 viafb_init_dvi_size();
2048}
2049
2050static void init_lvds_chip_info(void)
2051{
2052 if (viafb_lcd_panel_id > LCD_PANEL_ID_MAXIMUM)
2053 viaparinfo->lvds_setting_info->get_lcd_size_method =
2054 GET_LCD_SIZE_BY_VGA_BIOS;
2055 else
2056 viaparinfo->lvds_setting_info->get_lcd_size_method =
2057 GET_LCD_SIZE_BY_USER_SETTING;
2058
2059 viafb_lvds_trasmitter_identify();
2060 viafb_init_lcd_size();
2061 viafb_init_lvds_output_interface(&viaparinfo->chip_info->lvds_chip_info,
2062 viaparinfo->lvds_setting_info);
2063 if (viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name) {
2064 viafb_init_lvds_output_interface(&viaparinfo->chip_info->
2065 lvds_chip_info2, viaparinfo->lvds_setting_info2);
2066 }
2067 /*If CX700,two singel LCD, we need to reassign
2068 LCD interface to different LVDS port */
2069 if ((UNICHROME_CX700 == viaparinfo->chip_info->gfx_chip_name)
2070 && (HW_LAYOUT_LCD1_LCD2 == viafb_display_hardware_layout)) {
2071 if ((INTEGRATED_LVDS == viaparinfo->chip_info->lvds_chip_info.
2072 lvds_chip_name) && (INTEGRATED_LVDS ==
2073 viaparinfo->chip_info->
2074 lvds_chip_info2.lvds_chip_name)) {
2075 viaparinfo->chip_info->lvds_chip_info.output_interface =
2076 INTERFACE_LVDS0;
2077 viaparinfo->chip_info->lvds_chip_info2.
2078 output_interface =
2079 INTERFACE_LVDS1;
2080 }
2081 }
2082
2083 DEBUG_MSG(KERN_INFO "LVDS Chip = %d\n",
2084 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
2085 DEBUG_MSG(KERN_INFO "LVDS1 output_interface = %d\n",
2086 viaparinfo->chip_info->lvds_chip_info.output_interface);
2087 DEBUG_MSG(KERN_INFO "LVDS2 output_interface = %d\n",
2088 viaparinfo->chip_info->lvds_chip_info.output_interface);
2089}
2090
2091void viafb_init_dac(int set_iga)
2092{
2093 int i;
2094 u8 tmp;
2095
2096 if (set_iga == IGA1) {
2097 /* access Primary Display's LUT */
2098 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2099 /* turn off LCK */
2100 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
2101 for (i = 0; i < 256; i++) {
2102 write_dac_reg(i, palLUT_table[i].red,
2103 palLUT_table[i].green,
2104 palLUT_table[i].blue);
2105 }
2106 /* turn on LCK */
2107 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2108 } else {
2109 tmp = viafb_read_reg(VIACR, CR6A);
2110 /* access Secondary Display's LUT */
2111 viafb_write_reg_mask(CR6A, VIACR, 0x40, BIT6);
2112 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
2113 for (i = 0; i < 256; i++) {
2114 write_dac_reg(i, palLUT_table[i].red,
2115 palLUT_table[i].green,
2116 palLUT_table[i].blue);
2117 }
2118 /* set IGA1 DAC for default */
2119 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0);
2120 viafb_write_reg(CR6A, VIACR, tmp);
2121 }
2122}
2123
2124static void device_screen_off(void)
2125{
2126 /* turn off CRT screen (IGA1) */
2127 viafb_write_reg_mask(SR01, VIASR, 0x20, BIT5);
2128}
2129
2130static void device_screen_on(void)
2131{
2132 /* turn on CRT screen (IGA1) */
2133 viafb_write_reg_mask(SR01, VIASR, 0x00, BIT5);
2134}
2135
2136static void set_display_channel(void)
2137{
2138 /*If viafb_LCD2_ON, on cx700, internal lvds's information
2139 is keeped on lvds_setting_info2 */
2140 if (viafb_LCD2_ON &&
2141 viaparinfo->lvds_setting_info2->device_lcd_dualedge) {
2142 /* For dual channel LCD: */
2143 /* Set to Dual LVDS channel. */
2144 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2145 } else if (viafb_LCD_ON && viafb_DVI_ON) {
2146 /* For LCD+DFP: */
2147 /* Set to LVDS1 + TMDS channel. */
2148 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
2149 } else if (viafb_DVI_ON) {
2150 /* Set to single TMDS channel. */
2151 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
2152 } else if (viafb_LCD_ON) {
2153 if (viaparinfo->lvds_setting_info->device_lcd_dualedge) {
2154 /* For dual channel LCD: */
2155 /* Set to Dual LVDS channel. */
2156 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
2157 } else {
2158 /* Set to LVDS0 + LVDS1 channel. */
2159 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2160 }
2161 }
2162}
2163
2164int viafb_setmode(int vmode_index, int hor_res, int ver_res, int video_bpp,
2165 int vmode_index1, int hor_res1, int ver_res1, int video_bpp1)
2166{
2167 int i, j;
2168 int port;
2169 u8 value, index, mask;
2170 struct VideoModeTable *vmode_tbl;
2171 struct crt_mode_table *crt_timing;
2172 struct VideoModeTable *vmode_tbl1 = NULL;
2173 struct crt_mode_table *crt_timing1 = NULL;
2174
2175 DEBUG_MSG(KERN_INFO "Set Mode!!\n");
2176 DEBUG_MSG(KERN_INFO
2177 "vmode_index=%d hor_res=%d ver_res=%d video_bpp=%d\n",
2178 vmode_index, hor_res, ver_res, video_bpp);
2179
2180 device_screen_off();
2181 vmode_tbl = &CLE266Modes[search_mode_setting(vmode_index)];
2182 crt_timing = vmode_tbl->crtc;
2183
2184 if (viafb_SAMM_ON == 1) {
2185 vmode_tbl1 = &CLE266Modes[search_mode_setting(vmode_index1)];
2186 crt_timing1 = vmode_tbl1->crtc;
2187 }
2188
2189 inb(VIAStatus);
2190 outb(0x00, VIAAR);
2191
2192 /* Write Common Setting for Video Mode */
2193 switch (viaparinfo->chip_info->gfx_chip_name) {
2194 case UNICHROME_CLE266:
2195 viafb_write_regx(CLE266_ModeXregs, NUM_TOTAL_CLE266_ModeXregs);
2196 break;
2197
2198 case UNICHROME_K400:
2199 viafb_write_regx(KM400_ModeXregs, NUM_TOTAL_KM400_ModeXregs);
2200 break;
2201
2202 case UNICHROME_K800:
2203 case UNICHROME_PM800:
2204 viafb_write_regx(CN400_ModeXregs, NUM_TOTAL_CN400_ModeXregs);
2205 break;
2206
2207 case UNICHROME_CN700:
2208 case UNICHROME_K8M890:
2209 case UNICHROME_P4M890:
2210 case UNICHROME_P4M900:
2211 viafb_write_regx(CN700_ModeXregs, NUM_TOTAL_CN700_ModeXregs);
2212 break;
2213
2214 case UNICHROME_CX700:
d61e0bf3 2215 case UNICHROME_VX800:
0e3ca33a 2216 viafb_write_regx(CX700_ModeXregs, NUM_TOTAL_CX700_ModeXregs);
d61e0bf3
JC		 2217 break;
2218 }
2219
2220 device_off();
2221
2222 /* Fill VPIT Parameters */
2223 /* Write Misc Register */
2224 outb(VPIT.Misc, VIAWMisc);
2225
2226 /* Write Sequencer */
2227 for (i = 1; i <= StdSR; i++) {
2228 outb(i, VIASR);
2229 outb(VPIT.SR[i - 1], VIASR + 1);
2230 }
2231
09cf1180
FTS		 2232 viafb_set_primary_address(0);
2233 viafb_set_secondary_address(viafb_SAMM_ON ? viafb_second_offset : 0);
d61e0bf3
JC		 2234 viafb_set_iga_path();
2235
2236 /* Write CRTC */
2237 viafb_fill_crtc_timing(crt_timing, vmode_index, video_bpp / 8, IGA1);
2238
2239 /* Write Graphic Controller */
2240 for (i = 0; i < StdGR; i++) {
2241 outb(i, VIAGR);
2242 outb(VPIT.GR[i], VIAGR + 1);
2243 }
2244
2245 /* Write Attribute Controller */
2246 for (i = 0; i < StdAR; i++) {
2247 inb(VIAStatus);
2248 outb(i, VIAAR);
2249 outb(VPIT.AR[i], VIAAR);
2250 }
2251
2252 inb(VIAStatus);
2253 outb(0x20, VIAAR);
2254
2255 /* Update Patch Register */
2256
2257 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2258 || (viaparinfo->chip_info->gfx_chip_name == UNICHROME_K400)) {
2259 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2260 if (res_patch_table[i].mode_index == vmode_index) {
2261 for (j = 0;
2262 j < res_patch_table[i].table_length; j++) {
2263 index =
2264 res_patch_table[i].
2265 io_reg_table[j].index;
2266 port =
2267 res_patch_table[i].
2268 io_reg_table[j].port;
2269 value =
2270 res_patch_table[i].
2271 io_reg_table[j].value;
2272 mask =
2273 res_patch_table[i].
2274 io_reg_table[j].mask;
2275 viafb_write_reg_mask(index, port, value,
2276 mask);
2277 }
2278 }
2279 }
2280 }
2281
2282 if (viafb_SAMM_ON == 1) {
2283 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266)
2284 || (viaparinfo->chip_info->gfx_chip_name ==
2285 UNICHROME_K400)) {
2286 for (i = 0; i < NUM_TOTAL_PATCH_MODE; i++) {
2287 if (res_patch_table[i].mode_index ==
2288 vmode_index1) {
2289 for (j = 0;
2290 j <
2291 res_patch_table[i].
2292 table_length; j++) {
2293 index =
2294 res_patch_table[i].
2295 io_reg_table[j].index;
2296 port =
2297 res_patch_table[i].
2298 io_reg_table[j].port;
2299 value =
2300 res_patch_table[i].
2301 io_reg_table[j].value;
2302 mask =
2303 res_patch_table[i].
2304 io_reg_table[j].mask;
2305 viafb_write_reg_mask(index,
2306 port, value, mask);
2307 }
2308 }
2309 }
2310 }
2311 }
2312
2d6e8851
FTS		 2313 viafb_set_primary_pitch(viafbinfo->fix.line_length);
2314 viafb_set_secondary_pitch(viafb_dual_fb ? viafbinfo1->fix.line_length
2315 : viafbinfo->fix.line_length);
d61e0bf3
JC		 2316 /* Update Refresh Rate Setting */
2317
2318 /* Clear On Screen */
2319
2320 /* CRT set mode */
2321 if (viafb_CRT_ON) {
2322 if (viafb_SAMM_ON && (viaparinfo->crt_setting_info->iga_path ==
2323 IGA2)) {
2324 viafb_fill_crtc_timing(crt_timing1, vmode_index1,
2325 video_bpp1 / 8,
2326 viaparinfo->crt_setting_info->iga_path);
2327 } else {
2328 viafb_fill_crtc_timing(crt_timing, vmode_index,
2329 video_bpp / 8,
2330 viaparinfo->crt_setting_info->iga_path);
2331 }
2332
2333 set_crt_output_path(viaparinfo->crt_setting_info->iga_path);
2334
2335 /* Patch if set_hres is not 8 alignment (1366) to viafb_setmode
2336 to 8 alignment (1368),there is several pixels (2 pixels)
2337 on right side of screen. */
2338 if (hor_res % 8) {
2339 viafb_unlock_crt();
2340 viafb_write_reg(CR02, VIACR,
2341 viafb_read_reg(VIACR, CR02) - 1);
2342 viafb_lock_crt();
2343 }
2344 }
2345
2346 if (viafb_DVI_ON) {
2347 if (viafb_SAMM_ON &&
2348 (viaparinfo->tmds_setting_info->iga_path == IGA2)) {
2349 viafb_dvi_set_mode(viafb_get_mode_index
2350 (viaparinfo->tmds_setting_info->h_active,
2351 viaparinfo->tmds_setting_info->
52159444 2352 v_active),
d61e0bf3
JC		 2353 video_bpp1, viaparinfo->
2354 tmds_setting_info->iga_path);
2355 } else {
2356 viafb_dvi_set_mode(viafb_get_mode_index
2357 (viaparinfo->tmds_setting_info->h_active,
2358 viaparinfo->
52159444 2359 tmds_setting_info->v_active),
d61e0bf3
JC		 2360 video_bpp, viaparinfo->
2361 tmds_setting_info->iga_path);
2362 }
2363 }
2364
2365 if (viafb_LCD_ON) {
2366 if (viafb_SAMM_ON &&
2367 (viaparinfo->lvds_setting_info->iga_path == IGA2)) {
2368 viaparinfo->lvds_setting_info->bpp = video_bpp1;
2369 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2370 lvds_setting_info,
2371 &viaparinfo->chip_info->lvds_chip_info);
2372 } else {
2373 /* IGA1 doesn't have LCD scaling, so set it center. */
2374 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
2375 viaparinfo->lvds_setting_info->display_method =
2376 LCD_CENTERING;
2377 }
2378 viaparinfo->lvds_setting_info->bpp = video_bpp;
2379 viafb_lcd_set_mode(crt_timing, viaparinfo->
2380 lvds_setting_info,
2381 &viaparinfo->chip_info->lvds_chip_info);
2382 }
2383 }
2384 if (viafb_LCD2_ON) {
2385 if (viafb_SAMM_ON &&
2386 (viaparinfo->lvds_setting_info2->iga_path == IGA2)) {
2387 viaparinfo->lvds_setting_info2->bpp = video_bpp1;
2388 viafb_lcd_set_mode(crt_timing1, viaparinfo->
2389 lvds_setting_info2,
2390 &viaparinfo->chip_info->lvds_chip_info2);
2391 } else {
2392 /* IGA1 doesn't have LCD scaling, so set it center. */
2393 if (viaparinfo->lvds_setting_info2->iga_path == IGA1) {
2394 viaparinfo->lvds_setting_info2->display_method =
2395 LCD_CENTERING;
2396 }
2397 viaparinfo->lvds_setting_info2->bpp = video_bpp;
2398 viafb_lcd_set_mode(crt_timing, viaparinfo->
2399 lvds_setting_info2,
2400 &viaparinfo->chip_info->lvds_chip_info2);
2401 }
2402 }
2403
2404 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
2405 && (viafb_LCD_ON || viafb_DVI_ON))
2406 set_display_channel();
2407
2408 /* If set mode normally, save resolution information for hot-plug . */
2409 if (!viafb_hotplug) {
2410 viafb_hotplug_Xres = hor_res;
2411 viafb_hotplug_Yres = ver_res;
2412 viafb_hotplug_bpp = video_bpp;
2413 viafb_hotplug_refresh = viafb_refresh;
2414
2415 if (viafb_DVI_ON)
2416 viafb_DeviceStatus = DVI_Device;
2417 else
2418 viafb_DeviceStatus = CRT_Device;
2419 }
2420 device_on();
2421
2422 if (viafb_SAMM_ON == 1)
2423 viafb_write_reg_mask(CR6A, VIACR, 0xC0, BIT6 + BIT7);
2424
2425 device_screen_on();
2426 return 1;
2427}
2428
2429int viafb_get_pixclock(int hres, int vres, int vmode_refresh)
2430{
2431 int i;
2432
2433 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2434 if ((hres == res_map_refresh_tbl[i].hres)
2435 && (vres == res_map_refresh_tbl[i].vres)
2436 && (vmode_refresh == res_map_refresh_tbl[i].vmode_refresh))
2437 return res_map_refresh_tbl[i].pixclock;
2438 }
2439 return RES_640X480_60HZ_PIXCLOCK;
2440
2441}
2442
2443int viafb_get_refresh(int hres, int vres, u32 long_refresh)
2444{
2445#define REFRESH_TOLERANCE 3
2446 int i, nearest = -1, diff = REFRESH_TOLERANCE;
2447 for (i = 0; i < NUM_TOTAL_RES_MAP_REFRESH; i++) {
2448 if ((hres == res_map_refresh_tbl[i].hres)
2449 && (vres == res_map_refresh_tbl[i].vres)
2450 && (diff > (abs(long_refresh -
2451 res_map_refresh_tbl[i].vmode_refresh)))) {
2452 diff = abs(long_refresh - res_map_refresh_tbl[i].
2453 vmode_refresh);
2454 nearest = i;
2455 }
2456 }
2457#undef REFRESH_TOLERANCE
2458 if (nearest > 0)
2459 return res_map_refresh_tbl[nearest].vmode_refresh;
2460 return 60;
2461}
2462
2463static void device_off(void)
2464{
2465 viafb_crt_disable();
2466 viafb_dvi_disable();
2467 viafb_lcd_disable();
2468}
2469
2470static void device_on(void)
2471{
2472 if (viafb_CRT_ON == 1)
2473 viafb_crt_enable();
2474 if (viafb_DVI_ON == 1)
2475 viafb_dvi_enable();
2476 if (viafb_LCD_ON == 1)
2477 viafb_lcd_enable();
2478}
2479
2480void viafb_crt_disable(void)
2481{
2482 viafb_write_reg_mask(CR36, VIACR, BIT5 + BIT4, BIT5 + BIT4);
2483}
2484
2485void viafb_crt_enable(void)
2486{
2487 viafb_write_reg_mask(CR36, VIACR, 0x0, BIT5 + BIT4);
2488}
2489
68fa9208 2490void viafb_get_mmio_info(unsigned long *mmio_base, u32 *mmio_len)
d61e0bf3
JC		 2491{
2492 struct pci_dev *pdev = NULL;
2493 u32 vendor, device;
2494 u32 i;
2495
2496 for (i = 0; pciidlist[i].vendor != 0; i++)
2497 if (viaparinfo->chip_info->gfx_chip_name ==
2498 pciidlist[i].chip_index)
2499 break;
2500
2501 if (!pciidlist[i].vendor)
2502 return ;
2503
2504 vendor = pciidlist[i].vendor;
2505 device = pciidlist[i].device;
2506
2507 pdev = pci_get_device(vendor, device, NULL);
2508
2509 if (!pdev) {
2510 *mmio_base = 0;
2511 *mmio_len = 0;
2512 return ;
2513 }
2514
2515 *mmio_base = pci_resource_start(pdev, 1);
2516 *mmio_len = pci_resource_len(pdev, 1);
2517
2518 pci_dev_put(pdev);
2519}
2520
2521static void enable_second_display_channel(void)
2522{
2523 /* to enable second display channel. */
2524 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2525 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2526 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2527}
2528
2529static void disable_second_display_channel(void)
2530{
2531 /* to disable second display channel. */
2532 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT6);
2533 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
2534 viafb_write_reg_mask(CR6A, VIACR, BIT6, BIT6);
2535}
2536
2537void viafb_get_fb_info(unsigned int *fb_base, unsigned int *fb_len)
2538{
2539 struct pci_dev *pdev = NULL;
2540 u32 vendor, device;
2541 u32 i;
2542
2543 for (i = 0; pciidlist[i].vendor != 0; i++)
2544 if (viaparinfo->chip_info->gfx_chip_name ==
2545 pciidlist[i].chip_index)
2546 break;
2547
2548 if (!pciidlist[i].vendor)
2549 return ;
2550
2551 vendor = pciidlist[i].vendor;
2552 device = pciidlist[i].device;
2553
2554 pdev = pci_get_device(vendor, device, NULL);
2555
2556 if (!pdev) {
2557 *fb_base = viafb_read_reg(VIASR, SR30) << 24;
2558 *fb_len = viafb_get_memsize();
2559 DEBUG_MSG(KERN_INFO "Get FB info from SR30!\n");
2560 DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
2561 DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
2562 return ;
2563 }
2564
2565 *fb_base = (unsigned int)pci_resource_start(pdev, 0);
2566 *fb_len = get_fb_size_from_pci();
2567 DEBUG_MSG(KERN_INFO "Get FB info from PCI system!\n");
2568 DEBUG_MSG(KERN_INFO "fb_base = %08x\n", *fb_base);
2569 DEBUG_MSG(KERN_INFO "fb_len = %08x\n", *fb_len);
2570
2571 pci_dev_put(pdev);
2572}
2573
2574static int get_fb_size_from_pci(void)
2575{
2576 unsigned long configid, deviceid, FBSize = 0;
2577 int VideoMemSize;
2578 int DeviceFound = false;
2579
2580 for (configid = 0x80000000; configid < 0x80010800; configid += 0x100) {
2581 outl(configid, (unsigned long)0xCF8);
2582 deviceid = (inl((unsigned long)0xCFC) >> 16) & 0xffff;
2583
2584 switch (deviceid) {
2585 case CLE266:
2586 case KM400:
2587 outl(configid + 0xE0, (unsigned long)0xCF8);
2588 FBSize = inl((unsigned long)0xCFC);
2589 DeviceFound = true; /* Found device id */
2590 break;
2591
2592 case CN400_FUNCTION3:
2593 case CN700_FUNCTION3:
2594 case CX700_FUNCTION3:
2595 case KM800_FUNCTION3:
2596 case KM890_FUNCTION3:
2597 case P4M890_FUNCTION3:
2598 case P4M900_FUNCTION3:
2599 case VX800_FUNCTION3:
2600 /*case CN750_FUNCTION3: */
2601 outl(configid + 0xA0, (unsigned long)0xCF8);
2602 FBSize = inl((unsigned long)0xCFC);
2603 DeviceFound = true; /* Found device id */
2604 break;
2605
2606 default:
2607 break;
2608 }
2609
2610 if (DeviceFound)
2611 break;
2612 }
2613
2614 DEBUG_MSG(KERN_INFO "Device ID = %lx\n", deviceid);
2615
2616 FBSize = FBSize & 0x00007000;
2617 DEBUG_MSG(KERN_INFO "FB Size = %x\n", FBSize);
2618
2619 if (viaparinfo->chip_info->gfx_chip_name < UNICHROME_CX700) {
2620 switch (FBSize) {
2621 case 0x00004000:
2622 VideoMemSize = (16 << 20); /*16M */
2623 break;
2624
2625 case 0x00005000:
2626 VideoMemSize = (32 << 20); /*32M */
2627 break;
2628
2629 case 0x00006000:
2630 VideoMemSize = (64 << 20); /*64M */
2631 break;
2632
2633 default:
2634 VideoMemSize = (32 << 20); /*32M */
2635 break;
2636 }
2637 } else {
2638 switch (FBSize) {
2639 case 0x00001000:
2640 VideoMemSize = (8 << 20); /*8M */
2641 break;
2642
2643 case 0x00002000:
2644 VideoMemSize = (16 << 20); /*16M */
2645 break;
2646
2647 case 0x00003000:
2648 VideoMemSize = (32 << 20); /*32M */
2649 break;
2650
2651 case 0x00004000:
2652 VideoMemSize = (64 << 20); /*64M */
2653 break;
2654
2655 case 0x00005000:
2656 VideoMemSize = (128 << 20); /*128M */
2657 break;
2658
2659 case 0x00006000:
2660 VideoMemSize = (256 << 20); /*256M */
2661 break;
2662
2663 default:
2664 VideoMemSize = (32 << 20); /*32M */
2665 break;
2666 }
2667 }
2668
2669 return VideoMemSize;
2670}
2671
2672void viafb_set_dpa_gfx(int output_interface, struct GFX_DPA_SETTING\
2673 *p_gfx_dpa_setting)
2674{
2675 switch (output_interface) {
2676 case INTERFACE_DVP0:
2677 {
2678 /* DVP0 Clock Polarity and Adjust: */
2679 viafb_write_reg_mask(CR96, VIACR,
2680 p_gfx_dpa_setting->DVP0, 0x0F);
2681
2682 /* DVP0 Clock and Data Pads Driving: */
2683 viafb_write_reg_mask(SR1E, VIASR,
2684 p_gfx_dpa_setting->DVP0ClockDri_S, BIT2);
2685 viafb_write_reg_mask(SR2A, VIASR,
2686 p_gfx_dpa_setting->DVP0ClockDri_S1,
2687 BIT4);
2688 viafb_write_reg_mask(SR1B, VIASR,
2689 p_gfx_dpa_setting->DVP0DataDri_S, BIT1);
2690 viafb_write_reg_mask(SR2A, VIASR,
2691 p_gfx_dpa_setting->DVP0DataDri_S1, BIT5);
2692 break;
2693 }
2694
2695 case INTERFACE_DVP1:
2696 {
2697 /* DVP1 Clock Polarity and Adjust: */
2698 viafb_write_reg_mask(CR9B, VIACR,
2699 p_gfx_dpa_setting->DVP1, 0x0F);
2700
2701 /* DVP1 Clock and Data Pads Driving: */
2702 viafb_write_reg_mask(SR65, VIASR,
2703 p_gfx_dpa_setting->DVP1Driving, 0x0F);
2704 break;
2705 }
2706
2707 case INTERFACE_DFP_HIGH:
2708 {
2709 viafb_write_reg_mask(CR97, VIACR,
2710 p_gfx_dpa_setting->DFPHigh, 0x0F);
2711 break;
2712 }
2713
2714 case INTERFACE_DFP_LOW:
2715 {
2716 viafb_write_reg_mask(CR99, VIACR,
2717 p_gfx_dpa_setting->DFPLow, 0x0F);
2718 break;
2719 }
2720
2721 case INTERFACE_DFP:
2722 {
2723 viafb_write_reg_mask(CR97, VIACR,
2724 p_gfx_dpa_setting->DFPHigh, 0x0F);
2725 viafb_write_reg_mask(CR99, VIACR,
2726 p_gfx_dpa_setting->DFPLow, 0x0F);
2727 break;
2728 }
2729 }
2730}
2731
d61e0bf3
JC		 2732/*According var's xres, yres fill var's other timing information*/
2733void viafb_fill_var_timing_info(struct fb_var_screeninfo *var, int refresh,
2734 int mode_index)
2735{
2736 struct VideoModeTable *vmode_tbl = NULL;
2737 struct crt_mode_table *crt_timing = NULL;
2738 struct display_timing crt_reg;
2739 int i = 0, index = 0;
2740 vmode_tbl = &CLE266Modes[search_mode_setting(mode_index)];
2741 crt_timing = vmode_tbl->crtc;
2742 for (i = 0; i < vmode_tbl->mode_array; i++) {
2743 index = i;
2744 if (crt_timing[i].refresh_rate == refresh)
2745 break;
2746 }
2747
2748 crt_reg = crt_timing[index].crtc;
2749 switch (var->bits_per_pixel) {
2750 case 8:
2751 var->red.offset = 0;
2752 var->green.offset = 0;
2753 var->blue.offset = 0;
2754 var->red.length = 6;
2755 var->green.length = 6;
2756 var->blue.length = 6;
2757 break;
2758 case 16:
2759 var->red.offset = 11;
2760 var->green.offset = 5;
2761 var->blue.offset = 0;
2762 var->red.length = 5;
2763 var->green.length = 6;
2764 var->blue.length = 5;
2765 break;
2766 case 32:
2767 var->red.offset = 16;
2768 var->green.offset = 8;
2769 var->blue.offset = 0;
2770 var->red.length = 8;
2771 var->green.length = 8;
2772 var->blue.length = 8;
2773 break;
2774 default:
2775 /* never happed, put here to keep consistent */
2776 break;
2777 }
2778
2779 var->pixclock = viafb_get_pixclock(var->xres, var->yres, refresh);
2780 var->left_margin =
2781 crt_reg.hor_total - (crt_reg.hor_sync_start + crt_reg.hor_sync_end);
2782 var->right_margin = crt_reg.hor_sync_start - crt_reg.hor_addr;
2783 var->hsync_len = crt_reg.hor_sync_end;
2784 var->upper_margin =
2785 crt_reg.ver_total - (crt_reg.ver_sync_start + crt_reg.ver_sync_end);
2786 var->lower_margin = crt_reg.ver_sync_start - crt_reg.ver_addr;
2787 var->vsync_len = crt_reg.ver_sync_end;
2788}
Linux kernel - Deliverables
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