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viafb: remove duplicated scaling code
[deliverable/linux.git] / drivers / video / via / lcd.c
CommitLineData
ac6c97e2
JC		 1/*
2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
4
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public
7 * License as published by the Free Software Foundation;
8 * either version 2, or (at your option) any later version.
9
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even
12 * the implied warranty of MERCHANTABILITY or FITNESS FOR
13 * A PARTICULAR PURPOSE.See the GNU General Public License
14 * for more details.
15
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc.,
19 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 */
ec66841e
JC		 21#include <linux/via-core.h>
22#include <linux/via_i2c.h>
ac6c97e2
JC		 23#include "global.h"
24#include "lcdtbl.h"
25
dd73d686
FTS		 26#define viafb_compact_res(x, y) (((x)<<16)|(y))
27
ac6c97e2
JC		 28static struct _lcd_scaling_factor lcd_scaling_factor = {
29 /* LCD Horizontal Scaling Factor Register */
30 {LCD_HOR_SCALING_FACTOR_REG_NUM,
31 {{CR9F, 0, 1}, {CR77, 0, 7}, {CR79, 4, 5} } },
32 /* LCD Vertical Scaling Factor Register */
33 {LCD_VER_SCALING_FACTOR_REG_NUM,
34 {{CR79, 3, 3}, {CR78, 0, 7}, {CR79, 6, 7} } }
35};
36static struct _lcd_scaling_factor lcd_scaling_factor_CLE = {
37 /* LCD Horizontal Scaling Factor Register */
38 {LCD_HOR_SCALING_FACTOR_REG_NUM_CLE, {{CR77, 0, 7}, {CR79, 4, 5} } },
39 /* LCD Vertical Scaling Factor Register */
40 {LCD_VER_SCALING_FACTOR_REG_NUM_CLE, {{CR78, 0, 7}, {CR79, 6, 7} } }
41};
42
43static int check_lvds_chip(int device_id_subaddr, int device_id);
44static bool lvds_identify_integratedlvds(void);
9b24b00c 45static void fp_id_to_vindex(int panel_id);
ac6c97e2
JC		 46static int lvds_register_read(int index);
47static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
48 int panel_vres);
ac6c97e2
JC		 49static void via_pitch_alignment_patch_lcd(
50 struct lvds_setting_information *plvds_setting_info,
51 struct lvds_chip_information
52 *plvds_chip_info);
53static void lcd_patch_skew_dvp0(struct lvds_setting_information
54 *plvds_setting_info,
55 struct lvds_chip_information *plvds_chip_info);
56static void lcd_patch_skew_dvp1(struct lvds_setting_information
57 *plvds_setting_info,
58 struct lvds_chip_information *plvds_chip_info);
59static void lcd_patch_skew(struct lvds_setting_information
60 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info);
61
62static void integrated_lvds_disable(struct lvds_setting_information
63 *plvds_setting_info,
64 struct lvds_chip_information *plvds_chip_info);
65static void integrated_lvds_enable(struct lvds_setting_information
66 *plvds_setting_info,
67 struct lvds_chip_information *plvds_chip_info);
68static void lcd_powersequence_off(void);
69static void lcd_powersequence_on(void);
70static void fill_lcd_format(void);
71static void check_diport_of_integrated_lvds(
72 struct lvds_chip_information *plvds_chip_info,
73 struct lvds_setting_information
74 *plvds_setting_info);
75static struct display_timing lcd_centering_timging(struct display_timing
76 mode_crt_reg,
77 struct display_timing panel_crt_reg);
ac6c97e2
JC		 78
79static int check_lvds_chip(int device_id_subaddr, int device_id)
80{
81 if (lvds_register_read(device_id_subaddr) == device_id)
82 return OK;
83 else
84 return FAIL;
85}
86
87void viafb_init_lcd_size(void)
88{
89 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size()\n");
90 DEBUG_MSG(KERN_INFO
91 "viaparinfo->lvds_setting_info->get_lcd_size_method %d\n",
92 viaparinfo->lvds_setting_info->get_lcd_size_method);
93
94 switch (viaparinfo->lvds_setting_info->get_lcd_size_method) {
95 case GET_LCD_SIZE_BY_SYSTEM_BIOS:
96 break;
97 case GET_LCD_SZIE_BY_HW_STRAPPING:
98 break;
99 case GET_LCD_SIZE_BY_VGA_BIOS:
100 DEBUG_MSG(KERN_INFO "Get LCD Size method by VGA BIOS !!\n");
9b24b00c 101 fp_id_to_vindex(viafb_lcd_panel_id);
ac6c97e2
JC		 102 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
103 viaparinfo->lvds_setting_info->lcd_panel_id);
ac6c97e2
JC		 104 break;
105 case GET_LCD_SIZE_BY_USER_SETTING:
106 DEBUG_MSG(KERN_INFO "Get LCD Size method by user setting !!\n");
9b24b00c 107 fp_id_to_vindex(viafb_lcd_panel_id);
ac6c97e2
JC		 108 DEBUG_MSG(KERN_INFO "LCD Panel_ID = %d\n",
109 viaparinfo->lvds_setting_info->lcd_panel_id);
ac6c97e2
JC		 110 break;
111 default:
112 DEBUG_MSG(KERN_INFO "viafb_init_lcd_size fail\n");
113 viaparinfo->lvds_setting_info->lcd_panel_id =
114 LCD_PANEL_ID1_800X600;
9b24b00c 115 fp_id_to_vindex(LCD_PANEL_ID1_800X600);
ac6c97e2
JC		 116 }
117 viaparinfo->lvds_setting_info2->lcd_panel_id =
118 viaparinfo->lvds_setting_info->lcd_panel_id;
ac6c97e2
JC		 119 viaparinfo->lvds_setting_info2->lcd_panel_hres =
120 viaparinfo->lvds_setting_info->lcd_panel_hres;
121 viaparinfo->lvds_setting_info2->lcd_panel_vres =
122 viaparinfo->lvds_setting_info->lcd_panel_vres;
123 viaparinfo->lvds_setting_info2->device_lcd_dualedge =
124 viaparinfo->lvds_setting_info->device_lcd_dualedge;
125 viaparinfo->lvds_setting_info2->LCDDithering =
126 viaparinfo->lvds_setting_info->LCDDithering;
127}
128
129static bool lvds_identify_integratedlvds(void)
130{
131 if (viafb_display_hardware_layout == HW_LAYOUT_LCD_EXTERNAL_LCD2) {
132 /* Two dual channel LCD (Internal LVDS + External LVDS): */
133 /* If we have an external LVDS, such as VT1636, we should
134 have its chip ID already. */
135 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
136 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
137 INTEGRATED_LVDS;
2c0e0c88
JP		 138 DEBUG_MSG(KERN_INFO "Support two dual channel LVDS! "
139 "(Internal LVDS + External LVDS)\n");
ac6c97e2
JC		 140 } else {
141 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
142 INTEGRATED_LVDS;
2c0e0c88
JP		 143 DEBUG_MSG(KERN_INFO "Not found external LVDS, "
144 "so can't support two dual channel LVDS!\n");
ac6c97e2
JC		 145 }
146 } else if (viafb_display_hardware_layout == HW_LAYOUT_LCD1_LCD2) {
147 /* Two single channel LCD (Internal LVDS + Internal LVDS): */
148 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
149 INTEGRATED_LVDS;
150 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name =
151 INTEGRATED_LVDS;
2c0e0c88
JP		 152 DEBUG_MSG(KERN_INFO "Support two single channel LVDS! "
153 "(Internal LVDS + Internal LVDS)\n");
ac6c97e2
JC		 154 } else if (viafb_display_hardware_layout != HW_LAYOUT_DVI_ONLY) {
155 /* If we have found external LVDS, just use it,
156 otherwise, we will use internal LVDS as default. */
157 if (!viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
158 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
159 INTEGRATED_LVDS;
160 DEBUG_MSG(KERN_INFO "Found Integrated LVDS!\n");
161 }
162 } else {
163 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
164 NON_LVDS_TRANSMITTER;
165 DEBUG_MSG(KERN_INFO "Do not support LVDS!\n");
166 return false;
167 }
168
169 return true;
170}
171
172int viafb_lvds_trasmitter_identify(void)
173{
f045f77b
JC		 174 if (viafb_lvds_identify_vt1636(VIA_PORT_31)) {
175 viaparinfo->chip_info->lvds_chip_info.i2c_port = VIA_PORT_31;
ac6c97e2 176 DEBUG_MSG(KERN_INFO
277d32a3 177 "Found VIA VT1636 LVDS on port i2c 0x31\n");
ac6c97e2 178 } else {
f045f77b 179 if (viafb_lvds_identify_vt1636(VIA_PORT_2C)) {
ac6c97e2 180 viaparinfo->chip_info->lvds_chip_info.i2c_port =
f045f77b 181 VIA_PORT_2C;
ac6c97e2 182 DEBUG_MSG(KERN_INFO
277d32a3 183 "Found VIA VT1636 LVDS on port gpio 0x2c\n");
ac6c97e2
JC		 184 }
185 }
186
187 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700)
188 lvds_identify_integratedlvds();
189
190 if (viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
191 return true;
192 /* Check for VT1631: */
193 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name = VT1631_LVDS;
194 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
195 VT1631_LVDS_I2C_ADDR;
196
197 if (check_lvds_chip(VT1631_DEVICE_ID_REG, VT1631_DEVICE_ID) != FAIL) {
198 DEBUG_MSG(KERN_INFO "\n VT1631 LVDS ! \n");
199 DEBUG_MSG(KERN_INFO "\n %2d",
200 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
201 DEBUG_MSG(KERN_INFO "\n %2d",
202 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name);
203 return OK;
204 }
205
206 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name =
207 NON_LVDS_TRANSMITTER;
208 viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr =
209 VT1631_LVDS_I2C_ADDR;
210 return FAIL;
211}
212
9b24b00c 213static void fp_id_to_vindex(int panel_id)
ac6c97e2
JC		 214{
215 DEBUG_MSG(KERN_INFO "fp_get_panel_id()\n");
216
217 if (panel_id > LCD_PANEL_ID_MAXIMUM)
218 viafb_lcd_panel_id = panel_id =
219 viafb_read_reg(VIACR, CR3F) & 0x0F;
220
221 switch (panel_id) {
222 case 0x0:
223 viaparinfo->lvds_setting_info->lcd_panel_hres = 640;
224 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
225 viaparinfo->lvds_setting_info->lcd_panel_id =
226 LCD_PANEL_ID0_640X480;
227 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
228 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 229 break;
230 case 0x1:
231 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
232 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
233 viaparinfo->lvds_setting_info->lcd_panel_id =
234 LCD_PANEL_ID1_800X600;
235 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
236 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 237 break;
238 case 0x2:
239 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
240 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
241 viaparinfo->lvds_setting_info->lcd_panel_id =
242 LCD_PANEL_ID2_1024X768;
243 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
244 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 245 break;
246 case 0x3:
247 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
248 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
249 viaparinfo->lvds_setting_info->lcd_panel_id =
250 LCD_PANEL_ID3_1280X768;
251 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
252 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 253 break;
254 case 0x4:
255 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
256 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
257 viaparinfo->lvds_setting_info->lcd_panel_id =
258 LCD_PANEL_ID4_1280X1024;
259 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
260 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 261 break;
262 case 0x5:
263 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
264 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
265 viaparinfo->lvds_setting_info->lcd_panel_id =
266 LCD_PANEL_ID5_1400X1050;
267 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
268 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 269 break;
270 case 0x6:
271 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
272 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
273 viaparinfo->lvds_setting_info->lcd_panel_id =
274 LCD_PANEL_ID6_1600X1200;
275 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
276 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 277 break;
278 case 0x8:
279 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
280 viaparinfo->lvds_setting_info->lcd_panel_vres = 480;
281 viaparinfo->lvds_setting_info->lcd_panel_id =
282 LCD_PANEL_IDA_800X480;
283 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
284 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 285 break;
286 case 0x9:
287 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
288 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
289 viaparinfo->lvds_setting_info->lcd_panel_id =
290 LCD_PANEL_ID2_1024X768;
291 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
292 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 293 break;
294 case 0xA:
295 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
296 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
297 viaparinfo->lvds_setting_info->lcd_panel_id =
298 LCD_PANEL_ID2_1024X768;
299 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
300 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 301 break;
302 case 0xB:
303 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
304 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
305 viaparinfo->lvds_setting_info->lcd_panel_id =
306 LCD_PANEL_ID2_1024X768;
307 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
308 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 309 break;
310 case 0xC:
311 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
312 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
313 viaparinfo->lvds_setting_info->lcd_panel_id =
314 LCD_PANEL_ID3_1280X768;
315 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
316 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 317 break;
318 case 0xD:
319 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
320 viaparinfo->lvds_setting_info->lcd_panel_vres = 1024;
321 viaparinfo->lvds_setting_info->lcd_panel_id =
322 LCD_PANEL_ID4_1280X1024;
323 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
324 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 325 break;
326 case 0xE:
327 viaparinfo->lvds_setting_info->lcd_panel_hres = 1400;
328 viaparinfo->lvds_setting_info->lcd_panel_vres = 1050;
329 viaparinfo->lvds_setting_info->lcd_panel_id =
330 LCD_PANEL_ID5_1400X1050;
331 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
332 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 333 break;
334 case 0xF:
335 viaparinfo->lvds_setting_info->lcd_panel_hres = 1600;
336 viaparinfo->lvds_setting_info->lcd_panel_vres = 1200;
337 viaparinfo->lvds_setting_info->lcd_panel_id =
338 LCD_PANEL_ID6_1600X1200;
339 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
340 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 341 break;
342 case 0x10:
343 viaparinfo->lvds_setting_info->lcd_panel_hres = 1366;
344 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
345 viaparinfo->lvds_setting_info->lcd_panel_id =
346 LCD_PANEL_ID7_1366X768;
347 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
348 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 349 break;
350 case 0x11:
351 viaparinfo->lvds_setting_info->lcd_panel_hres = 1024;
352 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
353 viaparinfo->lvds_setting_info->lcd_panel_id =
354 LCD_PANEL_ID8_1024X600;
355 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
356 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 357 break;
358 case 0x12:
359 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
360 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
361 viaparinfo->lvds_setting_info->lcd_panel_id =
362 LCD_PANEL_ID3_1280X768;
363 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
364 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 365 break;
366 case 0x13:
367 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
368 viaparinfo->lvds_setting_info->lcd_panel_vres = 800;
369 viaparinfo->lvds_setting_info->lcd_panel_id =
370 LCD_PANEL_ID9_1280X800;
371 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
372 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 373 break;
374 case 0x14:
375 viaparinfo->lvds_setting_info->lcd_panel_hres = 1360;
376 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
377 viaparinfo->lvds_setting_info->lcd_panel_id =
378 LCD_PANEL_IDB_1360X768;
379 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
380 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 381 break;
382 case 0x15:
383 viaparinfo->lvds_setting_info->lcd_panel_hres = 1280;
384 viaparinfo->lvds_setting_info->lcd_panel_vres = 768;
385 viaparinfo->lvds_setting_info->lcd_panel_id =
386 LCD_PANEL_ID3_1280X768;
387 viaparinfo->lvds_setting_info->device_lcd_dualedge = 1;
388 viaparinfo->lvds_setting_info->LCDDithering = 0;
ac6c97e2
JC		 389 break;
390 case 0x16:
391 viaparinfo->lvds_setting_info->lcd_panel_hres = 480;
392 viaparinfo->lvds_setting_info->lcd_panel_vres = 640;
393 viaparinfo->lvds_setting_info->lcd_panel_id =
394 LCD_PANEL_IDC_480X640;
395 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
396 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2 397 break;
c205d932
CB		 398 case 0x17:
399 /* OLPC XO-1.5 panel */
400 viaparinfo->lvds_setting_info->lcd_panel_hres = 1200;
401 viaparinfo->lvds_setting_info->lcd_panel_vres = 900;
402 viaparinfo->lvds_setting_info->lcd_panel_id =
403 LCD_PANEL_IDD_1200X900;
404 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
405 viaparinfo->lvds_setting_info->LCDDithering = 0;
406 break;
ac6c97e2
JC		 407 default:
408 viaparinfo->lvds_setting_info->lcd_panel_hres = 800;
409 viaparinfo->lvds_setting_info->lcd_panel_vres = 600;
410 viaparinfo->lvds_setting_info->lcd_panel_id =
411 LCD_PANEL_ID1_800X600;
412 viaparinfo->lvds_setting_info->device_lcd_dualedge = 0;
413 viaparinfo->lvds_setting_info->LCDDithering = 1;
ac6c97e2
JC		 414 }
415}
416
417static int lvds_register_read(int index)
418{
419 u8 data;
420
f045f77b 421 viafb_i2c_readbyte(VIA_PORT_2C,
277d32a3 422 (u8) viaparinfo->chip_info->lvds_chip_info.lvds_chip_slave_addr,
ac6c97e2
JC		 423 (u8) index, &data);
424 return data;
425}
426
427static void load_lcd_scaling(int set_hres, int set_vres, int panel_hres,
428 int panel_vres)
429{
430 int reg_value = 0;
431 int viafb_load_reg_num;
432 struct io_register *reg = NULL;
433
434 DEBUG_MSG(KERN_INFO "load_lcd_scaling()!!\n");
435
436 /* LCD Scaling Enable */
437 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
ac6c97e2
JC		 438
439 /* Check if expansion for horizontal */
440 if (set_hres != panel_hres) {
441 /* Load Horizontal Scaling Factor */
442 switch (viaparinfo->chip_info->gfx_chip_name) {
443 case UNICHROME_CLE266:
444 case UNICHROME_K400:
445 reg_value =
446 CLE266_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
447 viafb_load_reg_num =
448 lcd_scaling_factor_CLE.lcd_hor_scaling_factor.
449 reg_num;
450 reg = lcd_scaling_factor_CLE.lcd_hor_scaling_factor.reg;
451 viafb_load_reg(reg_value,
452 viafb_load_reg_num, reg, VIACR);
453 break;
454 case UNICHROME_K800:
455 case UNICHROME_PM800:
456 case UNICHROME_CN700:
457 case UNICHROME_CX700:
458 case UNICHROME_K8M890:
459 case UNICHROME_P4M890:
4a73d70e 460 case UNICHROME_P4M900:
ac6c97e2
JC		 461 reg_value =
462 K800_LCD_HOR_SCF_FORMULA(set_hres, panel_hres);
463 /* Horizontal scaling enabled */
464 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
465 viafb_load_reg_num =
466 lcd_scaling_factor.lcd_hor_scaling_factor.reg_num;
467 reg = lcd_scaling_factor.lcd_hor_scaling_factor.reg;
468 viafb_load_reg(reg_value,
469 viafb_load_reg_num, reg, VIACR);
470 break;
471 }
472
473 DEBUG_MSG(KERN_INFO "Horizontal Scaling value = %d", reg_value);
474 } else {
475 /* Horizontal scaling disabled */
476 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
477 }
478
479 /* Check if expansion for vertical */
480 if (set_vres != panel_vres) {
481 /* Load Vertical Scaling Factor */
482 switch (viaparinfo->chip_info->gfx_chip_name) {
483 case UNICHROME_CLE266:
484 case UNICHROME_K400:
485 reg_value =
486 CLE266_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
487 viafb_load_reg_num =
488 lcd_scaling_factor_CLE.lcd_ver_scaling_factor.
489 reg_num;
490 reg = lcd_scaling_factor_CLE.lcd_ver_scaling_factor.reg;
491 viafb_load_reg(reg_value,
492 viafb_load_reg_num, reg, VIACR);
493 break;
494 case UNICHROME_K800:
495 case UNICHROME_PM800:
496 case UNICHROME_CN700:
497 case UNICHROME_CX700:
498 case UNICHROME_K8M890:
499 case UNICHROME_P4M890:
4a73d70e 500 case UNICHROME_P4M900:
ac6c97e2
JC		 501 reg_value =
502 K800_LCD_VER_SCF_FORMULA(set_vres, panel_vres);
503 /* Vertical scaling enabled */
504 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3);
505 viafb_load_reg_num =
506 lcd_scaling_factor.lcd_ver_scaling_factor.reg_num;
507 reg = lcd_scaling_factor.lcd_ver_scaling_factor.reg;
508 viafb_load_reg(reg_value,
509 viafb_load_reg_num, reg, VIACR);
510 break;
511 }
512
513 DEBUG_MSG(KERN_INFO "Vertical Scaling value = %d", reg_value);
514 } else {
515 /* Vertical scaling disabled */
516 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3);
517 }
518}
519
ac6c97e2
JC		 520static void via_pitch_alignment_patch_lcd(
521 struct lvds_setting_information *plvds_setting_info,
522 struct lvds_chip_information
523 *plvds_chip_info)
524{
525 unsigned char cr13, cr35, cr65, cr66, cr67;
526 unsigned long dwScreenPitch = 0;
527 unsigned long dwPitch;
528
529 dwPitch = plvds_setting_info->h_active * (plvds_setting_info->bpp >> 3);
530 if (dwPitch & 0x1F) {
531 dwScreenPitch = ((dwPitch + 31) & ~31) >> 3;
532 if (plvds_setting_info->iga_path == IGA2) {
533 if (plvds_setting_info->bpp > 8) {
534 cr66 = (unsigned char)(dwScreenPitch & 0xFF);
535 viafb_write_reg(CR66, VIACR, cr66);
536 cr67 = viafb_read_reg(VIACR, CR67) & 0xFC;
537 cr67 |=
538 (unsigned
539 char)((dwScreenPitch & 0x300) >> 8);
540 viafb_write_reg(CR67, VIACR, cr67);
541 }
542
543 /* Fetch Count */
544 cr67 = viafb_read_reg(VIACR, CR67) & 0xF3;
545 cr67 |= (unsigned char)((dwScreenPitch & 0x600) >> 7);
546 viafb_write_reg(CR67, VIACR, cr67);
547 cr65 = (unsigned char)((dwScreenPitch >> 1) & 0xFF);
548 cr65 += 2;
549 viafb_write_reg(CR65, VIACR, cr65);
550 } else {
551 if (plvds_setting_info->bpp > 8) {
552 cr13 = (unsigned char)(dwScreenPitch & 0xFF);
553 viafb_write_reg(CR13, VIACR, cr13);
554 cr35 = viafb_read_reg(VIACR, CR35) & 0x1F;
555 cr35 |=
556 (unsigned
557 char)((dwScreenPitch & 0x700) >> 3);
558 viafb_write_reg(CR35, VIACR, cr35);
559 }
560 }
561 }
562}
563static void lcd_patch_skew_dvp0(struct lvds_setting_information
564 *plvds_setting_info,
565 struct lvds_chip_information *plvds_chip_info)
566{
567 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
568 switch (viaparinfo->chip_info->gfx_chip_name) {
569 case UNICHROME_P4M900:
570 viafb_vt1636_patch_skew_on_vt3364(plvds_setting_info,
571 plvds_chip_info);
572 break;
573 case UNICHROME_P4M890:
574 viafb_vt1636_patch_skew_on_vt3327(plvds_setting_info,
575 plvds_chip_info);
576 break;
577 }
578 }
579}
580static void lcd_patch_skew_dvp1(struct lvds_setting_information
581 *plvds_setting_info,
582 struct lvds_chip_information *plvds_chip_info)
583{
584 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) {
585 switch (viaparinfo->chip_info->gfx_chip_name) {
586 case UNICHROME_CX700:
587 viafb_vt1636_patch_skew_on_vt3324(plvds_setting_info,
588 plvds_chip_info);
589 break;
590 }
591 }
592}
593static void lcd_patch_skew(struct lvds_setting_information
594 *plvds_setting_info, struct lvds_chip_information *plvds_chip_info)
595{
596 DEBUG_MSG(KERN_INFO "lcd_patch_skew\n");
597 switch (plvds_chip_info->output_interface) {
598 case INTERFACE_DVP0:
599 lcd_patch_skew_dvp0(plvds_setting_info, plvds_chip_info);
600 break;
601 case INTERFACE_DVP1:
602 lcd_patch_skew_dvp1(plvds_setting_info, plvds_chip_info);
603 break;
604 case INTERFACE_DFP_LOW:
605 if (UNICHROME_P4M900 == viaparinfo->chip_info->gfx_chip_name) {
606 viafb_write_reg_mask(CR99, VIACR, 0x08,
607 BIT0 + BIT1 + BIT2 + BIT3);
608 }
609 break;
610 }
611}
612
613/* LCD Set Mode */
614void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
615 struct lvds_setting_information *plvds_setting_info,
616 struct lvds_chip_information *plvds_chip_info)
617{
ac6c97e2
JC		 618 int set_iga = plvds_setting_info->iga_path;
619 int mode_bpp = plvds_setting_info->bpp;
dd73d686
FTS		 620 int set_hres = plvds_setting_info->h_active;
621 int set_vres = plvds_setting_info->v_active;
622 int panel_hres = plvds_setting_info->lcd_panel_hres;
623 int panel_vres = plvds_setting_info->lcd_panel_vres;
ac6c97e2 624 u32 pll_D_N;
ac6c97e2
JC		 625 struct display_timing mode_crt_reg, panel_crt_reg;
626 struct crt_mode_table *panel_crt_table = NULL;
dd73d686
FTS		 627 struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
628 panel_vres);
ac6c97e2
JC		 629
630 DEBUG_MSG(KERN_INFO "viafb_lcd_set_mode!!\n");
631 /* Get mode table */
632 mode_crt_reg = mode_crt_table->crtc;
633 /* Get panel table Pointer */
ac6c97e2
JC		 634 panel_crt_table = vmode_tbl->crtc;
635 panel_crt_reg = panel_crt_table->crtc;
636 DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
ac6c97e2
JC		 637 if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
638 viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
639 plvds_setting_info->vclk = panel_crt_table->clk;
640 if (set_iga == IGA1) {
641 /* IGA1 doesn't have LCD scaling, so set it as centering. */
642 viafb_load_crtc_timing(lcd_centering_timging
643 (mode_crt_reg, panel_crt_reg), IGA1);
644 } else {
645 /* Expansion */
646 if ((plvds_setting_info->display_method ==
647 LCD_EXPANDSION) & ((set_hres != panel_hres)
648 || (set_vres != panel_vres))) {
649 /* expansion timing IGA2 loaded panel set timing*/
650 viafb_load_crtc_timing(panel_crt_reg, IGA2);
651 DEBUG_MSG(KERN_INFO "viafb_load_crtc_timing!!\n");
652 load_lcd_scaling(set_hres, set_vres, panel_hres,
653 panel_vres);
654 DEBUG_MSG(KERN_INFO "load_lcd_scaling!!\n");
655 } else { /* Centering */
656 /* centering timing IGA2 always loaded panel
657 and mode releative timing */
658 viafb_load_crtc_timing(lcd_centering_timging
659 (mode_crt_reg, panel_crt_reg), IGA2);
660 viafb_write_reg_mask(CR79, VIACR, 0x00,
661 BIT0 + BIT1 + BIT2);
662 /* LCD scaling disabled */
663 }
664 }
665
4bbac05f
FTS		 666 /* Fetch count for IGA2 only */
667 viafb_load_fetch_count_reg(set_hres, mode_bpp / 8, set_iga);
ac6c97e2 668
4bbac05f
FTS		 669 if ((viaparinfo->chip_info->gfx_chip_name != UNICHROME_CLE266)
670 && (viaparinfo->chip_info->gfx_chip_name != UNICHROME_K400))
671 viafb_load_FIFO_reg(set_iga, set_hres, set_vres);
ac6c97e2
JC		 672
673 fill_lcd_format();
674
675 pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk);
676 DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
677 viafb_set_vclock(pll_D_N, set_iga);
678
679 viafb_set_output_path(DEVICE_LCD, set_iga,
680 plvds_chip_info->output_interface);
681 lcd_patch_skew(plvds_setting_info, plvds_chip_info);
682
683 /* If K8M800, enable LCD Prefetch Mode. */
684 if ((viaparinfo->chip_info->gfx_chip_name == UNICHROME_K800)
685 || (UNICHROME_K8M890 == viaparinfo->chip_info->gfx_chip_name))
686 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
687
ac6c97e2
JC		 688 /* Patch for non 32bit alignment mode */
689 via_pitch_alignment_patch_lcd(plvds_setting_info, plvds_chip_info);
690}
691
692static void integrated_lvds_disable(struct lvds_setting_information
693 *plvds_setting_info,
694 struct lvds_chip_information *plvds_chip_info)
695{
696 bool turn_off_first_powersequence = false;
697 bool turn_off_second_powersequence = false;
698 if (INTERFACE_LVDS0LVDS1 == plvds_chip_info->output_interface)
699 turn_off_first_powersequence = true;
700 if (INTERFACE_LVDS0 == plvds_chip_info->output_interface)
701 turn_off_first_powersequence = true;
702 if (INTERFACE_LVDS1 == plvds_chip_info->output_interface)
703 turn_off_second_powersequence = true;
704 if (turn_off_second_powersequence) {
705 /* Use second power sequence control: */
706
707 /* Turn off power sequence. */
708 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
709
710 /* Turn off back light. */
711 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
712 }
713 if (turn_off_first_powersequence) {
714 /* Use first power sequence control: */
715
716 /* Turn off power sequence. */
717 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3);
718
719 /* Turn off back light. */
720 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
721 }
722
723 /* Turn DFP High/Low Pad off. */
724 viafb_write_reg_mask(SR2A, VIASR, 0, BIT0 + BIT1 + BIT2 + BIT3);
725
726 /* Power off LVDS channel. */
727 switch (plvds_chip_info->output_interface) {
728 case INTERFACE_LVDS0:
729 {
730 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
731 break;
732 }
733
734 case INTERFACE_LVDS1:
735 {
736 viafb_write_reg_mask(CRD2, VIACR, 0x40, BIT6);
737 break;
738 }
739
740 case INTERFACE_LVDS0LVDS1:
741 {
742 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
743 break;
744 }
745 }
746}
747
748static void integrated_lvds_enable(struct lvds_setting_information
749 *plvds_setting_info,
750 struct lvds_chip_information *plvds_chip_info)
751{
ac6c97e2
JC		 752 DEBUG_MSG(KERN_INFO "integrated_lvds_enable, out_interface:%d\n",
753 plvds_chip_info->output_interface);
754 if (plvds_setting_info->lcd_mode == LCD_SPWG)
755 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
e6bf0d2c 756 else
ac6c97e2 757 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
ac6c97e2 758
e6bf0d2c
HW		 759 switch (plvds_chip_info->output_interface) {
760 case INTERFACE_LVDS0LVDS1:
761 case INTERFACE_LVDS0:
ac6c97e2 762 /* Use first power sequence control: */
ac6c97e2
JC		 763 /* Use hardware control power sequence. */
764 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
ac6c97e2
JC		 765 /* Turn on back light. */
766 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
ac6c97e2
JC		 767 /* Turn on hardware power sequence. */
768 viafb_write_reg_mask(CR6A, VIACR, 0x08, BIT3);
e6bf0d2c
HW		 769 break;
770 case INTERFACE_LVDS1:
771 /* Use second power sequence control: */
772 /* Use hardware control power sequence. */
773 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
774 /* Turn on back light. */
775 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
776 /* Turn on hardware power sequence. */
777 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
778 break;
ac6c97e2
JC		 779 }
780
781 /* Turn DFP High/Low pad on. */
782 viafb_write_reg_mask(SR2A, VIASR, 0x0F, BIT0 + BIT1 + BIT2 + BIT3);
783
784 /* Power on LVDS channel. */
785 switch (plvds_chip_info->output_interface) {
786 case INTERFACE_LVDS0:
787 {
788 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
789 break;
790 }
791
792 case INTERFACE_LVDS1:
793 {
794 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6);
795 break;
796 }
797
798 case INTERFACE_LVDS0LVDS1:
799 {
800 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
801 break;
802 }
803 }
804}
805
806void viafb_lcd_disable(void)
807{
808
809 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
810 lcd_powersequence_off();
811 /* DI1 pad off */
812 viafb_write_reg_mask(SR1E, VIASR, 0x00, 0x30);
813 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
814 if (viafb_LCD2_ON
815 && (INTEGRATED_LVDS ==
816 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
817 integrated_lvds_disable(viaparinfo->lvds_setting_info,
818 &viaparinfo->chip_info->lvds_chip_info2);
819 if (INTEGRATED_LVDS ==
820 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
821 integrated_lvds_disable(viaparinfo->lvds_setting_info,
822 &viaparinfo->chip_info->lvds_chip_info);
823 if (VT1636_LVDS == viaparinfo->chip_info->
824 lvds_chip_info.lvds_chip_name)
825 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
826 &viaparinfo->chip_info->lvds_chip_info);
827 } else if (VT1636_LVDS ==
828 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
829 viafb_disable_lvds_vt1636(viaparinfo->lvds_setting_info,
830 &viaparinfo->chip_info->lvds_chip_info);
831 } else {
832 /* DFP-HL pad off */
833 viafb_write_reg_mask(SR2A, VIASR, 0x00, 0x0F);
834 /* Backlight off */
835 viafb_write_reg_mask(SR3D, VIASR, 0x00, 0x20);
836 /* 24 bit DI data paht off */
837 viafb_write_reg_mask(CR91, VIACR, 0x80, 0x80);
838 /* Simultaneout disabled */
839 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
840 }
841
842 /* Disable expansion bit */
843 viafb_write_reg_mask(CR79, VIACR, 0x00, 0x01);
844 /* CRT path set to IGA1 */
845 viafb_write_reg_mask(SR16, VIASR, 0x00, 0x40);
846 /* Simultaneout disabled */
847 viafb_write_reg_mask(CR6B, VIACR, 0x00, 0x08);
848 /* IGA2 path disabled */
849 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
850
851}
852
853void viafb_lcd_enable(void)
854{
855 if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CLE266) {
856 /* DI1 pad on */
857 viafb_write_reg_mask(SR1E, VIASR, 0x30, 0x30);
858 lcd_powersequence_on();
859 } else if (viaparinfo->chip_info->gfx_chip_name == UNICHROME_CX700) {
860 if (viafb_LCD2_ON && (INTEGRATED_LVDS ==
861 viaparinfo->chip_info->lvds_chip_info2.lvds_chip_name))
862 integrated_lvds_enable(viaparinfo->lvds_setting_info2, \
863 &viaparinfo->chip_info->lvds_chip_info2);
864 if (INTEGRATED_LVDS ==
865 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name)
866 integrated_lvds_enable(viaparinfo->lvds_setting_info,
867 &viaparinfo->chip_info->lvds_chip_info);
868 if (VT1636_LVDS == viaparinfo->chip_info->
869 lvds_chip_info.lvds_chip_name)
870 viafb_enable_lvds_vt1636(viaparinfo->
871 lvds_setting_info, &viaparinfo->chip_info->
872 lvds_chip_info);
873 } else if (VT1636_LVDS ==
874 viaparinfo->chip_info->lvds_chip_info.lvds_chip_name) {
875 viafb_enable_lvds_vt1636(viaparinfo->lvds_setting_info,
876 &viaparinfo->chip_info->lvds_chip_info);
877 } else {
878 /* DFP-HL pad on */
879 viafb_write_reg_mask(SR2A, VIASR, 0x0F, 0x0F);
880 /* Backlight on */
881 viafb_write_reg_mask(SR3D, VIASR, 0x20, 0x20);
882 /* 24 bit DI data paht on */
883 viafb_write_reg_mask(CR91, VIACR, 0x00, 0x80);
884
885 /* Set data source selection bit by iga path */
886 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
887 /* DFP-H set to IGA1 */
888 viafb_write_reg_mask(CR97, VIACR, 0x00, 0x10);
889 /* DFP-L set to IGA1 */
890 viafb_write_reg_mask(CR99, VIACR, 0x00, 0x10);
891 } else {
892 /* DFP-H set to IGA2 */
893 viafb_write_reg_mask(CR97, VIACR, 0x10, 0x10);
894 /* DFP-L set to IGA2 */
895 viafb_write_reg_mask(CR99, VIACR, 0x10, 0x10);
896 }
897 /* LCD enabled */
898 viafb_write_reg_mask(CR6A, VIACR, 0x48, 0x48);
899 }
900
4bbac05f 901 if (viaparinfo->lvds_setting_info->iga_path == IGA1) {
ac6c97e2
JC		 902 /* CRT path set to IGA2 */
903 viafb_write_reg_mask(SR16, VIASR, 0x40, 0x40);
904 /* IGA2 path disabled */
905 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x80);
906 /* IGA2 path enabled */
907 } else { /* IGA2 */
908 viafb_write_reg_mask(CR6A, VIACR, 0x80, 0x80);
909 }
910
911}
912
913static void lcd_powersequence_off(void)
914{
915 int i, mask, data;
916
917 /* Software control power sequence */
918 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
919
920 for (i = 0; i < 3; i++) {
921 mask = PowerSequenceOff[0][i];
922 data = PowerSequenceOff[1][i] & mask;
923 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
924 udelay(PowerSequenceOff[2][i]);
925 }
926
927 /* Disable LCD */
928 viafb_write_reg_mask(CR6A, VIACR, 0x00, 0x08);
929}
930
931static void lcd_powersequence_on(void)
932{
933 int i, mask, data;
934
935 /* Software control power sequence */
936 viafb_write_reg_mask(CR91, VIACR, 0x11, 0x11);
937
938 /* Enable LCD */
939 viafb_write_reg_mask(CR6A, VIACR, 0x08, 0x08);
940
941 for (i = 0; i < 3; i++) {
942 mask = PowerSequenceOn[0][i];
943 data = PowerSequenceOn[1][i] & mask;
944 viafb_write_reg_mask(CR91, VIACR, (u8) data, (u8) mask);
945 udelay(PowerSequenceOn[2][i]);
946 }
947
948 udelay(1);
949}
950
951static void fill_lcd_format(void)
952{
953 u8 bdithering = 0, bdual = 0;
954
955 if (viaparinfo->lvds_setting_info->device_lcd_dualedge)
956 bdual = BIT4;
957 if (viaparinfo->lvds_setting_info->LCDDithering)
958 bdithering = BIT0;
959 /* Dual & Dithering */
960 viafb_write_reg_mask(CR88, VIACR, (bdithering | bdual), BIT4 + BIT0);
961}
962
963static void check_diport_of_integrated_lvds(
964 struct lvds_chip_information *plvds_chip_info,
965 struct lvds_setting_information
966 *plvds_setting_info)
967{
968 /* Determine LCD DI Port by hardware layout. */
969 switch (viafb_display_hardware_layout) {
970 case HW_LAYOUT_LCD_ONLY:
971 {
972 if (plvds_setting_info->device_lcd_dualedge) {
973 plvds_chip_info->output_interface =
974 INTERFACE_LVDS0LVDS1;
975 } else {
976 plvds_chip_info->output_interface =
977 INTERFACE_LVDS0;
978 }
979
980 break;
981 }
982
983 case HW_LAYOUT_DVI_ONLY:
984 {
985 plvds_chip_info->output_interface = INTERFACE_NONE;
986 break;
987 }
988
989 case HW_LAYOUT_LCD1_LCD2:
990 case HW_LAYOUT_LCD_EXTERNAL_LCD2:
991 {
992 plvds_chip_info->output_interface =
993 INTERFACE_LVDS0LVDS1;
994 break;
995 }
996
997 case HW_LAYOUT_LCD_DVI:
998 {
999 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1000 break;
1001 }
1002
1003 default:
1004 {
1005 plvds_chip_info->output_interface = INTERFACE_LVDS1;
1006 break;
1007 }
1008 }
1009
1010 DEBUG_MSG(KERN_INFO
1011 "Display Hardware Layout: 0x%x, LCD DI Port: 0x%x\n",
1012 viafb_display_hardware_layout,
1013 plvds_chip_info->output_interface);
1014}
1015
1016void viafb_init_lvds_output_interface(struct lvds_chip_information
1017 *plvds_chip_info,
1018 struct lvds_setting_information
1019 *plvds_setting_info)
1020{
1021 if (INTERFACE_NONE != plvds_chip_info->output_interface) {
1022 /*Do nothing, lcd port is specified by module parameter */
1023 return;
1024 }
1025
1026 switch (plvds_chip_info->lvds_chip_name) {
1027
1028 case VT1636_LVDS:
1029 switch (viaparinfo->chip_info->gfx_chip_name) {
1030 case UNICHROME_CX700:
1031 plvds_chip_info->output_interface = INTERFACE_DVP1;
1032 break;
1033 case UNICHROME_CN700:
1034 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1035 break;
1036 default:
1037 plvds_chip_info->output_interface = INTERFACE_DVP0;
1038 break;
1039 }
1040 break;
1041
1042 case INTEGRATED_LVDS:
1043 check_diport_of_integrated_lvds(plvds_chip_info,
1044 plvds_setting_info);
1045 break;
1046
1047 default:
1048 switch (viaparinfo->chip_info->gfx_chip_name) {
1049 case UNICHROME_K8M890:
1050 case UNICHROME_P4M900:
1051 case UNICHROME_P4M890:
1052 plvds_chip_info->output_interface = INTERFACE_DFP_LOW;
1053 break;
1054 default:
1055 plvds_chip_info->output_interface = INTERFACE_DFP;
1056 break;
1057 }
1058 break;
1059 }
1060}
1061
1062static struct display_timing lcd_centering_timging(struct display_timing
1063 mode_crt_reg,
1064 struct display_timing panel_crt_reg)
1065{
1066 struct display_timing crt_reg;
1067
1068 crt_reg.hor_total = panel_crt_reg.hor_total;
1069 crt_reg.hor_addr = mode_crt_reg.hor_addr;
1070 crt_reg.hor_blank_start =
1071 (panel_crt_reg.hor_addr - mode_crt_reg.hor_addr) / 2 +
1072 crt_reg.hor_addr;
1073 crt_reg.hor_blank_end = panel_crt_reg.hor_blank_end;
1074 crt_reg.hor_sync_start =
1075 (panel_crt_reg.hor_sync_start -
1076 panel_crt_reg.hor_blank_start) + crt_reg.hor_blank_start;
1077 crt_reg.hor_sync_end = panel_crt_reg.hor_sync_end;
1078
1079 crt_reg.ver_total = panel_crt_reg.ver_total;
1080 crt_reg.ver_addr = mode_crt_reg.ver_addr;
1081 crt_reg.ver_blank_start =
1082 (panel_crt_reg.ver_addr - mode_crt_reg.ver_addr) / 2 +
1083 crt_reg.ver_addr;
1084 crt_reg.ver_blank_end = panel_crt_reg.ver_blank_end;
1085 crt_reg.ver_sync_start =
1086 (panel_crt_reg.ver_sync_start -
1087 panel_crt_reg.ver_blank_start) + crt_reg.ver_blank_start;
1088 crt_reg.ver_sync_end = panel_crt_reg.ver_sync_end;
1089
1090 return crt_reg;
1091}
1092
ac6c97e2
JC		 1093bool viafb_lcd_get_mobile_state(bool *mobile)
1094{
1095 unsigned char *romptr, *tableptr;
1096 u8 core_base;
1097 unsigned char *biosptr;
1098 /* Rom address */
1099 u32 romaddr = 0x000C0000;
1100 u16 start_pattern = 0;
1101
1102 biosptr = ioremap(romaddr, 0x10000);
1103
1104 memcpy(&start_pattern, biosptr, 2);
1105 /* Compare pattern */
1106 if (start_pattern == 0xAA55) {
1107 /* Get the start of Table */
1108 /* 0x1B means BIOS offset position */
1109 romptr = biosptr + 0x1B;
1110 tableptr = biosptr + *((u16 *) romptr);
1111
1112 /* Get the start of biosver structure */
1113 /* 18 means BIOS version position. */
1114 romptr = tableptr + 18;
1115 romptr = biosptr + *((u16 *) romptr);
1116
1117 /* The offset should be 44, but the
1118 actual image is less three char. */
1119 /* pRom += 44; */
1120 romptr += 41;
1121
1122 core_base = *romptr++;
1123
1124 if (core_base & 0x8)
1125 *mobile = false;
1126 else
1127 *mobile = true;
1128 /* release memory */
1129 iounmap(biosptr);
1130
1131 return true;
1132 } else {
1133 iounmap(biosptr);
1134 return false;
1135 }
1136}
Linux kernel - Deliverables
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