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d42823ef JC |
1 | /* |
2 | * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. | |
3 | * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. | |
4 | ||
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public | |
7 | * License as published by the Free Software Foundation; | |
8 | * either version 2, or (at your option) any later version. | |
9 | ||
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTIES OR REPRESENTATIONS; without even | |
12 | * the implied warranty of MERCHANTABILITY or FITNESS FOR | |
13 | * A PARTICULAR PURPOSE.See the GNU General Public License | |
14 | * for more details. | |
15 | ||
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., | |
19 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
20 | */ | |
21 | ||
22 | #include "global.h" | |
23 | /* For VT3324: */ | |
24 | struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3324[] = { | |
25 | /* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */ | |
26 | {LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */ | |
27 | {LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */ | |
28 | {LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */ | |
29 | {LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */ | |
30 | {LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */ | |
31 | {LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */ | |
32 | {LCD_PANEL_ID6_1600X1200, 0x0B, 0x03} /* For 1600x1200 */ | |
33 | }; | |
34 | ||
35 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3324[] = { | |
36 | /* ClkRange, DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1, | |
37 | DVP1Driving, DFPHigh, DFPLow */ | |
38 | /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B, | |
39 | SR65, CR97, CR99 */ | |
40 | /* LCK/VCK < 30000000 will use this value */ | |
41 | {DPA_CLK_RANGE_30M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, | |
42 | 0x00}, | |
43 | /* 30000000 < LCK/VCK < 50000000 will use this value */ | |
44 | {DPA_CLK_RANGE_30_50M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, | |
45 | 0x00}, | |
46 | /* 50000000 < LCK/VCK < 70000000 will use this value */ | |
47 | {DPA_CLK_RANGE_50_70M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, | |
48 | 0x00}, | |
49 | /* 70000000 < LCK/VCK < 100000000 will use this value */ | |
50 | {DPA_CLK_RANGE_70_100M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, | |
51 | 0x00}, | |
52 | /* 100000000 < LCK/VCK < 15000000 will use this value */ | |
53 | {DPA_CLK_RANGE_100_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, | |
54 | 0x00}, | |
55 | /* 15000000 < LCK/VCK will use this value */ | |
56 | {DPA_CLK_RANGE_150M, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x00, | |
57 | 0x00}, | |
58 | }; | |
59 | ||
60 | /* For VT3327: */ | |
61 | struct VT1636_DPA_SETTING VT1636_DPA_SETTING_TBL_VT3327[] = { | |
62 | /* Panel ID, CLK_SEL_ST1[09], CLK_SEL_ST2[08] */ | |
63 | {LCD_PANEL_ID0_640X480, 0x00, 0x00}, /* For 640x480 */ | |
64 | {LCD_PANEL_ID1_800X600, 0x00, 0x00}, /* For 800x600 */ | |
65 | {LCD_PANEL_ID2_1024X768, 0x00, 0x00}, /* For 1024x768 */ | |
66 | {LCD_PANEL_ID3_1280X768, 0x00, 0x00}, /* For 1280x768 */ | |
67 | {LCD_PANEL_ID4_1280X1024, 0x00, 0x00}, /* For 1280x1024 */ | |
68 | {LCD_PANEL_ID5_1400X1050, 0x00, 0x00}, /* For 1400x1050 */ | |
69 | {LCD_PANEL_ID6_1600X1200, 0x00, 0x00} /* For 1600x1200 */ | |
70 | }; | |
71 | ||
72 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3327[] = { | |
73 | /* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1, | |
74 | DVP1Driving, DFPHigh, DFPLow */ | |
75 | /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B, | |
76 | SR65, CR97, CR99 */ | |
77 | /* LCK/VCK < 30000000 will use this value */ | |
78 | {DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01}, | |
79 | /* 30000000 < LCK/VCK < 50000000 will use this value */ | |
80 | {DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01}, | |
81 | /* 50000000 < LCK/VCK < 70000000 will use this value */ | |
82 | {DPA_CLK_RANGE_50_70M, 0x06, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x01}, | |
83 | /* 70000000 < LCK/VCK < 100000000 will use this value */ | |
84 | {DPA_CLK_RANGE_70_100M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x03}, | |
85 | /* 100000000 < LCK/VCK < 15000000 will use this value */ | |
86 | {DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x01, 0x02}, | |
87 | /* 15000000 < LCK/VCK will use this value */ | |
88 | {DPA_CLK_RANGE_150M, 0x00, 0x20, 0x00, 0x10, 0x00, 0x03, 0x00, 0x0D, 0x03}, | |
89 | }; | |
90 | ||
91 | /* For VT3364: */ | |
92 | struct GFX_DPA_SETTING GFX_DPA_SETTING_TBL_VT3364[] = { | |
93 | /* ClkRange,DVP0, DVP0DataDriving, DVP0ClockDriving, DVP1, | |
94 | DVP1Driving, DFPHigh, DFPLow */ | |
95 | /* CR96, SR2A[5], SR1B[1], SR2A[4], SR1E[2], CR9B, | |
96 | SR65, CR97, CR99 */ | |
97 | /* LCK/VCK < 30000000 will use this value */ | |
98 | {DPA_CLK_RANGE_30M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
99 | /* 30000000 < LCK/VCK < 50000000 will use this value */ | |
100 | {DPA_CLK_RANGE_30_50M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
101 | /* 50000000 < LCK/VCK < 70000000 will use this value */ | |
102 | {DPA_CLK_RANGE_50_70M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
103 | /* 70000000 < LCK/VCK < 100000000 will use this value */ | |
104 | {DPA_CLK_RANGE_70_100M, 0x07, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
105 | /* 100000000 < LCK/VCK < 15000000 will use this value */ | |
106 | {DPA_CLK_RANGE_100_150M, 0x03, 0x00, 0x02, 0x00, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
107 | /* 15000000 < LCK/VCK will use this value */ | |
108 | {DPA_CLK_RANGE_150M, 0x01, 0x00, 0x02, 0x10, 0x00, 0x03, 0x00, 0x00, 0x08}, | |
109 | }; |