Commit | Line | Data |
---|---|---|
558b7bd8 OZ |
1 | /* |
2 | * linux/drivers/video/vt8623fb.c - fbdev driver for | |
3 | * integrated graphic core in VIA VT8623 [CLE266] chipset | |
4 | * | |
5 | * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org> | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file COPYING in the main directory of this archive for | |
9 | * more details. | |
10 | * | |
11 | * Code is based on s3fb, some parts are from David Boucher's viafb | |
12 | * (http://davesdomain.org.uk/viafb/) | |
13 | */ | |
14 | ||
558b7bd8 OZ |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/mm.h> | |
20 | #include <linux/tty.h> | |
558b7bd8 OZ |
21 | #include <linux/delay.h> |
22 | #include <linux/fb.h> | |
23 | #include <linux/svga.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/pci.h> | |
ac751efa | 26 | #include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */ |
558b7bd8 OZ |
27 | #include <video/vga.h> |
28 | ||
29 | #ifdef CONFIG_MTRR | |
30 | #include <asm/mtrr.h> | |
31 | #endif | |
32 | ||
33 | struct vt8623fb_info { | |
34 | char __iomem *mmio_base; | |
35 | int mtrr_reg; | |
36 | struct vgastate state; | |
37 | struct mutex open_lock; | |
38 | unsigned int ref_count; | |
39 | u32 pseudo_palette[16]; | |
40 | }; | |
41 | ||
42 | ||
43 | ||
44 | /* ------------------------------------------------------------------------- */ | |
45 | ||
46 | static const struct svga_fb_format vt8623fb_formats[] = { | |
47 | { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, | |
48 | FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP8, FB_VISUAL_PSEUDOCOLOR, 16, 16}, | |
49 | { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, | |
50 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 16, 16}, | |
51 | { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1, | |
52 | FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 16, 16}, | |
53 | { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0, | |
54 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 8}, | |
55 | /* {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0, | |
56 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, */ | |
57 | {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0, | |
58 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 4, 4}, | |
59 | {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0, | |
60 | FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 2}, | |
61 | SVGA_FORMAT_END | |
62 | }; | |
63 | ||
64 | static const struct svga_pll vt8623_pll = {2, 127, 2, 7, 0, 3, | |
65 | 60000, 300000, 14318}; | |
66 | ||
67 | /* CRT timing register sets */ | |
68 | ||
3552f09a AB |
69 | static struct vga_regset vt8623_h_total_regs[] = {{0x00, 0, 7}, {0x36, 3, 3}, VGA_REGSET_END}; |
70 | static struct vga_regset vt8623_h_display_regs[] = {{0x01, 0, 7}, VGA_REGSET_END}; | |
71 | static struct vga_regset vt8623_h_blank_start_regs[] = {{0x02, 0, 7}, VGA_REGSET_END}; | |
72 | static struct vga_regset vt8623_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, {0x33, 5, 5}, VGA_REGSET_END}; | |
73 | static struct vga_regset vt8623_h_sync_start_regs[] = {{0x04, 0, 7}, {0x33, 4, 4}, VGA_REGSET_END}; | |
74 | static struct vga_regset vt8623_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END}; | |
75 | ||
76 | static struct vga_regset vt8623_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x35, 0, 0}, VGA_REGSET_END}; | |
77 | static struct vga_regset vt8623_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x35, 2, 2}, VGA_REGSET_END}; | |
78 | static struct vga_regset vt8623_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x35, 3, 3}, VGA_REGSET_END}; | |
79 | static struct vga_regset vt8623_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END}; | |
80 | static struct vga_regset vt8623_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x35, 1, 1}, VGA_REGSET_END}; | |
81 | static struct vga_regset vt8623_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END}; | |
82 | ||
83 | static struct vga_regset vt8623_offset_regs[] = {{0x13, 0, 7}, {0x35, 5, 7}, VGA_REGSET_END}; | |
84 | static struct vga_regset vt8623_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x33, 0, 2}, {0x35, 4, 4}, VGA_REGSET_END}; | |
85 | static struct vga_regset vt8623_fetch_count_regs[] = {{0x1C, 0, 7}, {0x1D, 0, 1}, VGA_REGSET_END}; | |
86 | static struct vga_regset vt8623_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x34, 0, 7}, {0x48, 0, 1}, VGA_REGSET_END}; | |
87 | ||
88 | static struct svga_timing_regs vt8623_timing_regs = { | |
558b7bd8 OZ |
89 | vt8623_h_total_regs, vt8623_h_display_regs, vt8623_h_blank_start_regs, |
90 | vt8623_h_blank_end_regs, vt8623_h_sync_start_regs, vt8623_h_sync_end_regs, | |
91 | vt8623_v_total_regs, vt8623_v_display_regs, vt8623_v_blank_start_regs, | |
92 | vt8623_v_blank_end_regs, vt8623_v_sync_start_regs, vt8623_v_sync_end_regs, | |
93 | }; | |
94 | ||
95 | ||
96 | /* ------------------------------------------------------------------------- */ | |
97 | ||
98 | ||
99 | /* Module parameters */ | |
100 | ||
cc6c549c | 101 | static char *mode_option = "640x480-8@60"; |
558b7bd8 OZ |
102 | |
103 | #ifdef CONFIG_MTRR | |
104 | static int mtrr = 1; | |
105 | #endif | |
106 | ||
107 | MODULE_AUTHOR("(c) 2006 Ondrej Zajicek <santiago@crfreenet.org>"); | |
108 | MODULE_LICENSE("GPL"); | |
109 | MODULE_DESCRIPTION("fbdev driver for integrated graphics core in VIA VT8623 [CLE266]"); | |
110 | ||
cc6c549c KH |
111 | module_param(mode_option, charp, 0644); |
112 | MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)"); | |
9e3f0ca8 KH |
113 | module_param_named(mode, mode_option, charp, 0); |
114 | MODULE_PARM_DESC(mode, "Default video mode e.g. '648x480-8@60' (deprecated)"); | |
558b7bd8 OZ |
115 | |
116 | #ifdef CONFIG_MTRR | |
117 | module_param(mtrr, int, 0444); | |
118 | MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)"); | |
119 | #endif | |
120 | ||
121 | ||
122 | /* ------------------------------------------------------------------------- */ | |
123 | ||
124 | ||
125 | static struct fb_tile_ops vt8623fb_tile_ops = { | |
126 | .fb_settile = svga_settile, | |
127 | .fb_tilecopy = svga_tilecopy, | |
128 | .fb_tilefill = svga_tilefill, | |
129 | .fb_tileblit = svga_tileblit, | |
130 | .fb_tilecursor = svga_tilecursor, | |
131 | .fb_get_tilemax = svga_get_tilemax, | |
132 | }; | |
133 | ||
134 | ||
135 | /* ------------------------------------------------------------------------- */ | |
136 | ||
137 | ||
138 | /* image data is MSB-first, fb structure is MSB-first too */ | |
139 | static inline u32 expand_color(u32 c) | |
140 | { | |
141 | return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF; | |
142 | } | |
143 | ||
144 | /* vt8623fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */ | |
145 | static void vt8623fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image) | |
146 | { | |
147 | u32 fg = expand_color(image->fg_color); | |
148 | u32 bg = expand_color(image->bg_color); | |
149 | const u8 *src1, *src; | |
150 | u8 __iomem *dst1; | |
151 | u32 __iomem *dst; | |
152 | u32 val; | |
153 | int x, y; | |
154 | ||
155 | src1 = image->data; | |
156 | dst1 = info->screen_base + (image->dy * info->fix.line_length) | |
157 | + ((image->dx / 8) * 4); | |
158 | ||
159 | for (y = 0; y < image->height; y++) { | |
160 | src = src1; | |
161 | dst = (u32 __iomem *) dst1; | |
162 | for (x = 0; x < image->width; x += 8) { | |
163 | val = *(src++) * 0x01010101; | |
164 | val = (val & fg) | (~val & bg); | |
165 | fb_writel(val, dst++); | |
166 | } | |
167 | src1 += image->width / 8; | |
168 | dst1 += info->fix.line_length; | |
169 | } | |
170 | } | |
171 | ||
172 | /* vt8623fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */ | |
173 | static void vt8623fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
174 | { | |
175 | u32 fg = expand_color(rect->color); | |
176 | u8 __iomem *dst1; | |
177 | u32 __iomem *dst; | |
178 | int x, y; | |
179 | ||
180 | dst1 = info->screen_base + (rect->dy * info->fix.line_length) | |
181 | + ((rect->dx / 8) * 4); | |
182 | ||
183 | for (y = 0; y < rect->height; y++) { | |
184 | dst = (u32 __iomem *) dst1; | |
185 | for (x = 0; x < rect->width; x += 8) { | |
186 | fb_writel(fg, dst++); | |
187 | } | |
188 | dst1 += info->fix.line_length; | |
189 | } | |
190 | } | |
191 | ||
192 | ||
193 | /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */ | |
194 | static inline u32 expand_pixel(u32 c) | |
195 | { | |
196 | return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) | | |
197 | ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF; | |
198 | } | |
199 | ||
200 | /* vt8623fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */ | |
201 | static void vt8623fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image) | |
202 | { | |
203 | u32 fg = image->fg_color * 0x11111111; | |
204 | u32 bg = image->bg_color * 0x11111111; | |
205 | const u8 *src1, *src; | |
206 | u8 __iomem *dst1; | |
207 | u32 __iomem *dst; | |
208 | u32 val; | |
209 | int x, y; | |
210 | ||
211 | src1 = image->data; | |
212 | dst1 = info->screen_base + (image->dy * info->fix.line_length) | |
213 | + ((image->dx / 8) * 4); | |
214 | ||
215 | for (y = 0; y < image->height; y++) { | |
216 | src = src1; | |
217 | dst = (u32 __iomem *) dst1; | |
218 | for (x = 0; x < image->width; x += 8) { | |
219 | val = expand_pixel(*(src++)); | |
220 | val = (val & fg) | (~val & bg); | |
221 | fb_writel(val, dst++); | |
222 | } | |
223 | src1 += image->width / 8; | |
224 | dst1 += info->fix.line_length; | |
225 | } | |
226 | } | |
227 | ||
228 | static void vt8623fb_imageblit(struct fb_info *info, const struct fb_image *image) | |
229 | { | |
230 | if ((info->var.bits_per_pixel == 4) && (image->depth == 1) | |
231 | && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) { | |
232 | if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES) | |
233 | vt8623fb_iplan_imageblit(info, image); | |
234 | else | |
235 | vt8623fb_cfb4_imageblit(info, image); | |
236 | } else | |
237 | cfb_imageblit(info, image); | |
238 | } | |
239 | ||
240 | static void vt8623fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect) | |
241 | { | |
242 | if ((info->var.bits_per_pixel == 4) | |
243 | && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0) | |
244 | && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)) | |
245 | vt8623fb_iplan_fillrect(info, rect); | |
246 | else | |
247 | cfb_fillrect(info, rect); | |
248 | } | |
249 | ||
250 | ||
251 | /* ------------------------------------------------------------------------- */ | |
252 | ||
253 | ||
254 | static void vt8623_set_pixclock(struct fb_info *info, u32 pixclock) | |
255 | { | |
256 | u16 m, n, r; | |
257 | u8 regval; | |
258 | int rv; | |
259 | ||
260 | rv = svga_compute_pll(&vt8623_pll, 1000000000 / pixclock, &m, &n, &r, info->node); | |
261 | if (rv < 0) { | |
262 | printk(KERN_ERR "fb%d: cannot set requested pixclock, keeping old value\n", info->node); | |
263 | return; | |
264 | } | |
265 | ||
266 | /* Set VGA misc register */ | |
267 | regval = vga_r(NULL, VGA_MIS_R); | |
268 | vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD); | |
269 | ||
270 | /* Set clock registers */ | |
271 | vga_wseq(NULL, 0x46, (n | (r << 6))); | |
272 | vga_wseq(NULL, 0x47, m); | |
273 | ||
274 | udelay(1000); | |
275 | ||
276 | /* PLL reset */ | |
277 | svga_wseq_mask(0x40, 0x02, 0x02); | |
278 | svga_wseq_mask(0x40, 0x00, 0x02); | |
279 | } | |
280 | ||
281 | ||
282 | static int vt8623fb_open(struct fb_info *info, int user) | |
283 | { | |
284 | struct vt8623fb_info *par = info->par; | |
285 | ||
286 | mutex_lock(&(par->open_lock)); | |
287 | if (par->ref_count == 0) { | |
288 | memset(&(par->state), 0, sizeof(struct vgastate)); | |
289 | par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP; | |
290 | par->state.num_crtc = 0xA2; | |
291 | par->state.num_seq = 0x50; | |
292 | save_vga(&(par->state)); | |
293 | } | |
294 | ||
295 | par->ref_count++; | |
296 | mutex_unlock(&(par->open_lock)); | |
297 | ||
298 | return 0; | |
299 | } | |
300 | ||
301 | static int vt8623fb_release(struct fb_info *info, int user) | |
302 | { | |
303 | struct vt8623fb_info *par = info->par; | |
304 | ||
305 | mutex_lock(&(par->open_lock)); | |
306 | if (par->ref_count == 0) { | |
307 | mutex_unlock(&(par->open_lock)); | |
308 | return -EINVAL; | |
309 | } | |
310 | ||
311 | if (par->ref_count == 1) | |
312 | restore_vga(&(par->state)); | |
313 | ||
314 | par->ref_count--; | |
315 | mutex_unlock(&(par->open_lock)); | |
316 | ||
317 | return 0; | |
318 | } | |
319 | ||
320 | static int vt8623fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info) | |
321 | { | |
322 | int rv, mem, step; | |
323 | ||
324 | /* Find appropriate format */ | |
325 | rv = svga_match_format (vt8623fb_formats, var, NULL); | |
326 | if (rv < 0) | |
327 | { | |
328 | printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node); | |
329 | return rv; | |
330 | } | |
331 | ||
332 | /* Do not allow to have real resoulution larger than virtual */ | |
333 | if (var->xres > var->xres_virtual) | |
334 | var->xres_virtual = var->xres; | |
335 | ||
336 | if (var->yres > var->yres_virtual) | |
337 | var->yres_virtual = var->yres; | |
338 | ||
339 | /* Round up xres_virtual to have proper alignment of lines */ | |
340 | step = vt8623fb_formats[rv].xresstep - 1; | |
341 | var->xres_virtual = (var->xres_virtual+step) & ~step; | |
342 | ||
343 | /* Check whether have enough memory */ | |
344 | mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual; | |
345 | if (mem > info->screen_size) | |
346 | { | |
347 | printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n", info->node, mem >> 10, (unsigned int) (info->screen_size >> 10)); | |
348 | return -EINVAL; | |
349 | } | |
350 | ||
351 | /* Text mode is limited to 256 kB of memory */ | |
352 | if ((var->bits_per_pixel == 0) && (mem > (256*1024))) | |
353 | { | |
354 | printk(KERN_ERR "fb%d: text framebuffer size too large (%d kB requested, 256 kB possible)\n", info->node, mem >> 10); | |
355 | return -EINVAL; | |
356 | } | |
357 | ||
358 | rv = svga_check_timings (&vt8623_timing_regs, var, info->node); | |
359 | if (rv < 0) | |
360 | { | |
361 | printk(KERN_ERR "fb%d: invalid timings requested\n", info->node); | |
362 | return rv; | |
363 | } | |
364 | ||
365 | /* Interlaced mode not supported */ | |
366 | if (var->vmode & FB_VMODE_INTERLACED) | |
367 | return -EINVAL; | |
368 | ||
369 | return 0; | |
370 | } | |
371 | ||
372 | ||
373 | static int vt8623fb_set_par(struct fb_info *info) | |
374 | { | |
375 | u32 mode, offset_value, fetch_value, screen_size; | |
21da386d | 376 | struct vt8623fb_info *par = info->par; |
558b7bd8 OZ |
377 | u32 bpp = info->var.bits_per_pixel; |
378 | ||
379 | if (bpp != 0) { | |
380 | info->fix.ypanstep = 1; | |
381 | info->fix.line_length = (info->var.xres_virtual * bpp) / 8; | |
382 | ||
383 | info->flags &= ~FBINFO_MISC_TILEBLITTING; | |
384 | info->tileops = NULL; | |
385 | ||
386 | /* in 4bpp supports 8p wide tiles only, any tiles otherwise */ | |
387 | info->pixmap.blit_x = (bpp == 4) ? (1 << (8 - 1)) : (~(u32)0); | |
388 | info->pixmap.blit_y = ~(u32)0; | |
389 | ||
390 | offset_value = (info->var.xres_virtual * bpp) / 64; | |
391 | fetch_value = ((info->var.xres * bpp) / 128) + 4; | |
392 | ||
393 | if (bpp == 4) | |
394 | fetch_value = (info->var.xres / 8) + 8; /* + 0 is OK */ | |
395 | ||
396 | screen_size = info->var.yres_virtual * info->fix.line_length; | |
397 | } else { | |
398 | info->fix.ypanstep = 16; | |
399 | info->fix.line_length = 0; | |
400 | ||
401 | info->flags |= FBINFO_MISC_TILEBLITTING; | |
402 | info->tileops = &vt8623fb_tile_ops; | |
403 | ||
404 | /* supports 8x16 tiles only */ | |
405 | info->pixmap.blit_x = 1 << (8 - 1); | |
406 | info->pixmap.blit_y = 1 << (16 - 1); | |
407 | ||
408 | offset_value = info->var.xres_virtual / 16; | |
409 | fetch_value = (info->var.xres / 8) + 8; | |
410 | screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64; | |
411 | } | |
412 | ||
413 | info->var.xoffset = 0; | |
414 | info->var.yoffset = 0; | |
415 | info->var.activate = FB_ACTIVATE_NOW; | |
416 | ||
417 | /* Unlock registers */ | |
418 | svga_wseq_mask(0x10, 0x01, 0x01); | |
419 | svga_wcrt_mask(0x11, 0x00, 0x80); | |
420 | svga_wcrt_mask(0x47, 0x00, 0x01); | |
421 | ||
422 | /* Device, screen and sync off */ | |
423 | svga_wseq_mask(0x01, 0x20, 0x20); | |
424 | svga_wcrt_mask(0x36, 0x30, 0x30); | |
425 | svga_wcrt_mask(0x17, 0x00, 0x80); | |
426 | ||
427 | /* Set default values */ | |
e2fade2c | 428 | svga_set_default_gfx_regs(par->state.vgabase); |
f51a14dd | 429 | svga_set_default_atc_regs(par->state.vgabase); |
558b7bd8 OZ |
430 | svga_set_default_seq_regs(); |
431 | svga_set_default_crt_regs(); | |
21da386d DM |
432 | svga_wcrt_multi(par->state.vgabase, vt8623_line_compare_regs, 0xFFFFFFFF); |
433 | svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, 0); | |
558b7bd8 | 434 | |
21da386d | 435 | svga_wcrt_multi(par->state.vgabase, vt8623_offset_regs, offset_value); |
dc6aff3a | 436 | svga_wseq_multi(par->state.vgabase, vt8623_fetch_count_regs, fetch_value); |
558b7bd8 | 437 | |
8f5af9de OZ |
438 | /* Clear H/V Skew */ |
439 | svga_wcrt_mask(0x03, 0x00, 0x60); | |
440 | svga_wcrt_mask(0x05, 0x00, 0x60); | |
441 | ||
558b7bd8 OZ |
442 | if (info->var.vmode & FB_VMODE_DOUBLE) |
443 | svga_wcrt_mask(0x09, 0x80, 0x80); | |
444 | else | |
445 | svga_wcrt_mask(0x09, 0x00, 0x80); | |
446 | ||
447 | svga_wseq_mask(0x1E, 0xF0, 0xF0); // DI/DVP bus | |
448 | svga_wseq_mask(0x2A, 0x0F, 0x0F); // DI/DVP bus | |
af901ca1 | 449 | svga_wseq_mask(0x16, 0x08, 0xBF); // FIFO read threshold |
558b7bd8 OZ |
450 | vga_wseq(NULL, 0x17, 0x1F); // FIFO depth |
451 | vga_wseq(NULL, 0x18, 0x4E); | |
452 | svga_wseq_mask(0x1A, 0x08, 0x08); // enable MMIO ? | |
453 | ||
454 | vga_wcrt(NULL, 0x32, 0x00); | |
455 | vga_wcrt(NULL, 0x34, 0x00); | |
456 | vga_wcrt(NULL, 0x6A, 0x80); | |
457 | vga_wcrt(NULL, 0x6A, 0xC0); | |
458 | ||
459 | vga_wgfx(NULL, 0x20, 0x00); | |
460 | vga_wgfx(NULL, 0x21, 0x00); | |
461 | vga_wgfx(NULL, 0x22, 0x00); | |
462 | ||
463 | /* Set SR15 according to number of bits per pixel */ | |
464 | mode = svga_match_format(vt8623fb_formats, &(info->var), &(info->fix)); | |
465 | switch (mode) { | |
466 | case 0: | |
467 | pr_debug("fb%d: text mode\n", info->node); | |
468 | svga_set_textmode_vga_regs(); | |
469 | svga_wseq_mask(0x15, 0x00, 0xFE); | |
470 | svga_wcrt_mask(0x11, 0x60, 0x70); | |
471 | break; | |
472 | case 1: | |
473 | pr_debug("fb%d: 4 bit pseudocolor\n", info->node); | |
474 | vga_wgfx(NULL, VGA_GFX_MODE, 0x40); | |
475 | svga_wseq_mask(0x15, 0x20, 0xFE); | |
476 | svga_wcrt_mask(0x11, 0x00, 0x70); | |
477 | break; | |
478 | case 2: | |
479 | pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node); | |
480 | svga_wseq_mask(0x15, 0x00, 0xFE); | |
481 | svga_wcrt_mask(0x11, 0x00, 0x70); | |
482 | break; | |
483 | case 3: | |
484 | pr_debug("fb%d: 8 bit pseudocolor\n", info->node); | |
485 | svga_wseq_mask(0x15, 0x22, 0xFE); | |
486 | break; | |
487 | case 4: | |
488 | pr_debug("fb%d: 5/6/5 truecolor\n", info->node); | |
489 | svga_wseq_mask(0x15, 0xB6, 0xFE); | |
490 | break; | |
491 | case 5: | |
492 | pr_debug("fb%d: 8/8/8 truecolor\n", info->node); | |
493 | svga_wseq_mask(0x15, 0xAE, 0xFE); | |
494 | break; | |
495 | default: | |
496 | printk(KERN_ERR "vt8623fb: unsupported mode - bug\n"); | |
497 | return (-EINVAL); | |
498 | } | |
499 | ||
500 | vt8623_set_pixclock(info, info->var.pixclock); | |
501 | svga_set_timings(&vt8623_timing_regs, &(info->var), 1, 1, | |
502 | (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1, 1, | |
503 | 1, info->node); | |
504 | ||
505 | memset_io(info->screen_base, 0x00, screen_size); | |
506 | ||
507 | /* Device and screen back on */ | |
508 | svga_wcrt_mask(0x17, 0x80, 0x80); | |
509 | svga_wcrt_mask(0x36, 0x00, 0x30); | |
510 | svga_wseq_mask(0x01, 0x00, 0x20); | |
511 | ||
512 | return 0; | |
513 | } | |
514 | ||
515 | ||
516 | static int vt8623fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue, | |
517 | u_int transp, struct fb_info *fb) | |
518 | { | |
519 | switch (fb->var.bits_per_pixel) { | |
520 | case 0: | |
521 | case 4: | |
522 | if (regno >= 16) | |
523 | return -EINVAL; | |
524 | ||
525 | outb(0x0F, VGA_PEL_MSK); | |
526 | outb(regno, VGA_PEL_IW); | |
527 | outb(red >> 10, VGA_PEL_D); | |
528 | outb(green >> 10, VGA_PEL_D); | |
529 | outb(blue >> 10, VGA_PEL_D); | |
530 | break; | |
531 | case 8: | |
532 | if (regno >= 256) | |
533 | return -EINVAL; | |
534 | ||
535 | outb(0xFF, VGA_PEL_MSK); | |
536 | outb(regno, VGA_PEL_IW); | |
537 | outb(red >> 10, VGA_PEL_D); | |
538 | outb(green >> 10, VGA_PEL_D); | |
539 | outb(blue >> 10, VGA_PEL_D); | |
540 | break; | |
541 | case 16: | |
542 | if (regno >= 16) | |
543 | return 0; | |
544 | ||
545 | if (fb->var.green.length == 5) | |
546 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) | | |
547 | ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11); | |
548 | else if (fb->var.green.length == 6) | |
549 | ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) | | |
550 | ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11); | |
551 | else | |
552 | return -EINVAL; | |
553 | break; | |
554 | case 24: | |
555 | case 32: | |
556 | if (regno >= 16) | |
557 | return 0; | |
558 | ||
559 | /* ((transp & 0xFF00) << 16) */ | |
560 | ((u32*)fb->pseudo_palette)[regno] = ((red & 0xFF00) << 8) | | |
561 | (green & 0xFF00) | ((blue & 0xFF00) >> 8); | |
562 | break; | |
563 | default: | |
564 | return -EINVAL; | |
565 | } | |
566 | ||
567 | return 0; | |
568 | } | |
569 | ||
570 | ||
571 | static int vt8623fb_blank(int blank_mode, struct fb_info *info) | |
572 | { | |
573 | switch (blank_mode) { | |
574 | case FB_BLANK_UNBLANK: | |
575 | pr_debug("fb%d: unblank\n", info->node); | |
576 | svga_wcrt_mask(0x36, 0x00, 0x30); | |
577 | svga_wseq_mask(0x01, 0x00, 0x20); | |
578 | break; | |
579 | case FB_BLANK_NORMAL: | |
580 | pr_debug("fb%d: blank\n", info->node); | |
581 | svga_wcrt_mask(0x36, 0x00, 0x30); | |
582 | svga_wseq_mask(0x01, 0x20, 0x20); | |
583 | break; | |
584 | case FB_BLANK_HSYNC_SUSPEND: | |
585 | pr_debug("fb%d: DPMS standby (hsync off)\n", info->node); | |
586 | svga_wcrt_mask(0x36, 0x10, 0x30); | |
587 | svga_wseq_mask(0x01, 0x20, 0x20); | |
588 | break; | |
589 | case FB_BLANK_VSYNC_SUSPEND: | |
590 | pr_debug("fb%d: DPMS suspend (vsync off)\n", info->node); | |
591 | svga_wcrt_mask(0x36, 0x20, 0x30); | |
592 | svga_wseq_mask(0x01, 0x20, 0x20); | |
593 | break; | |
594 | case FB_BLANK_POWERDOWN: | |
595 | pr_debug("fb%d: DPMS off (no sync)\n", info->node); | |
596 | svga_wcrt_mask(0x36, 0x30, 0x30); | |
597 | svga_wseq_mask(0x01, 0x20, 0x20); | |
598 | break; | |
599 | } | |
600 | ||
601 | return 0; | |
602 | } | |
603 | ||
604 | ||
605 | static int vt8623fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) | |
606 | { | |
21da386d | 607 | struct vt8623fb_info *par = info->par; |
558b7bd8 OZ |
608 | unsigned int offset; |
609 | ||
610 | /* Calculate the offset */ | |
611 | if (var->bits_per_pixel == 0) { | |
612 | offset = (var->yoffset / 16) * var->xres_virtual + var->xoffset; | |
613 | offset = offset >> 3; | |
614 | } else { | |
615 | offset = (var->yoffset * info->fix.line_length) + | |
616 | (var->xoffset * var->bits_per_pixel / 8); | |
617 | offset = offset >> ((var->bits_per_pixel == 4) ? 2 : 1); | |
618 | } | |
619 | ||
620 | /* Set the offset */ | |
21da386d | 621 | svga_wcrt_multi(par->state.vgabase, vt8623_start_address_regs, offset); |
558b7bd8 OZ |
622 | |
623 | return 0; | |
624 | } | |
625 | ||
626 | ||
627 | /* ------------------------------------------------------------------------- */ | |
628 | ||
629 | ||
630 | /* Frame buffer operations */ | |
631 | ||
632 | static struct fb_ops vt8623fb_ops = { | |
633 | .owner = THIS_MODULE, | |
634 | .fb_open = vt8623fb_open, | |
635 | .fb_release = vt8623fb_release, | |
636 | .fb_check_var = vt8623fb_check_var, | |
637 | .fb_set_par = vt8623fb_set_par, | |
638 | .fb_setcolreg = vt8623fb_setcolreg, | |
639 | .fb_blank = vt8623fb_blank, | |
640 | .fb_pan_display = vt8623fb_pan_display, | |
641 | .fb_fillrect = vt8623fb_fillrect, | |
642 | .fb_copyarea = cfb_copyarea, | |
643 | .fb_imageblit = vt8623fb_imageblit, | |
5a87ede9 | 644 | .fb_get_caps = svga_get_caps, |
558b7bd8 OZ |
645 | }; |
646 | ||
647 | ||
648 | /* PCI probe */ | |
649 | ||
650 | static int __devinit vt8623_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) | |
651 | { | |
652 | struct fb_info *info; | |
653 | struct vt8623fb_info *par; | |
654 | unsigned int memsize1, memsize2; | |
655 | int rc; | |
656 | ||
657 | /* Ignore secondary VGA device because there is no VGA arbitration */ | |
658 | if (! svga_primary_device(dev)) { | |
659 | dev_info(&(dev->dev), "ignoring secondary device\n"); | |
660 | return -ENODEV; | |
661 | } | |
662 | ||
663 | /* Allocate and fill driver data structure */ | |
20e061fb | 664 | info = framebuffer_alloc(sizeof(struct vt8623fb_info), &(dev->dev)); |
558b7bd8 OZ |
665 | if (! info) { |
666 | dev_err(&(dev->dev), "cannot allocate memory\n"); | |
667 | return -ENOMEM; | |
668 | } | |
669 | ||
670 | par = info->par; | |
671 | mutex_init(&par->open_lock); | |
672 | ||
673 | info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN; | |
674 | info->fbops = &vt8623fb_ops; | |
675 | ||
676 | /* Prepare PCI device */ | |
677 | ||
678 | rc = pci_enable_device(dev); | |
679 | if (rc < 0) { | |
594a8819 | 680 | dev_err(info->device, "cannot enable PCI device\n"); |
558b7bd8 OZ |
681 | goto err_enable_device; |
682 | } | |
683 | ||
684 | rc = pci_request_regions(dev, "vt8623fb"); | |
685 | if (rc < 0) { | |
594a8819 | 686 | dev_err(info->device, "cannot reserve framebuffer region\n"); |
558b7bd8 OZ |
687 | goto err_request_regions; |
688 | } | |
689 | ||
690 | info->fix.smem_start = pci_resource_start(dev, 0); | |
691 | info->fix.smem_len = pci_resource_len(dev, 0); | |
692 | info->fix.mmio_start = pci_resource_start(dev, 1); | |
693 | info->fix.mmio_len = pci_resource_len(dev, 1); | |
694 | ||
695 | /* Map physical IO memory address into kernel space */ | |
696 | info->screen_base = pci_iomap(dev, 0, 0); | |
697 | if (! info->screen_base) { | |
698 | rc = -ENOMEM; | |
594a8819 | 699 | dev_err(info->device, "iomap for framebuffer failed\n"); |
558b7bd8 OZ |
700 | goto err_iomap_1; |
701 | } | |
702 | ||
703 | par->mmio_base = pci_iomap(dev, 1, 0); | |
704 | if (! par->mmio_base) { | |
705 | rc = -ENOMEM; | |
594a8819 | 706 | dev_err(info->device, "iomap for MMIO failed\n"); |
558b7bd8 OZ |
707 | goto err_iomap_2; |
708 | } | |
709 | ||
710 | /* Find how many physical memory there is on card */ | |
711 | memsize1 = (vga_rseq(NULL, 0x34) + 1) >> 1; | |
712 | memsize2 = vga_rseq(NULL, 0x39) << 2; | |
713 | ||
714 | if ((16 <= memsize1) && (memsize1 <= 64) && (memsize1 == memsize2)) | |
715 | info->screen_size = memsize1 << 20; | |
716 | else { | |
594a8819 | 717 | dev_err(info->device, "memory size detection failed (%x %x), suppose 16 MB\n", memsize1, memsize2); |
558b7bd8 OZ |
718 | info->screen_size = 16 << 20; |
719 | } | |
720 | ||
721 | info->fix.smem_len = info->screen_size; | |
722 | strcpy(info->fix.id, "VIA VT8623"); | |
723 | info->fix.type = FB_TYPE_PACKED_PIXELS; | |
724 | info->fix.visual = FB_VISUAL_PSEUDOCOLOR; | |
725 | info->fix.ypanstep = 0; | |
726 | info->fix.accel = FB_ACCEL_NONE; | |
727 | info->pseudo_palette = (void*)par->pseudo_palette; | |
728 | ||
729 | /* Prepare startup mode */ | |
730 | ||
d6d1b650 | 731 | kparam_block_sysfs_write(mode_option); |
cc6c549c | 732 | rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8); |
d6d1b650 | 733 | kparam_unblock_sysfs_write(mode_option); |
558b7bd8 OZ |
734 | if (! ((rc == 1) || (rc == 2))) { |
735 | rc = -EINVAL; | |
594a8819 | 736 | dev_err(info->device, "mode %s not found\n", mode_option); |
558b7bd8 OZ |
737 | goto err_find_mode; |
738 | } | |
739 | ||
740 | rc = fb_alloc_cmap(&info->cmap, 256, 0); | |
741 | if (rc < 0) { | |
594a8819 | 742 | dev_err(info->device, "cannot allocate colormap\n"); |
558b7bd8 OZ |
743 | goto err_alloc_cmap; |
744 | } | |
745 | ||
746 | rc = register_framebuffer(info); | |
747 | if (rc < 0) { | |
594a8819 | 748 | dev_err(info->device, "cannot register framebugger\n"); |
558b7bd8 OZ |
749 | goto err_reg_fb; |
750 | } | |
751 | ||
752 | printk(KERN_INFO "fb%d: %s on %s, %d MB RAM\n", info->node, info->fix.id, | |
753 | pci_name(dev), info->fix.smem_len >> 20); | |
754 | ||
755 | /* Record a reference to the driver data */ | |
756 | pci_set_drvdata(dev, info); | |
757 | ||
758 | #ifdef CONFIG_MTRR | |
759 | if (mtrr) { | |
760 | par->mtrr_reg = -1; | |
761 | par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1); | |
762 | } | |
763 | #endif | |
764 | ||
765 | return 0; | |
766 | ||
767 | /* Error handling */ | |
768 | err_reg_fb: | |
769 | fb_dealloc_cmap(&info->cmap); | |
770 | err_alloc_cmap: | |
771 | err_find_mode: | |
772 | pci_iounmap(dev, par->mmio_base); | |
773 | err_iomap_2: | |
774 | pci_iounmap(dev, info->screen_base); | |
775 | err_iomap_1: | |
776 | pci_release_regions(dev); | |
777 | err_request_regions: | |
778 | /* pci_disable_device(dev); */ | |
779 | err_enable_device: | |
780 | framebuffer_release(info); | |
781 | return rc; | |
782 | } | |
783 | ||
784 | /* PCI remove */ | |
785 | ||
786 | static void __devexit vt8623_pci_remove(struct pci_dev *dev) | |
787 | { | |
788 | struct fb_info *info = pci_get_drvdata(dev); | |
558b7bd8 OZ |
789 | |
790 | if (info) { | |
38d473f9 OZ |
791 | struct vt8623fb_info *par = info->par; |
792 | ||
558b7bd8 OZ |
793 | #ifdef CONFIG_MTRR |
794 | if (par->mtrr_reg >= 0) { | |
795 | mtrr_del(par->mtrr_reg, 0, 0); | |
796 | par->mtrr_reg = -1; | |
797 | } | |
798 | #endif | |
799 | ||
800 | unregister_framebuffer(info); | |
801 | fb_dealloc_cmap(&info->cmap); | |
802 | ||
803 | pci_iounmap(dev, info->screen_base); | |
804 | pci_iounmap(dev, par->mmio_base); | |
805 | pci_release_regions(dev); | |
806 | /* pci_disable_device(dev); */ | |
807 | ||
808 | pci_set_drvdata(dev, NULL); | |
809 | framebuffer_release(info); | |
810 | } | |
811 | } | |
812 | ||
813 | ||
814 | #ifdef CONFIG_PM | |
815 | /* PCI suspend */ | |
816 | ||
817 | static int vt8623_pci_suspend(struct pci_dev* dev, pm_message_t state) | |
818 | { | |
819 | struct fb_info *info = pci_get_drvdata(dev); | |
820 | struct vt8623fb_info *par = info->par; | |
821 | ||
594a8819 | 822 | dev_info(info->device, "suspend\n"); |
558b7bd8 | 823 | |
ac751efa | 824 | console_lock(); |
558b7bd8 OZ |
825 | mutex_lock(&(par->open_lock)); |
826 | ||
827 | if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) { | |
828 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 829 | console_unlock(); |
558b7bd8 OZ |
830 | return 0; |
831 | } | |
832 | ||
833 | fb_set_suspend(info, 1); | |
834 | ||
835 | pci_save_state(dev); | |
836 | pci_disable_device(dev); | |
837 | pci_set_power_state(dev, pci_choose_state(dev, state)); | |
838 | ||
839 | mutex_unlock(&(par->open_lock)); | |
ac751efa | 840 | console_unlock(); |
558b7bd8 OZ |
841 | |
842 | return 0; | |
843 | } | |
844 | ||
845 | ||
846 | /* PCI resume */ | |
847 | ||
848 | static int vt8623_pci_resume(struct pci_dev* dev) | |
849 | { | |
850 | struct fb_info *info = pci_get_drvdata(dev); | |
851 | struct vt8623fb_info *par = info->par; | |
852 | ||
594a8819 | 853 | dev_info(info->device, "resume\n"); |
558b7bd8 | 854 | |
ac751efa | 855 | console_lock(); |
558b7bd8 OZ |
856 | mutex_lock(&(par->open_lock)); |
857 | ||
950d442a JL |
858 | if (par->ref_count == 0) |
859 | goto fail; | |
558b7bd8 OZ |
860 | |
861 | pci_set_power_state(dev, PCI_D0); | |
862 | pci_restore_state(dev); | |
863 | ||
864 | if (pci_enable_device(dev)) | |
865 | goto fail; | |
866 | ||
867 | pci_set_master(dev); | |
868 | ||
869 | vt8623fb_set_par(info); | |
870 | fb_set_suspend(info, 0); | |
871 | ||
558b7bd8 | 872 | fail: |
950d442a | 873 | mutex_unlock(&(par->open_lock)); |
ac751efa | 874 | console_unlock(); |
558b7bd8 OZ |
875 | |
876 | return 0; | |
877 | } | |
878 | #else | |
879 | #define vt8623_pci_suspend NULL | |
880 | #define vt8623_pci_resume NULL | |
881 | #endif /* CONFIG_PM */ | |
882 | ||
883 | /* List of boards that we are trying to support */ | |
884 | ||
885 | static struct pci_device_id vt8623_devices[] __devinitdata = { | |
886 | {PCI_DEVICE(PCI_VENDOR_ID_VIA, 0x3122)}, | |
887 | {0, 0, 0, 0, 0, 0, 0} | |
888 | }; | |
889 | ||
890 | MODULE_DEVICE_TABLE(pci, vt8623_devices); | |
891 | ||
892 | static struct pci_driver vt8623fb_pci_driver = { | |
893 | .name = "vt8623fb", | |
894 | .id_table = vt8623_devices, | |
895 | .probe = vt8623_pci_probe, | |
896 | .remove = __devexit_p(vt8623_pci_remove), | |
897 | .suspend = vt8623_pci_suspend, | |
898 | .resume = vt8623_pci_resume, | |
899 | }; | |
900 | ||
901 | /* Cleanup */ | |
902 | ||
903 | static void __exit vt8623fb_cleanup(void) | |
904 | { | |
905 | pr_debug("vt8623fb: cleaning up\n"); | |
906 | pci_unregister_driver(&vt8623fb_pci_driver); | |
907 | } | |
908 | ||
909 | /* Driver Initialisation */ | |
910 | ||
3552f09a | 911 | static int __init vt8623fb_init(void) |
558b7bd8 OZ |
912 | { |
913 | ||
914 | #ifndef MODULE | |
915 | char *option = NULL; | |
916 | ||
917 | if (fb_get_options("vt8623fb", &option)) | |
918 | return -ENODEV; | |
919 | ||
920 | if (option && *option) | |
cc6c549c | 921 | mode_option = option; |
558b7bd8 OZ |
922 | #endif |
923 | ||
924 | pr_debug("vt8623fb: initializing\n"); | |
925 | return pci_register_driver(&vt8623fb_pci_driver); | |
926 | } | |
927 | ||
928 | /* ------------------------------------------------------------------------- */ | |
929 | ||
930 | /* Modularization */ | |
931 | ||
932 | module_init(vt8623fb_init); | |
933 | module_exit(vt8623fb_cleanup); |