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Merge remote-tracking branch 'char-misc/char-misc-next'
[deliverable/linux.git] / drivers / vme / bridges / vme_tsi148.c
CommitLineData
d22b8ed9
MW		 1/*
2 * Support for the Tundra TSI148 VME-PCI Bridge Chip
3 *
66bd8db5
MW		 4 * Author: Martyn Welch <martyn.welch@ge.com>
5 * Copyright 2008 GE Intelligent Platforms Embedded Systems, Inc.
d22b8ed9
MW		 6 *
7 * Based on work by Tom Armistead and Ajit Prem
8 * Copyright 2004 Motorola Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
d22b8ed9
MW		 16#include <linux/module.h>
17#include <linux/moduleparam.h>
18#include <linux/mm.h>
19#include <linux/types.h>
20#include <linux/errno.h>
21#include <linux/proc_fs.h>
22#include <linux/pci.h>
23#include <linux/poll.h>
24#include <linux/dma-mapping.h>
25#include <linux/interrupt.h>
26#include <linux/spinlock.h>
6af783c8 27#include <linux/sched.h>
5a0e3ad6 28#include <linux/slab.h>
7946328f
MW		 29#include <linux/time.h>
30#include <linux/io.h>
31#include <linux/uaccess.h>
ac1a4f2c 32#include <linux/byteorder/generic.h>
db3b9e99 33#include <linux/vme.h>
d22b8ed9 34
d22b8ed9
MW		 35#include "../vme_bridge.h"
36#include "vme_tsi148.h"
37
d22b8ed9
MW		 38static int tsi148_probe(struct pci_dev *, const struct pci_device_id *);
39static void tsi148_remove(struct pci_dev *);
d22b8ed9
MW		 40
41
29848ac9 42/* Module parameter */
90ab5ee9 43static bool err_chk;
638f199d 44static int geoid;
d22b8ed9 45
584721ca 46static const char driver_name[] = "vme_tsi148";
d22b8ed9 47
c3a09c18 48static const struct pci_device_id tsi148_ids[] = {
d22b8ed9
MW		 49 { PCI_DEVICE(PCI_VENDOR_ID_TUNDRA, PCI_DEVICE_ID_TUNDRA_TSI148) },
50 { },
51};
52
553ebb8e
AIB		 53MODULE_DEVICE_TABLE(pci, tsi148_ids);
54
d22b8ed9
MW		 55static struct pci_driver tsi148_driver = {
56 .name = driver_name,
57 .id_table = tsi148_ids,
58 .probe = tsi148_probe,
59 .remove = tsi148_remove,
60};
61
62static void reg_join(unsigned int high, unsigned int low,
63 unsigned long long *variable)
64{
65 *variable = (unsigned long long)high << 32;
66 *variable |= (unsigned long long)low;
67}
68
69static void reg_split(unsigned long long variable, unsigned int *high,
70 unsigned int *low)
71{
72 *low = (unsigned int)variable & 0xFFFFFFFF;
73 *high = (unsigned int)(variable >> 32);
74}
75
76/*
77 * Wakes up DMA queue.
78 */
29848ac9
MW		 79static u32 tsi148_DMA_irqhandler(struct tsi148_driver *bridge,
80 int channel_mask)
d22b8ed9
MW		 81{
82 u32 serviced = 0;
83
84 if (channel_mask & TSI148_LCSR_INTS_DMA0S) {
886953e9 85 wake_up(&bridge->dma_queue[0]);
d22b8ed9
MW		 86 serviced |= TSI148_LCSR_INTC_DMA0C;
87 }
88 if (channel_mask & TSI148_LCSR_INTS_DMA1S) {
886953e9 89 wake_up(&bridge->dma_queue[1]);
d22b8ed9
MW		 90 serviced |= TSI148_LCSR_INTC_DMA1C;
91 }
92
93 return serviced;
94}
95
96/*
97 * Wake up location monitor queue
98 */
29848ac9 99static u32 tsi148_LM_irqhandler(struct tsi148_driver *bridge, u32 stat)
d22b8ed9
MW		 100{
101 int i;
102 u32 serviced = 0;
103
104 for (i = 0; i < 4; i++) {
7946328f 105 if (stat & TSI148_LCSR_INTS_LMS[i]) {
d22b8ed9 106 /* We only enable interrupts if the callback is set */
fa54b326 107 bridge->lm_callback[i](bridge->lm_data[i]);
d22b8ed9
MW		 108 serviced |= TSI148_LCSR_INTC_LMC[i];
109 }
110 }
111
112 return serviced;
113}
114
115/*
116 * Wake up mail box queue.
117 *
118 * XXX This functionality is not exposed up though API.
119 */
48d9356e 120static u32 tsi148_MB_irqhandler(struct vme_bridge *tsi148_bridge, u32 stat)
d22b8ed9
MW		 121{
122 int i;
123 u32 val;
124 u32 serviced = 0;
48d9356e
MW		 125 struct tsi148_driver *bridge;
126
127 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 128
129 for (i = 0; i < 4; i++) {
7946328f 130 if (stat & TSI148_LCSR_INTS_MBS[i]) {
29848ac9 131 val = ioread32be(bridge->base + TSI148_GCSR_MBOX[i]);
48d9356e
MW		 132 dev_err(tsi148_bridge->parent, "VME Mailbox %d received"
133 ": 0x%x\n", i, val);
d22b8ed9
MW		 134 serviced |= TSI148_LCSR_INTC_MBC[i];
135 }
136 }
137
138 return serviced;
139}
140
141/*
142 * Display error & status message when PERR (PCI) exception interrupt occurs.
143 */
48d9356e 144static u32 tsi148_PERR_irqhandler(struct vme_bridge *tsi148_bridge)
d22b8ed9 145{
48d9356e
MW		 146 struct tsi148_driver *bridge;
147
148 bridge = tsi148_bridge->driver_priv;
149
150 dev_err(tsi148_bridge->parent, "PCI Exception at address: 0x%08x:%08x, "
151 "attributes: %08x\n",
29848ac9
MW		 152 ioread32be(bridge->base + TSI148_LCSR_EDPAU),
153 ioread32be(bridge->base + TSI148_LCSR_EDPAL),
48d9356e
MW		 154 ioread32be(bridge->base + TSI148_LCSR_EDPAT));
155
156 dev_err(tsi148_bridge->parent, "PCI-X attribute reg: %08x, PCI-X split "
157 "completion reg: %08x\n",
29848ac9 158 ioread32be(bridge->base + TSI148_LCSR_EDPXA),
48d9356e 159 ioread32be(bridge->base + TSI148_LCSR_EDPXS));
d22b8ed9 160
29848ac9 161 iowrite32be(TSI148_LCSR_EDPAT_EDPCL, bridge->base + TSI148_LCSR_EDPAT);
d22b8ed9
MW		 162
163 return TSI148_LCSR_INTC_PERRC;
164}
165
166/*
167 * Save address and status when VME error interrupt occurs.
168 */
29848ac9 169static u32 tsi148_VERR_irqhandler(struct vme_bridge *tsi148_bridge)
d22b8ed9
MW		 170{
171 unsigned int error_addr_high, error_addr_low;
172 unsigned long long error_addr;
173 u32 error_attrib;
472f16f3 174 int error_am;
29848ac9
MW		 175 struct tsi148_driver *bridge;
176
177 bridge = tsi148_bridge->driver_priv;
d22b8ed9 178
29848ac9
MW		 179 error_addr_high = ioread32be(bridge->base + TSI148_LCSR_VEAU);
180 error_addr_low = ioread32be(bridge->base + TSI148_LCSR_VEAL);
181 error_attrib = ioread32be(bridge->base + TSI148_LCSR_VEAT);
472f16f3 182 error_am = (error_attrib & TSI148_LCSR_VEAT_AM_M) >> 8;
d22b8ed9
MW		 183
184 reg_join(error_addr_high, error_addr_low, &error_addr);
185
186 /* Check for exception register overflow (we have lost error data) */
7946328f 187 if (error_attrib & TSI148_LCSR_VEAT_VEOF) {
48d9356e
MW		 188 dev_err(tsi148_bridge->parent, "VME Bus Exception Overflow "
189 "Occurred\n");
d22b8ed9
MW		 190 }
191
e2c6393f 192 if (err_chk)
472f16f3 193 vme_bus_error_handler(tsi148_bridge, error_addr, error_am);
e2c6393f 194 else
e31c51e4
MW		 195 dev_err(tsi148_bridge->parent,
196 "VME Bus Error at address: 0x%llx, attributes: %08x\n",
197 error_addr, error_attrib);
d22b8ed9
MW		 198
199 /* Clear Status */
29848ac9 200 iowrite32be(TSI148_LCSR_VEAT_VESCL, bridge->base + TSI148_LCSR_VEAT);
d22b8ed9
MW		 201
202 return TSI148_LCSR_INTC_VERRC;
203}
204
205/*
206 * Wake up IACK queue.
207 */
29848ac9 208static u32 tsi148_IACK_irqhandler(struct tsi148_driver *bridge)
d22b8ed9 209{
886953e9 210 wake_up(&bridge->iack_queue);
d22b8ed9
MW		 211
212 return TSI148_LCSR_INTC_IACKC;
213}
214
215/*
216 * Calling VME bus interrupt callback if provided.
217 */
29848ac9
MW		 218static u32 tsi148_VIRQ_irqhandler(struct vme_bridge *tsi148_bridge,
219 u32 stat)
d22b8ed9
MW		 220{
221 int vec, i, serviced = 0;
29848ac9
MW		 222 struct tsi148_driver *bridge;
223
224 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 225
226 for (i = 7; i > 0; i--) {
227 if (stat & (1 << i)) {
228 /*
7946328f
MW		 229 * Note: Even though the registers are defined as
230 * 32-bits in the spec, we only want to issue 8-bit
231 * IACK cycles on the bus, read from offset 3.
d22b8ed9 232 */
29848ac9 233 vec = ioread8(bridge->base + TSI148_LCSR_VIACK[i] + 3);
d22b8ed9 234
c813f592 235 vme_irq_handler(tsi148_bridge, i, vec);
d22b8ed9
MW		 236
237 serviced |= (1 << i);
238 }
239 }
240
241 return serviced;
242}
243
244/*
245 * Top level interrupt handler. Clears appropriate interrupt status bits and
246 * then calls appropriate sub handler(s).
247 */
29848ac9 248static irqreturn_t tsi148_irqhandler(int irq, void *ptr)
d22b8ed9
MW		 249{
250 u32 stat, enable, serviced = 0;
29848ac9
MW		 251 struct vme_bridge *tsi148_bridge;
252 struct tsi148_driver *bridge;
253
254 tsi148_bridge = ptr;
255
256 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 257
258 /* Determine which interrupts are unmasked and set */
29848ac9
MW		 259 enable = ioread32be(bridge->base + TSI148_LCSR_INTEO);
260 stat = ioread32be(bridge->base + TSI148_LCSR_INTS);
d22b8ed9
MW		 261
262 /* Only look at unmasked interrupts */
263 stat &= enable;
264
7946328f 265 if (unlikely(!stat))
d22b8ed9 266 return IRQ_NONE;
d22b8ed9
MW		 267
268 /* Call subhandlers as appropriate */
269 /* DMA irqs */
270 if (stat & (TSI148_LCSR_INTS_DMA1S | TSI148_LCSR_INTS_DMA0S))
29848ac9 271 serviced |= tsi148_DMA_irqhandler(bridge, stat);
d22b8ed9
MW		 272
273 /* Location monitor irqs */
274 if (stat & (TSI148_LCSR_INTS_LM3S | TSI148_LCSR_INTS_LM2S |
275 TSI148_LCSR_INTS_LM1S | TSI148_LCSR_INTS_LM0S))
29848ac9 276 serviced |= tsi148_LM_irqhandler(bridge, stat);
d22b8ed9
MW		 277
278 /* Mail box irqs */
279 if (stat & (TSI148_LCSR_INTS_MB3S | TSI148_LCSR_INTS_MB2S |
280 TSI148_LCSR_INTS_MB1S | TSI148_LCSR_INTS_MB0S))
48d9356e 281 serviced |= tsi148_MB_irqhandler(tsi148_bridge, stat);
d22b8ed9
MW		 282
283 /* PCI bus error */
284 if (stat & TSI148_LCSR_INTS_PERRS)
48d9356e 285 serviced |= tsi148_PERR_irqhandler(tsi148_bridge);
d22b8ed9
MW		 286
287 /* VME bus error */
288 if (stat & TSI148_LCSR_INTS_VERRS)
29848ac9 289 serviced |= tsi148_VERR_irqhandler(tsi148_bridge);
d22b8ed9
MW		 290
291 /* IACK irq */
292 if (stat & TSI148_LCSR_INTS_IACKS)
29848ac9 293 serviced |= tsi148_IACK_irqhandler(bridge);
d22b8ed9
MW		 294
295 /* VME bus irqs */
296 if (stat & (TSI148_LCSR_INTS_IRQ7S | TSI148_LCSR_INTS_IRQ6S |
297 TSI148_LCSR_INTS_IRQ5S | TSI148_LCSR_INTS_IRQ4S |
298 TSI148_LCSR_INTS_IRQ3S | TSI148_LCSR_INTS_IRQ2S |
299 TSI148_LCSR_INTS_IRQ1S))
29848ac9 300 serviced |= tsi148_VIRQ_irqhandler(tsi148_bridge, stat);
d22b8ed9
MW		 301
302 /* Clear serviced interrupts */
29848ac9 303 iowrite32be(serviced, bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 304
305 return IRQ_HANDLED;
306}
307
29848ac9 308static int tsi148_irq_init(struct vme_bridge *tsi148_bridge)
d22b8ed9
MW		 309{
310 int result;
311 unsigned int tmp;
312 struct pci_dev *pdev;
29848ac9
MW		 313 struct tsi148_driver *bridge;
314
177581fa 315 pdev = to_pci_dev(tsi148_bridge->parent);
d22b8ed9 316
29848ac9 317 bridge = tsi148_bridge->driver_priv;
d22b8ed9 318
d22b8ed9
MW		 319 result = request_irq(pdev->irq,
320 tsi148_irqhandler,
321 IRQF_SHARED,
29848ac9 322 driver_name, tsi148_bridge);
d22b8ed9 323 if (result) {
48d9356e
MW		 324 dev_err(tsi148_bridge->parent, "Can't get assigned pci irq "
325 "vector %02X\n", pdev->irq);
d22b8ed9
MW		 326 return result;
327 }
328
329 /* Enable and unmask interrupts */
330 tmp = TSI148_LCSR_INTEO_DMA1EO | TSI148_LCSR_INTEO_DMA0EO |
331 TSI148_LCSR_INTEO_MB3EO | TSI148_LCSR_INTEO_MB2EO |
332 TSI148_LCSR_INTEO_MB1EO | TSI148_LCSR_INTEO_MB0EO |
333 TSI148_LCSR_INTEO_PERREO | TSI148_LCSR_INTEO_VERREO |
334 TSI148_LCSR_INTEO_IACKEO;
335
29848ac9 336 /* This leaves the following interrupts masked.
d22b8ed9
MW		 337 * TSI148_LCSR_INTEO_VIEEO
338 * TSI148_LCSR_INTEO_SYSFLEO
339 * TSI148_LCSR_INTEO_ACFLEO
340 */
341
342 /* Don't enable Location Monitor interrupts here - they will be
343 * enabled when the location monitors are properly configured and
344 * a callback has been attached.
345 * TSI148_LCSR_INTEO_LM0EO
346 * TSI148_LCSR_INTEO_LM1EO
347 * TSI148_LCSR_INTEO_LM2EO
348 * TSI148_LCSR_INTEO_LM3EO
349 */
350
351 /* Don't enable VME interrupts until we add a handler, else the board
352 * will respond to it and we don't want that unless it knows how to
353 * properly deal with it.
354 * TSI148_LCSR_INTEO_IRQ7EO
355 * TSI148_LCSR_INTEO_IRQ6EO
356 * TSI148_LCSR_INTEO_IRQ5EO
357 * TSI148_LCSR_INTEO_IRQ4EO
358 * TSI148_LCSR_INTEO_IRQ3EO
359 * TSI148_LCSR_INTEO_IRQ2EO
360 * TSI148_LCSR_INTEO_IRQ1EO
361 */
362
363 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
364 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
365
366 return 0;
367}
368
a82ad05e
EC		 369static void tsi148_irq_exit(struct vme_bridge *tsi148_bridge,
370 struct pci_dev *pdev)
d22b8ed9 371{
a82ad05e
EC		 372 struct tsi148_driver *bridge = tsi148_bridge->driver_priv;
373
d22b8ed9 374 /* Turn off interrupts */
29848ac9
MW		 375 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEO);
376 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9
MW		 377
378 /* Clear all interrupts */
29848ac9 379 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 380
381 /* Detach interrupt handler */
a82ad05e 382 free_irq(pdev->irq, tsi148_bridge);
d22b8ed9
MW		 383}
384
385/*
386 * Check to see if an IACk has been received, return true (1) or false (0).
387 */
5ade6c4d 388static int tsi148_iack_received(struct tsi148_driver *bridge)
d22b8ed9
MW		 389{
390 u32 tmp;
391
29848ac9 392 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 393
394 if (tmp & TSI148_LCSR_VICR_IRQS)
395 return 0;
396 else
397 return 1;
398}
399
400/*
c813f592 401 * Configure VME interrupt
d22b8ed9 402 */
5ade6c4d 403static void tsi148_irq_set(struct vme_bridge *tsi148_bridge, int level,
29848ac9 404 int state, int sync)
d22b8ed9 405{
75155020 406 struct pci_dev *pdev;
c813f592 407 u32 tmp;
29848ac9
MW		 408 struct tsi148_driver *bridge;
409
410 bridge = tsi148_bridge->driver_priv;
d22b8ed9 411
c813f592
MW		 412 /* We need to do the ordering differently for enabling and disabling */
413 if (state == 0) {
29848ac9 414 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 415 tmp &= ~TSI148_LCSR_INTEN_IRQEN[level - 1];
29848ac9 416 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
df455175 417
29848ac9 418 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
df455175 419 tmp &= ~TSI148_LCSR_INTEO_IRQEO[level - 1];
29848ac9 420 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
75155020 421
c813f592 422 if (sync != 0) {
177581fa 423 pdev = to_pci_dev(tsi148_bridge->parent);
c813f592
MW		 424 synchronize_irq(pdev->irq);
425 }
426 } else {
29848ac9 427 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
c813f592 428 tmp |= TSI148_LCSR_INTEO_IRQEO[level - 1];
29848ac9 429 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
df455175 430
29848ac9 431 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
c813f592 432 tmp |= TSI148_LCSR_INTEN_IRQEN[level - 1];
29848ac9 433 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
c813f592 434 }
d22b8ed9
MW		 435}
436
437/*
438 * Generate a VME bus interrupt at the requested level & vector. Wait for
439 * interrupt to be acked.
d22b8ed9 440 */
5ade6c4d
EC		 441static int tsi148_irq_generate(struct vme_bridge *tsi148_bridge, int level,
442 int statid)
d22b8ed9
MW		 443{
444 u32 tmp;
29848ac9
MW		 445 struct tsi148_driver *bridge;
446
447 bridge = tsi148_bridge->driver_priv;
d22b8ed9 448
886953e9 449 mutex_lock(&bridge->vme_int);
d22b8ed9
MW		 450
451 /* Read VICR register */
29848ac9 452 tmp = ioread32be(bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 453
454 /* Set Status/ID */
455 tmp = (tmp & ~TSI148_LCSR_VICR_STID_M) |
456 (statid & TSI148_LCSR_VICR_STID_M);
29848ac9 457 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 458
459 /* Assert VMEbus IRQ */
460 tmp = tmp | TSI148_LCSR_VICR_IRQL[level];
29848ac9 461 iowrite32be(tmp, bridge->base + TSI148_LCSR_VICR);
d22b8ed9
MW		 462
463 /* XXX Consider implementing a timeout? */
29848ac9
MW		 464 wait_event_interruptible(bridge->iack_queue,
465 tsi148_iack_received(bridge));
d22b8ed9 466
886953e9 467 mutex_unlock(&bridge->vme_int);
d22b8ed9
MW		 468
469 return 0;
470}
471
d22b8ed9
MW		 472/*
473 * Initialize a slave window with the requested attributes.
474 */
5ade6c4d 475static int tsi148_slave_set(struct vme_slave_resource *image, int enabled,
d22b8ed9 476 unsigned long long vme_base, unsigned long long size,
6af04b06 477 dma_addr_t pci_base, u32 aspace, u32 cycle)
d22b8ed9
MW		 478{
479 unsigned int i, addr = 0, granularity = 0;
480 unsigned int temp_ctl = 0;
481 unsigned int vme_base_low, vme_base_high;
482 unsigned int vme_bound_low, vme_bound_high;
483 unsigned int pci_offset_low, pci_offset_high;
484 unsigned long long vme_bound, pci_offset;
48d9356e 485 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 486 struct tsi148_driver *bridge;
487
48d9356e
MW		 488 tsi148_bridge = image->parent;
489 bridge = tsi148_bridge->driver_priv;
d22b8ed9 490
d22b8ed9
MW		 491 i = image->number;
492
493 switch (aspace) {
494 case VME_A16:
495 granularity = 0x10;
496 addr |= TSI148_LCSR_ITAT_AS_A16;
497 break;
498 case VME_A24:
499 granularity = 0x1000;
500 addr |= TSI148_LCSR_ITAT_AS_A24;
501 break;
502 case VME_A32:
503 granularity = 0x10000;
504 addr |= TSI148_LCSR_ITAT_AS_A32;
505 break;
506 case VME_A64:
507 granularity = 0x10000;
508 addr |= TSI148_LCSR_ITAT_AS_A64;
509 break;
d22b8ed9 510 default:
48d9356e 511 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 512 return -EINVAL;
513 break;
514 }
515
516 /* Convert 64-bit variables to 2x 32-bit variables */
517 reg_split(vme_base, &vme_base_high, &vme_base_low);
518
519 /*
520 * Bound address is a valid address for the window, adjust
521 * accordingly
522 */
523 vme_bound = vme_base + size - granularity;
524 reg_split(vme_bound, &vme_bound_high, &vme_bound_low);
525 pci_offset = (unsigned long long)pci_base - vme_base;
526 reg_split(pci_offset, &pci_offset_high, &pci_offset_low);
527
528 if (vme_base_low & (granularity - 1)) {
48d9356e 529 dev_err(tsi148_bridge->parent, "Invalid VME base alignment\n");
d22b8ed9
MW		 530 return -EINVAL;
531 }
532 if (vme_bound_low & (granularity - 1)) {
48d9356e 533 dev_err(tsi148_bridge->parent, "Invalid VME bound alignment\n");
d22b8ed9
MW		 534 return -EINVAL;
535 }
536 if (pci_offset_low & (granularity - 1)) {
48d9356e
MW		 537 dev_err(tsi148_bridge->parent, "Invalid PCI Offset "
538 "alignment\n");
d22b8ed9
MW		 539 return -EINVAL;
540 }
541
d22b8ed9 542 /* Disable while we are mucking around */
29848ac9 543 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 544 TSI148_LCSR_OFFSET_ITAT);
545 temp_ctl &= ~TSI148_LCSR_ITAT_EN;
29848ac9 546 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 547 TSI148_LCSR_OFFSET_ITAT);
548
549 /* Setup mapping */
29848ac9 550 iowrite32be(vme_base_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 551 TSI148_LCSR_OFFSET_ITSAU);
29848ac9 552 iowrite32be(vme_base_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 553 TSI148_LCSR_OFFSET_ITSAL);
29848ac9 554 iowrite32be(vme_bound_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 555 TSI148_LCSR_OFFSET_ITEAU);
29848ac9 556 iowrite32be(vme_bound_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 557 TSI148_LCSR_OFFSET_ITEAL);
29848ac9 558 iowrite32be(pci_offset_high, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 559 TSI148_LCSR_OFFSET_ITOFU);
29848ac9 560 iowrite32be(pci_offset_low, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 561 TSI148_LCSR_OFFSET_ITOFL);
562
d22b8ed9
MW		 563 /* Setup 2eSST speeds */
564 temp_ctl &= ~TSI148_LCSR_ITAT_2eSSTM_M;
565 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
566 case VME_2eSST160:
567 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_160;
568 break;
569 case VME_2eSST267:
570 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_267;
571 break;
572 case VME_2eSST320:
573 temp_ctl |= TSI148_LCSR_ITAT_2eSSTM_320;
574 break;
575 }
576
577 /* Setup cycle types */
578 temp_ctl &= ~(0x1F << 7);
579 if (cycle & VME_BLT)
580 temp_ctl |= TSI148_LCSR_ITAT_BLT;
581 if (cycle & VME_MBLT)
582 temp_ctl |= TSI148_LCSR_ITAT_MBLT;
583 if (cycle & VME_2eVME)
584 temp_ctl |= TSI148_LCSR_ITAT_2eVME;
585 if (cycle & VME_2eSST)
586 temp_ctl |= TSI148_LCSR_ITAT_2eSST;
587 if (cycle & VME_2eSSTB)
588 temp_ctl |= TSI148_LCSR_ITAT_2eSSTB;
589
590 /* Setup address space */
591 temp_ctl &= ~TSI148_LCSR_ITAT_AS_M;
592 temp_ctl |= addr;
593
594 temp_ctl &= ~0xF;
595 if (cycle & VME_SUPER)
596 temp_ctl |= TSI148_LCSR_ITAT_SUPR ;
597 if (cycle & VME_USER)
598 temp_ctl |= TSI148_LCSR_ITAT_NPRIV;
599 if (cycle & VME_PROG)
600 temp_ctl |= TSI148_LCSR_ITAT_PGM;
601 if (cycle & VME_DATA)
602 temp_ctl |= TSI148_LCSR_ITAT_DATA;
603
604 /* Write ctl reg without enable */
29848ac9 605 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 606 TSI148_LCSR_OFFSET_ITAT);
607
608 if (enabled)
609 temp_ctl |= TSI148_LCSR_ITAT_EN;
610
29848ac9 611 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 612 TSI148_LCSR_OFFSET_ITAT);
613
614 return 0;
615}
616
617/*
618 * Get slave window configuration.
d22b8ed9 619 */
5ade6c4d 620static int tsi148_slave_get(struct vme_slave_resource *image, int *enabled,
d22b8ed9 621 unsigned long long *vme_base, unsigned long long *size,
6af04b06 622 dma_addr_t *pci_base, u32 *aspace, u32 *cycle)
d22b8ed9
MW		 623{
624 unsigned int i, granularity = 0, ctl = 0;
625 unsigned int vme_base_low, vme_base_high;
626 unsigned int vme_bound_low, vme_bound_high;
627 unsigned int pci_offset_low, pci_offset_high;
628 unsigned long long vme_bound, pci_offset;
29848ac9 629 struct tsi148_driver *bridge;
d22b8ed9 630
29848ac9 631 bridge = image->parent->driver_priv;
d22b8ed9
MW		 632
633 i = image->number;
634
635 /* Read registers */
29848ac9 636 ctl = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 637 TSI148_LCSR_OFFSET_ITAT);
638
29848ac9 639 vme_base_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 640 TSI148_LCSR_OFFSET_ITSAU);
29848ac9 641 vme_base_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 642 TSI148_LCSR_OFFSET_ITSAL);
29848ac9 643 vme_bound_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 644 TSI148_LCSR_OFFSET_ITEAU);
29848ac9 645 vme_bound_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 646 TSI148_LCSR_OFFSET_ITEAL);
29848ac9 647 pci_offset_high = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 648 TSI148_LCSR_OFFSET_ITOFU);
29848ac9 649 pci_offset_low = ioread32be(bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9
MW		 650 TSI148_LCSR_OFFSET_ITOFL);
651
652 /* Convert 64-bit variables to 2x 32-bit variables */
653 reg_join(vme_base_high, vme_base_low, vme_base);
654 reg_join(vme_bound_high, vme_bound_low, &vme_bound);
655 reg_join(pci_offset_high, pci_offset_low, &pci_offset);
656
098ced8f 657 *pci_base = (dma_addr_t)(*vme_base + pci_offset);
d22b8ed9
MW		 658
659 *enabled = 0;
660 *aspace = 0;
661 *cycle = 0;
662
663 if (ctl & TSI148_LCSR_ITAT_EN)
664 *enabled = 1;
665
666 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A16) {
667 granularity = 0x10;
668 *aspace |= VME_A16;
669 }
670 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A24) {
671 granularity = 0x1000;
672 *aspace |= VME_A24;
673 }
674 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A32) {
675 granularity = 0x10000;
676 *aspace |= VME_A32;
677 }
678 if ((ctl & TSI148_LCSR_ITAT_AS_M) == TSI148_LCSR_ITAT_AS_A64) {
679 granularity = 0x10000;
680 *aspace |= VME_A64;
681 }
682
683 /* Need granularity before we set the size */
684 *size = (unsigned long long)((vme_bound - *vme_base) + granularity);
685
686
687 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_160)
688 *cycle |= VME_2eSST160;
689 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_267)
690 *cycle |= VME_2eSST267;
691 if ((ctl & TSI148_LCSR_ITAT_2eSSTM_M) == TSI148_LCSR_ITAT_2eSSTM_320)
692 *cycle |= VME_2eSST320;
693
694 if (ctl & TSI148_LCSR_ITAT_BLT)
695 *cycle |= VME_BLT;
696 if (ctl & TSI148_LCSR_ITAT_MBLT)
697 *cycle |= VME_MBLT;
698 if (ctl & TSI148_LCSR_ITAT_2eVME)
699 *cycle |= VME_2eVME;
700 if (ctl & TSI148_LCSR_ITAT_2eSST)
701 *cycle |= VME_2eSST;
702 if (ctl & TSI148_LCSR_ITAT_2eSSTB)
703 *cycle |= VME_2eSSTB;
704
705 if (ctl & TSI148_LCSR_ITAT_SUPR)
706 *cycle |= VME_SUPER;
707 if (ctl & TSI148_LCSR_ITAT_NPRIV)
708 *cycle |= VME_USER;
709 if (ctl & TSI148_LCSR_ITAT_PGM)
710 *cycle |= VME_PROG;
711 if (ctl & TSI148_LCSR_ITAT_DATA)
712 *cycle |= VME_DATA;
713
714 return 0;
715}
716
717/*
718 * Allocate and map PCI Resource
719 */
720static int tsi148_alloc_resource(struct vme_master_resource *image,
721 unsigned long long size)
722{
723 unsigned long long existing_size;
724 int retval = 0;
725 struct pci_dev *pdev;
29848ac9
MW		 726 struct vme_bridge *tsi148_bridge;
727
728 tsi148_bridge = image->parent;
d22b8ed9 729
177581fa 730 pdev = to_pci_dev(tsi148_bridge->parent);
d22b8ed9 731
8fafb476
MW		 732 existing_size = (unsigned long long)(image->bus_resource.end -
733 image->bus_resource.start);
d22b8ed9
MW		 734
735 /* If the existing size is OK, return */
59c22904 736 if ((size != 0) && (existing_size == (size - 1)))
d22b8ed9
MW		 737 return 0;
738
739 if (existing_size != 0) {
740 iounmap(image->kern_base);
741 image->kern_base = NULL;
794a8946 742 kfree(image->bus_resource.name);
886953e9
EC		 743 release_resource(&image->bus_resource);
744 memset(&image->bus_resource, 0, sizeof(struct resource));
d22b8ed9
MW		 745 }
746
59c22904 747 /* Exit here if size is zero */
7946328f 748 if (size == 0)
59c22904 749 return 0;
59c22904 750
8fafb476 751 if (image->bus_resource.name == NULL) {
0aa3f139 752 image->bus_resource.name = kmalloc(VMENAMSIZ+3, GFP_ATOMIC);
8fafb476 753 if (image->bus_resource.name == NULL) {
48d9356e
MW		 754 dev_err(tsi148_bridge->parent, "Unable to allocate "
755 "memory for resource name\n");
d22b8ed9
MW		 756 retval = -ENOMEM;
757 goto err_name;
758 }
759 }
760
8fafb476 761 sprintf((char *)image->bus_resource.name, "%s.%d", tsi148_bridge->name,
d22b8ed9
MW		 762 image->number);
763
8fafb476
MW		 764 image->bus_resource.start = 0;
765 image->bus_resource.end = (unsigned long)size;
766 image->bus_resource.flags = IORESOURCE_MEM;
d22b8ed9
MW		 767
768 retval = pci_bus_alloc_resource(pdev->bus,
da5ae8a9 769 &image->bus_resource, size, 0x10000, PCIBIOS_MIN_MEM,
d22b8ed9
MW		 770 0, NULL, NULL);
771 if (retval) {
48d9356e
MW		 772 dev_err(tsi148_bridge->parent, "Failed to allocate mem "
773 "resource for window %d size 0x%lx start 0x%lx\n",
d22b8ed9 774 image->number, (unsigned long)size,
8fafb476 775 (unsigned long)image->bus_resource.start);
d22b8ed9
MW		 776 goto err_resource;
777 }
778
779 image->kern_base = ioremap_nocache(
8fafb476 780 image->bus_resource.start, size);
d22b8ed9 781 if (image->kern_base == NULL) {
48d9356e 782 dev_err(tsi148_bridge->parent, "Failed to remap resource\n");
d22b8ed9
MW		 783 retval = -ENOMEM;
784 goto err_remap;
785 }
786
787 return 0;
788
d22b8ed9 789err_remap:
886953e9 790 release_resource(&image->bus_resource);
d22b8ed9 791err_resource:
8fafb476 792 kfree(image->bus_resource.name);
886953e9 793 memset(&image->bus_resource, 0, sizeof(struct resource));
d22b8ed9
MW		 794err_name:
795 return retval;
796}
797
798/*
799 * Free and unmap PCI Resource
800 */
801static void tsi148_free_resource(struct vme_master_resource *image)
802{
803 iounmap(image->kern_base);
804 image->kern_base = NULL;
886953e9 805 release_resource(&image->bus_resource);
8fafb476 806 kfree(image->bus_resource.name);
886953e9 807 memset(&image->bus_resource, 0, sizeof(struct resource));
d22b8ed9
MW		 808}
809
810/*
811 * Set the attributes of an outbound window.
812 */
5ade6c4d 813static int tsi148_master_set(struct vme_master_resource *image, int enabled,
6af04b06
MW		 814 unsigned long long vme_base, unsigned long long size, u32 aspace,
815 u32 cycle, u32 dwidth)
d22b8ed9
MW		 816{
817 int retval = 0;
818 unsigned int i;
819 unsigned int temp_ctl = 0;
820 unsigned int pci_base_low, pci_base_high;
821 unsigned int pci_bound_low, pci_bound_high;
822 unsigned int vme_offset_low, vme_offset_high;
823 unsigned long long pci_bound, vme_offset, pci_base;
48d9356e 824 struct vme_bridge *tsi148_bridge;
29848ac9 825 struct tsi148_driver *bridge;
226572b1
JS		 826 struct pci_bus_region region;
827 struct pci_dev *pdev;
29848ac9 828
48d9356e
MW		 829 tsi148_bridge = image->parent;
830
831 bridge = tsi148_bridge->driver_priv;
d22b8ed9 832
177581fa 833 pdev = to_pci_dev(tsi148_bridge->parent);
226572b1 834
d22b8ed9
MW		 835 /* Verify input data */
836 if (vme_base & 0xFFFF) {
48d9356e
MW		 837 dev_err(tsi148_bridge->parent, "Invalid VME Window "
838 "alignment\n");
d22b8ed9
MW		 839 retval = -EINVAL;
840 goto err_window;
841 }
59c22904
MW		 842
843 if ((size == 0) && (enabled != 0)) {
48d9356e
MW		 844 dev_err(tsi148_bridge->parent, "Size must be non-zero for "
845 "enabled windows\n");
d22b8ed9
MW		 846 retval = -EINVAL;
847 goto err_window;
848 }
849
886953e9 850 spin_lock(&image->lock);
d22b8ed9
MW		 851
852 /* Let's allocate the resource here rather than further up the stack as
25985edc 853 * it avoids pushing loads of bus dependent stuff up the stack. If size
59c22904 854 * is zero, any existing resource will be freed.
d22b8ed9
MW		 855 */
856 retval = tsi148_alloc_resource(image, size);
857 if (retval) {
886953e9 858 spin_unlock(&image->lock);
48d9356e 859 dev_err(tsi148_bridge->parent, "Unable to allocate memory for "
59c22904 860 "resource\n");
d22b8ed9
MW		 861 goto err_res;
862 }
863
59c22904
MW		 864 if (size == 0) {
865 pci_base = 0;
866 pci_bound = 0;
867 vme_offset = 0;
868 } else {
226572b1
JS		 869 pcibios_resource_to_bus(pdev->bus, &region,
870 &image->bus_resource);
871 pci_base = region.start;
59c22904
MW		 872
873 /*
874 * Bound address is a valid address for the window, adjust
875 * according to window granularity.
876 */
877 pci_bound = pci_base + (size - 0x10000);
878 vme_offset = vme_base - pci_base;
879 }
d22b8ed9
MW		 880
881 /* Convert 64-bit variables to 2x 32-bit variables */
882 reg_split(pci_base, &pci_base_high, &pci_base_low);
883 reg_split(pci_bound, &pci_bound_high, &pci_bound_low);
884 reg_split(vme_offset, &vme_offset_high, &vme_offset_low);
885
886 if (pci_base_low & 0xFFFF) {
886953e9 887 spin_unlock(&image->lock);
48d9356e 888 dev_err(tsi148_bridge->parent, "Invalid PCI base alignment\n");
d22b8ed9
MW		 889 retval = -EINVAL;
890 goto err_gran;
891 }
892 if (pci_bound_low & 0xFFFF) {
886953e9 893 spin_unlock(&image->lock);
48d9356e 894 dev_err(tsi148_bridge->parent, "Invalid PCI bound alignment\n");
d22b8ed9
MW		 895 retval = -EINVAL;
896 goto err_gran;
897 }
898 if (vme_offset_low & 0xFFFF) {
886953e9 899 spin_unlock(&image->lock);
48d9356e
MW		 900 dev_err(tsi148_bridge->parent, "Invalid VME Offset "
901 "alignment\n");
d22b8ed9
MW		 902 retval = -EINVAL;
903 goto err_gran;
904 }
905
906 i = image->number;
907
908 /* Disable while we are mucking around */
29848ac9 909 temp_ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 910 TSI148_LCSR_OFFSET_OTAT);
911 temp_ctl &= ~TSI148_LCSR_OTAT_EN;
29848ac9 912 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 913 TSI148_LCSR_OFFSET_OTAT);
914
d22b8ed9
MW		 915 /* Setup 2eSST speeds */
916 temp_ctl &= ~TSI148_LCSR_OTAT_2eSSTM_M;
917 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
918 case VME_2eSST160:
919 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_160;
920 break;
921 case VME_2eSST267:
922 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_267;
923 break;
924 case VME_2eSST320:
925 temp_ctl |= TSI148_LCSR_OTAT_2eSSTM_320;
926 break;
927 }
928
929 /* Setup cycle types */
930 if (cycle & VME_BLT) {
931 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
932 temp_ctl |= TSI148_LCSR_OTAT_TM_BLT;
933 }
934 if (cycle & VME_MBLT) {
935 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
936 temp_ctl |= TSI148_LCSR_OTAT_TM_MBLT;
937 }
938 if (cycle & VME_2eVME) {
939 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
940 temp_ctl |= TSI148_LCSR_OTAT_TM_2eVME;
941 }
942 if (cycle & VME_2eSST) {
943 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
944 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSST;
945 }
946 if (cycle & VME_2eSSTB) {
48d9356e
MW		 947 dev_warn(tsi148_bridge->parent, "Currently not setting "
948 "Broadcast Select Registers\n");
d22b8ed9
MW		 949 temp_ctl &= ~TSI148_LCSR_OTAT_TM_M;
950 temp_ctl |= TSI148_LCSR_OTAT_TM_2eSSTB;
951 }
952
953 /* Setup data width */
954 temp_ctl &= ~TSI148_LCSR_OTAT_DBW_M;
955 switch (dwidth) {
956 case VME_D16:
957 temp_ctl |= TSI148_LCSR_OTAT_DBW_16;
958 break;
959 case VME_D32:
960 temp_ctl |= TSI148_LCSR_OTAT_DBW_32;
961 break;
962 default:
886953e9 963 spin_unlock(&image->lock);
48d9356e 964 dev_err(tsi148_bridge->parent, "Invalid data width\n");
d22b8ed9
MW		 965 retval = -EINVAL;
966 goto err_dwidth;
967 }
968
969 /* Setup address space */
970 temp_ctl &= ~TSI148_LCSR_OTAT_AMODE_M;
971 switch (aspace) {
972 case VME_A16:
973 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A16;
974 break;
975 case VME_A24:
976 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A24;
977 break;
978 case VME_A32:
979 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A32;
980 break;
981 case VME_A64:
982 temp_ctl |= TSI148_LCSR_OTAT_AMODE_A64;
983 break;
984 case VME_CRCSR:
985 temp_ctl |= TSI148_LCSR_OTAT_AMODE_CRCSR;
986 break;
987 case VME_USER1:
988 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER1;
989 break;
990 case VME_USER2:
991 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER2;
992 break;
993 case VME_USER3:
994 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER3;
995 break;
996 case VME_USER4:
997 temp_ctl |= TSI148_LCSR_OTAT_AMODE_USER4;
998 break;
999 default:
886953e9 1000 spin_unlock(&image->lock);
48d9356e 1001 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 1002 retval = -EINVAL;
1003 goto err_aspace;
1004 break;
1005 }
1006
1007 temp_ctl &= ~(3<<4);
1008 if (cycle & VME_SUPER)
1009 temp_ctl |= TSI148_LCSR_OTAT_SUP;
1010 if (cycle & VME_PROG)
1011 temp_ctl |= TSI148_LCSR_OTAT_PGM;
1012
1013 /* Setup mapping */
29848ac9 1014 iowrite32be(pci_base_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1015 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1016 iowrite32be(pci_base_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1017 TSI148_LCSR_OFFSET_OTSAL);
29848ac9 1018 iowrite32be(pci_bound_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1019 TSI148_LCSR_OFFSET_OTEAU);
29848ac9 1020 iowrite32be(pci_bound_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1021 TSI148_LCSR_OFFSET_OTEAL);
29848ac9 1022 iowrite32be(vme_offset_high, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1023 TSI148_LCSR_OFFSET_OTOFU);
29848ac9 1024 iowrite32be(vme_offset_low, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1025 TSI148_LCSR_OFFSET_OTOFL);
1026
d22b8ed9 1027 /* Write ctl reg without enable */
29848ac9 1028 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1029 TSI148_LCSR_OFFSET_OTAT);
1030
1031 if (enabled)
1032 temp_ctl |= TSI148_LCSR_OTAT_EN;
1033
29848ac9 1034 iowrite32be(temp_ctl, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1035 TSI148_LCSR_OFFSET_OTAT);
1036
886953e9 1037 spin_unlock(&image->lock);
d22b8ed9
MW		 1038 return 0;
1039
1040err_aspace:
1041err_dwidth:
1042err_gran:
1043 tsi148_free_resource(image);
1044err_res:
1045err_window:
1046 return retval;
1047
1048}
1049
1050/*
1051 * Set the attributes of an outbound window.
1052 *
1053 * XXX Not parsing prefetch information.
1054 */
5ade6c4d 1055static int __tsi148_master_get(struct vme_master_resource *image, int *enabled,
6af04b06
MW		 1056 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1057 u32 *cycle, u32 *dwidth)
d22b8ed9
MW		 1058{
1059 unsigned int i, ctl;
1060 unsigned int pci_base_low, pci_base_high;
1061 unsigned int pci_bound_low, pci_bound_high;
1062 unsigned int vme_offset_low, vme_offset_high;
1063
1064 unsigned long long pci_base, pci_bound, vme_offset;
29848ac9
MW		 1065 struct tsi148_driver *bridge;
1066
1067 bridge = image->parent->driver_priv;
d22b8ed9
MW		 1068
1069 i = image->number;
1070
29848ac9 1071 ctl = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1072 TSI148_LCSR_OFFSET_OTAT);
1073
29848ac9 1074 pci_base_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1075 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1076 pci_base_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1077 TSI148_LCSR_OFFSET_OTSAL);
29848ac9 1078 pci_bound_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1079 TSI148_LCSR_OFFSET_OTEAU);
29848ac9 1080 pci_bound_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1081 TSI148_LCSR_OFFSET_OTEAL);
29848ac9 1082 vme_offset_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1083 TSI148_LCSR_OFFSET_OTOFU);
29848ac9 1084 vme_offset_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1085 TSI148_LCSR_OFFSET_OTOFL);
1086
1087 /* Convert 64-bit variables to 2x 32-bit variables */
1088 reg_join(pci_base_high, pci_base_low, &pci_base);
1089 reg_join(pci_bound_high, pci_bound_low, &pci_bound);
1090 reg_join(vme_offset_high, vme_offset_low, &vme_offset);
1091
1092 *vme_base = pci_base + vme_offset;
1093 *size = (unsigned long long)(pci_bound - pci_base) + 0x10000;
1094
1095 *enabled = 0;
1096 *aspace = 0;
1097 *cycle = 0;
1098 *dwidth = 0;
1099
1100 if (ctl & TSI148_LCSR_OTAT_EN)
1101 *enabled = 1;
1102
1103 /* Setup address space */
1104 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A16)
1105 *aspace |= VME_A16;
1106 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A24)
1107 *aspace |= VME_A24;
1108 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A32)
1109 *aspace |= VME_A32;
1110 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_A64)
1111 *aspace |= VME_A64;
1112 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_CRCSR)
1113 *aspace |= VME_CRCSR;
1114 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER1)
1115 *aspace |= VME_USER1;
1116 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER2)
1117 *aspace |= VME_USER2;
1118 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER3)
1119 *aspace |= VME_USER3;
1120 if ((ctl & TSI148_LCSR_OTAT_AMODE_M) == TSI148_LCSR_OTAT_AMODE_USER4)
1121 *aspace |= VME_USER4;
1122
1123 /* Setup 2eSST speeds */
1124 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_160)
1125 *cycle |= VME_2eSST160;
1126 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_267)
1127 *cycle |= VME_2eSST267;
1128 if ((ctl & TSI148_LCSR_OTAT_2eSSTM_M) == TSI148_LCSR_OTAT_2eSSTM_320)
1129 *cycle |= VME_2eSST320;
1130
1131 /* Setup cycle types */
7946328f 1132 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_SCT)
d22b8ed9 1133 *cycle |= VME_SCT;
7946328f 1134 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_BLT)
d22b8ed9 1135 *cycle |= VME_BLT;
7946328f 1136 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_MBLT)
d22b8ed9 1137 *cycle |= VME_MBLT;
7946328f 1138 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eVME)
d22b8ed9 1139 *cycle |= VME_2eVME;
7946328f 1140 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSST)
d22b8ed9 1141 *cycle |= VME_2eSST;
7946328f 1142 if ((ctl & TSI148_LCSR_OTAT_TM_M) == TSI148_LCSR_OTAT_TM_2eSSTB)
d22b8ed9
MW		 1143 *cycle |= VME_2eSSTB;
1144
1145 if (ctl & TSI148_LCSR_OTAT_SUP)
1146 *cycle |= VME_SUPER;
1147 else
1148 *cycle |= VME_USER;
1149
1150 if (ctl & TSI148_LCSR_OTAT_PGM)
1151 *cycle |= VME_PROG;
1152 else
1153 *cycle |= VME_DATA;
1154
1155 /* Setup data width */
1156 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_16)
1157 *dwidth = VME_D16;
1158 if ((ctl & TSI148_LCSR_OTAT_DBW_M) == TSI148_LCSR_OTAT_DBW_32)
1159 *dwidth = VME_D32;
1160
1161 return 0;
1162}
1163
1164
5ade6c4d 1165static int tsi148_master_get(struct vme_master_resource *image, int *enabled,
6af04b06
MW		 1166 unsigned long long *vme_base, unsigned long long *size, u32 *aspace,
1167 u32 *cycle, u32 *dwidth)
d22b8ed9
MW		 1168{
1169 int retval;
1170
886953e9 1171 spin_lock(&image->lock);
d22b8ed9
MW		 1172
1173 retval = __tsi148_master_get(image, enabled, vme_base, size, aspace,
1174 cycle, dwidth);
1175
886953e9 1176 spin_unlock(&image->lock);
d22b8ed9
MW		 1177
1178 return retval;
1179}
1180
5ade6c4d 1181static ssize_t tsi148_master_read(struct vme_master_resource *image, void *buf,
d22b8ed9
MW		 1182 size_t count, loff_t offset)
1183{
1184 int retval, enabled;
1185 unsigned long long vme_base, size;
6af04b06 1186 u32 aspace, cycle, dwidth;
d3337eb1 1187 struct vme_error_handler *handler = NULL;
29848ac9 1188 struct vme_bridge *tsi148_bridge;
4e8764d9 1189 void __iomem *addr = image->kern_base + offset;
363e2e6f
MW		 1190 unsigned int done = 0;
1191 unsigned int count32;
29848ac9
MW		 1192
1193 tsi148_bridge = image->parent;
d22b8ed9 1194
886953e9 1195 spin_lock(&image->lock);
d22b8ed9 1196
0b049662
DK		 1197 if (err_chk) {
1198 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace,
1199 &cycle, &dwidth);
1200 handler = vme_register_error_handler(tsi148_bridge, aspace,
1201 vme_base + offset, count);
1202 if (!handler) {
1203 spin_unlock(&image->lock);
1204 return -ENOMEM;
1205 }
1206 }
1207
363e2e6f 1208 /* The following code handles VME address alignment. We cannot use
a2a720e1
MW		 1209 * memcpy_xxx here because it may cut data transfers in to 8-bit
1210 * cycles when D16 or D32 cycles are required on the VME bus.
363e2e6f
MW		 1211 * On the other hand, the bridge itself assures that the maximum data
1212 * cycle configured for the transfer is used and splits it
1213 * automatically for non-aligned addresses, so we don't want the
1214 * overhead of needlessly forcing small transfers for the entire cycle.
1215 */
1216 if ((uintptr_t)addr & 0x1) {
1217 *(u8 *)buf = ioread8(addr);
1218 done += 1;
1219 if (done == count)
1220 goto out;
1221 }
f0342e66 1222 if ((uintptr_t)(addr + done) & 0x2) {
363e2e6f
MW		 1223 if ((count - done) < 2) {
1224 *(u8 *)(buf + done) = ioread8(addr + done);
1225 done += 1;
1226 goto out;
1227 } else {
1228 *(u16 *)(buf + done) = ioread16(addr + done);
1229 done += 2;
1230 }
1231 }
1232
1233 count32 = (count - done) & ~0x3;
a2a720e1
MW		 1234 while (done < count32) {
1235 *(u32 *)(buf + done) = ioread32(addr + done);
1236 done += 4;
363e2e6f
MW		 1237 }
1238
1239 if ((count - done) & 0x2) {
1240 *(u16 *)(buf + done) = ioread16(addr + done);
1241 done += 2;
1242 }
1243 if ((count - done) & 0x1) {
1244 *(u8 *)(buf + done) = ioread8(addr + done);
1245 done += 1;
1246 }
1247
1248out:
d22b8ed9
MW		 1249 retval = count;
1250
0b049662
DK		 1251 if (err_chk) {
1252 if (handler->num_errors) {
1253 dev_err(image->parent->parent,
1254 "First VME read error detected an at address 0x%llx\n",
1255 handler->first_error);
1256 retval = handler->first_error - (vme_base + offset);
1257 }
1258 vme_unregister_error_handler(handler);
d22b8ed9
MW		 1259 }
1260
886953e9 1261 spin_unlock(&image->lock);
d22b8ed9
MW		 1262
1263 return retval;
1264}
1265
1266
5ade6c4d 1267static ssize_t tsi148_master_write(struct vme_master_resource *image, void *buf,
d22b8ed9
MW		 1268 size_t count, loff_t offset)
1269{
1270 int retval = 0, enabled;
1271 unsigned long long vme_base, size;
6af04b06 1272 u32 aspace, cycle, dwidth;
4e8764d9 1273 void __iomem *addr = image->kern_base + offset;
363e2e6f
MW		 1274 unsigned int done = 0;
1275 unsigned int count32;
d22b8ed9 1276
d3337eb1 1277 struct vme_error_handler *handler = NULL;
29848ac9
MW		 1278 struct vme_bridge *tsi148_bridge;
1279 struct tsi148_driver *bridge;
1280
1281 tsi148_bridge = image->parent;
1282
1283 bridge = tsi148_bridge->driver_priv;
d22b8ed9 1284
886953e9 1285 spin_lock(&image->lock);
d22b8ed9 1286
0b049662
DK		 1287 if (err_chk) {
1288 __tsi148_master_get(image, &enabled, &vme_base, &size, &aspace,
1289 &cycle, &dwidth);
1290 handler = vme_register_error_handler(tsi148_bridge, aspace,
1291 vme_base + offset, count);
1292 if (!handler) {
1293 spin_unlock(&image->lock);
1294 return -ENOMEM;
1295 }
1296 }
1297
363e2e6f 1298 /* Here we apply for the same strategy we do in master_read
a2a720e1 1299 * function in order to assure the correct cycles.
363e2e6f
MW		 1300 */
1301 if ((uintptr_t)addr & 0x1) {
1302 iowrite8(*(u8 *)buf, addr);
1303 done += 1;
1304 if (done == count)
1305 goto out;
1306 }
f0342e66 1307 if ((uintptr_t)(addr + done) & 0x2) {
363e2e6f
MW		 1308 if ((count - done) < 2) {
1309 iowrite8(*(u8 *)(buf + done), addr + done);
1310 done += 1;
1311 goto out;
1312 } else {
1313 iowrite16(*(u16 *)(buf + done), addr + done);
1314 done += 2;
1315 }
1316 }
1317
1318 count32 = (count - done) & ~0x3;
a2a720e1
MW		 1319 while (done < count32) {
1320 iowrite32(*(u32 *)(buf + done), addr + done);
1321 done += 4;
363e2e6f
MW		 1322 }
1323
1324 if ((count - done) & 0x2) {
1325 iowrite16(*(u16 *)(buf + done), addr + done);
1326 done += 2;
1327 }
1328 if ((count - done) & 0x1) {
1329 iowrite8(*(u8 *)(buf + done), addr + done);
1330 done += 1;
1331 }
1332
1333out:
d22b8ed9
MW		 1334 retval = count;
1335
1336 /*
1337 * Writes are posted. We need to do a read on the VME bus to flush out
25985edc 1338 * all of the writes before we check for errors. We can't guarantee
d22b8ed9
MW		 1339 * that reading the data we have just written is safe. It is believed
1340 * that there isn't any read, write re-ordering, so we can read any
1341 * location in VME space, so lets read the Device ID from the tsi148's
1342 * own registers as mapped into CR/CSR space.
1343 *
1344 * We check for saved errors in the written address range/space.
1345 */
1346
0b049662
DK		 1347 if (err_chk) {
1348 ioread16(bridge->flush_image->kern_base + 0x7F000);
d22b8ed9 1349
0b049662
DK		 1350 if (handler->num_errors) {
1351 dev_warn(tsi148_bridge->parent,
1352 "First VME write error detected an at address 0x%llx\n",
1353 handler->first_error);
1354 retval = handler->first_error - (vme_base + offset);
1355 }
1356 vme_unregister_error_handler(handler);
d22b8ed9
MW		 1357 }
1358
886953e9 1359 spin_unlock(&image->lock);
d22b8ed9
MW		 1360
1361 return retval;
1362}
1363
1364/*
1365 * Perform an RMW cycle on the VME bus.
1366 *
1367 * Requires a previously configured master window, returns final value.
1368 */
5ade6c4d 1369static unsigned int tsi148_master_rmw(struct vme_master_resource *image,
d22b8ed9
MW		 1370 unsigned int mask, unsigned int compare, unsigned int swap,
1371 loff_t offset)
1372{
1373 unsigned long long pci_addr;
1374 unsigned int pci_addr_high, pci_addr_low;
1375 u32 tmp, result;
1376 int i;
29848ac9 1377 struct tsi148_driver *bridge;
d22b8ed9 1378
29848ac9 1379 bridge = image->parent->driver_priv;
d22b8ed9
MW		 1380
1381 /* Find the PCI address that maps to the desired VME address */
1382 i = image->number;
1383
1384 /* Locking as we can only do one of these at a time */
886953e9 1385 mutex_lock(&bridge->vme_rmw);
d22b8ed9
MW		 1386
1387 /* Lock image */
886953e9 1388 spin_lock(&image->lock);
d22b8ed9 1389
29848ac9 1390 pci_addr_high = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9 1391 TSI148_LCSR_OFFSET_OTSAU);
29848ac9 1392 pci_addr_low = ioread32be(bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 1393 TSI148_LCSR_OFFSET_OTSAL);
1394
1395 reg_join(pci_addr_high, pci_addr_low, &pci_addr);
1396 reg_split(pci_addr + offset, &pci_addr_high, &pci_addr_low);
1397
1398 /* Configure registers */
29848ac9
MW		 1399 iowrite32be(mask, bridge->base + TSI148_LCSR_RMWEN);
1400 iowrite32be(compare, bridge->base + TSI148_LCSR_RMWC);
1401 iowrite32be(swap, bridge->base + TSI148_LCSR_RMWS);
1402 iowrite32be(pci_addr_high, bridge->base + TSI148_LCSR_RMWAU);
1403 iowrite32be(pci_addr_low, bridge->base + TSI148_LCSR_RMWAL);
d22b8ed9
MW		 1404
1405 /* Enable RMW */
29848ac9 1406 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9 1407 tmp |= TSI148_LCSR_VMCTRL_RMWEN;
29848ac9 1408 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9
MW		 1409
1410 /* Kick process off with a read to the required address. */
1411 result = ioread32be(image->kern_base + offset);
1412
1413 /* Disable RMW */
29848ac9 1414 tmp = ioread32be(bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9 1415 tmp &= ~TSI148_LCSR_VMCTRL_RMWEN;
29848ac9 1416 iowrite32be(tmp, bridge->base + TSI148_LCSR_VMCTRL);
d22b8ed9 1417
886953e9 1418 spin_unlock(&image->lock);
d22b8ed9 1419
886953e9 1420 mutex_unlock(&bridge->vme_rmw);
d22b8ed9
MW		 1421
1422 return result;
1423}
1424
ac1a4f2c 1425static int tsi148_dma_set_vme_src_attributes(struct device *dev, __be32 *attr,
6af04b06 1426 u32 aspace, u32 cycle, u32 dwidth)
d22b8ed9 1427{
ac1a4f2c
MW		 1428 u32 val;
1429
1430 val = be32_to_cpu(*attr);
1431
d22b8ed9
MW		 1432 /* Setup 2eSST speeds */
1433 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1434 case VME_2eSST160:
ac1a4f2c 1435 val |= TSI148_LCSR_DSAT_2eSSTM_160;
d22b8ed9
MW		 1436 break;
1437 case VME_2eSST267:
ac1a4f2c 1438 val |= TSI148_LCSR_DSAT_2eSSTM_267;
d22b8ed9
MW		 1439 break;
1440 case VME_2eSST320:
ac1a4f2c 1441 val |= TSI148_LCSR_DSAT_2eSSTM_320;
d22b8ed9
MW		 1442 break;
1443 }
1444
1445 /* Setup cycle types */
7946328f 1446 if (cycle & VME_SCT)
ac1a4f2c 1447 val |= TSI148_LCSR_DSAT_TM_SCT;
7946328f
MW		 1448
1449 if (cycle & VME_BLT)
ac1a4f2c 1450 val |= TSI148_LCSR_DSAT_TM_BLT;
7946328f
MW		 1451
1452 if (cycle & VME_MBLT)
ac1a4f2c 1453 val |= TSI148_LCSR_DSAT_TM_MBLT;
7946328f
MW		 1454
1455 if (cycle & VME_2eVME)
ac1a4f2c 1456 val |= TSI148_LCSR_DSAT_TM_2eVME;
7946328f
MW		 1457
1458 if (cycle & VME_2eSST)
ac1a4f2c 1459 val |= TSI148_LCSR_DSAT_TM_2eSST;
7946328f 1460
d22b8ed9 1461 if (cycle & VME_2eSSTB) {
48d9356e
MW		 1462 dev_err(dev, "Currently not setting Broadcast Select "
1463 "Registers\n");
ac1a4f2c 1464 val |= TSI148_LCSR_DSAT_TM_2eSSTB;
d22b8ed9
MW		 1465 }
1466
1467 /* Setup data width */
1468 switch (dwidth) {
1469 case VME_D16:
ac1a4f2c 1470 val |= TSI148_LCSR_DSAT_DBW_16;
d22b8ed9
MW		 1471 break;
1472 case VME_D32:
ac1a4f2c 1473 val |= TSI148_LCSR_DSAT_DBW_32;
d22b8ed9
MW		 1474 break;
1475 default:
48d9356e 1476 dev_err(dev, "Invalid data width\n");
d22b8ed9
MW		 1477 return -EINVAL;
1478 }
1479
1480 /* Setup address space */
1481 switch (aspace) {
1482 case VME_A16:
ac1a4f2c 1483 val |= TSI148_LCSR_DSAT_AMODE_A16;
d22b8ed9
MW		 1484 break;
1485 case VME_A24:
ac1a4f2c 1486 val |= TSI148_LCSR_DSAT_AMODE_A24;
d22b8ed9
MW		 1487 break;
1488 case VME_A32:
ac1a4f2c 1489 val |= TSI148_LCSR_DSAT_AMODE_A32;
d22b8ed9
MW		 1490 break;
1491 case VME_A64:
ac1a4f2c 1492 val |= TSI148_LCSR_DSAT_AMODE_A64;
d22b8ed9
MW		 1493 break;
1494 case VME_CRCSR:
ac1a4f2c 1495 val |= TSI148_LCSR_DSAT_AMODE_CRCSR;
d22b8ed9
MW		 1496 break;
1497 case VME_USER1:
ac1a4f2c 1498 val |= TSI148_LCSR_DSAT_AMODE_USER1;
d22b8ed9
MW		 1499 break;
1500 case VME_USER2:
ac1a4f2c 1501 val |= TSI148_LCSR_DSAT_AMODE_USER2;
d22b8ed9
MW		 1502 break;
1503 case VME_USER3:
ac1a4f2c 1504 val |= TSI148_LCSR_DSAT_AMODE_USER3;
d22b8ed9
MW		 1505 break;
1506 case VME_USER4:
ac1a4f2c 1507 val |= TSI148_LCSR_DSAT_AMODE_USER4;
d22b8ed9
MW		 1508 break;
1509 default:
48d9356e 1510 dev_err(dev, "Invalid address space\n");
d22b8ed9
MW		 1511 return -EINVAL;
1512 break;
1513 }
1514
1515 if (cycle & VME_SUPER)
ac1a4f2c 1516 val |= TSI148_LCSR_DSAT_SUP;
d22b8ed9 1517 if (cycle & VME_PROG)
ac1a4f2c
MW		 1518 val |= TSI148_LCSR_DSAT_PGM;
1519
1520 *attr = cpu_to_be32(val);
d22b8ed9
MW		 1521
1522 return 0;
1523}
1524
ac1a4f2c 1525static int tsi148_dma_set_vme_dest_attributes(struct device *dev, __be32 *attr,
6af04b06 1526 u32 aspace, u32 cycle, u32 dwidth)
d22b8ed9 1527{
ac1a4f2c
MW		 1528 u32 val;
1529
1530 val = be32_to_cpu(*attr);
1531
d22b8ed9
MW		 1532 /* Setup 2eSST speeds */
1533 switch (cycle & (VME_2eSST160 | VME_2eSST267 | VME_2eSST320)) {
1534 case VME_2eSST160:
ac1a4f2c 1535 val |= TSI148_LCSR_DDAT_2eSSTM_160;
d22b8ed9
MW		 1536 break;
1537 case VME_2eSST267:
ac1a4f2c 1538 val |= TSI148_LCSR_DDAT_2eSSTM_267;
d22b8ed9
MW		 1539 break;
1540 case VME_2eSST320:
ac1a4f2c 1541 val |= TSI148_LCSR_DDAT_2eSSTM_320;
d22b8ed9
MW		 1542 break;
1543 }
1544
1545 /* Setup cycle types */
7946328f 1546 if (cycle & VME_SCT)
ac1a4f2c 1547 val |= TSI148_LCSR_DDAT_TM_SCT;
7946328f
MW		 1548
1549 if (cycle & VME_BLT)
ac1a4f2c 1550 val |= TSI148_LCSR_DDAT_TM_BLT;
7946328f
MW		 1551
1552 if (cycle & VME_MBLT)
ac1a4f2c 1553 val |= TSI148_LCSR_DDAT_TM_MBLT;
7946328f
MW		 1554
1555 if (cycle & VME_2eVME)
ac1a4f2c 1556 val |= TSI148_LCSR_DDAT_TM_2eVME;
7946328f
MW		 1557
1558 if (cycle & VME_2eSST)
ac1a4f2c 1559 val |= TSI148_LCSR_DDAT_TM_2eSST;
7946328f 1560
d22b8ed9 1561 if (cycle & VME_2eSSTB) {
48d9356e
MW		 1562 dev_err(dev, "Currently not setting Broadcast Select "
1563 "Registers\n");
ac1a4f2c 1564 val |= TSI148_LCSR_DDAT_TM_2eSSTB;
d22b8ed9
MW		 1565 }
1566
1567 /* Setup data width */
1568 switch (dwidth) {
1569 case VME_D16:
ac1a4f2c 1570 val |= TSI148_LCSR_DDAT_DBW_16;
d22b8ed9
MW		 1571 break;
1572 case VME_D32:
ac1a4f2c 1573 val |= TSI148_LCSR_DDAT_DBW_32;
d22b8ed9
MW		 1574 break;
1575 default:
48d9356e 1576 dev_err(dev, "Invalid data width\n");
d22b8ed9
MW		 1577 return -EINVAL;
1578 }
1579
1580 /* Setup address space */
1581 switch (aspace) {
1582 case VME_A16:
ac1a4f2c 1583 val |= TSI148_LCSR_DDAT_AMODE_A16;
d22b8ed9
MW		 1584 break;
1585 case VME_A24:
ac1a4f2c 1586 val |= TSI148_LCSR_DDAT_AMODE_A24;
d22b8ed9
MW		 1587 break;
1588 case VME_A32:
ac1a4f2c 1589 val |= TSI148_LCSR_DDAT_AMODE_A32;
d22b8ed9
MW		 1590 break;
1591 case VME_A64:
ac1a4f2c 1592 val |= TSI148_LCSR_DDAT_AMODE_A64;
d22b8ed9
MW		 1593 break;
1594 case VME_CRCSR:
ac1a4f2c 1595 val |= TSI148_LCSR_DDAT_AMODE_CRCSR;
d22b8ed9
MW		 1596 break;
1597 case VME_USER1:
ac1a4f2c 1598 val |= TSI148_LCSR_DDAT_AMODE_USER1;
d22b8ed9
MW		 1599 break;
1600 case VME_USER2:
ac1a4f2c 1601 val |= TSI148_LCSR_DDAT_AMODE_USER2;
d22b8ed9
MW		 1602 break;
1603 case VME_USER3:
ac1a4f2c 1604 val |= TSI148_LCSR_DDAT_AMODE_USER3;
d22b8ed9
MW		 1605 break;
1606 case VME_USER4:
ac1a4f2c 1607 val |= TSI148_LCSR_DDAT_AMODE_USER4;
d22b8ed9
MW		 1608 break;
1609 default:
48d9356e 1610 dev_err(dev, "Invalid address space\n");
d22b8ed9
MW		 1611 return -EINVAL;
1612 break;
1613 }
1614
1615 if (cycle & VME_SUPER)
ac1a4f2c 1616 val |= TSI148_LCSR_DDAT_SUP;
d22b8ed9 1617 if (cycle & VME_PROG)
ac1a4f2c
MW		 1618 val |= TSI148_LCSR_DDAT_PGM;
1619
1620 *attr = cpu_to_be32(val);
d22b8ed9
MW		 1621
1622 return 0;
1623}
1624
1625/*
1626 * Add a link list descriptor to the list
ac1a4f2c
MW		 1627 *
1628 * Note: DMA engine expects the DMA descriptor to be big endian.
d22b8ed9 1629 */
5ade6c4d
EC		 1630static int tsi148_dma_list_add(struct vme_dma_list *list,
1631 struct vme_dma_attr *src, struct vme_dma_attr *dest, size_t count)
d22b8ed9
MW		 1632{
1633 struct tsi148_dma_entry *entry, *prev;
ac1a4f2c 1634 u32 address_high, address_low, val;
d22b8ed9
MW		 1635 struct vme_dma_pattern *pattern_attr;
1636 struct vme_dma_pci *pci_attr;
1637 struct vme_dma_vme *vme_attr;
d22b8ed9 1638 int retval = 0;
48d9356e
MW		 1639 struct vme_bridge *tsi148_bridge;
1640
1641 tsi148_bridge = list->parent->parent;
d22b8ed9 1642
bb9ea89e 1643 /* Descriptor must be aligned on 64-bit boundaries */
7946328f 1644 entry = kmalloc(sizeof(struct tsi148_dma_entry), GFP_KERNEL);
d22b8ed9 1645 if (entry == NULL) {
48d9356e
MW		 1646 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
1647 "dma resource structure\n");
d22b8ed9
MW		 1648 retval = -ENOMEM;
1649 goto err_mem;
1650 }
1651
1652 /* Test descriptor alignment */
886953e9 1653 if ((unsigned long)&entry->descriptor & 0x7) {
48d9356e
MW		 1654 dev_err(tsi148_bridge->parent, "Descriptor not aligned to 8 "
1655 "byte boundary as required: %p\n",
886953e9 1656 &entry->descriptor);
d22b8ed9
MW		 1657 retval = -EINVAL;
1658 goto err_align;
1659 }
1660
1661 /* Given we are going to fill out the structure, we probably don't
1662 * need to zero it, but better safe than sorry for now.
1663 */
886953e9 1664 memset(&entry->descriptor, 0, sizeof(struct tsi148_dma_descriptor));
d22b8ed9
MW		 1665
1666 /* Fill out source part */
1667 switch (src->type) {
1668 case VME_DMA_PATTERN:
c4d82fbb 1669 pattern_attr = src->private;
d22b8ed9 1670
ac1a4f2c
MW		 1671 entry->descriptor.dsal = cpu_to_be32(pattern_attr->pattern);
1672
1673 val = TSI148_LCSR_DSAT_TYP_PAT;
1674
d22b8ed9 1675 /* Default behaviour is 32 bit pattern */
7946328f 1676 if (pattern_attr->type & VME_DMA_PATTERN_BYTE)
ac1a4f2c 1677 val |= TSI148_LCSR_DSAT_PSZ;
7946328f 1678
d22b8ed9 1679 /* It seems that the default behaviour is to increment */
7946328f 1680 if ((pattern_attr->type & VME_DMA_PATTERN_INCREMENT) == 0)
ac1a4f2c
MW		 1681 val |= TSI148_LCSR_DSAT_NIN;
1682 entry->descriptor.dsat = cpu_to_be32(val);
d22b8ed9
MW		 1683 break;
1684 case VME_DMA_PCI:
c4d82fbb 1685 pci_attr = src->private;
d22b8ed9
MW		 1686
1687 reg_split((unsigned long long)pci_attr->address, &address_high,
1688 &address_low);
ac1a4f2c
MW		 1689 entry->descriptor.dsau = cpu_to_be32(address_high);
1690 entry->descriptor.dsal = cpu_to_be32(address_low);
1691 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_PCI);
d22b8ed9
MW		 1692 break;
1693 case VME_DMA_VME:
c4d82fbb 1694 vme_attr = src->private;
d22b8ed9
MW		 1695
1696 reg_split((unsigned long long)vme_attr->address, &address_high,
1697 &address_low);
ac1a4f2c
MW		 1698 entry->descriptor.dsau = cpu_to_be32(address_high);
1699 entry->descriptor.dsal = cpu_to_be32(address_low);
1700 entry->descriptor.dsat = cpu_to_be32(TSI148_LCSR_DSAT_TYP_VME);
d22b8ed9
MW		 1701
1702 retval = tsi148_dma_set_vme_src_attributes(
886953e9 1703 tsi148_bridge->parent, &entry->descriptor.dsat,
48d9356e 1704 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
7946328f 1705 if (retval < 0)
d22b8ed9
MW		 1706 goto err_source;
1707 break;
1708 default:
48d9356e 1709 dev_err(tsi148_bridge->parent, "Invalid source type\n");
d22b8ed9
MW		 1710 retval = -EINVAL;
1711 goto err_source;
1712 break;
1713 }
1714
1715 /* Assume last link - this will be over-written by adding another */
ac1a4f2c
MW		 1716 entry->descriptor.dnlau = cpu_to_be32(0);
1717 entry->descriptor.dnlal = cpu_to_be32(TSI148_LCSR_DNLAL_LLA);
d22b8ed9
MW		 1718
1719 /* Fill out destination part */
1720 switch (dest->type) {
1721 case VME_DMA_PCI:
c4d82fbb 1722 pci_attr = dest->private;
d22b8ed9
MW		 1723
1724 reg_split((unsigned long long)pci_attr->address, &address_high,
1725 &address_low);
ac1a4f2c
MW		 1726 entry->descriptor.ddau = cpu_to_be32(address_high);
1727 entry->descriptor.ddal = cpu_to_be32(address_low);
1728 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_PCI);
d22b8ed9
MW		 1729 break;
1730 case VME_DMA_VME:
c4d82fbb 1731 vme_attr = dest->private;
d22b8ed9
MW		 1732
1733 reg_split((unsigned long long)vme_attr->address, &address_high,
1734 &address_low);
ac1a4f2c
MW		 1735 entry->descriptor.ddau = cpu_to_be32(address_high);
1736 entry->descriptor.ddal = cpu_to_be32(address_low);
1737 entry->descriptor.ddat = cpu_to_be32(TSI148_LCSR_DDAT_TYP_VME);
d22b8ed9
MW		 1738
1739 retval = tsi148_dma_set_vme_dest_attributes(
886953e9 1740 tsi148_bridge->parent, &entry->descriptor.ddat,
48d9356e 1741 vme_attr->aspace, vme_attr->cycle, vme_attr->dwidth);
7946328f 1742 if (retval < 0)
d22b8ed9
MW		 1743 goto err_dest;
1744 break;
1745 default:
48d9356e 1746 dev_err(tsi148_bridge->parent, "Invalid destination type\n");
d22b8ed9
MW		 1747 retval = -EINVAL;
1748 goto err_dest;
1749 break;
1750 }
1751
1752 /* Fill out count */
ac1a4f2c 1753 entry->descriptor.dcnt = cpu_to_be32((u32)count);
d22b8ed9
MW		 1754
1755 /* Add to list */
886953e9 1756 list_add_tail(&entry->list, &list->entries);
d22b8ed9 1757
b2383c90
DK		 1758 entry->dma_handle = dma_map_single(tsi148_bridge->parent,
1759 &entry->descriptor,
1760 sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
1761 if (dma_mapping_error(tsi148_bridge->parent, entry->dma_handle)) {
1762 dev_err(tsi148_bridge->parent, "DMA mapping error\n");
1763 retval = -EINVAL;
1764 goto err_dma;
1765 }
1766
d22b8ed9 1767 /* Fill out previous descriptors "Next Address" */
886953e9 1768 if (entry->list.prev != &list->entries) {
ac1a4f2c
MW		 1769 reg_split((unsigned long long)entry->dma_handle, &address_high,
1770 &address_low);
b2383c90
DK		 1771 prev = list_entry(entry->list.prev, struct tsi148_dma_entry,
1772 list);
f656eaee
DK		 1773 prev->descriptor.dnlau = cpu_to_be32(address_high);
1774 prev->descriptor.dnlal = cpu_to_be32(address_low);
ac1a4f2c 1775
d22b8ed9
MW		 1776 }
1777
1778 return 0;
1779
b2383c90 1780err_dma:
d22b8ed9
MW		 1781err_dest:
1782err_source:
1783err_align:
1784 kfree(entry);
1785err_mem:
1786 return retval;
1787}
1788
1789/*
1790 * Check to see if the provided DMA channel is busy.
1791 */
29848ac9 1792static int tsi148_dma_busy(struct vme_bridge *tsi148_bridge, int channel)
d22b8ed9
MW		 1793{
1794 u32 tmp;
29848ac9
MW		 1795 struct tsi148_driver *bridge;
1796
1797 bridge = tsi148_bridge->driver_priv;
d22b8ed9 1798
29848ac9 1799 tmp = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
d22b8ed9
MW		 1800 TSI148_LCSR_OFFSET_DSTA);
1801
1802 if (tmp & TSI148_LCSR_DSTA_BSY)
1803 return 0;
1804 else
1805 return 1;
1806
1807}
1808
1809/*
1810 * Execute a previously generated link list
1811 *
1812 * XXX Need to provide control register configuration.
1813 */
5ade6c4d 1814static int tsi148_dma_list_exec(struct vme_dma_list *list)
d22b8ed9
MW		 1815{
1816 struct vme_dma_resource *ctrlr;
75c66b6d 1817 int channel, retval;
d22b8ed9 1818 struct tsi148_dma_entry *entry;
d22b8ed9
MW		 1819 u32 bus_addr_high, bus_addr_low;
1820 u32 val, dctlreg = 0;
48d9356e 1821 struct vme_bridge *tsi148_bridge;
29848ac9 1822 struct tsi148_driver *bridge;
d22b8ed9
MW		 1823
1824 ctrlr = list->parent;
1825
48d9356e
MW		 1826 tsi148_bridge = ctrlr->parent;
1827
1828 bridge = tsi148_bridge->driver_priv;
29848ac9 1829
886953e9 1830 mutex_lock(&ctrlr->mtx);
d22b8ed9
MW		 1831
1832 channel = ctrlr->number;
1833
886953e9 1834 if (!list_empty(&ctrlr->running)) {
d22b8ed9
MW		 1835 /*
1836 * XXX We have an active DMA transfer and currently haven't
1837 * sorted out the mechanism for "pending" DMA transfers.
1838 * Return busy.
1839 */
1840 /* Need to add to pending here */
886953e9 1841 mutex_unlock(&ctrlr->mtx);
d22b8ed9
MW		 1842 return -EBUSY;
1843 } else {
886953e9 1844 list_add(&list->list, &ctrlr->running);
d22b8ed9 1845 }
d22b8ed9
MW		 1846
1847 /* Get first bus address and write into registers */
886953e9 1848 entry = list_first_entry(&list->entries, struct tsi148_dma_entry,
d22b8ed9
MW		 1849 list);
1850
886953e9 1851 mutex_unlock(&ctrlr->mtx);
d22b8ed9 1852
3abc48ae 1853 reg_split(entry->dma_handle, &bus_addr_high, &bus_addr_low);
d22b8ed9 1854
29848ac9 1855 iowrite32be(bus_addr_high, bridge->base +
d22b8ed9 1856 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAU);
29848ac9 1857 iowrite32be(bus_addr_low, bridge->base +
d22b8ed9
MW		 1858 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DNLAL);
1859
ac1a4f2c
MW		 1860 dctlreg = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
1861 TSI148_LCSR_OFFSET_DCTL);
1862
d22b8ed9 1863 /* Start the operation */
29848ac9 1864 iowrite32be(dctlreg | TSI148_LCSR_DCTL_DGO, bridge->base +
d22b8ed9
MW		 1865 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1866
75c66b6d 1867 retval = wait_event_interruptible(bridge->dma_queue[channel],
29848ac9 1868 tsi148_dma_busy(ctrlr->parent, channel));
ac1a4f2c 1869
75c66b6d
DK		 1870 if (retval) {
1871 iowrite32be(dctlreg | TSI148_LCSR_DCTL_ABT, bridge->base +
1872 TSI148_LCSR_DMA[channel] + TSI148_LCSR_OFFSET_DCTL);
1873 /* Wait for the operation to abort */
1874 wait_event(bridge->dma_queue[channel],
1875 tsi148_dma_busy(ctrlr->parent, channel));
1876 retval = -EINTR;
1877 goto exit;
1878 }
1879
d22b8ed9
MW		 1880 /*
1881 * Read status register, this register is valid until we kick off a
1882 * new transfer.
1883 */
29848ac9 1884 val = ioread32be(bridge->base + TSI148_LCSR_DMA[channel] +
d22b8ed9
MW		 1885 TSI148_LCSR_OFFSET_DSTA);
1886
1887 if (val & TSI148_LCSR_DSTA_VBE) {
48d9356e 1888 dev_err(tsi148_bridge->parent, "DMA Error. DSTA=%08X\n", val);
d22b8ed9
MW		 1889 retval = -EIO;
1890 }
1891
75c66b6d 1892exit:
d22b8ed9 1893 /* Remove list from running list */
886953e9
EC		 1894 mutex_lock(&ctrlr->mtx);
1895 list_del(&list->list);
1896 mutex_unlock(&ctrlr->mtx);
d22b8ed9
MW		 1897
1898 return retval;
1899}
1900
1901/*
1902 * Clean up a previously generated link list
1903 *
1904 * We have a separate function, don't assume that the chain can't be reused.
1905 */
5ade6c4d 1906static int tsi148_dma_list_empty(struct vme_dma_list *list)
d22b8ed9
MW		 1907{
1908 struct list_head *pos, *temp;
7946328f 1909 struct tsi148_dma_entry *entry;
d22b8ed9 1910
3abc48ae
MW		 1911 struct vme_bridge *tsi148_bridge = list->parent->parent;
1912
d22b8ed9 1913 /* detach and free each entry */
886953e9 1914 list_for_each_safe(pos, temp, &list->entries) {
d22b8ed9
MW		 1915 list_del(pos);
1916 entry = list_entry(pos, struct tsi148_dma_entry, list);
3abc48ae
MW		 1917
1918 dma_unmap_single(tsi148_bridge->parent, entry->dma_handle,
1919 sizeof(struct tsi148_dma_descriptor), DMA_TO_DEVICE);
d22b8ed9
MW		 1920 kfree(entry);
1921 }
1922
7946328f 1923 return 0;
d22b8ed9
MW		 1924}
1925
1926/*
1927 * All 4 location monitors reside at the same base - this is therefore a
1928 * system wide configuration.
1929 *
1930 * This does not enable the LM monitor - that should be done when the first
1931 * callback is attached and disabled when the last callback is removed.
1932 */
5ade6c4d 1933static int tsi148_lm_set(struct vme_lm_resource *lm, unsigned long long lm_base,
6af04b06 1934 u32 aspace, u32 cycle)
d22b8ed9
MW		 1935{
1936 u32 lm_base_high, lm_base_low, lm_ctl = 0;
1937 int i;
48d9356e 1938 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 1939 struct tsi148_driver *bridge;
1940
48d9356e
MW		 1941 tsi148_bridge = lm->parent;
1942
1943 bridge = tsi148_bridge->driver_priv;
d22b8ed9 1944
886953e9 1945 mutex_lock(&lm->mtx);
d22b8ed9
MW		 1946
1947 /* If we already have a callback attached, we can't move it! */
42fb5031 1948 for (i = 0; i < lm->monitors; i++) {
29848ac9 1949 if (bridge->lm_callback[i] != NULL) {
886953e9 1950 mutex_unlock(&lm->mtx);
48d9356e
MW		 1951 dev_err(tsi148_bridge->parent, "Location monitor "
1952 "callback attached, can't reset\n");
d22b8ed9
MW		 1953 return -EBUSY;
1954 }
1955 }
1956
1957 switch (aspace) {
1958 case VME_A16:
1959 lm_ctl |= TSI148_LCSR_LMAT_AS_A16;
1960 break;
1961 case VME_A24:
1962 lm_ctl |= TSI148_LCSR_LMAT_AS_A24;
1963 break;
1964 case VME_A32:
1965 lm_ctl |= TSI148_LCSR_LMAT_AS_A32;
1966 break;
1967 case VME_A64:
1968 lm_ctl |= TSI148_LCSR_LMAT_AS_A64;
1969 break;
1970 default:
886953e9 1971 mutex_unlock(&lm->mtx);
48d9356e 1972 dev_err(tsi148_bridge->parent, "Invalid address space\n");
d22b8ed9
MW		 1973 return -EINVAL;
1974 break;
1975 }
1976
1977 if (cycle & VME_SUPER)
1978 lm_ctl |= TSI148_LCSR_LMAT_SUPR ;
1979 if (cycle & VME_USER)
1980 lm_ctl |= TSI148_LCSR_LMAT_NPRIV;
1981 if (cycle & VME_PROG)
1982 lm_ctl |= TSI148_LCSR_LMAT_PGM;
1983 if (cycle & VME_DATA)
1984 lm_ctl |= TSI148_LCSR_LMAT_DATA;
1985
1986 reg_split(lm_base, &lm_base_high, &lm_base_low);
1987
29848ac9
MW		 1988 iowrite32be(lm_base_high, bridge->base + TSI148_LCSR_LMBAU);
1989 iowrite32be(lm_base_low, bridge->base + TSI148_LCSR_LMBAL);
1990 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 1991
886953e9 1992 mutex_unlock(&lm->mtx);
d22b8ed9
MW		 1993
1994 return 0;
1995}
1996
1997/* Get configuration of the callback monitor and return whether it is enabled
1998 * or disabled.
1999 */
5ade6c4d 2000static int tsi148_lm_get(struct vme_lm_resource *lm,
6af04b06 2001 unsigned long long *lm_base, u32 *aspace, u32 *cycle)
d22b8ed9
MW		 2002{
2003 u32 lm_base_high, lm_base_low, lm_ctl, enabled = 0;
29848ac9
MW		 2004 struct tsi148_driver *bridge;
2005
2006 bridge = lm->parent->driver_priv;
d22b8ed9 2007
886953e9 2008 mutex_lock(&lm->mtx);
d22b8ed9 2009
29848ac9
MW		 2010 lm_base_high = ioread32be(bridge->base + TSI148_LCSR_LMBAU);
2011 lm_base_low = ioread32be(bridge->base + TSI148_LCSR_LMBAL);
2012 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2013
2014 reg_join(lm_base_high, lm_base_low, lm_base);
2015
2016 if (lm_ctl & TSI148_LCSR_LMAT_EN)
2017 enabled = 1;
2018
7946328f 2019 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A16)
d22b8ed9 2020 *aspace |= VME_A16;
7946328f
MW		 2021
2022 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A24)
d22b8ed9 2023 *aspace |= VME_A24;
7946328f
MW		 2024
2025 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A32)
d22b8ed9 2026 *aspace |= VME_A32;
7946328f
MW		 2027
2028 if ((lm_ctl & TSI148_LCSR_LMAT_AS_M) == TSI148_LCSR_LMAT_AS_A64)
d22b8ed9 2029 *aspace |= VME_A64;
7946328f 2030
d22b8ed9
MW		 2031
2032 if (lm_ctl & TSI148_LCSR_LMAT_SUPR)
2033 *cycle |= VME_SUPER;
2034 if (lm_ctl & TSI148_LCSR_LMAT_NPRIV)
2035 *cycle |= VME_USER;
2036 if (lm_ctl & TSI148_LCSR_LMAT_PGM)
2037 *cycle |= VME_PROG;
2038 if (lm_ctl & TSI148_LCSR_LMAT_DATA)
2039 *cycle |= VME_DATA;
2040
886953e9 2041 mutex_unlock(&lm->mtx);
d22b8ed9
MW		 2042
2043 return enabled;
2044}
2045
2046/*
2047 * Attach a callback to a specific location monitor.
2048 *
2049 * Callback will be passed the monitor triggered.
2050 */
5ade6c4d 2051static int tsi148_lm_attach(struct vme_lm_resource *lm, int monitor,
fa54b326 2052 void (*callback)(void *), void *data)
d22b8ed9
MW		 2053{
2054 u32 lm_ctl, tmp;
48d9356e 2055 struct vme_bridge *tsi148_bridge;
29848ac9
MW		 2056 struct tsi148_driver *bridge;
2057
48d9356e
MW		 2058 tsi148_bridge = lm->parent;
2059
2060 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2061
886953e9 2062 mutex_lock(&lm->mtx);
d22b8ed9
MW		 2063
2064 /* Ensure that the location monitor is configured - need PGM or DATA */
29848ac9 2065 lm_ctl = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 2066 if ((lm_ctl & (TSI148_LCSR_LMAT_PGM | TSI148_LCSR_LMAT_DATA)) == 0) {
886953e9 2067 mutex_unlock(&lm->mtx);
48d9356e
MW		 2068 dev_err(tsi148_bridge->parent, "Location monitor not properly "
2069 "configured\n");
d22b8ed9
MW		 2070 return -EINVAL;
2071 }
2072
2073 /* Check that a callback isn't already attached */
29848ac9 2074 if (bridge->lm_callback[monitor] != NULL) {
886953e9 2075 mutex_unlock(&lm->mtx);
48d9356e 2076 dev_err(tsi148_bridge->parent, "Existing callback attached\n");
d22b8ed9
MW		 2077 return -EBUSY;
2078 }
2079
2080 /* Attach callback */
29848ac9 2081 bridge->lm_callback[monitor] = callback;
fa54b326 2082 bridge->lm_data[monitor] = data;
d22b8ed9
MW		 2083
2084 /* Enable Location Monitor interrupt */
29848ac9 2085 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2086 tmp |= TSI148_LCSR_INTEN_LMEN[monitor];
29848ac9 2087 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2088
29848ac9 2089 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
d22b8ed9 2090 tmp |= TSI148_LCSR_INTEO_LMEO[monitor];
29848ac9 2091 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
d22b8ed9
MW		 2092
2093 /* Ensure that global Location Monitor Enable set */
2094 if ((lm_ctl & TSI148_LCSR_LMAT_EN) == 0) {
2095 lm_ctl |= TSI148_LCSR_LMAT_EN;
29848ac9 2096 iowrite32be(lm_ctl, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2097 }
2098
886953e9 2099 mutex_unlock(&lm->mtx);
d22b8ed9
MW		 2100
2101 return 0;
2102}
2103
2104/*
2105 * Detach a callback function forn a specific location monitor.
2106 */
5ade6c4d 2107static int tsi148_lm_detach(struct vme_lm_resource *lm, int monitor)
d22b8ed9
MW		 2108{
2109 u32 lm_en, tmp;
29848ac9
MW		 2110 struct tsi148_driver *bridge;
2111
2112 bridge = lm->parent->driver_priv;
d22b8ed9 2113
886953e9 2114 mutex_lock(&lm->mtx);
d22b8ed9
MW		 2115
2116 /* Disable Location Monitor and ensure previous interrupts are clear */
29848ac9 2117 lm_en = ioread32be(bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2118 lm_en &= ~TSI148_LCSR_INTEN_LMEN[monitor];
29848ac9 2119 iowrite32be(lm_en, bridge->base + TSI148_LCSR_INTEN);
d22b8ed9 2120
29848ac9 2121 tmp = ioread32be(bridge->base + TSI148_LCSR_INTEO);
d22b8ed9 2122 tmp &= ~TSI148_LCSR_INTEO_LMEO[monitor];
29848ac9 2123 iowrite32be(tmp, bridge->base + TSI148_LCSR_INTEO);
d22b8ed9
MW		 2124
2125 iowrite32be(TSI148_LCSR_INTC_LMC[monitor],
29848ac9 2126 bridge->base + TSI148_LCSR_INTC);
d22b8ed9
MW		 2127
2128 /* Detach callback */
29848ac9 2129 bridge->lm_callback[monitor] = NULL;
fa54b326 2130 bridge->lm_data[monitor] = NULL;
d22b8ed9
MW		 2131
2132 /* If all location monitors disabled, disable global Location Monitor */
2133 if ((lm_en & (TSI148_LCSR_INTS_LM0S | TSI148_LCSR_INTS_LM1S |
2134 TSI148_LCSR_INTS_LM2S | TSI148_LCSR_INTS_LM3S)) == 0) {
29848ac9 2135 tmp = ioread32be(bridge->base + TSI148_LCSR_LMAT);
d22b8ed9 2136 tmp &= ~TSI148_LCSR_LMAT_EN;
29848ac9 2137 iowrite32be(tmp, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2138 }
2139
886953e9 2140 mutex_unlock(&lm->mtx);
d22b8ed9
MW		 2141
2142 return 0;
2143}
2144
2145/*
2146 * Determine Geographical Addressing
2147 */
5ade6c4d 2148static int tsi148_slot_get(struct vme_bridge *tsi148_bridge)
d22b8ed9 2149{
7946328f 2150 u32 slot = 0;
29848ac9
MW		 2151 struct tsi148_driver *bridge;
2152
2153 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2154
638f199d 2155 if (!geoid) {
29848ac9 2156 slot = ioread32be(bridge->base + TSI148_LCSR_VSTAT);
638f199d
MW		 2157 slot = slot & TSI148_LCSR_VSTAT_GA_M;
2158 } else
2159 slot = geoid;
2160
d22b8ed9
MW		 2161 return (int)slot;
2162}
2163
8a508ff4 2164static void *tsi148_alloc_consistent(struct device *parent, size_t size,
7f58f025
MV		 2165 dma_addr_t *dma)
2166{
2167 struct pci_dev *pdev;
2168
2169 /* Find pci_dev container of dev */
177581fa 2170 pdev = to_pci_dev(parent);
7f58f025
MV		 2171
2172 return pci_alloc_consistent(pdev, size, dma);
2173}
2174
8a508ff4
HS		 2175static void tsi148_free_consistent(struct device *parent, size_t size,
2176 void *vaddr, dma_addr_t dma)
7f58f025
MV		 2177{
2178 struct pci_dev *pdev;
2179
2180 /* Find pci_dev container of dev */
177581fa 2181 pdev = to_pci_dev(parent);
7f58f025
MV		 2182
2183 pci_free_consistent(pdev, size, vaddr, dma);
2184}
2185
d22b8ed9
MW		 2186/*
2187 * Configure CR/CSR space
2188 *
2189 * Access to the CR/CSR can be configured at power-up. The location of the
2190 * CR/CSR registers in the CR/CSR address space is determined by the boards
2191 * Auto-ID or Geographic address. This function ensures that the window is
2192 * enabled at an offset consistent with the boards geopgraphic address.
2193 *
2194 * Each board has a 512kB window, with the highest 4kB being used for the
2195 * boards registers, this means there is a fix length 508kB window which must
2196 * be mapped onto PCI memory.
2197 */
29848ac9
MW		 2198static int tsi148_crcsr_init(struct vme_bridge *tsi148_bridge,
2199 struct pci_dev *pdev)
d22b8ed9
MW		 2200{
2201 u32 cbar, crat, vstat;
2202 u32 crcsr_bus_high, crcsr_bus_low;
2203 int retval;
29848ac9
MW		 2204 struct tsi148_driver *bridge;
2205
2206 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 2207
2208 /* Allocate mem for CR/CSR image */
88b2608c
JP		 2209 bridge->crcsr_kernel = pci_zalloc_consistent(pdev, VME_CRCSR_BUF_SIZE,
2210 &bridge->crcsr_bus);
29848ac9 2211 if (bridge->crcsr_kernel == NULL) {
48d9356e
MW		 2212 dev_err(tsi148_bridge->parent, "Failed to allocate memory for "
2213 "CR/CSR image\n");
d22b8ed9
MW		 2214 return -ENOMEM;
2215 }
2216
29848ac9 2217 reg_split(bridge->crcsr_bus, &crcsr_bus_high, &crcsr_bus_low);
d22b8ed9 2218
29848ac9
MW		 2219 iowrite32be(crcsr_bus_high, bridge->base + TSI148_LCSR_CROU);
2220 iowrite32be(crcsr_bus_low, bridge->base + TSI148_LCSR_CROL);
d22b8ed9
MW		 2221
2222 /* Ensure that the CR/CSR is configured at the correct offset */
29848ac9 2223 cbar = ioread32be(bridge->base + TSI148_CBAR);
d22b8ed9
MW		 2224 cbar = (cbar & TSI148_CRCSR_CBAR_M)>>3;
2225
29848ac9 2226 vstat = tsi148_slot_get(tsi148_bridge);
d22b8ed9
MW		 2227
2228 if (cbar != vstat) {
638f199d 2229 cbar = vstat;
48d9356e 2230 dev_info(tsi148_bridge->parent, "Setting CR/CSR offset\n");
29848ac9 2231 iowrite32be(cbar<<3, bridge->base + TSI148_CBAR);
d22b8ed9 2232 }
48d9356e 2233 dev_info(tsi148_bridge->parent, "CR/CSR Offset: %d\n", cbar);
d22b8ed9 2234
29848ac9 2235 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
2981795c
MW		 2236 if (crat & TSI148_LCSR_CRAT_EN)
2237 dev_info(tsi148_bridge->parent, "CR/CSR already enabled\n");
2238 else {
48d9356e 2239 dev_info(tsi148_bridge->parent, "Enabling CR/CSR space\n");
d22b8ed9 2240 iowrite32be(crat | TSI148_LCSR_CRAT_EN,
29848ac9 2241 bridge->base + TSI148_LCSR_CRAT);
2981795c 2242 }
d22b8ed9
MW		 2243
2244 /* If we want flushed, error-checked writes, set up a window
2245 * over the CR/CSR registers. We read from here to safely flush
2246 * through VME writes.
2247 */
7946328f 2248 if (err_chk) {
29848ac9
MW		 2249 retval = tsi148_master_set(bridge->flush_image, 1,
2250 (vstat * 0x80000), 0x80000, VME_CRCSR, VME_SCT,
2251 VME_D16);
d22b8ed9 2252 if (retval)
48d9356e
MW		 2253 dev_err(tsi148_bridge->parent, "Configuring flush image"
2254 " failed\n");
d22b8ed9
MW		 2255 }
2256
2257 return 0;
2258
2259}
2260
29848ac9
MW		 2261static void tsi148_crcsr_exit(struct vme_bridge *tsi148_bridge,
2262 struct pci_dev *pdev)
d22b8ed9
MW		 2263{
2264 u32 crat;
29848ac9
MW		 2265 struct tsi148_driver *bridge;
2266
2267 bridge = tsi148_bridge->driver_priv;
d22b8ed9
MW		 2268
2269 /* Turn off CR/CSR space */
29848ac9 2270 crat = ioread32be(bridge->base + TSI148_LCSR_CRAT);
d22b8ed9 2271 iowrite32be(crat & ~TSI148_LCSR_CRAT_EN,
29848ac9 2272 bridge->base + TSI148_LCSR_CRAT);
d22b8ed9
MW		 2273
2274 /* Free image */
29848ac9
MW		 2275 iowrite32be(0, bridge->base + TSI148_LCSR_CROU);
2276 iowrite32be(0, bridge->base + TSI148_LCSR_CROL);
d22b8ed9 2277
29848ac9
MW		 2278 pci_free_consistent(pdev, VME_CRCSR_BUF_SIZE, bridge->crcsr_kernel,
2279 bridge->crcsr_bus);
d22b8ed9
MW		 2280}
2281
2282static int tsi148_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2283{
2284 int retval, i, master_num;
2285 u32 data;
b49c32ba 2286 struct list_head *pos = NULL, *n;
29848ac9
MW		 2287 struct vme_bridge *tsi148_bridge;
2288 struct tsi148_driver *tsi148_device;
d22b8ed9
MW		 2289 struct vme_master_resource *master_image;
2290 struct vme_slave_resource *slave_image;
2291 struct vme_dma_resource *dma_ctrlr;
42fb5031 2292 struct vme_lm_resource *lm;
d22b8ed9
MW		 2293
2294 /* If we want to support more than one of each bridge, we need to
2295 * dynamically generate this so we get one per device
2296 */
7a6cb0d5 2297 tsi148_bridge = kzalloc(sizeof(struct vme_bridge), GFP_KERNEL);
d22b8ed9
MW		 2298 if (tsi148_bridge == NULL) {
2299 dev_err(&pdev->dev, "Failed to allocate memory for device "
2300 "structure\n");
2301 retval = -ENOMEM;
2302 goto err_struct;
2303 }
326071b3 2304 vme_init_bridge(tsi148_bridge);
d22b8ed9 2305
7a6cb0d5 2306 tsi148_device = kzalloc(sizeof(struct tsi148_driver), GFP_KERNEL);
29848ac9
MW		 2307 if (tsi148_device == NULL) {
2308 dev_err(&pdev->dev, "Failed to allocate memory for device "
2309 "structure\n");
2310 retval = -ENOMEM;
2311 goto err_driver;
2312 }
2313
29848ac9
MW		 2314 tsi148_bridge->driver_priv = tsi148_device;
2315
d22b8ed9
MW		 2316 /* Enable the device */
2317 retval = pci_enable_device(pdev);
2318 if (retval) {
2319 dev_err(&pdev->dev, "Unable to enable device\n");
2320 goto err_enable;
2321 }
2322
2323 /* Map Registers */
2324 retval = pci_request_regions(pdev, driver_name);
2325 if (retval) {
2326 dev_err(&pdev->dev, "Unable to reserve resources\n");
2327 goto err_resource;
2328 }
2329
2330 /* map registers in BAR 0 */
29848ac9
MW		 2331 tsi148_device->base = ioremap_nocache(pci_resource_start(pdev, 0),
2332 4096);
2333 if (!tsi148_device->base) {
d22b8ed9
MW		 2334 dev_err(&pdev->dev, "Unable to remap CRG region\n");
2335 retval = -EIO;
2336 goto err_remap;
2337 }
2338
2339 /* Check to see if the mapping worked out */
29848ac9 2340 data = ioread32(tsi148_device->base + TSI148_PCFS_ID) & 0x0000FFFF;
d22b8ed9
MW		 2341 if (data != PCI_VENDOR_ID_TUNDRA) {
2342 dev_err(&pdev->dev, "CRG region check failed\n");
2343 retval = -EIO;
2344 goto err_test;
2345 }
2346
2347 /* Initialize wait queues & mutual exclusion flags */
886953e9
EC		 2348 init_waitqueue_head(&tsi148_device->dma_queue[0]);
2349 init_waitqueue_head(&tsi148_device->dma_queue[1]);
2350 init_waitqueue_head(&tsi148_device->iack_queue);
2351 mutex_init(&tsi148_device->vme_int);
2352 mutex_init(&tsi148_device->vme_rmw);
d22b8ed9 2353
886953e9 2354 tsi148_bridge->parent = &pdev->dev;
d22b8ed9
MW		 2355 strcpy(tsi148_bridge->name, driver_name);
2356
2357 /* Setup IRQ */
2358 retval = tsi148_irq_init(tsi148_bridge);
2359 if (retval != 0) {
2360 dev_err(&pdev->dev, "Chip Initialization failed.\n");
2361 goto err_irq;
2362 }
2363
2364 /* If we are going to flush writes, we need to read from the VME bus.
2365 * We need to do this safely, thus we read the devices own CR/CSR
2366 * register. To do this we must set up a window in CR/CSR space and
2367 * hence have one less master window resource available.
2368 */
2369 master_num = TSI148_MAX_MASTER;
7946328f 2370 if (err_chk) {
d22b8ed9 2371 master_num--;
29848ac9 2372
32414878 2373 tsi148_device->flush_image =
29848ac9
MW		 2374 kmalloc(sizeof(struct vme_master_resource), GFP_KERNEL);
2375 if (tsi148_device->flush_image == NULL) {
d22b8ed9
MW		 2376 dev_err(&pdev->dev, "Failed to allocate memory for "
2377 "flush resource structure\n");
2378 retval = -ENOMEM;
2379 goto err_master;
2380 }
29848ac9 2381 tsi148_device->flush_image->parent = tsi148_bridge;
886953e9 2382 spin_lock_init(&tsi148_device->flush_image->lock);
29848ac9
MW		 2383 tsi148_device->flush_image->locked = 1;
2384 tsi148_device->flush_image->number = master_num;
886953e9 2385 memset(&tsi148_device->flush_image->bus_resource, 0,
d22b8ed9 2386 sizeof(struct resource));
29848ac9 2387 tsi148_device->flush_image->kern_base = NULL;
d22b8ed9
MW		 2388 }
2389
2390 /* Add master windows to list */
d22b8ed9 2391 for (i = 0; i < master_num; i++) {
7946328f
MW		 2392 master_image = kmalloc(sizeof(struct vme_master_resource),
2393 GFP_KERNEL);
d22b8ed9
MW		 2394 if (master_image == NULL) {
2395 dev_err(&pdev->dev, "Failed to allocate memory for "
2396 "master resource structure\n");
2397 retval = -ENOMEM;
2398 goto err_master;
2399 }
2400 master_image->parent = tsi148_bridge;
886953e9 2401 spin_lock_init(&master_image->lock);
d22b8ed9
MW		 2402 master_image->locked = 0;
2403 master_image->number = i;
2404 master_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
08e03c26
MW		 2405 VME_A64 | VME_CRCSR | VME_USER1 | VME_USER2 |
2406 VME_USER3 | VME_USER4;
d22b8ed9
MW		 2407 master_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2408 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2409 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2410 VME_PROG | VME_DATA;
2411 master_image->width_attr = VME_D16 | VME_D32;
886953e9 2412 memset(&master_image->bus_resource, 0,
d22b8ed9
MW		 2413 sizeof(struct resource));
2414 master_image->kern_base = NULL;
886953e9
EC		 2415 list_add_tail(&master_image->list,
2416 &tsi148_bridge->master_resources);
d22b8ed9
MW		 2417 }
2418
2419 /* Add slave windows to list */
d22b8ed9 2420 for (i = 0; i < TSI148_MAX_SLAVE; i++) {
7946328f
MW		 2421 slave_image = kmalloc(sizeof(struct vme_slave_resource),
2422 GFP_KERNEL);
d22b8ed9
MW		 2423 if (slave_image == NULL) {
2424 dev_err(&pdev->dev, "Failed to allocate memory for "
2425 "slave resource structure\n");
2426 retval = -ENOMEM;
2427 goto err_slave;
2428 }
2429 slave_image->parent = tsi148_bridge;
886953e9 2430 mutex_init(&slave_image->mtx);
d22b8ed9
MW		 2431 slave_image->locked = 0;
2432 slave_image->number = i;
2433 slave_image->address_attr = VME_A16 | VME_A24 | VME_A32 |
08e03c26 2434 VME_A64;
d22b8ed9
MW		 2435 slave_image->cycle_attr = VME_SCT | VME_BLT | VME_MBLT |
2436 VME_2eVME | VME_2eSST | VME_2eSSTB | VME_2eSST160 |
2437 VME_2eSST267 | VME_2eSST320 | VME_SUPER | VME_USER |
2438 VME_PROG | VME_DATA;
886953e9
EC		 2439 list_add_tail(&slave_image->list,
2440 &tsi148_bridge->slave_resources);
d22b8ed9
MW		 2441 }
2442
2443 /* Add dma engines to list */
d22b8ed9 2444 for (i = 0; i < TSI148_MAX_DMA; i++) {
7946328f
MW		 2445 dma_ctrlr = kmalloc(sizeof(struct vme_dma_resource),
2446 GFP_KERNEL);
d22b8ed9
MW		 2447 if (dma_ctrlr == NULL) {
2448 dev_err(&pdev->dev, "Failed to allocate memory for "
2449 "dma resource structure\n");
2450 retval = -ENOMEM;
2451 goto err_dma;
2452 }
2453 dma_ctrlr->parent = tsi148_bridge;
886953e9 2454 mutex_init(&dma_ctrlr->mtx);
d22b8ed9
MW		 2455 dma_ctrlr->locked = 0;
2456 dma_ctrlr->number = i;
4f723df4
MW		 2457 dma_ctrlr->route_attr = VME_DMA_VME_TO_MEM |
2458 VME_DMA_MEM_TO_VME | VME_DMA_VME_TO_VME |
2459 VME_DMA_MEM_TO_MEM | VME_DMA_PATTERN_TO_VME |
2460 VME_DMA_PATTERN_TO_MEM;
886953e9
EC		 2461 INIT_LIST_HEAD(&dma_ctrlr->pending);
2462 INIT_LIST_HEAD(&dma_ctrlr->running);
2463 list_add_tail(&dma_ctrlr->list,
2464 &tsi148_bridge->dma_resources);
d22b8ed9
MW		 2465 }
2466
42fb5031 2467 /* Add location monitor to list */
42fb5031
MW		 2468 lm = kmalloc(sizeof(struct vme_lm_resource), GFP_KERNEL);
2469 if (lm == NULL) {
2470 dev_err(&pdev->dev, "Failed to allocate memory for "
2471 "location monitor resource structure\n");
2472 retval = -ENOMEM;
2473 goto err_lm;
2474 }
2475 lm->parent = tsi148_bridge;
886953e9 2476 mutex_init(&lm->mtx);
42fb5031
MW		 2477 lm->locked = 0;
2478 lm->number = 1;
2479 lm->monitors = 4;
886953e9 2480 list_add_tail(&lm->list, &tsi148_bridge->lm_resources);
42fb5031 2481
d22b8ed9
MW		 2482 tsi148_bridge->slave_get = tsi148_slave_get;
2483 tsi148_bridge->slave_set = tsi148_slave_set;
2484 tsi148_bridge->master_get = tsi148_master_get;
2485 tsi148_bridge->master_set = tsi148_master_set;
2486 tsi148_bridge->master_read = tsi148_master_read;
2487 tsi148_bridge->master_write = tsi148_master_write;
2488 tsi148_bridge->master_rmw = tsi148_master_rmw;
2489 tsi148_bridge->dma_list_add = tsi148_dma_list_add;
2490 tsi148_bridge->dma_list_exec = tsi148_dma_list_exec;
2491 tsi148_bridge->dma_list_empty = tsi148_dma_list_empty;
c813f592
MW		 2492 tsi148_bridge->irq_set = tsi148_irq_set;
2493 tsi148_bridge->irq_generate = tsi148_irq_generate;
d22b8ed9
MW		 2494 tsi148_bridge->lm_set = tsi148_lm_set;
2495 tsi148_bridge->lm_get = tsi148_lm_get;
2496 tsi148_bridge->lm_attach = tsi148_lm_attach;
2497 tsi148_bridge->lm_detach = tsi148_lm_detach;
2498 tsi148_bridge->slot_get = tsi148_slot_get;
7f58f025
MV		 2499 tsi148_bridge->alloc_consistent = tsi148_alloc_consistent;
2500 tsi148_bridge->free_consistent = tsi148_free_consistent;
d22b8ed9 2501
29848ac9 2502 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9 2503 dev_info(&pdev->dev, "Board is%s the VME system controller\n",
7946328f 2504 (data & TSI148_LCSR_VSTAT_SCONS) ? "" : " not");
29848ac9 2505 if (!geoid)
638f199d
MW		 2506 dev_info(&pdev->dev, "VME geographical address is %d\n",
2507 data & TSI148_LCSR_VSTAT_GA_M);
29848ac9 2508 else
638f199d
MW		 2509 dev_info(&pdev->dev, "VME geographical address is set to %d\n",
2510 geoid);
29848ac9 2511
d22b8ed9
MW		 2512 dev_info(&pdev->dev, "VME Write and flush and error check is %s\n",
2513 err_chk ? "enabled" : "disabled");
2514
0686ab7a
WY		 2515 retval = tsi148_crcsr_init(tsi148_bridge, pdev);
2516 if (retval) {
d22b8ed9
MW		 2517 dev_err(&pdev->dev, "CR/CSR configuration failed.\n");
2518 goto err_crcsr;
4839737b 2519 }
d22b8ed9 2520
d22b8ed9
MW		 2521 retval = vme_register_bridge(tsi148_bridge);
2522 if (retval != 0) {
2523 dev_err(&pdev->dev, "Chip Registration failed.\n");
2524 goto err_reg;
2525 }
2526
29848ac9
MW		 2527 pci_set_drvdata(pdev, tsi148_bridge);
2528
d22b8ed9 2529 /* Clear VME bus "board fail", and "power-up reset" lines */
29848ac9 2530 data = ioread32be(tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9
MW		 2531 data &= ~TSI148_LCSR_VSTAT_BRDFL;
2532 data |= TSI148_LCSR_VSTAT_CPURST;
29848ac9 2533 iowrite32be(data, tsi148_device->base + TSI148_LCSR_VSTAT);
d22b8ed9
MW		 2534
2535 return 0;
2536
d22b8ed9 2537err_reg:
29848ac9 2538 tsi148_crcsr_exit(tsi148_bridge, pdev);
d22b8ed9 2539err_crcsr:
42fb5031
MW		 2540err_lm:
2541 /* resources are stored in link list */
b49c32ba 2542 list_for_each_safe(pos, n, &tsi148_bridge->lm_resources) {
42fb5031
MW		 2543 lm = list_entry(pos, struct vme_lm_resource, list);
2544 list_del(pos);
2545 kfree(lm);
2546 }
d22b8ed9
MW		 2547err_dma:
2548 /* resources are stored in link list */
b49c32ba 2549 list_for_each_safe(pos, n, &tsi148_bridge->dma_resources) {
d22b8ed9
MW		 2550 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2551 list_del(pos);
2552 kfree(dma_ctrlr);
2553 }
2554err_slave:
2555 /* resources are stored in link list */
b49c32ba 2556 list_for_each_safe(pos, n, &tsi148_bridge->slave_resources) {
d22b8ed9
MW		 2557 slave_image = list_entry(pos, struct vme_slave_resource, list);
2558 list_del(pos);
2559 kfree(slave_image);
2560 }
2561err_master:
2562 /* resources are stored in link list */
b49c32ba 2563 list_for_each_safe(pos, n, &tsi148_bridge->master_resources) {
7946328f
MW		 2564 master_image = list_entry(pos, struct vme_master_resource,
2565 list);
d22b8ed9
MW		 2566 list_del(pos);
2567 kfree(master_image);
2568 }
2569
a82ad05e 2570 tsi148_irq_exit(tsi148_bridge, pdev);
d22b8ed9
MW		 2571err_irq:
2572err_test:
29848ac9 2573 iounmap(tsi148_device->base);
d22b8ed9
MW		 2574err_remap:
2575 pci_release_regions(pdev);
2576err_resource:
2577 pci_disable_device(pdev);
2578err_enable:
29848ac9
MW		 2579 kfree(tsi148_device);
2580err_driver:
d22b8ed9
MW		 2581 kfree(tsi148_bridge);
2582err_struct:
2583 return retval;
2584
2585}
2586
2587static void tsi148_remove(struct pci_dev *pdev)
2588{
2589 struct list_head *pos = NULL;
b558ba2f 2590 struct list_head *tmplist;
d22b8ed9
MW		 2591 struct vme_master_resource *master_image;
2592 struct vme_slave_resource *slave_image;
2593 struct vme_dma_resource *dma_ctrlr;
2594 int i;
29848ac9
MW		 2595 struct tsi148_driver *bridge;
2596 struct vme_bridge *tsi148_bridge = pci_get_drvdata(pdev);
2597
2598 bridge = tsi148_bridge->driver_priv;
d22b8ed9 2599
d22b8ed9 2600
29848ac9 2601 dev_dbg(&pdev->dev, "Driver is being unloaded.\n");
d22b8ed9
MW		 2602
2603 /*
2604 * Shutdown all inbound and outbound windows.
2605 */
2606 for (i = 0; i < 8; i++) {
29848ac9 2607 iowrite32be(0, bridge->base + TSI148_LCSR_IT[i] +
d22b8ed9 2608 TSI148_LCSR_OFFSET_ITAT);
29848ac9 2609 iowrite32be(0, bridge->base + TSI148_LCSR_OT[i] +
d22b8ed9
MW		 2610 TSI148_LCSR_OFFSET_OTAT);
2611 }
2612
2613 /*
2614 * Shutdown Location monitor.
2615 */
29848ac9 2616 iowrite32be(0, bridge->base + TSI148_LCSR_LMAT);
d22b8ed9
MW		 2617
2618 /*
2619 * Shutdown CRG map.
2620 */
29848ac9 2621 iowrite32be(0, bridge->base + TSI148_LCSR_CSRAT);
d22b8ed9
MW		 2622
2623 /*
2624 * Clear error status.
2625 */
29848ac9
MW		 2626 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_EDPAT);
2627 iowrite32be(0xFFFFFFFF, bridge->base + TSI148_LCSR_VEAT);
2628 iowrite32be(0x07000700, bridge->base + TSI148_LCSR_PSTAT);
d22b8ed9
MW		 2629
2630 /*
2631 * Remove VIRQ interrupt (if any)
2632 */
29848ac9
MW		 2633 if (ioread32be(bridge->base + TSI148_LCSR_VICR) & 0x800)
2634 iowrite32be(0x8000, bridge->base + TSI148_LCSR_VICR);
d22b8ed9 2635
d22b8ed9
MW		 2636 /*
2637 * Map all Interrupts to PCI INTA
2638 */
29848ac9
MW		 2639 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM1);
2640 iowrite32be(0x0, bridge->base + TSI148_LCSR_INTM2);
d22b8ed9 2641
a82ad05e 2642 tsi148_irq_exit(tsi148_bridge, pdev);
d22b8ed9
MW		 2643
2644 vme_unregister_bridge(tsi148_bridge);
2645
29848ac9 2646 tsi148_crcsr_exit(tsi148_bridge, pdev);
d22b8ed9
MW		 2647
2648 /* resources are stored in link list */
b558ba2f 2649 list_for_each_safe(pos, tmplist, &tsi148_bridge->dma_resources) {
d22b8ed9
MW		 2650 dma_ctrlr = list_entry(pos, struct vme_dma_resource, list);
2651 list_del(pos);
2652 kfree(dma_ctrlr);
2653 }
2654
2655 /* resources are stored in link list */
b558ba2f 2656 list_for_each_safe(pos, tmplist, &tsi148_bridge->slave_resources) {
d22b8ed9
MW		 2657 slave_image = list_entry(pos, struct vme_slave_resource, list);
2658 list_del(pos);
2659 kfree(slave_image);
2660 }
2661
2662 /* resources are stored in link list */
b558ba2f 2663 list_for_each_safe(pos, tmplist, &tsi148_bridge->master_resources) {
638f199d
MW		 2664 master_image = list_entry(pos, struct vme_master_resource,
2665 list);
d22b8ed9
MW		 2666 list_del(pos);
2667 kfree(master_image);
2668 }
2669
29848ac9 2670 iounmap(bridge->base);
d22b8ed9
MW		 2671
2672 pci_release_regions(pdev);
2673
2674 pci_disable_device(pdev);
2675
29848ac9
MW		 2676 kfree(tsi148_bridge->driver_priv);
2677
d22b8ed9
MW		 2678 kfree(tsi148_bridge);
2679}
2680
01c07143 2681module_pci_driver(tsi148_driver);
d22b8ed9
MW		 2682
2683MODULE_PARM_DESC(err_chk, "Check for VME errors on reads and writes");
2684module_param(err_chk, bool, 0);
2685
638f199d
MW		 2686MODULE_PARM_DESC(geoid, "Override geographical addressing");
2687module_param(geoid, int, 0);
2688
d22b8ed9
MW		 2689MODULE_DESCRIPTION("VME driver for the Tundra Tempe VME bridge");
2690MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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