[deliverable/linux.git] / drivers / w1 / masters / omap_hdq.c

/*
 * drivers/w1/masters/omap_hdq.c
 *
 * Copyright (C) 2007,2012 Texas Instruments, Inc.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 *
 */
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sched.h>
#include <linux/pm_runtime.h>

#include "../w1.h"
#include "../w1_int.h"

#define	MOD_NAME	"OMAP_HDQ:"

#define OMAP_HDQ_REVISION			0x00
#define OMAP_HDQ_TX_DATA			0x04
#define OMAP_HDQ_RX_DATA			0x08
#define OMAP_HDQ_CTRL_STATUS			0x0c
#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK	(1<<6)
#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE	(1<<5)
#define OMAP_HDQ_CTRL_STATUS_GO			(1<<4)
#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION	(1<<2)
#define OMAP_HDQ_CTRL_STATUS_DIR		(1<<1)
#define OMAP_HDQ_CTRL_STATUS_MODE		(1<<0)
#define OMAP_HDQ_INT_STATUS			0x10
#define OMAP_HDQ_INT_STATUS_TXCOMPLETE		(1<<2)
#define OMAP_HDQ_INT_STATUS_RXCOMPLETE		(1<<1)
#define OMAP_HDQ_INT_STATUS_TIMEOUT		(1<<0)
#define OMAP_HDQ_SYSCONFIG			0x14
#define OMAP_HDQ_SYSCONFIG_SOFTRESET		(1<<1)
#define OMAP_HDQ_SYSCONFIG_AUTOIDLE		(1<<0)
#define OMAP_HDQ_SYSSTATUS			0x18
#define OMAP_HDQ_SYSSTATUS_RESETDONE		(1<<0)

#define OMAP_HDQ_FLAG_CLEAR			0
#define OMAP_HDQ_FLAG_SET			1
#define OMAP_HDQ_TIMEOUT			(HZ/5)

#define OMAP_HDQ_MAX_USER			4

static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
static int w1_id;

struct hdq_data {
	struct device		*dev;
	void __iomem		*hdq_base;
	/* lock status update */
	struct  mutex		hdq_mutex;
	int			hdq_usecount;
	u8			hdq_irqstatus;
	/* device lock */
	spinlock_t		hdq_spinlock;
	/*
	 * Used to control the call to omap_hdq_get and omap_hdq_put.
	 * HDQ Protocol: Write the CMD|REG_address first, followed by
	 * the data wrire or read.
	 */
	int			init_trans;
};

static int omap_hdq_probe(struct platform_device *pdev);
static int omap_hdq_remove(struct platform_device *pdev);

static struct platform_driver omap_hdq_driver = {
	.probe =	omap_hdq_probe,
	.remove =	omap_hdq_remove,
	.driver =	{
		.name =	"omap_hdq",
	},
};

static u8 omap_w1_read_byte(void *_hdq);
static void omap_w1_write_byte(void *_hdq, u8 byte);
static u8 omap_w1_reset_bus(void *_hdq);
static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
		u8 search_type,	w1_slave_found_callback slave_found);


static struct w1_bus_master omap_w1_master = {
	.read_byte	= omap_w1_read_byte,
	.write_byte	= omap_w1_write_byte,
	.reset_bus	= omap_w1_reset_bus,
	.search		= omap_w1_search_bus,
};

/* HDQ register I/O routines */
static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
{
	return __raw_readl(hdq_data->hdq_base + offset);
}

static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
{
	__raw_writel(val, hdq_data->hdq_base + offset);
}

static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
			u8 val, u8 mask)
{
	u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
			| (val & mask);
	__raw_writel(new_val, hdq_data->hdq_base + offset);

	return new_val;
}

/*
 * Wait for one or more bits in flag change.
 * HDQ_FLAG_SET: wait until any bit in the flag is set.
 * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
 * return 0 on success and -ETIMEDOUT in the case of timeout.
 */
static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
		u8 flag, u8 flag_set, u8 *status)
{
	int ret = 0;
	unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;

	if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
		/* wait for the flag clear */
		while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
			&& time_before(jiffies, timeout)) {
			schedule_timeout_uninterruptible(1);
		}
		if (*status & flag)
			ret = -ETIMEDOUT;
	} else if (flag_set == OMAP_HDQ_FLAG_SET) {
		/* wait for the flag set */
		while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
			&& time_before(jiffies, timeout)) {
			schedule_timeout_uninterruptible(1);
		}
		if (!(*status & flag))
			ret = -ETIMEDOUT;
	} else
		return -EINVAL;

	return ret;
}

/* write out a byte and fill *status with HDQ_INT_STATUS */
static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
{
	int ret;
	u8 tmp_status;
	unsigned long irqflags;

	*status = 0;

	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
	/* clear interrupt flags via a dummy read */
	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
	/* ISR loads it with new INT_STATUS */
	hdq_data->hdq_irqstatus = 0;
	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);

	hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);

	/* set the GO bit */
	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
		OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
	/* wait for the TXCOMPLETE bit */
	ret = wait_event_timeout(hdq_wait_queue,
		hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
	if (ret == 0) {
		dev_dbg(hdq_data->dev, "TX wait elapsed\n");
		ret = -ETIMEDOUT;
		goto out;
	}

	*status = hdq_data->hdq_irqstatus;
	/* check irqstatus */
	if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
		dev_dbg(hdq_data->dev, "timeout waiting for"
			" TXCOMPLETE/RXCOMPLETE, %x", *status);
		ret = -ETIMEDOUT;
		goto out;
	}

	/* wait for the GO bit return to zero */
	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
			OMAP_HDQ_CTRL_STATUS_GO,
			OMAP_HDQ_FLAG_CLEAR, &tmp_status);
	if (ret) {
		dev_dbg(hdq_data->dev, "timeout waiting GO bit"
			" return to zero, %x", tmp_status);
	}

out:
	return ret;
}

/* HDQ Interrupt service routine */
static irqreturn_t hdq_isr(int irq, void *_hdq)
{
	struct hdq_data *hdq_data = _hdq;
	unsigned long irqflags;

	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
	hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
	dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);

	if (hdq_data->hdq_irqstatus &
		(OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
		| OMAP_HDQ_INT_STATUS_TIMEOUT)) {
		/* wake up sleeping process */
		wake_up(&hdq_wait_queue);
	}

	return IRQ_HANDLED;
}

/* HDQ Mode: always return success */
static u8 omap_w1_reset_bus(void *_hdq)
{
	return 0;
}

/* W1 search callback function */
static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
		u8 search_type, w1_slave_found_callback slave_found)
{
	u64 module_id, rn_le, cs, id;

	if (w1_id)
		module_id = w1_id;
	else
		module_id = 0x1;

	rn_le = cpu_to_le64(module_id);
	/*
	 * HDQ might not obey truly the 1-wire spec.
	 * So calculate CRC based on module parameter.
	 */
	cs = w1_calc_crc8((u8 *)&rn_le, 7);
	id = (cs << 56) | module_id;

	slave_found(master_dev, id);
}

static int _omap_hdq_reset(struct hdq_data *hdq_data)
{
	int ret;
	u8 tmp_status;

	hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
	/*
	 * Select HDQ mode & enable clocks.
	 * It is observed that INT flags can't be cleared via a read and GO/INIT
	 * won't return to zero if interrupt is disabled. So we always enable
	 * interrupt.
	 */
	hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
		OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
		OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);

	/* wait for reset to complete */
	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
		OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
	if (ret)
		dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
				tmp_status);
	else {
		hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
			OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
			OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
		hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
			OMAP_HDQ_SYSCONFIG_AUTOIDLE);
	}

	return ret;
}

/* Issue break pulse to the device */
static int omap_hdq_break(struct hdq_data *hdq_data)
{
	int ret = 0;
	u8 tmp_status;
	unsigned long irqflags;

	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	if (ret < 0) {
		dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
		ret = -EINTR;
		goto rtn;
	}

	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
	/* clear interrupt flags via a dummy read */
	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
	/* ISR loads it with new INT_STATUS */
	hdq_data->hdq_irqstatus = 0;
	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);

	/* set the INIT and GO bit */
	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
		OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
		OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
		OMAP_HDQ_CTRL_STATUS_GO);

	/* wait for the TIMEOUT bit */
	ret = wait_event_timeout(hdq_wait_queue,
		hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
	if (ret == 0) {
		dev_dbg(hdq_data->dev, "break wait elapsed\n");
		ret = -EINTR;
		goto out;
	}

	tmp_status = hdq_data->hdq_irqstatus;
	/* check irqstatus */
	if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
		dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
				tmp_status);
		ret = -ETIMEDOUT;
		goto out;
	}
	/*
	 * wait for both INIT and GO bits rerurn to zero.
	 * zero wait time expected for interrupt mode.
	 */
	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
			OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
			OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
			&tmp_status);
	if (ret)
		dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
			" return to zero, %x", tmp_status);

out:
	mutex_unlock(&hdq_data->hdq_mutex);
rtn:
	return ret;
}

static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
{
	int ret = 0;
	u8 status;

	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	if (ret < 0) {
		ret = -EINTR;
		goto rtn;
	}

	if (!hdq_data->hdq_usecount) {
		ret = -EINVAL;
		goto out;
	}

	if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
		hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
			OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
			OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
		/*
		 * The RX comes immediately after TX.
		 */
		wait_event_timeout(hdq_wait_queue,
				   (hdq_data->hdq_irqstatus
				    & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
				   OMAP_HDQ_TIMEOUT);

		hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
			OMAP_HDQ_CTRL_STATUS_DIR);
		status = hdq_data->hdq_irqstatus;
		/* check irqstatus */
		if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
			dev_dbg(hdq_data->dev, "timeout waiting for"
				" RXCOMPLETE, %x", status);
			ret = -ETIMEDOUT;
			goto out;
		}
	}
	/* the data is ready. Read it in! */
	*val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
out:
	mutex_unlock(&hdq_data->hdq_mutex);
rtn:
	return ret;

}

/* Enable clocks and set the controller to HDQ mode */
static int omap_hdq_get(struct hdq_data *hdq_data)
{
	int ret = 0;

	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	if (ret < 0) {
		ret = -EINTR;
		goto rtn;
	}

	if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
		dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
		ret = -EINVAL;
		goto out;
	} else {
		hdq_data->hdq_usecount++;
		try_module_get(THIS_MODULE);
		if (1 == hdq_data->hdq_usecount) {

			pm_runtime_get_sync(hdq_data->dev);

			/* make sure HDQ is out of reset */
			if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
				OMAP_HDQ_SYSSTATUS_RESETDONE)) {
				ret = _omap_hdq_reset(hdq_data);
				if (ret)
					/* back up the count */
					hdq_data->hdq_usecount--;
			} else {
				/* select HDQ mode & enable clocks */
				hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
					OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
					OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
				hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
					OMAP_HDQ_SYSCONFIG_AUTOIDLE);
				hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
			}
		}
	}

out:
	mutex_unlock(&hdq_data->hdq_mutex);
rtn:
	return ret;
}

/* Disable clocks to the module */
static int omap_hdq_put(struct hdq_data *hdq_data)
{
	int ret = 0;

	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	if (ret < 0)
		return -EINTR;

	if (0 == hdq_data->hdq_usecount) {
		dev_dbg(hdq_data->dev, "attempt to decrement use count"
			" when it is zero");
		ret = -EINVAL;
	} else {
		hdq_data->hdq_usecount--;
		module_put(THIS_MODULE);
		if (0 == hdq_data->hdq_usecount)
			pm_runtime_put_sync(hdq_data->dev);
	}
	mutex_unlock(&hdq_data->hdq_mutex);

	return ret;
}

/* Read a byte of data from the device */
static u8 omap_w1_read_byte(void *_hdq)
{
	struct hdq_data *hdq_data = _hdq;
	u8 val = 0;
	int ret;

	ret = hdq_read_byte(hdq_data, &val);
	if (ret) {
		ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
		if (ret < 0) {
			dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
			return -EINTR;
		}
		hdq_data->init_trans = 0;
		mutex_unlock(&hdq_data->hdq_mutex);
		omap_hdq_put(hdq_data);
		return -1;
	}

	/* Write followed by a read, release the module */
	if (hdq_data->init_trans) {
		ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
		if (ret < 0) {
			dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
			return -EINTR;
		}
		hdq_data->init_trans = 0;
		mutex_unlock(&hdq_data->hdq_mutex);
		omap_hdq_put(hdq_data);
	}

	return val;
}

/* Write a byte of data to the device */
static void omap_w1_write_byte(void *_hdq, u8 byte)
{
	struct hdq_data *hdq_data = _hdq;
	int ret;
	u8 status;

	/* First write to initialize the transfer */
	if (hdq_data->init_trans == 0)
		omap_hdq_get(hdq_data);

	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	if (ret < 0) {
		dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
		return;
	}
	hdq_data->init_trans++;
	mutex_unlock(&hdq_data->hdq_mutex);

	ret = hdq_write_byte(hdq_data, byte, &status);
	if (ret < 0) {
		dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
		return;
	}

	/* Second write, data transferred. Release the module */
	if (hdq_data->init_trans > 1) {
		omap_hdq_put(hdq_data);
		ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
		if (ret < 0) {
			dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
			return;
		}
		hdq_data->init_trans = 0;
		mutex_unlock(&hdq_data->hdq_mutex);
	}
}

static int omap_hdq_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct hdq_data *hdq_data;
	struct resource *res;
	int ret, irq;
	u8 rev;

	hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL);
	if (!hdq_data) {
		dev_dbg(&pdev->dev, "unable to allocate memory\n");
		return -ENOMEM;
	}

	hdq_data->dev = dev;
	platform_set_drvdata(pdev, hdq_data);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	hdq_data->hdq_base = devm_ioremap_resource(dev, res);
	if (IS_ERR(hdq_data->hdq_base))
		return PTR_ERR(hdq_data->hdq_base);

	hdq_data->hdq_usecount = 0;
	mutex_init(&hdq_data->hdq_mutex);

	pm_runtime_enable(&pdev->dev);
	pm_runtime_get_sync(&pdev->dev);

	rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
	dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
		(rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");

	spin_lock_init(&hdq_data->hdq_spinlock);

	irq = platform_get_irq(pdev, 0);
	if (irq	< 0) {
		ret = -ENXIO;
		goto err_irq;
	}

	ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data);
	if (ret < 0) {
		dev_dbg(&pdev->dev, "could not request irq\n");
		goto err_irq;
	}

	omap_hdq_break(hdq_data);

	pm_runtime_put_sync(&pdev->dev);

	omap_w1_master.data = hdq_data;

	ret = w1_add_master_device(&omap_w1_master);
	if (ret) {
		dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
		goto err_w1;
	}

	return 0;

err_irq:
	pm_runtime_put_sync(&pdev->dev);
err_w1:
	pm_runtime_disable(&pdev->dev);

	return ret;
}

static int omap_hdq_remove(struct platform_device *pdev)
{
	struct hdq_data *hdq_data = platform_get_drvdata(pdev);

	mutex_lock(&hdq_data->hdq_mutex);

	if (hdq_data->hdq_usecount) {
		dev_dbg(&pdev->dev, "removed when use count is not zero\n");
		mutex_unlock(&hdq_data->hdq_mutex);
		return -EBUSY;
	}

	mutex_unlock(&hdq_data->hdq_mutex);

	/* remove module dependency */
	pm_runtime_disable(&pdev->dev);

	return 0;
}

module_platform_driver(omap_hdq_driver);

module_param(w1_id, int, S_IRUSR);
MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection");

MODULE_AUTHOR("Texas Instruments");
MODULE_DESCRIPTION("HDQ driver Library");
MODULE_LICENSE("GPL");
Commit	Line	Data
9f2bc79f MC	1	/*
	2	* drivers/w1/masters/omap_hdq.c
	3	*
c354a864	4	* Copyright (C) 2007,2012 Texas Instruments, Inc.
9f2bc79f MC	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*
	10	*/
	11	#include <linux/kernel.h>
	12	#include <linux/module.h>
	13	#include <linux/platform_device.h>
	14	#include <linux/interrupt.h>
5a0e3ad6	15	#include <linux/slab.h>
9f2bc79f	16	#include <linux/err.h>
9f2bc79f	17	#include <linux/io.h>
81fa08f2	18	#include <linux/sched.h>
c354a864	19	#include <linux/pm_runtime.h>
9f2bc79f	20
9f2bc79f MC	21	#include "../w1.h"
	22	#include "../w1_int.h"
	23
	24	#define MOD_NAME "OMAP_HDQ:"
	25
	26	#define OMAP_HDQ_REVISION 0x00
	27	#define OMAP_HDQ_TX_DATA 0x04
	28	#define OMAP_HDQ_RX_DATA 0x08
	29	#define OMAP_HDQ_CTRL_STATUS 0x0c
	30	#define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK (1<<6)
	31	#define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE (1<<5)
	32	#define OMAP_HDQ_CTRL_STATUS_GO (1<<4)
	33	#define OMAP_HDQ_CTRL_STATUS_INITIALIZATION (1<<2)
	34	#define OMAP_HDQ_CTRL_STATUS_DIR (1<<1)
	35	#define OMAP_HDQ_CTRL_STATUS_MODE (1<<0)
	36	#define OMAP_HDQ_INT_STATUS 0x10
	37	#define OMAP_HDQ_INT_STATUS_TXCOMPLETE (1<<2)
	38	#define OMAP_HDQ_INT_STATUS_RXCOMPLETE (1<<1)
	39	#define OMAP_HDQ_INT_STATUS_TIMEOUT (1<<0)
	40	#define OMAP_HDQ_SYSCONFIG 0x14
	41	#define OMAP_HDQ_SYSCONFIG_SOFTRESET (1<<1)
	42	#define OMAP_HDQ_SYSCONFIG_AUTOIDLE (1<<0)
	43	#define OMAP_HDQ_SYSSTATUS 0x18
	44	#define OMAP_HDQ_SYSSTATUS_RESETDONE (1<<0)
	45
	46	#define OMAP_HDQ_FLAG_CLEAR 0
	47	#define OMAP_HDQ_FLAG_SET 1
	48	#define OMAP_HDQ_TIMEOUT (HZ/5)
	49
	50	#define OMAP_HDQ_MAX_USER 4
	51
	52	static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
	53	static int w1_id;
	54
	55	struct hdq_data {
	56	struct device *dev;
	57	void __iomem *hdq_base;
	58	/* lock status update */
	59	struct mutex hdq_mutex;
	60	int hdq_usecount;
9f2bc79f MC	61	u8 hdq_irqstatus;
	62	/* device lock */
	63	spinlock_t hdq_spinlock;
	64	/*
	65	* Used to control the call to omap_hdq_get and omap_hdq_put.
	66	* HDQ Protocol: Write the CMD\|REG_address first, followed by
	67	* the data wrire or read.
	68	*/
	69	int init_trans;
	70	};
	71
479e2bce	72	static int omap_hdq_probe(struct platform_device *pdev);
82849a93	73	static int omap_hdq_remove(struct platform_device *pdev);
9f2bc79f MC	74
	75	static struct platform_driver omap_hdq_driver = {
	76	.probe = omap_hdq_probe,
f91a66c9	77	.remove = omap_hdq_remove,
9f2bc79f MC	78	.driver = {
	79	.name = "omap_hdq",
	80	},
	81	};
	82
	83	static u8 omap_w1_read_byte(void *_hdq);
	84	static void omap_w1_write_byte(void *_hdq, u8 byte);
	85	static u8 omap_w1_reset_bus(void *_hdq);
06b0d4dc SM	86	static void omap_w1_search_bus(void _hdq, struct w1_master master_dev,
06b0d4dc SM	87	u8 search_type, w1_slave_found_callback slave_found);
9f2bc79f MC	88
	89
	90	static struct w1_bus_master omap_w1_master = {
	91	.read_byte = omap_w1_read_byte,
	92	.write_byte = omap_w1_write_byte,
	93	.reset_bus = omap_w1_reset_bus,
	94	.search = omap_w1_search_bus,
	95	};
	96
	97	/* HDQ register I/O routines */
	98	static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
	99	{
2acd0894	100	return __raw_readl(hdq_data->hdq_base + offset);
9f2bc79f MC	101	}
	102
	103	static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
	104	{
2acd0894	105	__raw_writel(val, hdq_data->hdq_base + offset);
9f2bc79f MC	106	}
	107
	108	static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
	109	u8 val, u8 mask)
	110	{
2acd0894	111	u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
9f2bc79f	112	\| (val & mask);
2acd0894	113	__raw_writel(new_val, hdq_data->hdq_base + offset);
9f2bc79f MC	114
	115	return new_val;
	116	}
	117
	118	/*
	119	* Wait for one or more bits in flag change.
	120	* HDQ_FLAG_SET: wait until any bit in the flag is set.
	121	* HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
	122	* return 0 on success and -ETIMEDOUT in the case of timeout.
	123	*/
	124	static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
	125	u8 flag, u8 flag_set, u8 *status)
	126	{
	127	int ret = 0;
	128	unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
	129
	130	if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
	131	/* wait for the flag clear */
	132	while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
	133	&& time_before(jiffies, timeout)) {
	134	schedule_timeout_uninterruptible(1);
	135	}
	136	if (*status & flag)
	137	ret = -ETIMEDOUT;
	138	} else if (flag_set == OMAP_HDQ_FLAG_SET) {
	139	/* wait for the flag set */
	140	while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
	141	&& time_before(jiffies, timeout)) {
	142	schedule_timeout_uninterruptible(1);
	143	}
	144	if (!(*status & flag))
	145	ret = -ETIMEDOUT;
	146	} else
	147	return -EINVAL;
	148
	149	return ret;
	150	}
	151
	152	/* write out a byte and fill status with HDQ_INT_STATUS /
	153	static int hdq_write_byte(struct hdq_data hdq_data, u8 val, u8 status)
	154	{
	155	int ret;
	156	u8 tmp_status;
	157	unsigned long irqflags;
	158
	159	*status = 0;
	160
	161	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
	162	/* clear interrupt flags via a dummy read */
	163	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
	164	/* ISR loads it with new INT_STATUS */
	165	hdq_data->hdq_irqstatus = 0;
	166	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
	167
	168	hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
	169
	170	/* set the GO bit */
	171	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
	172	OMAP_HDQ_CTRL_STATUS_DIR \| OMAP_HDQ_CTRL_STATUS_GO);
	173	/* wait for the TXCOMPLETE bit */
	174	ret = wait_event_timeout(hdq_wait_queue,
	175	hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
	176	if (ret == 0) {
	177	dev_dbg(hdq_data->dev, "TX wait elapsed\n");
7b5362a6	178	ret = -ETIMEDOUT;
9f2bc79f MC	179	goto out;
	180	}
	181
	182	*status = hdq_data->hdq_irqstatus;
	183	/* check irqstatus */
	184	if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
	185	dev_dbg(hdq_data->dev, "timeout waiting for"
7b5362a6	186	" TXCOMPLETE/RXCOMPLETE, %x", *status);
9f2bc79f MC	187	ret = -ETIMEDOUT;
	188	goto out;
	189	}
	190
	191	/* wait for the GO bit return to zero */
	192	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
	193	OMAP_HDQ_CTRL_STATUS_GO,
	194	OMAP_HDQ_FLAG_CLEAR, &tmp_status);
	195	if (ret) {
	196	dev_dbg(hdq_data->dev, "timeout waiting GO bit"
7b5362a6	197	" return to zero, %x", tmp_status);
9f2bc79f MC	198	}
	199
	200	out:
	201	return ret;
	202	}
	203
	204	/* HDQ Interrupt service routine */
	205	static irqreturn_t hdq_isr(int irq, void *_hdq)
	206	{
	207	struct hdq_data *hdq_data = _hdq;
	208	unsigned long irqflags;
	209
	210	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
	211	hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
	212	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
	213	dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
	214
	215	if (hdq_data->hdq_irqstatus &
	216	(OMAP_HDQ_INT_STATUS_TXCOMPLETE \| OMAP_HDQ_INT_STATUS_RXCOMPLETE
	217	\| OMAP_HDQ_INT_STATUS_TIMEOUT)) {
	218	/* wake up sleeping process */
	219	wake_up(&hdq_wait_queue);
	220	}
	221
	222	return IRQ_HANDLED;
	223	}
	224
	225	/* HDQ Mode: always return success */
	226	static u8 omap_w1_reset_bus(void *_hdq)
	227	{
	228	return 0;
	229	}
	230
	231	/* W1 search callback function */
06b0d4dc SM	232	static void omap_w1_search_bus(void _hdq, struct w1_master master_dev,
06b0d4dc SM	233	u8 search_type, w1_slave_found_callback slave_found)
9f2bc79f MC	234	{
	235	u64 module_id, rn_le, cs, id;
	236
	237	if (w1_id)
	238	module_id = w1_id;
	239	else
	240	module_id = 0x1;
	241
	242	rn_le = cpu_to_le64(module_id);
	243	/*
	244	* HDQ might not obey truly the 1-wire spec.
	245	* So calculate CRC based on module parameter.
	246	*/
	247	cs = w1_calc_crc8((u8 *)&rn_le, 7);
	248	id = (cs << 56) \| module_id;
	249
06b0d4dc	250	slave_found(master_dev, id);
9f2bc79f MC	251	}
	252
	253	static int _omap_hdq_reset(struct hdq_data *hdq_data)
	254	{
	255	int ret;
	256	u8 tmp_status;
	257
	258	hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG, OMAP_HDQ_SYSCONFIG_SOFTRESET);
	259	/*
	260	* Select HDQ mode & enable clocks.
	261	* It is observed that INT flags can't be cleared via a read and GO/INIT
	262	* won't return to zero if interrupt is disabled. So we always enable
	263	* interrupt.
	264	*/
	265	hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
	266	OMAP_HDQ_CTRL_STATUS_CLOCKENABLE \|
	267	OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
	268
	269	/* wait for reset to complete */
	270	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
	271	OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
	272	if (ret)
	273	dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
	274	tmp_status);
	275	else {
	276	hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
	277	OMAP_HDQ_CTRL_STATUS_CLOCKENABLE \|
	278	OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
	279	hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
	280	OMAP_HDQ_SYSCONFIG_AUTOIDLE);
	281	}
	282
	283	return ret;
	284	}
	285
	286	/* Issue break pulse to the device */
	287	static int omap_hdq_break(struct hdq_data *hdq_data)
	288	{
	289	int ret = 0;
	290	u8 tmp_status;
	291	unsigned long irqflags;
	292
	293	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	294	if (ret < 0) {
	295	dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
	296	ret = -EINTR;
	297	goto rtn;
	298	}
	299
	300	spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
	301	/* clear interrupt flags via a dummy read */
	302	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
	303	/* ISR loads it with new INT_STATUS */
	304	hdq_data->hdq_irqstatus = 0;
	305	spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
	306
	307	/* set the INIT and GO bit */
	308	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
	309	OMAP_HDQ_CTRL_STATUS_INITIALIZATION \| OMAP_HDQ_CTRL_STATUS_GO,
	310	OMAP_HDQ_CTRL_STATUS_DIR \| OMAP_HDQ_CTRL_STATUS_INITIALIZATION \|
	311	OMAP_HDQ_CTRL_STATUS_GO);
	312
	313	/* wait for the TIMEOUT bit */
	314	ret = wait_event_timeout(hdq_wait_queue,
315	hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
316	if (ret == 0) {
317	dev_dbg(hdq_data->dev, "break wait elapsed\n");
318	ret = -EINTR;
319	goto out;
320	}
321
322	tmp_status = hdq_data->hdq_irqstatus;
323	/* check irqstatus */
324	if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
325	dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
326	tmp_status);
327	ret = -ETIMEDOUT;
328	goto out;
329	}
330	/*
331	* wait for both INIT and GO bits rerurn to zero.
332	* zero wait time expected for interrupt mode.
333	*/
334	ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
335	OMAP_HDQ_CTRL_STATUS_INITIALIZATION \|
336	OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
337	&tmp_status);
338	if (ret)
339	dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
7b5362a6	340	" return to zero, %x", tmp_status);
9f2bc79f MC	341
	342	out:
	343	mutex_unlock(&hdq_data->hdq_mutex);
	344	rtn:
	345	return ret;
	346	}
	347
	348	static int hdq_read_byte(struct hdq_data hdq_data, u8 val)
	349	{
	350	int ret = 0;
	351	u8 status;
9f2bc79f MC	352
	353	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	354	if (ret < 0) {
	355	ret = -EINTR;
	356	goto rtn;
	357	}
	358
	359	if (!hdq_data->hdq_usecount) {
	360	ret = -EINVAL;
	361	goto out;
	362	}
	363
	364	if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
	365	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
	366	OMAP_HDQ_CTRL_STATUS_DIR \| OMAP_HDQ_CTRL_STATUS_GO,
	367	OMAP_HDQ_CTRL_STATUS_DIR \| OMAP_HDQ_CTRL_STATUS_GO);
	368	/*
b7e938d0	369	* The RX comes immediately after TX.
9f2bc79f	370	*/
b7e938d0 N	371	wait_event_timeout(hdq_wait_queue,
	372	(hdq_data->hdq_irqstatus
	373	& OMAP_HDQ_INT_STATUS_RXCOMPLETE),
	374	OMAP_HDQ_TIMEOUT);
	375
9f2bc79f MC	376	hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
	377	OMAP_HDQ_CTRL_STATUS_DIR);
	378	status = hdq_data->hdq_irqstatus;
	379	/* check irqstatus */
	380	if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
	381	dev_dbg(hdq_data->dev, "timeout waiting for"
7b5362a6	382	" RXCOMPLETE, %x", status);
9f2bc79f MC	383	ret = -ETIMEDOUT;
	384	goto out;
	385	}
	386	}
	387	/* the data is ready. Read it in! */
	388	*val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
	389	out:
	390	mutex_unlock(&hdq_data->hdq_mutex);
	391	rtn:
7b5362a6	392	return ret;
9f2bc79f MC	393
	394	}
	395
	396	/* Enable clocks and set the controller to HDQ mode */
	397	static int omap_hdq_get(struct hdq_data *hdq_data)
	398	{
	399	int ret = 0;
	400
	401	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	402	if (ret < 0) {
	403	ret = -EINTR;
	404	goto rtn;
	405	}
	406
	407	if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
	408	dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
	409	ret = -EINVAL;
	410	goto out;
	411	} else {
	412	hdq_data->hdq_usecount++;
	413	try_module_get(THIS_MODULE);
	414	if (1 == hdq_data->hdq_usecount) {
c354a864 PW	415
c354a864 PW	416	pm_runtime_get_sync(hdq_data->dev);
9f2bc79f MC	417
	418	/* make sure HDQ is out of reset */
	419	if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
	420	OMAP_HDQ_SYSSTATUS_RESETDONE)) {
	421	ret = _omap_hdq_reset(hdq_data);
	422	if (ret)
	423	/* back up the count */
	424	hdq_data->hdq_usecount--;
	425	} else {
	426	/* select HDQ mode & enable clocks */
	427	hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
	428	OMAP_HDQ_CTRL_STATUS_CLOCKENABLE \|
	429	OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
	430	hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
	431	OMAP_HDQ_SYSCONFIG_AUTOIDLE);
	432	hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
	433	}
	434	}
	435	}
	436
9f2bc79f MC	437	out:
	438	mutex_unlock(&hdq_data->hdq_mutex);
	439	rtn:
	440	return ret;
	441	}
	442
	443	/* Disable clocks to the module */
	444	static int omap_hdq_put(struct hdq_data *hdq_data)
	445	{
	446	int ret = 0;
	447
	448	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	449	if (ret < 0)
	450	return -EINTR;
	451
	452	if (0 == hdq_data->hdq_usecount) {
	453	dev_dbg(hdq_data->dev, "attempt to decrement use count"
7b5362a6	454	" when it is zero");
9f2bc79f MC	455	ret = -EINVAL;
	456	} else {
	457	hdq_data->hdq_usecount--;
	458	module_put(THIS_MODULE);
c354a864 PW	459	if (0 == hdq_data->hdq_usecount)
c354a864 PW	460	pm_runtime_put_sync(hdq_data->dev);
9f2bc79f MC	461	}
	462	mutex_unlock(&hdq_data->hdq_mutex);
	463
	464	return ret;
	465	}
	466
	467	/* Read a byte of data from the device */
	468	static u8 omap_w1_read_byte(void *_hdq)
	469	{
	470	struct hdq_data *hdq_data = _hdq;
	471	u8 val = 0;
	472	int ret;
	473
	474	ret = hdq_read_byte(hdq_data, &val);
	475	if (ret) {
	476	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	477	if (ret < 0) {
	478	dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
	479	return -EINTR;
	480	}
	481	hdq_data->init_trans = 0;
	482	mutex_unlock(&hdq_data->hdq_mutex);
	483	omap_hdq_put(hdq_data);
	484	return -1;
	485	}
	486
	487	/* Write followed by a read, release the module */
	488	if (hdq_data->init_trans) {
	489	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	490	if (ret < 0) {
	491	dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
	492	return -EINTR;
	493	}
	494	hdq_data->init_trans = 0;
	495	mutex_unlock(&hdq_data->hdq_mutex);
	496	omap_hdq_put(hdq_data);
	497	}
	498
	499	return val;
	500	}
	501
	502	/* Write a byte of data to the device */
	503	static void omap_w1_write_byte(void *_hdq, u8 byte)
	504	{
	505	struct hdq_data *hdq_data = _hdq;
	506	int ret;
	507	u8 status;
	508
	509	/* First write to initialize the transfer */
	510	if (hdq_data->init_trans == 0)
	511	omap_hdq_get(hdq_data);
	512
	513	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	514	if (ret < 0) {
	515	dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
	516	return;
	517	}
	518	hdq_data->init_trans++;
	519	mutex_unlock(&hdq_data->hdq_mutex);
	520
	521	ret = hdq_write_byte(hdq_data, byte, &status);
7b5362a6	522	if (ret < 0) {
9f2bc79f MC	523	dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
	524	return;
	525	}
	526
25985edc	527	/* Second write, data transferred. Release the module */
9f2bc79f MC	528	if (hdq_data->init_trans > 1) {
	529	omap_hdq_put(hdq_data);
	530	ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
	531	if (ret < 0) {
	532	dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
	533	return;
	534	}
	535	hdq_data->init_trans = 0;
	536	mutex_unlock(&hdq_data->hdq_mutex);
	537	}
9f2bc79f MC	538	}
9f2bc79f MC	539
479e2bce	540	static int omap_hdq_probe(struct platform_device *pdev)
9f2bc79f	541	{
19afea50	542	struct device *dev = &pdev->dev;
9f2bc79f MC	543	struct hdq_data *hdq_data;
	544	struct resource *res;
	545	int ret, irq;
	546	u8 rev;
	547
19afea50	548	hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL);
9f2bc79f MC	549	if (!hdq_data) {
9f2bc79f MC	550	dev_dbg(&pdev->dev, "unable to allocate memory\n");
19afea50	551	return -ENOMEM;
9f2bc79f MC	552	}
9f2bc79f MC	553
19afea50	554	hdq_data->dev = dev;
9f2bc79f MC	555	platform_set_drvdata(pdev, hdq_data);
	556
	557	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4d6dc3a7 TR	558	hdq_data->hdq_base = devm_ioremap_resource(dev, res);
	559	if (IS_ERR(hdq_data->hdq_base))
	560	return PTR_ERR(hdq_data->hdq_base);
9f2bc79f	561
9f2bc79f MC	562	hdq_data->hdq_usecount = 0;
	563	mutex_init(&hdq_data->hdq_mutex);
	564
c354a864 PW	565	pm_runtime_enable(&pdev->dev);
c354a864 PW	566	pm_runtime_get_sync(&pdev->dev);
9f2bc79f MC	567
	568	rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
	569	dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
	570	(rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
	571
	572	spin_lock_init(&hdq_data->hdq_spinlock);
	573
	574	irq = platform_get_irq(pdev, 0);
	575	if (irq < 0) {
	576	ret = -ENXIO;
	577	goto err_irq;
	578	}
	579
fe576a58	580	ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data);
9f2bc79f MC	581	if (ret < 0) {
	582	dev_dbg(&pdev->dev, "could not request irq\n");
	583	goto err_irq;
	584	}
	585
	586	omap_hdq_break(hdq_data);
	587
c354a864	588	pm_runtime_put_sync(&pdev->dev);
9f2bc79f MC	589
	590	omap_w1_master.data = hdq_data;
	591
	592	ret = w1_add_master_device(&omap_w1_master);
	593	if (ret) {
	594	dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
	595	goto err_w1;
	596	}
	597
	598	return 0;
	599
9f2bc79f	600	err_irq:
c354a864 PW	601	pm_runtime_put_sync(&pdev->dev);
	602	err_w1:
	603	pm_runtime_disable(&pdev->dev);
80d02d27	604
9f2bc79f	605	return ret;
9f2bc79f MC	606	}
9f2bc79f MC	607
82849a93	608	static int omap_hdq_remove(struct platform_device *pdev)
9f2bc79f MC	609	{
	610	struct hdq_data *hdq_data = platform_get_drvdata(pdev);
	611
	612	mutex_lock(&hdq_data->hdq_mutex);
	613
	614	if (hdq_data->hdq_usecount) {
	615	dev_dbg(&pdev->dev, "removed when use count is not zero\n");
2020002a	616	mutex_unlock(&hdq_data->hdq_mutex);
9f2bc79f MC	617	return -EBUSY;
	618	}
	619
	620	mutex_unlock(&hdq_data->hdq_mutex);
	621
	622	/* remove module dependency */
c354a864	623	pm_runtime_disable(&pdev->dev);
9f2bc79f MC	624
	625	return 0;
	626	}
	627
8650bbb5	628	module_platform_driver(omap_hdq_driver);
9f2bc79f MC	629
	630	module_param(w1_id, int, S_IRUSR);
	631	MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection");
	632
	633	MODULE_AUTHOR("Texas Instruments");
	634	MODULE_DESCRIPTION("HDQ driver Library");
	635	MODULE_LICENSE("GPL");