Merge git://git.infradead.org/users/eparis/audit
[deliverable/linux.git] / drivers / watchdog / booke_wdt.c
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a2f40ccd 1/*
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2 * Watchdog timer for PowerPC Book-E systems
3 *
4 * Author: Matthew McClintock
4c8d3d99 5 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
a2f40ccd 6 *
112e7546 7 * Copyright 2005, 2008, 2010-2011 Freescale Semiconductor Inc.
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8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
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15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
16
a2f40ccd 17#include <linux/module.h>
f172ddc6 18#include <linux/smp.h>
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19#include <linux/watchdog.h>
20
21#include <asm/reg_booke.h>
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22#include <asm/time.h>
23#include <asm/div64.h>
a2f40ccd 24
40ebbcbf 25/* If the kernel parameter wdt=1, the watchdog will be enabled at boot.
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26 * Also, the wdt_period sets the watchdog timer period timeout.
27 * For E500 cpus the wdt_period sets which bit changing from 0->1 will
28 * trigger a watchog timeout. This watchdog timeout will occur 3 times, the
29 * first time nothing will happen, the second time a watchdog exception will
30 * occur, and the final time the board will reset.
31 */
32
f172ddc6 33u32 booke_wdt_enabled;
e0dc09ff 34u32 booke_wdt_period = CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT;
a2f40ccd 35
be0884ce 36#ifdef CONFIG_PPC_FSL_BOOK3E
dcfb7484 37#define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15))
0fb06571 38#define WDTP_MASK (WDTP(0x3f))
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39#else
40#define WDTP(x) (TCR_WP(x))
0a0e9e0c 41#define WDTP_MASK (TCR_WP_MASK)
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42#endif
43
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44/* Checks wdt=x and wdt_period=xx command-line option */
45notrace int __init early_parse_wdt(char *p)
46{
47 if (p && strncmp(p, "0", 1) != 0)
48 booke_wdt_enabled = 1;
49
50 return 0;
51}
52early_param("wdt", early_parse_wdt);
53
54int __init early_parse_wdt_period(char *p)
55{
56 unsigned long ret;
57 if (p) {
58 if (!kstrtol(p, 0, &ret))
59 booke_wdt_period = ret;
60 }
61
62 return 0;
63}
64early_param("wdt_period", early_parse_wdt_period);
65
52e5cc4e 66#ifdef CONFIG_PPC_FSL_BOOK3E
f172ddc6 67
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68/* For the specified period, determine the number of seconds
69 * corresponding to the reset time. There will be a watchdog
70 * exception at approximately 3/5 of this time.
71 *
72 * The formula to calculate this is given by:
73 * 2.5 * (2^(63-period+1)) / timebase_freq
74 *
75 * In order to simplify things, we assume that period is
76 * at least 1. This will still result in a very long timeout.
77 */
78static unsigned long long period_to_sec(unsigned int period)
79{
80 unsigned long long tmp = 1ULL << (64 - period);
81 unsigned long tmp2 = ppc_tb_freq;
82
83 /* tmp may be a very large number and we don't want to overflow,
84 * so divide the timebase freq instead of multiplying tmp
85 */
86 tmp2 = tmp2 / 5 * 2;
87
88 do_div(tmp, tmp2);
89 return tmp;
90}
91
92/*
93 * This procedure will find the highest period which will give a timeout
94 * greater than the one required. e.g. for a bus speed of 66666666 and
95 * and a parameter of 2 secs, then this procedure will return a value of 38.
96 */
97static unsigned int sec_to_period(unsigned int secs)
98{
99 unsigned int period;
100 for (period = 63; period > 0; period--) {
101 if (period_to_sec(period) >= secs)
102 return period;
103 }
104 return 0;
105}
106
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107#define MAX_WDT_TIMEOUT period_to_sec(1)
108
109#else /* CONFIG_PPC_FSL_BOOK3E */
110
111static unsigned long long period_to_sec(unsigned int period)
112{
113 return period;
114}
115
116static unsigned int sec_to_period(unsigned int secs)
117{
118 return secs;
119}
120
121#define MAX_WDT_TIMEOUT 3 /* from Kconfig */
122
123#endif /* !CONFIG_PPC_FSL_BOOK3E */
124
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125static void __booke_wdt_set(void *data)
126{
127 u32 val;
d2deebab 128 struct watchdog_device *wdog = data;
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129
130 val = mfspr(SPRN_TCR);
131 val &= ~WDTP_MASK;
d2deebab 132 val |= WDTP(sec_to_period(wdog->timeout));
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133
134 mtspr(SPRN_TCR, val);
135}
136
d2deebab 137static void booke_wdt_set(void *data)
6ae98ed1 138{
d2deebab 139 on_each_cpu(__booke_wdt_set, data, 0);
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140}
141
f172ddc6 142static void __booke_wdt_ping(void *data)
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143{
144 mtspr(SPRN_TSR, TSR_ENW|TSR_WIS);
145}
146
52e5cc4e 147static int booke_wdt_ping(struct watchdog_device *wdog)
f172ddc6 148{
f6f88e9b 149 on_each_cpu(__booke_wdt_ping, NULL, 0);
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150
151 return 0;
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152}
153
154static void __booke_wdt_enable(void *data)
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155{
156 u32 val;
d2deebab 157 struct watchdog_device *wdog = data;
a2f40ccd 158
f31909c0 159 /* clear status before enabling watchdog */
f172ddc6 160 __booke_wdt_ping(NULL);
a2f40ccd 161 val = mfspr(SPRN_TCR);
0a0e9e0c 162 val &= ~WDTP_MASK;
d2deebab 163 val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(sec_to_period(wdog->timeout)));
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164
165 mtspr(SPRN_TCR, val);
166}
167
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168/**
169 * booke_wdt_disable - disable the watchdog on the given CPU
170 *
171 * This function is called on each CPU. It disables the watchdog on that CPU.
172 *
173 * TCR[WRC] cannot be changed once it has been set to non-zero, but we can
174 * effectively disable the watchdog by setting its period to the maximum value.
175 */
176static void __booke_wdt_disable(void *data)
177{
178 u32 val;
179
180 val = mfspr(SPRN_TCR);
181 val &= ~(TCR_WIE | WDTP_MASK);
182 mtspr(SPRN_TCR, val);
183
184 /* clear status to make sure nothing is pending */
185 __booke_wdt_ping(NULL);
186
187}
188
d2deebab 189static int booke_wdt_start(struct watchdog_device *wdog)
a2f40ccd 190{
d2deebab 191 on_each_cpu(__booke_wdt_enable, wdog, 0);
52e5cc4e 192 pr_debug("watchdog enabled (timeout = %u sec)\n", wdog->timeout);
a2f40ccd 193
52e5cc4e 194 return 0;
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195}
196
52e5cc4e 197static int booke_wdt_stop(struct watchdog_device *wdog)
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198{
199 on_each_cpu(__booke_wdt_disable, NULL, 0);
27c766aa 200 pr_debug("watchdog disabled\n");
5d63c134 201
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202 return 0;
203}
204
205static int booke_wdt_set_timeout(struct watchdog_device *wdt_dev,
206 unsigned int timeout)
207{
208 if (timeout > MAX_WDT_TIMEOUT)
209 return -EINVAL;
52e5cc4e 210 wdt_dev->timeout = timeout;
d2deebab 211 booke_wdt_set(wdt_dev);
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212
213 return 0;
214}
215
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216static struct watchdog_info booke_wdt_info = {
217 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
218 .identity = "PowerPC Book-E Watchdog",
219};
220
221static struct watchdog_ops booke_wdt_ops = {
f172ddc6 222 .owner = THIS_MODULE,
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223 .start = booke_wdt_start,
224 .stop = booke_wdt_stop,
225 .ping = booke_wdt_ping,
226 .set_timeout = booke_wdt_set_timeout,
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227};
228
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229static struct watchdog_device booke_wdt_dev = {
230 .info = &booke_wdt_info,
231 .ops = &booke_wdt_ops,
232 .min_timeout = 1,
233 .max_timeout = 0xFFFF
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234};
235
236static void __exit booke_wdt_exit(void)
237{
52e5cc4e 238 watchdog_unregister_device(&booke_wdt_dev);
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239}
240
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241static int __init booke_wdt_init(void)
242{
243 int ret = 0;
52e5cc4e 244 bool nowayout = WATCHDOG_NOWAYOUT;
a2f40ccd 245
27c766aa 246 pr_info("powerpc book-e watchdog driver loaded\n");
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247 booke_wdt_info.firmware_version = cur_cpu_spec->pvr_value;
248 booke_wdt_set_timeout(&booke_wdt_dev,
d2deebab 249 period_to_sec(booke_wdt_period));
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250 watchdog_set_nowayout(&booke_wdt_dev, nowayout);
251 if (booke_wdt_enabled)
d2deebab 252 booke_wdt_start(&booke_wdt_dev);
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253
254 ret = watchdog_register_device(&booke_wdt_dev);
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255
256 return ret;
257}
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258
259module_init(booke_wdt_init);
260module_exit(booke_wdt_exit);
261
262MODULE_DESCRIPTION("PowerPC Book-E watchdog driver");
263MODULE_LICENSE("GPL");
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