Commit | Line | Data |
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a2f40ccd | 1 | /* |
a2f40ccd KG |
2 | * Watchdog timer for PowerPC Book-E systems |
3 | * | |
4 | * Author: Matthew McClintock | |
4c8d3d99 | 5 | * Maintainer: Kumar Gala <galak@kernel.crashing.org> |
a2f40ccd | 6 | * |
112e7546 | 7 | * Copyright 2005, 2008, 2010-2011 Freescale Semiconductor Inc. |
a2f40ccd KG |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | */ | |
14 | ||
27c766aa JP |
15 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
16 | ||
a2f40ccd KG |
17 | #include <linux/module.h> |
18 | #include <linux/fs.h> | |
f172ddc6 | 19 | #include <linux/smp.h> |
a2f40ccd KG |
20 | #include <linux/miscdevice.h> |
21 | #include <linux/notifier.h> | |
22 | #include <linux/watchdog.h> | |
00e9c205 | 23 | #include <linux/uaccess.h> |
a2f40ccd KG |
24 | |
25 | #include <asm/reg_booke.h> | |
dcfb7484 CF |
26 | #include <asm/time.h> |
27 | #include <asm/div64.h> | |
a2f40ccd | 28 | |
40ebbcbf | 29 | /* If the kernel parameter wdt=1, the watchdog will be enabled at boot. |
a2f40ccd KG |
30 | * Also, the wdt_period sets the watchdog timer period timeout. |
31 | * For E500 cpus the wdt_period sets which bit changing from 0->1 will | |
32 | * trigger a watchog timeout. This watchdog timeout will occur 3 times, the | |
33 | * first time nothing will happen, the second time a watchdog exception will | |
34 | * occur, and the final time the board will reset. | |
35 | */ | |
36 | ||
f172ddc6 | 37 | u32 booke_wdt_enabled; |
e0dc09ff | 38 | u32 booke_wdt_period = CONFIG_BOOKE_WDT_DEFAULT_TIMEOUT; |
a2f40ccd | 39 | |
be0884ce | 40 | #ifdef CONFIG_PPC_FSL_BOOK3E |
dcfb7484 | 41 | #define WDTP(x) ((((x)&0x3)<<30)|(((x)&0x3c)<<15)) |
0fb06571 | 42 | #define WDTP_MASK (WDTP(0x3f)) |
a2f40ccd KG |
43 | #else |
44 | #define WDTP(x) (TCR_WP(x)) | |
0a0e9e0c | 45 | #define WDTP_MASK (TCR_WP_MASK) |
a2f40ccd KG |
46 | #endif |
47 | ||
f172ddc6 CG |
48 | static DEFINE_SPINLOCK(booke_wdt_lock); |
49 | ||
dcfb7484 CF |
50 | /* For the specified period, determine the number of seconds |
51 | * corresponding to the reset time. There will be a watchdog | |
52 | * exception at approximately 3/5 of this time. | |
53 | * | |
54 | * The formula to calculate this is given by: | |
55 | * 2.5 * (2^(63-period+1)) / timebase_freq | |
56 | * | |
57 | * In order to simplify things, we assume that period is | |
58 | * at least 1. This will still result in a very long timeout. | |
59 | */ | |
60 | static unsigned long long period_to_sec(unsigned int period) | |
61 | { | |
62 | unsigned long long tmp = 1ULL << (64 - period); | |
63 | unsigned long tmp2 = ppc_tb_freq; | |
64 | ||
65 | /* tmp may be a very large number and we don't want to overflow, | |
66 | * so divide the timebase freq instead of multiplying tmp | |
67 | */ | |
68 | tmp2 = tmp2 / 5 * 2; | |
69 | ||
70 | do_div(tmp, tmp2); | |
71 | return tmp; | |
72 | } | |
73 | ||
74 | /* | |
75 | * This procedure will find the highest period which will give a timeout | |
76 | * greater than the one required. e.g. for a bus speed of 66666666 and | |
77 | * and a parameter of 2 secs, then this procedure will return a value of 38. | |
78 | */ | |
79 | static unsigned int sec_to_period(unsigned int secs) | |
80 | { | |
81 | unsigned int period; | |
82 | for (period = 63; period > 0; period--) { | |
83 | if (period_to_sec(period) >= secs) | |
84 | return period; | |
85 | } | |
86 | return 0; | |
87 | } | |
88 | ||
6ae98ed1 RV |
89 | static void __booke_wdt_set(void *data) |
90 | { | |
91 | u32 val; | |
92 | ||
93 | val = mfspr(SPRN_TCR); | |
94 | val &= ~WDTP_MASK; | |
95 | val |= WDTP(booke_wdt_period); | |
96 | ||
97 | mtspr(SPRN_TCR, val); | |
98 | } | |
99 | ||
100 | static void booke_wdt_set(void) | |
101 | { | |
102 | on_each_cpu(__booke_wdt_set, NULL, 0); | |
103 | } | |
104 | ||
f172ddc6 | 105 | static void __booke_wdt_ping(void *data) |
f31909c0 SR |
106 | { |
107 | mtspr(SPRN_TSR, TSR_ENW|TSR_WIS); | |
108 | } | |
109 | ||
f172ddc6 CG |
110 | static void booke_wdt_ping(void) |
111 | { | |
f6f88e9b | 112 | on_each_cpu(__booke_wdt_ping, NULL, 0); |
f172ddc6 CG |
113 | } |
114 | ||
115 | static void __booke_wdt_enable(void *data) | |
a2f40ccd KG |
116 | { |
117 | u32 val; | |
118 | ||
f31909c0 | 119 | /* clear status before enabling watchdog */ |
f172ddc6 | 120 | __booke_wdt_ping(NULL); |
a2f40ccd | 121 | val = mfspr(SPRN_TCR); |
0a0e9e0c | 122 | val &= ~WDTP_MASK; |
39cdc4bf | 123 | val |= (TCR_WIE|TCR_WRC(WRC_CHIP)|WDTP(booke_wdt_period)); |
a2f40ccd KG |
124 | |
125 | mtspr(SPRN_TCR, val); | |
126 | } | |
127 | ||
fbdd7144 TT |
128 | /** |
129 | * booke_wdt_disable - disable the watchdog on the given CPU | |
130 | * | |
131 | * This function is called on each CPU. It disables the watchdog on that CPU. | |
132 | * | |
133 | * TCR[WRC] cannot be changed once it has been set to non-zero, but we can | |
134 | * effectively disable the watchdog by setting its period to the maximum value. | |
135 | */ | |
136 | static void __booke_wdt_disable(void *data) | |
137 | { | |
138 | u32 val; | |
139 | ||
140 | val = mfspr(SPRN_TCR); | |
141 | val &= ~(TCR_WIE | WDTP_MASK); | |
142 | mtspr(SPRN_TCR, val); | |
143 | ||
144 | /* clear status to make sure nothing is pending */ | |
145 | __booke_wdt_ping(NULL); | |
146 | ||
147 | } | |
148 | ||
f172ddc6 | 149 | static ssize_t booke_wdt_write(struct file *file, const char __user *buf, |
a2f40ccd KG |
150 | size_t count, loff_t *ppos) |
151 | { | |
152 | booke_wdt_ping(); | |
153 | return count; | |
154 | } | |
155 | ||
d8d8b63b | 156 | static struct watchdog_info ident = { |
f172ddc6 CG |
157 | .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING, |
158 | .identity = "PowerPC Book-E Watchdog", | |
a2f40ccd KG |
159 | }; |
160 | ||
00e9c205 AC |
161 | static long booke_wdt_ioctl(struct file *file, |
162 | unsigned int cmd, unsigned long arg) | |
a2f40ccd KG |
163 | { |
164 | u32 tmp = 0; | |
538bacf8 | 165 | u32 __user *p = (u32 __user *)arg; |
a2f40ccd KG |
166 | |
167 | switch (cmd) { | |
168 | case WDIOC_GETSUPPORT: | |
127c6e73 | 169 | return copy_to_user(p, &ident, sizeof(ident)) ? -EFAULT : 0; |
a2f40ccd | 170 | case WDIOC_GETSTATUS: |
8b18085a | 171 | return put_user(0, p); |
a2f40ccd KG |
172 | case WDIOC_GETBOOTSTATUS: |
173 | /* XXX: something is clearing TSR */ | |
174 | tmp = mfspr(SPRN_TSR) & TSR_WRS(3); | |
8b18085a | 175 | /* returns CARDRESET if last reset was caused by the WDT */ |
127c6e73 | 176 | return put_user((tmp ? WDIOF_CARDRESET : 0), p); |
0c06090c WVS |
177 | case WDIOC_SETOPTIONS: |
178 | if (get_user(tmp, p)) | |
127c6e73 | 179 | return -EFAULT; |
0c06090c WVS |
180 | if (tmp == WDIOS_ENABLECARD) { |
181 | booke_wdt_ping(); | |
182 | break; | |
183 | } else | |
184 | return -EINVAL; | |
185 | return 0; | |
a2f40ccd KG |
186 | case WDIOC_KEEPALIVE: |
187 | booke_wdt_ping(); | |
188 | return 0; | |
189 | case WDIOC_SETTIMEOUT: | |
dcfb7484 | 190 | if (get_user(tmp, p)) |
a2f40ccd | 191 | return -EFAULT; |
be0884ce | 192 | #ifdef CONFIG_PPC_FSL_BOOK3E |
dcfb7484 CF |
193 | /* period of 1 gives the largest possible timeout */ |
194 | if (tmp > period_to_sec(1)) | |
195 | return -EINVAL; | |
196 | booke_wdt_period = sec_to_period(tmp); | |
197 | #else | |
198 | booke_wdt_period = tmp; | |
199 | #endif | |
6ae98ed1 | 200 | booke_wdt_set(); |
741b9c7d | 201 | /* Fall */ |
a2f40ccd | 202 | case WDIOC_GETTIMEOUT: |
741b9c7d DA |
203 | #ifdef CONFIG_FSL_BOOKE |
204 | return put_user(period_to_sec(booke_wdt_period), p); | |
205 | #else | |
538bacf8 | 206 | return put_user(booke_wdt_period, p); |
741b9c7d | 207 | #endif |
a2f40ccd | 208 | default: |
795b89d2 | 209 | return -ENOTTY; |
a2f40ccd KG |
210 | } |
211 | ||
212 | return 0; | |
213 | } | |
f172ddc6 | 214 | |
5d63c134 TT |
215 | /* wdt_is_active stores wether or not the /dev/watchdog device is opened */ |
216 | static unsigned long wdt_is_active; | |
217 | ||
f172ddc6 | 218 | static int booke_wdt_open(struct inode *inode, struct file *file) |
a2f40ccd | 219 | { |
5d63c134 TT |
220 | /* /dev/watchdog can only be opened once */ |
221 | if (test_and_set_bit(0, &wdt_is_active)) | |
222 | return -EBUSY; | |
223 | ||
f172ddc6 | 224 | spin_lock(&booke_wdt_lock); |
39cdc4bf KG |
225 | if (booke_wdt_enabled == 0) { |
226 | booke_wdt_enabled = 1; | |
f6f88e9b | 227 | on_each_cpu(__booke_wdt_enable, NULL, 0); |
27c766aa JP |
228 | pr_debug("watchdog enabled (timeout = %llu sec)\n", |
229 | period_to_sec(booke_wdt_period)); | |
a2f40ccd | 230 | } |
f172ddc6 | 231 | spin_unlock(&booke_wdt_lock); |
a2f40ccd | 232 | |
ec9505a7 | 233 | return nonseekable_open(inode, file); |
a2f40ccd KG |
234 | } |
235 | ||
fbdd7144 TT |
236 | static int booke_wdt_release(struct inode *inode, struct file *file) |
237 | { | |
5d63c134 TT |
238 | #ifndef CONFIG_WATCHDOG_NOWAYOUT |
239 | /* Normally, the watchdog is disabled when /dev/watchdog is closed, but | |
240 | * if CONFIG_WATCHDOG_NOWAYOUT is defined, then it means that the | |
241 | * watchdog should remain enabled. So we disable it only if | |
242 | * CONFIG_WATCHDOG_NOWAYOUT is not defined. | |
243 | */ | |
fbdd7144 TT |
244 | on_each_cpu(__booke_wdt_disable, NULL, 0); |
245 | booke_wdt_enabled = 0; | |
27c766aa | 246 | pr_debug("watchdog disabled\n"); |
5d63c134 TT |
247 | #endif |
248 | ||
249 | clear_bit(0, &wdt_is_active); | |
fbdd7144 TT |
250 | |
251 | return 0; | |
252 | } | |
253 | ||
62322d25 | 254 | static const struct file_operations booke_wdt_fops = { |
f172ddc6 CG |
255 | .owner = THIS_MODULE, |
256 | .llseek = no_llseek, | |
257 | .write = booke_wdt_write, | |
00e9c205 | 258 | .unlocked_ioctl = booke_wdt_ioctl, |
f172ddc6 | 259 | .open = booke_wdt_open, |
fbdd7144 | 260 | .release = booke_wdt_release, |
a2f40ccd KG |
261 | }; |
262 | ||
263 | static struct miscdevice booke_wdt_miscdev = { | |
f172ddc6 CG |
264 | .minor = WATCHDOG_MINOR, |
265 | .name = "watchdog", | |
266 | .fops = &booke_wdt_fops, | |
a2f40ccd KG |
267 | }; |
268 | ||
269 | static void __exit booke_wdt_exit(void) | |
270 | { | |
271 | misc_deregister(&booke_wdt_miscdev); | |
272 | } | |
273 | ||
a2f40ccd KG |
274 | static int __init booke_wdt_init(void) |
275 | { | |
276 | int ret = 0; | |
277 | ||
27c766aa | 278 | pr_info("powerpc book-e watchdog driver loaded\n"); |
a78719c3 | 279 | ident.firmware_version = cur_cpu_spec->pvr_value; |
a2f40ccd KG |
280 | |
281 | ret = misc_register(&booke_wdt_miscdev); | |
282 | if (ret) { | |
27c766aa | 283 | pr_err("cannot register device (minor=%u, ret=%i)\n", |
112e7546 | 284 | WATCHDOG_MINOR, ret); |
a2f40ccd KG |
285 | return ret; |
286 | } | |
287 | ||
f172ddc6 | 288 | spin_lock(&booke_wdt_lock); |
39cdc4bf | 289 | if (booke_wdt_enabled == 1) { |
27c766aa | 290 | pr_info("watchdog enabled (timeout = %llu sec)\n", |
112e7546 | 291 | period_to_sec(booke_wdt_period)); |
f6f88e9b | 292 | on_each_cpu(__booke_wdt_enable, NULL, 0); |
a2f40ccd | 293 | } |
f172ddc6 | 294 | spin_unlock(&booke_wdt_lock); |
a2f40ccd KG |
295 | |
296 | return ret; | |
297 | } | |
fbdd7144 TT |
298 | |
299 | module_init(booke_wdt_init); | |
300 | module_exit(booke_wdt_exit); | |
301 | ||
302 | MODULE_DESCRIPTION("PowerPC Book-E watchdog driver"); | |
303 | MODULE_LICENSE("GPL"); |