[deliverable/linux.git] / drivers / watchdog / imx2_wdt.c

/*
 * Watchdog driver for IMX2 and later processors
 *
 *  Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
 *  Copyright (C) 2014 Freescale Semiconductor, Inc.
 *
 * some parts adapted by similar drivers from Darius Augulis and Vladimir
 * Zapolskiy, additional improvements by Wim Van Sebroeck.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
 *
 *			MX1:		MX2+:
 *			----		-----
 * Registers:		32-bit		16-bit
 * Stopable timer:	Yes		No
 * Need to enable clk:	No		Yes
 * Halt on suspend:	Manual		Can be automatic
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/jiffies.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/notifier.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/reboot.h>
#include <linux/regmap.h>
#include <linux/timer.h>
#include <linux/watchdog.h>

#define DRIVER_NAME "imx2-wdt"

#define IMX2_WDT_WCR		0x00		/* Control Register */
#define IMX2_WDT_WCR_WT		(0xFF << 8)	/* -> Watchdog Timeout Field */
#define IMX2_WDT_WCR_WRE	(1 << 3)	/* -> WDOG Reset Enable */
#define IMX2_WDT_WCR_WDE	(1 << 2)	/* -> Watchdog Enable */
#define IMX2_WDT_WCR_WDZST	(1 << 0)	/* -> Watchdog timer Suspend */

#define IMX2_WDT_WSR		0x02		/* Service Register */
#define IMX2_WDT_SEQ1		0x5555		/* -> service sequence 1 */
#define IMX2_WDT_SEQ2		0xAAAA		/* -> service sequence 2 */

#define IMX2_WDT_WRSR		0x04		/* Reset Status Register */
#define IMX2_WDT_WRSR_TOUT	(1 << 1)	/* -> Reset due to Timeout */

#define IMX2_WDT_WMCR		0x08		/* Misc Register */

#define IMX2_WDT_MAX_TIME	128
#define IMX2_WDT_DEFAULT_TIME	60		/* in seconds */

#define WDOG_SEC_TO_COUNT(s)	((s * 2 - 1) << 8)

struct imx2_wdt_device {
	struct clk *clk;
	struct regmap *regmap;
	struct timer_list timer;	/* Pings the watchdog when closed */
	struct watchdog_device wdog;
	struct notifier_block restart_handler;
};

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");


static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
module_param(timeout, uint, 0);
MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
				__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");

static const struct watchdog_info imx2_wdt_info = {
	.identity = "imx2+ watchdog",
	.options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
};

static int imx2_restart_handler(struct notifier_block *this, unsigned long mode,
				void *cmd)
{
	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
	struct imx2_wdt_device *wdev = container_of(this,
						    struct imx2_wdt_device,
						    restart_handler);
	/* Assert SRS signal */
	regmap_write(wdev->regmap, 0, wcr_enable);
	/*
	 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	 * written twice), we add another two writes to ensure there must be at
	 * least two writes happen in the same one 32kHz clock period.  We save
	 * the target check here, since the writes shouldn't be a huge burden
	 * for other platforms.
	 */
	regmap_write(wdev->regmap, 0, wcr_enable);
	regmap_write(wdev->regmap, 0, wcr_enable);

	/* wait for reset to assert... */
	mdelay(500);

	return NOTIFY_DONE;
}

static inline void imx2_wdt_setup(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	/* Suspend timer in low power mode, write once-only */
	val |= IMX2_WDT_WCR_WDZST;
	/* Strip the old watchdog Time-Out value */
	val &= ~IMX2_WDT_WCR_WT;
	/* Generate reset if WDOG times out */
	val &= ~IMX2_WDT_WCR_WRE;
	/* Keep Watchdog Disabled */
	val &= ~IMX2_WDT_WCR_WDE;
	/* Set the watchdog's Time-Out value */
	val |= WDOG_SEC_TO_COUNT(wdog->timeout);

	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);

	/* enable the watchdog */
	val |= IMX2_WDT_WCR_WDE;
	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
}

static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
{
	u32 val;

	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);

	return val & IMX2_WDT_WCR_WDE;
}

static int imx2_wdt_ping(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	return 0;
}

static void imx2_wdt_timer_ping(unsigned long arg)
{
	struct watchdog_device *wdog = (struct watchdog_device *)arg;
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	imx2_wdt_ping(wdog);
	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
}

static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int new_timeout)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	wdog->timeout = new_timeout;

	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
			   WDOG_SEC_TO_COUNT(new_timeout));
	return 0;
}

static int imx2_wdt_start(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/* delete the timer that pings the watchdog after close */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
	} else
		imx2_wdt_setup(wdog);

	return imx2_wdt_ping(wdog);
}

static int imx2_wdt_stop(struct watchdog_device *wdog)
{
	/*
	 * We don't need a clk_disable, it cannot be disabled once started.
	 * We use a timer to ping the watchdog while /dev/watchdog is closed
	 */
	imx2_wdt_timer_ping((unsigned long)wdog);
	return 0;
}

static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
{
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_timer_ping((unsigned long)wdog);
	}
}

static const struct watchdog_ops imx2_wdt_ops = {
	.owner = THIS_MODULE,
	.start = imx2_wdt_start,
	.stop = imx2_wdt_stop,
	.ping = imx2_wdt_ping,
	.set_timeout = imx2_wdt_set_timeout,
};

static const struct regmap_config imx2_wdt_regmap_config = {
	.reg_bits = 16,
	.reg_stride = 2,
	.val_bits = 16,
	.max_register = 0x8,
};

static int __init imx2_wdt_probe(struct platform_device *pdev)
{
	struct imx2_wdt_device *wdev;
	struct watchdog_device *wdog;
	struct resource *res;
	void __iomem *base;
	int ret;
	u32 val;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(base))
		return PTR_ERR(base);

	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
						 &imx2_wdt_regmap_config);
	if (IS_ERR(wdev->regmap)) {
		dev_err(&pdev->dev, "regmap init failed\n");
		return PTR_ERR(wdev->regmap);
	}

	wdev->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdev->clk)) {
		dev_err(&pdev->dev, "can't get Watchdog clock\n");
		return PTR_ERR(wdev->clk);
	}

	wdog			= &wdev->wdog;
	wdog->info		= &imx2_wdt_info;
	wdog->ops		= &imx2_wdt_ops;
	wdog->min_timeout	= 1;
	wdog->max_timeout	= IMX2_WDT_MAX_TIME;
	wdog->parent		= &pdev->dev;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;

	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	if (wdog->timeout != timeout)
		dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
			 timeout, wdog->timeout);

	platform_set_drvdata(pdev, wdog);
	watchdog_set_drvdata(wdog, wdev);
	watchdog_set_nowayout(wdog, nowayout);
	watchdog_init_timeout(wdog, timeout, &pdev->dev);

	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);

	imx2_wdt_ping_if_active(wdog);

	/*
	 * Disable the watchdog power down counter at boot. Otherwise the power
	 * down counter will pull down the #WDOG interrupt line for one clock
	 * cycle.
	 */
	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);

	ret = watchdog_register_device(wdog);
	if (ret) {
		dev_err(&pdev->dev, "cannot register watchdog device\n");
		goto disable_clk;
	}

	wdev->restart_handler.notifier_call = imx2_restart_handler;
	wdev->restart_handler.priority = 128;
	ret = register_restart_handler(&wdev->restart_handler);
	if (ret)
		dev_err(&pdev->dev, "cannot register restart handler\n");

	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
		 wdog->timeout, nowayout);

	return 0;

disable_clk:
	clk_disable_unprepare(wdev->clk);
	return ret;
}

static int __exit imx2_wdt_remove(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	unregister_restart_handler(&wdev->restart_handler);

	watchdog_unregister_device(wdog);

	if (imx2_wdt_is_running(wdev)) {
		del_timer_sync(&wdev->timer);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
	}
	return 0;
}

static void imx2_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	if (imx2_wdt_is_running(wdev)) {
		/*
		 * We are running, we need to delete the timer but will
		 * give max timeout before reboot will take place
		 */
		del_timer_sync(&wdev->timer);
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);
		dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
	}
}

#ifdef CONFIG_PM_SLEEP
/* Disable watchdog if it is active or non-active but still running */
static int imx2_wdt_suspend(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);

	/* The watchdog IP block is running */
	if (imx2_wdt_is_running(wdev)) {
		imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
		imx2_wdt_ping(wdog);

		/* The watchdog is not active */
		if (!watchdog_active(wdog))
			del_timer_sync(&wdev->timer);
	}

	clk_disable_unprepare(wdev->clk);

	return 0;
}

/* Enable watchdog and configure it if necessary */
static int imx2_wdt_resume(struct device *dev)
{
	struct watchdog_device *wdog = dev_get_drvdata(dev);
	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	int ret;

	ret = clk_prepare_enable(wdev->clk);
	if (ret)
		return ret;

	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
		/*
		 * If the watchdog is still active and resumes
		 * from deep sleep state, need to restart the
		 * watchdog again.
		 */
		imx2_wdt_setup(wdog);
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
	} else if (imx2_wdt_is_running(wdev)) {
		/* Resuming from non-deep sleep state. */
		imx2_wdt_set_timeout(wdog, wdog->timeout);
		imx2_wdt_ping(wdog);
		/*
		 * But the watchdog is not active, then start
		 * the timer again.
		 */
		if (!watchdog_active(wdog))
			mod_timer(&wdev->timer,
				  jiffies + wdog->timeout * HZ / 2);
	}

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
			 imx2_wdt_resume);

static const struct of_device_id imx2_wdt_dt_ids[] = {
	{ .compatible = "fsl,imx21-wdt", },
	{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);

static struct platform_driver imx2_wdt_driver = {
	.remove		= __exit_p(imx2_wdt_remove),
	.shutdown	= imx2_wdt_shutdown,
	.driver		= {
		.name	= DRIVER_NAME,
		.pm     = &imx2_wdt_pm_ops,
		.of_match_table = imx2_wdt_dt_ids,
	},
};

module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);

MODULE_AUTHOR("Wolfram Sang");
MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("platform:" DRIVER_NAME);
Commit	Line	Data
bb2fd8a8 WS	1	/*
	2	* Watchdog driver for IMX2 and later processors
	3	*
	4	* Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
1a9c5efa	5	* Copyright (C) 2014 Freescale Semiconductor, Inc.
bb2fd8a8 WS	6	*
	7	* some parts adapted by similar drivers from Darius Augulis and Vladimir
	8	* Zapolskiy, additional improvements by Wim Van Sebroeck.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published by
	12	* the Free Software Foundation.
	13	*
	14	* NOTE: MX1 has a slightly different Watchdog than MX2 and later:
	15	*
	16	* MX1: MX2+:
	17	* ---- -----
	18	* Registers: 32-bit 16-bit
	19	* Stopable timer: Yes No
	20	* Need to enable clk: No Yes
	21	* Halt on suspend: Manual Can be automatic
	22	*/
	23
30cb042a	24	#include <linux/clk.h>
334a9d81	25	#include <linux/delay.h>
bb2fd8a8	26	#include <linux/init.h>
30cb042a XL	27	#include <linux/io.h>
30cb042a XL	28	#include <linux/jiffies.h>
bb2fd8a8	29	#include <linux/kernel.h>
bb2fd8a8 WS	30	#include <linux/module.h>
bb2fd8a8 WS	31	#include <linux/moduleparam.h>
334a9d81	32	#include <linux/notifier.h>
f728f4bf	33	#include <linux/of_address.h>
bb2fd8a8	34	#include <linux/platform_device.h>
334a9d81	35	#include <linux/reboot.h>
a7977003	36	#include <linux/regmap.h>
bb2fd8a8	37	#include <linux/timer.h>
30cb042a	38	#include <linux/watchdog.h>
bb2fd8a8 WS	39
	40	#define DRIVER_NAME "imx2-wdt"
	41
	42	#define IMX2_WDT_WCR 0x00 /* Control Register */
	43	#define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
	44	#define IMX2_WDT_WCR_WRE (1 << 3) /* -> WDOG Reset Enable */
	45	#define IMX2_WDT_WCR_WDE (1 << 2) /* -> Watchdog Enable */
1a9c5efa	46	#define IMX2_WDT_WCR_WDZST (1 << 0) /* -> Watchdog timer Suspend */
bb2fd8a8 WS	47
	48	#define IMX2_WDT_WSR 0x02 /* Service Register */
	49	#define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
	50	#define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
	51
474ef121 OS	52	#define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
	53	#define IMX2_WDT_WRSR_TOUT (1 << 1) /* -> Reset due to Timeout */
	54
5fe65ce7 MP	55	#define IMX2_WDT_WMCR 0x08 /* Misc Register */
5fe65ce7 MP	56
bb2fd8a8 WS	57	#define IMX2_WDT_MAX_TIME 128
	58	#define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
	59
	60	#define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
	61
faad5de0	62	struct imx2_wdt_device {
bb2fd8a8	63	struct clk *clk;
a7977003	64	struct regmap *regmap;
bb2fd8a8	65	struct timer_list timer; /* Pings the watchdog when closed */
faad5de0	66	struct watchdog_device wdog;
334a9d81	67	struct notifier_block restart_handler;
faad5de0	68	};
bb2fd8a8	69
86a1e189 WVS	70	static bool nowayout = WATCHDOG_NOWAYOUT;
86a1e189 WVS	71	module_param(nowayout, bool, 0);
bb2fd8a8 WS	72	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
	73	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	74
	75
	76	static unsigned timeout = IMX2_WDT_DEFAULT_TIME;
	77	module_param(timeout, uint, 0);
	78	MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
	79	__MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
	80
	81	static const struct watchdog_info imx2_wdt_info = {
	82	.identity = "imx2+ watchdog",
	83	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \| WDIOF_MAGICCLOSE,
	84	};
	85
334a9d81 JL	86	static int imx2_restart_handler(struct notifier_block *this, unsigned long mode,
	87	void *cmd)
	88	{
	89	unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
	90	struct imx2_wdt_device *wdev = container_of(this,
	91	struct imx2_wdt_device,
	92	restart_handler);
	93	/* Assert SRS signal */
	94	regmap_write(wdev->regmap, 0, wcr_enable);
	95	/*
	96	* Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
	97	* written twice), we add another two writes to ensure there must be at
	98	* least two writes happen in the same one 32kHz clock period. We save
	99	* the target check here, since the writes shouldn't be a huge burden
	100	* for other platforms.
	101	*/
	102	regmap_write(wdev->regmap, 0, wcr_enable);
	103	regmap_write(wdev->regmap, 0, wcr_enable);
	104
	105	/* wait for reset to assert... */
	106	mdelay(500);
	107
	108	return NOTIFY_DONE;
	109	}
	110
faad5de0	111	static inline void imx2_wdt_setup(struct watchdog_device *wdog)
bb2fd8a8	112	{
faad5de0	113	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
a7977003 XL	114	u32 val;
a7977003 XL	115
faad5de0	116	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
bb2fd8a8	117
1a9c5efa AH	118	/* Suspend timer in low power mode, write once-only */
1a9c5efa AH	119	val \|= IMX2_WDT_WCR_WDZST;
bb2fd8a8 WS	120	/* Strip the old watchdog Time-Out value */
	121	val &= ~IMX2_WDT_WCR_WT;
	122	/* Generate reset if WDOG times out */
	123	val &= ~IMX2_WDT_WCR_WRE;
	124	/* Keep Watchdog Disabled */
	125	val &= ~IMX2_WDT_WCR_WDE;
	126	/* Set the watchdog's Time-Out value */
faad5de0	127	val \|= WDOG_SEC_TO_COUNT(wdog->timeout);
bb2fd8a8	128
faad5de0	129	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	130
	131	/* enable the watchdog */
	132	val \|= IMX2_WDT_WCR_WDE;
faad5de0	133	regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
bb2fd8a8 WS	134	}
bb2fd8a8 WS	135
faad5de0	136	static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
bb2fd8a8	137	{
faad5de0	138	u32 val;
bb2fd8a8	139
faad5de0 AG	140	regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
	141
	142	return val & IMX2_WDT_WCR_WDE;
bb2fd8a8 WS	143	}
bb2fd8a8 WS	144
faad5de0	145	static int imx2_wdt_ping(struct watchdog_device *wdog)
bb2fd8a8	146	{
faad5de0	147	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	148
faad5de0 AG	149	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
	150	regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
	151	return 0;
bb2fd8a8 WS	152	}
bb2fd8a8 WS	153
faad5de0	154	static void imx2_wdt_timer_ping(unsigned long arg)
bb2fd8a8	155	{
faad5de0 AG	156	struct watchdog_device wdog = (struct watchdog_device )arg;
	157	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	158
	159	/* ping it every wdog->timeout / 2 seconds to prevent reboot */
	160	imx2_wdt_ping(wdog);
	161	mod_timer(&wdev->timer, jiffies + wdog->timeout * HZ / 2);
bb2fd8a8 WS	162	}
bb2fd8a8 WS	163
faad5de0 AG	164	static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
faad5de0 AG	165	unsigned int new_timeout)
bb2fd8a8	166	{
faad5de0 AG	167	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
faad5de0 AG	168
30dd4a8f MG	169	wdog->timeout = new_timeout;
30dd4a8f MG	170
faad5de0	171	regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
a7977003	172	WDOG_SEC_TO_COUNT(new_timeout));
faad5de0	173	return 0;
bb2fd8a8 WS	174	}
bb2fd8a8 WS	175
faad5de0	176	static int imx2_wdt_start(struct watchdog_device *wdog)
bb2fd8a8	177	{
faad5de0	178	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	179
faad5de0 AG	180	if (imx2_wdt_is_running(wdev)) {
	181	/* delete the timer that pings the watchdog after close */
	182	del_timer_sync(&wdev->timer);
	183	imx2_wdt_set_timeout(wdog, wdog->timeout);
	184	} else
	185	imx2_wdt_setup(wdog);
	186
	187	return imx2_wdt_ping(wdog);
bb2fd8a8 WS	188	}
bb2fd8a8 WS	189
faad5de0	190	static int imx2_wdt_stop(struct watchdog_device *wdog)
bb2fd8a8	191	{
faad5de0 AG	192	/*
	193	* We don't need a clk_disable, it cannot be disabled once started.
	194	* We use a timer to ping the watchdog while /dev/watchdog is closed
	195	*/
	196	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	197	return 0;
	198	}
	199
faad5de0	200	static inline void imx2_wdt_ping_if_active(struct watchdog_device *wdog)
bb2fd8a8	201	{
faad5de0	202	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	203
faad5de0 AG	204	if (imx2_wdt_is_running(wdev)) {
	205	imx2_wdt_set_timeout(wdog, wdog->timeout);
	206	imx2_wdt_timer_ping((unsigned long)wdog);
bb2fd8a8 WS	207	}
	208	}
	209
4bd8ce33	210	static const struct watchdog_ops imx2_wdt_ops = {
bb2fd8a8	211	.owner = THIS_MODULE,
faad5de0 AG	212	.start = imx2_wdt_start,
	213	.stop = imx2_wdt_stop,
	214	.ping = imx2_wdt_ping,
	215	.set_timeout = imx2_wdt_set_timeout,
bb2fd8a8 WS	216	};
bb2fd8a8 WS	217
4bd8ce33	218	static const struct regmap_config imx2_wdt_regmap_config = {
a7977003 XL	219	.reg_bits = 16,
	220	.reg_stride = 2,
	221	.val_bits = 16,
	222	.max_register = 0x8,
	223	};
	224
bb2fd8a8 WS	225	static int __init imx2_wdt_probe(struct platform_device *pdev)
bb2fd8a8 WS	226	{
faad5de0 AG	227	struct imx2_wdt_device *wdev;
faad5de0 AG	228	struct watchdog_device *wdog;
bb2fd8a8	229	struct resource *res;
a7977003 XL	230	void __iomem *base;
a7977003 XL	231	int ret;
faad5de0 AG	232	u32 val;
	233
	234	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	235	if (!wdev)
	236	return -ENOMEM;
bb2fd8a8 WS	237
bb2fd8a8 WS	238	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
a7977003 XL	239	base = devm_ioremap_resource(&pdev->dev, res);
	240	if (IS_ERR(base))
	241	return PTR_ERR(base);
	242
faad5de0 AG	243	wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
	244	&imx2_wdt_regmap_config);
	245	if (IS_ERR(wdev->regmap)) {
a7977003	246	dev_err(&pdev->dev, "regmap init failed\n");
faad5de0	247	return PTR_ERR(wdev->regmap);
a7977003	248	}
bb2fd8a8	249
faad5de0 AG	250	wdev->clk = devm_clk_get(&pdev->dev, NULL);
faad5de0 AG	251	if (IS_ERR(wdev->clk)) {
bb2fd8a8	252	dev_err(&pdev->dev, "can't get Watchdog clock\n");
faad5de0	253	return PTR_ERR(wdev->clk);
bb2fd8a8 WS	254	}
bb2fd8a8 WS	255
faad5de0 AG	256	wdog = &wdev->wdog;
	257	wdog->info = &imx2_wdt_info;
	258	wdog->ops = &imx2_wdt_ops;
	259	wdog->min_timeout = 1;
	260	wdog->max_timeout = IMX2_WDT_MAX_TIME;
8135193c	261	wdog->parent = &pdev->dev;
bb2fd8a8	262
aefb163c FE	263	ret = clk_prepare_enable(wdev->clk);
	264	if (ret)
	265	return ret;
bb2fd8a8	266
faad5de0 AG	267	regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
faad5de0 AG	268	wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
bb2fd8a8	269
faad5de0 AG	270	wdog->timeout = clamp_t(unsigned, timeout, 1, IMX2_WDT_MAX_TIME);
	271	if (wdog->timeout != timeout)
	272	dev_warn(&pdev->dev, "Initial timeout out of range! Clamped from %u to %u\n",
	273	timeout, wdog->timeout);
	274
	275	platform_set_drvdata(pdev, wdog);
	276	watchdog_set_drvdata(wdog, wdev);
	277	watchdog_set_nowayout(wdog, nowayout);
	278	watchdog_init_timeout(wdog, timeout, &pdev->dev);
	279
	280	setup_timer(&wdev->timer, imx2_wdt_timer_ping, (unsigned long)wdog);
bb2fd8a8	281
faad5de0 AG	282	imx2_wdt_ping_if_active(wdog);
faad5de0 AG	283
5fe65ce7 MP	284	/*
	285	* Disable the watchdog power down counter at boot. Otherwise the power
	286	* down counter will pull down the #WDOG interrupt line for one clock
	287	* cycle.
	288	*/
	289	regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
	290
faad5de0 AG	291	ret = watchdog_register_device(wdog);
	292	if (ret) {
	293	dev_err(&pdev->dev, "cannot register watchdog device\n");
db11cba2	294	goto disable_clk;
faad5de0 AG	295	}
faad5de0 AG	296
334a9d81 JL	297	wdev->restart_handler.notifier_call = imx2_restart_handler;
	298	wdev->restart_handler.priority = 128;
	299	ret = register_restart_handler(&wdev->restart_handler);
	300	if (ret)
	301	dev_err(&pdev->dev, "cannot register restart handler\n");
	302
faad5de0 AG	303	dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
	304	wdog->timeout, nowayout);
	305
	306	return 0;
db11cba2 FE	307
	308	disable_clk:
	309	clk_disable_unprepare(wdev->clk);
	310	return ret;
bb2fd8a8 WS	311	}
	312
	313	static int __exit imx2_wdt_remove(struct platform_device *pdev)
	314	{
faad5de0 AG	315	struct watchdog_device *wdog = platform_get_drvdata(pdev);
faad5de0 AG	316	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
bb2fd8a8	317
334a9d81 JL	318	unregister_restart_handler(&wdev->restart_handler);
334a9d81 JL	319
faad5de0	320	watchdog_unregister_device(wdog);
bb2fd8a8	321
faad5de0 AG	322	if (imx2_wdt_is_running(wdev)) {
	323	del_timer_sync(&wdev->timer);
	324	imx2_wdt_ping(wdog);
	325	dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
bdf49574	326	}
bb2fd8a8 WS	327	return 0;
	328	}
	329
	330	static void imx2_wdt_shutdown(struct platform_device *pdev)
	331	{
faad5de0 AG	332	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	333	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	334
	335	if (imx2_wdt_is_running(wdev)) {
	336	/*
	337	* We are running, we need to delete the timer but will
	338	* give max timeout before reboot will take place
	339	*/
	340	del_timer_sync(&wdev->timer);
	341	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	342	imx2_wdt_ping(wdog);
	343	dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
bb2fd8a8 WS	344	}
	345	}
	346
aefbaf3a	347	#ifdef CONFIG_PM_SLEEP
bbd59009	348	/* Disable watchdog if it is active or non-active but still running */
aefbaf3a XL	349	static int imx2_wdt_suspend(struct device *dev)
	350	{
	351	struct watchdog_device *wdog = dev_get_drvdata(dev);
	352	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
	353
bbd59009 XL	354	/* The watchdog IP block is running */
	355	if (imx2_wdt_is_running(wdev)) {
	356	imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
	357	imx2_wdt_ping(wdog);
aefbaf3a	358
bbd59009 XL	359	/* The watchdog is not active */
	360	if (!watchdog_active(wdog))
	361	del_timer_sync(&wdev->timer);
	362	}
aefbaf3a XL	363
	364	clk_disable_unprepare(wdev->clk);
	365
	366	return 0;
	367	}
	368
	369	/* Enable watchdog and configure it if necessary */
	370	static int imx2_wdt_resume(struct device *dev)
	371	{
	372	struct watchdog_device *wdog = dev_get_drvdata(dev);
	373	struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
aefb163c	374	int ret;
aefbaf3a	375
aefb163c FE	376	ret = clk_prepare_enable(wdev->clk);
	377	if (ret)
	378	return ret;
aefbaf3a XL	379
aefbaf3a XL	380	if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
bbd59009 XL	381	/*
	382	* If the watchdog is still active and resumes
	383	* from deep sleep state, need to restart the
	384	* watchdog again.
aefbaf3a XL	385	*/
	386	imx2_wdt_setup(wdog);
	387	imx2_wdt_set_timeout(wdog, wdog->timeout);
	388	imx2_wdt_ping(wdog);
	389	} else if (imx2_wdt_is_running(wdev)) {
bbd59009 XL	390	/* Resuming from non-deep sleep state. */
bbd59009 XL	391	imx2_wdt_set_timeout(wdog, wdog->timeout);
aefbaf3a	392	imx2_wdt_ping(wdog);
bbd59009 XL	393	/*
	394	* But the watchdog is not active, then start
	395	* the timer again.
	396	*/
	397	if (!watchdog_active(wdog))
	398	mod_timer(&wdev->timer,
	399	jiffies + wdog->timeout * HZ / 2);
aefbaf3a XL	400	}
	401
	402	return 0;
	403	}
	404	#endif
	405
	406	static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
	407	imx2_wdt_resume);
	408
f5a427ee SG	409	static const struct of_device_id imx2_wdt_dt_ids[] = {
	410	{ .compatible = "fsl,imx21-wdt", },
	411	{ /* sentinel */ }
	412	};
813296a1	413	MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
f5a427ee	414
bb2fd8a8	415	static struct platform_driver imx2_wdt_driver = {
bb2fd8a8 WS	416	.remove = __exit_p(imx2_wdt_remove),
	417	.shutdown = imx2_wdt_shutdown,
	418	.driver = {
	419	.name = DRIVER_NAME,
aefbaf3a	420	.pm = &imx2_wdt_pm_ops,
f5a427ee	421	.of_match_table = imx2_wdt_dt_ids,
bb2fd8a8 WS	422	},
	423	};
	424
1cb9204c	425	module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
bb2fd8a8 WS	426
	427	MODULE_AUTHOR("Wolfram Sang");
	428	MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
	429	MODULE_LICENSE("GPL v2");
bb2fd8a8	430	MODULE_ALIAS("platform:" DRIVER_NAME);