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e1fee94f OS |
1 | /* |
2 | * Watchdog Timer Driver | |
3 | * for ITE IT87xx Environment Control - Low Pin Count Input / Output | |
4 | * | |
5 | * (c) Copyright 2007 Oliver Schuster <olivers137@aol.com> | |
6 | * | |
7 | * Based on softdog.c by Alan Cox, | |
8 | * 83977f_wdt.c by Jose Goncalves, | |
9 | * it87.c by Chris Gauthron, Jean Delvare | |
10 | * | |
11 | * Data-sheets: Publicly available at the ITE website | |
12 | * http://www.ite.com.tw/ | |
13 | * | |
14 | * Support of the watchdog timers, which are available on | |
ee3e9658 | 15 | * IT8716, IT8718, IT8720, IT8726 and IT8712 (J,K version). |
e1fee94f OS |
16 | * |
17 | * This program is free software; you can redistribute it and/or | |
18 | * modify it under the terms of the GNU General Public License | |
19 | * as published by the Free Software Foundation; either version | |
20 | * 2 of the License, or (at your option) any later version. | |
21 | * | |
22 | * This program is distributed in the hope that it will be useful, | |
23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
25 | * GNU General Public License for more details. | |
26 | * | |
27 | * You should have received a copy of the GNU General Public License | |
28 | * along with this program; if not, write to the Free Software | |
29 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
30 | */ | |
31 | ||
32 | #include <linux/module.h> | |
33 | #include <linux/moduleparam.h> | |
34 | #include <linux/types.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/fs.h> | |
37 | #include <linux/miscdevice.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/ioport.h> | |
40 | #include <linux/watchdog.h> | |
41 | #include <linux/notifier.h> | |
42 | #include <linux/reboot.h> | |
43 | #include <linux/uaccess.h> | |
44 | #include <linux/io.h> | |
45 | ||
46 | #include <asm/system.h> | |
47 | ||
ee3e9658 | 48 | #define WATCHDOG_VERSION "1.13" |
e1fee94f OS |
49 | #define WATCHDOG_NAME "IT87 WDT" |
50 | #define PFX WATCHDOG_NAME ": " | |
51 | #define DRIVER_VERSION WATCHDOG_NAME " driver, v" WATCHDOG_VERSION "\n" | |
52 | #define WD_MAGIC 'V' | |
53 | ||
54 | /* Defaults for Module Parameter */ | |
55 | #define DEFAULT_NOGAMEPORT 0 | |
56 | #define DEFAULT_EXCLUSIVE 1 | |
57 | #define DEFAULT_TIMEOUT 60 | |
58 | #define DEFAULT_TESTMODE 0 | |
59 | #define DEFAULT_NOWAYOUT WATCHDOG_NOWAYOUT | |
60 | ||
61 | /* IO Ports */ | |
62 | #define REG 0x2e | |
63 | #define VAL 0x2f | |
64 | ||
65 | /* Logical device Numbers LDN */ | |
66 | #define GPIO 0x07 | |
67 | #define GAMEPORT 0x09 | |
68 | #define CIR 0x0a | |
69 | ||
70 | /* Configuration Registers and Functions */ | |
71 | #define LDNREG 0x07 | |
72 | #define CHIPID 0x20 | |
73 | #define CHIPREV 0x22 | |
74 | #define ACTREG 0x30 | |
75 | #define BASEREG 0x60 | |
76 | ||
77 | /* Chip Id numbers */ | |
78 | #define NO_DEV_ID 0xffff | |
79 | #define IT8705_ID 0x8705 | |
80 | #define IT8712_ID 0x8712 | |
81 | #define IT8716_ID 0x8716 | |
82 | #define IT8718_ID 0x8718 | |
ee3e9658 | 83 | #define IT8720_ID 0x8720 |
e1fee94f OS |
84 | #define IT8726_ID 0x8726 /* the data sheet suggest wrongly 0x8716 */ |
85 | ||
86 | /* GPIO Configuration Registers LDN=0x07 */ | |
87 | #define WDTCTRL 0x71 | |
88 | #define WDTCFG 0x72 | |
89 | #define WDTVALLSB 0x73 | |
90 | #define WDTVALMSB 0x74 | |
91 | ||
92 | /* GPIO Bits WDTCTRL */ | |
93 | #define WDT_CIRINT 0x80 | |
94 | #define WDT_MOUSEINT 0x40 | |
95 | #define WDT_KYBINT 0x20 | |
ee3e9658 | 96 | #define WDT_GAMEPORT 0x10 /* not in it8718, it8720 */ |
e1fee94f OS |
97 | #define WDT_FORCE 0x02 |
98 | #define WDT_ZERO 0x01 | |
99 | ||
100 | /* GPIO Bits WDTCFG */ | |
101 | #define WDT_TOV1 0x80 | |
102 | #define WDT_KRST 0x40 | |
103 | #define WDT_TOVE 0x20 | |
104 | #define WDT_PWROK 0x10 | |
105 | #define WDT_INT_MASK 0x0f | |
106 | ||
107 | /* CIR Configuration Register LDN=0x0a */ | |
108 | #define CIR_ILS 0x70 | |
109 | ||
110 | /* The default Base address is not always available, we use this */ | |
111 | #define CIR_BASE 0x0208 | |
112 | ||
113 | /* CIR Controller */ | |
114 | #define CIR_DR(b) (b) | |
115 | #define CIR_IER(b) (b + 1) | |
116 | #define CIR_RCR(b) (b + 2) | |
117 | #define CIR_TCR1(b) (b + 3) | |
118 | #define CIR_TCR2(b) (b + 4) | |
119 | #define CIR_TSR(b) (b + 5) | |
120 | #define CIR_RSR(b) (b + 6) | |
121 | #define CIR_BDLR(b) (b + 5) | |
122 | #define CIR_BDHR(b) (b + 6) | |
123 | #define CIR_IIR(b) (b + 7) | |
124 | ||
125 | /* Default Base address of Game port */ | |
126 | #define GP_BASE_DEFAULT 0x0201 | |
127 | ||
128 | /* wdt_status */ | |
129 | #define WDTS_TIMER_RUN 0 | |
130 | #define WDTS_DEV_OPEN 1 | |
131 | #define WDTS_KEEPALIVE 2 | |
132 | #define WDTS_LOCKED 3 | |
133 | #define WDTS_USE_GP 4 | |
134 | #define WDTS_EXPECTED 5 | |
135 | ||
136 | static unsigned int base, gpact, ciract; | |
137 | static unsigned long wdt_status; | |
138 | static DEFINE_SPINLOCK(spinlock); | |
139 | ||
140 | static int nogameport = DEFAULT_NOGAMEPORT; | |
141 | static int exclusive = DEFAULT_EXCLUSIVE; | |
142 | static int timeout = DEFAULT_TIMEOUT; | |
143 | static int testmode = DEFAULT_TESTMODE; | |
144 | static int nowayout = DEFAULT_NOWAYOUT; | |
145 | ||
146 | module_param(nogameport, int, 0); | |
147 | MODULE_PARM_DESC(nogameport, "Forbid the activation of game port, default=" | |
148 | __MODULE_STRING(DEFAULT_NOGAMEPORT)); | |
149 | module_param(exclusive, int, 0); | |
150 | MODULE_PARM_DESC(exclusive, "Watchdog exclusive device open, default=" | |
151 | __MODULE_STRING(DEFAULT_EXCLUSIVE)); | |
152 | module_param(timeout, int, 0); | |
153 | MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds, default=" | |
154 | __MODULE_STRING(DEFAULT_TIMEOUT)); | |
155 | module_param(testmode, int, 0); | |
156 | MODULE_PARM_DESC(testmode, "Watchdog test mode (1 = no reboot), default=" | |
157 | __MODULE_STRING(DEFAULT_TESTMODE)); | |
158 | module_param(nowayout, int, 0); | |
159 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started, default=" | |
160 | __MODULE_STRING(WATCHDOG_NOWAYOUT)); | |
161 | ||
162 | /* Superio Chip */ | |
163 | ||
164 | static inline void superio_enter(void) | |
165 | { | |
166 | outb(0x87, REG); | |
167 | outb(0x01, REG); | |
168 | outb(0x55, REG); | |
169 | outb(0x55, REG); | |
170 | } | |
171 | ||
172 | static inline void superio_exit(void) | |
173 | { | |
174 | outb(0x02, REG); | |
175 | outb(0x02, VAL); | |
176 | } | |
177 | ||
178 | static inline void superio_select(int ldn) | |
179 | { | |
180 | outb(LDNREG, REG); | |
181 | outb(ldn, VAL); | |
182 | } | |
183 | ||
184 | static inline int superio_inb(int reg) | |
185 | { | |
186 | outb(reg, REG); | |
187 | return inb(VAL); | |
188 | } | |
189 | ||
190 | static inline void superio_outb(int val, int reg) | |
191 | { | |
143a2e54 WVS |
192 | outb(reg, REG); |
193 | outb(val, VAL); | |
e1fee94f OS |
194 | } |
195 | ||
196 | static inline int superio_inw(int reg) | |
197 | { | |
198 | int val; | |
199 | outb(reg++, REG); | |
200 | val = inb(VAL) << 8; | |
201 | outb(reg, REG); | |
202 | val |= inb(VAL); | |
203 | return val; | |
204 | } | |
205 | ||
206 | static inline void superio_outw(int val, int reg) | |
207 | { | |
143a2e54 WVS |
208 | outb(reg++, REG); |
209 | outb(val >> 8, VAL); | |
210 | outb(reg, REG); | |
211 | outb(val, VAL); | |
e1fee94f OS |
212 | } |
213 | ||
214 | /* watchdog timer handling */ | |
215 | ||
216 | static void wdt_keepalive(void) | |
217 | { | |
218 | if (test_bit(WDTS_USE_GP, &wdt_status)) | |
219 | inb(base); | |
220 | else | |
221 | /* The timer reloads with around 5 msec delay */ | |
222 | outb(0x55, CIR_DR(base)); | |
223 | set_bit(WDTS_KEEPALIVE, &wdt_status); | |
224 | } | |
225 | ||
226 | static void wdt_start(void) | |
227 | { | |
228 | unsigned long flags; | |
229 | ||
230 | spin_lock_irqsave(&spinlock, flags); | |
231 | superio_enter(); | |
232 | ||
233 | superio_select(GPIO); | |
234 | if (test_bit(WDTS_USE_GP, &wdt_status)) | |
235 | superio_outb(WDT_GAMEPORT, WDTCTRL); | |
236 | else | |
237 | superio_outb(WDT_CIRINT, WDTCTRL); | |
238 | if (!testmode) | |
239 | superio_outb(WDT_TOV1 | WDT_KRST | WDT_PWROK, WDTCFG); | |
240 | else | |
241 | superio_outb(WDT_TOV1, WDTCFG); | |
242 | superio_outb(timeout>>8, WDTVALMSB); | |
243 | superio_outb(timeout, WDTVALLSB); | |
244 | ||
245 | superio_exit(); | |
246 | spin_unlock_irqrestore(&spinlock, flags); | |
247 | } | |
248 | ||
249 | static void wdt_stop(void) | |
250 | { | |
251 | unsigned long flags; | |
252 | ||
253 | spin_lock_irqsave(&spinlock, flags); | |
254 | superio_enter(); | |
255 | ||
256 | superio_select(GPIO); | |
257 | superio_outb(0x00, WDTCTRL); | |
258 | superio_outb(WDT_TOV1, WDTCFG); | |
259 | superio_outb(0x00, WDTVALMSB); | |
260 | superio_outb(0x00, WDTVALLSB); | |
261 | ||
262 | superio_exit(); | |
263 | spin_unlock_irqrestore(&spinlock, flags); | |
264 | } | |
265 | ||
266 | /** | |
267 | * wdt_set_timeout - set a new timeout value with watchdog ioctl | |
268 | * @t: timeout value in seconds | |
269 | * | |
270 | * The hardware device has a 16 bit watchdog timer, thus the | |
271 | * timeout time ranges between 1 and 65535 seconds. | |
272 | * | |
273 | * Used within WDIOC_SETTIMEOUT watchdog device ioctl. | |
274 | */ | |
275 | ||
276 | static int wdt_set_timeout(int t) | |
277 | { | |
278 | unsigned long flags; | |
279 | ||
280 | if (t < 1 || t > 65535) | |
281 | return -EINVAL; | |
282 | ||
283 | timeout = t; | |
284 | ||
285 | spin_lock_irqsave(&spinlock, flags); | |
286 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { | |
287 | superio_enter(); | |
288 | ||
289 | superio_select(GPIO); | |
290 | superio_outb(t>>8, WDTVALMSB); | |
291 | superio_outb(t, WDTVALLSB); | |
292 | ||
293 | superio_exit(); | |
294 | } | |
295 | spin_unlock_irqrestore(&spinlock, flags); | |
296 | return 0; | |
297 | } | |
298 | ||
299 | /** | |
300 | * wdt_get_status - determines the status supported by watchdog ioctl | |
301 | * @status: status returned to user space | |
302 | * | |
303 | * The status bit of the device does not allow to distinguish | |
304 | * between a regular system reset and a watchdog forced reset. | |
305 | * But, in test mode it is useful, so it is supported through | |
306 | * WDIOC_GETSTATUS watchdog ioctl. Additionally the driver | |
307 | * reports the keepalive signal and the acception of the magic. | |
308 | * | |
309 | * Used within WDIOC_GETSTATUS watchdog device ioctl. | |
310 | */ | |
311 | ||
312 | static int wdt_get_status(int *status) | |
313 | { | |
314 | unsigned long flags; | |
315 | ||
316 | *status = 0; | |
317 | if (testmode) { | |
318 | spin_lock_irqsave(&spinlock, flags); | |
319 | superio_enter(); | |
320 | superio_select(GPIO); | |
321 | if (superio_inb(WDTCTRL) & WDT_ZERO) { | |
322 | superio_outb(0x00, WDTCTRL); | |
323 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
324 | *status |= WDIOF_CARDRESET; | |
325 | } | |
326 | ||
327 | superio_exit(); | |
328 | spin_unlock_irqrestore(&spinlock, flags); | |
329 | } | |
330 | if (test_and_clear_bit(WDTS_KEEPALIVE, &wdt_status)) | |
331 | *status |= WDIOF_KEEPALIVEPING; | |
332 | if (test_bit(WDTS_EXPECTED, &wdt_status)) | |
333 | *status |= WDIOF_MAGICCLOSE; | |
334 | return 0; | |
335 | } | |
336 | ||
337 | /* /dev/watchdog handling */ | |
338 | ||
339 | /** | |
340 | * wdt_open - watchdog file_operations .open | |
341 | * @inode: inode of the device | |
342 | * @file: file handle to the device | |
343 | * | |
344 | * The watchdog timer starts by opening the device. | |
345 | * | |
346 | * Used within the file operation of the watchdog device. | |
347 | */ | |
348 | ||
349 | static int wdt_open(struct inode *inode, struct file *file) | |
350 | { | |
351 | if (exclusive && test_and_set_bit(WDTS_DEV_OPEN, &wdt_status)) | |
352 | return -EBUSY; | |
353 | if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) { | |
354 | if (nowayout && !test_and_set_bit(WDTS_LOCKED, &wdt_status)) | |
355 | __module_get(THIS_MODULE); | |
356 | wdt_start(); | |
357 | } | |
358 | return nonseekable_open(inode, file); | |
359 | } | |
360 | ||
361 | /** | |
362 | * wdt_release - watchdog file_operations .release | |
363 | * @inode: inode of the device | |
364 | * @file: file handle to the device | |
365 | * | |
366 | * Closing the watchdog device either stops the watchdog timer | |
367 | * or in the case, that nowayout is set or the magic character | |
368 | * wasn't written, a critical warning about an running watchdog | |
369 | * timer is given. | |
370 | * | |
371 | * Used within the file operation of the watchdog device. | |
372 | */ | |
373 | ||
374 | static int wdt_release(struct inode *inode, struct file *file) | |
375 | { | |
376 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) { | |
377 | if (test_and_clear_bit(WDTS_EXPECTED, &wdt_status)) { | |
378 | wdt_stop(); | |
379 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
380 | } else { | |
381 | wdt_keepalive(); | |
382 | printk(KERN_CRIT PFX | |
383 | "unexpected close, not stopping watchdog!\n"); | |
384 | } | |
385 | } | |
386 | clear_bit(WDTS_DEV_OPEN, &wdt_status); | |
387 | return 0; | |
388 | } | |
389 | ||
390 | /** | |
391 | * wdt_write - watchdog file_operations .write | |
392 | * @file: file handle to the watchdog | |
393 | * @buf: buffer to write | |
394 | * @count: count of bytes | |
395 | * @ppos: pointer to the position to write. No seeks allowed | |
396 | * | |
397 | * A write to a watchdog device is defined as a keepalive signal. Any | |
398 | * write of data will do, as we don't define content meaning. | |
399 | * | |
400 | * Used within the file operation of the watchdog device. | |
401 | */ | |
402 | ||
403 | static ssize_t wdt_write(struct file *file, const char __user *buf, | |
404 | size_t count, loff_t *ppos) | |
405 | { | |
406 | if (count) { | |
407 | clear_bit(WDTS_EXPECTED, &wdt_status); | |
408 | wdt_keepalive(); | |
409 | } | |
410 | if (!nowayout) { | |
411 | size_t ofs; | |
412 | ||
413 | /* note: just in case someone wrote the magic character long ago */ | |
414 | for (ofs = 0; ofs != count; ofs++) { | |
415 | char c; | |
416 | if (get_user(c, buf + ofs)) | |
417 | return -EFAULT; | |
418 | if (c == WD_MAGIC) | |
419 | set_bit(WDTS_EXPECTED, &wdt_status); | |
420 | } | |
421 | } | |
422 | return count; | |
423 | } | |
424 | ||
42747d71 | 425 | static const struct watchdog_info ident = { |
e1fee94f OS |
426 | .options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE | WDIOF_KEEPALIVEPING, |
427 | .firmware_version = 1, | |
428 | .identity = WATCHDOG_NAME, | |
429 | }; | |
430 | ||
431 | /** | |
432 | * wdt_ioctl - watchdog file_operations .unlocked_ioctl | |
433 | * @file: file handle to the device | |
434 | * @cmd: watchdog command | |
435 | * @arg: argument pointer | |
436 | * | |
437 | * The watchdog API defines a common set of functions for all watchdogs | |
438 | * according to their available features. | |
439 | * | |
440 | * Used within the file operation of the watchdog device. | |
441 | */ | |
442 | ||
443 | static long wdt_ioctl(struct file *file, unsigned int cmd, unsigned long arg) | |
444 | { | |
445 | int rc = 0, status, new_options, new_timeout; | |
446 | union { | |
447 | struct watchdog_info __user *ident; | |
448 | int __user *i; | |
449 | } uarg; | |
450 | ||
451 | uarg.i = (int __user *)arg; | |
452 | ||
453 | switch (cmd) { | |
454 | case WDIOC_GETSUPPORT: | |
455 | return copy_to_user(uarg.ident, | |
456 | &ident, sizeof(ident)) ? -EFAULT : 0; | |
457 | ||
458 | case WDIOC_GETSTATUS: | |
459 | wdt_get_status(&status); | |
460 | return put_user(status, uarg.i); | |
461 | ||
462 | case WDIOC_GETBOOTSTATUS: | |
463 | return put_user(0, uarg.i); | |
464 | ||
465 | case WDIOC_KEEPALIVE: | |
466 | wdt_keepalive(); | |
467 | return 0; | |
468 | ||
469 | case WDIOC_SETOPTIONS: | |
470 | if (get_user(new_options, uarg.i)) | |
471 | return -EFAULT; | |
472 | ||
473 | switch (new_options) { | |
474 | case WDIOS_DISABLECARD: | |
475 | if (test_bit(WDTS_TIMER_RUN, &wdt_status)) | |
476 | wdt_stop(); | |
477 | clear_bit(WDTS_TIMER_RUN, &wdt_status); | |
478 | return 0; | |
479 | ||
480 | case WDIOS_ENABLECARD: | |
481 | if (!test_and_set_bit(WDTS_TIMER_RUN, &wdt_status)) | |
482 | wdt_start(); | |
483 | return 0; | |
484 | ||
485 | default: | |
486 | return -EFAULT; | |
487 | } | |
488 | ||
489 | case WDIOC_SETTIMEOUT: | |
490 | if (get_user(new_timeout, uarg.i)) | |
491 | return -EFAULT; | |
492 | rc = wdt_set_timeout(new_timeout); | |
493 | case WDIOC_GETTIMEOUT: | |
494 | if (put_user(timeout, uarg.i)) | |
495 | return -EFAULT; | |
496 | return rc; | |
497 | ||
498 | default: | |
499 | return -ENOTTY; | |
500 | } | |
501 | } | |
502 | ||
503 | static int wdt_notify_sys(struct notifier_block *this, unsigned long code, | |
504 | void *unused) | |
505 | { | |
506 | if (code == SYS_DOWN || code == SYS_HALT) | |
507 | wdt_stop(); | |
508 | return NOTIFY_DONE; | |
509 | } | |
510 | ||
511 | static const struct file_operations wdt_fops = { | |
512 | .owner = THIS_MODULE, | |
513 | .llseek = no_llseek, | |
514 | .write = wdt_write, | |
515 | .unlocked_ioctl = wdt_ioctl, | |
516 | .open = wdt_open, | |
517 | .release = wdt_release, | |
518 | }; | |
519 | ||
520 | static struct miscdevice wdt_miscdev = { | |
521 | .minor = WATCHDOG_MINOR, | |
522 | .name = "watchdog", | |
523 | .fops = &wdt_fops, | |
524 | }; | |
525 | ||
526 | static struct notifier_block wdt_notifier = { | |
527 | .notifier_call = wdt_notify_sys, | |
528 | }; | |
529 | ||
530 | static int __init it87_wdt_init(void) | |
531 | { | |
532 | int rc = 0; | |
ee3e9658 | 533 | int try_gameport = !nogameport; |
e1fee94f OS |
534 | u16 chip_type; |
535 | u8 chip_rev; | |
536 | unsigned long flags; | |
537 | ||
538 | spin_lock_irqsave(&spinlock, flags); | |
539 | superio_enter(); | |
540 | chip_type = superio_inw(CHIPID); | |
541 | chip_rev = superio_inb(CHIPREV) & 0x0f; | |
542 | superio_exit(); | |
543 | spin_unlock_irqrestore(&spinlock, flags); | |
544 | ||
545 | switch (chip_type) { | |
546 | case IT8716_ID: | |
e1fee94f OS |
547 | case IT8726_ID: |
548 | break; | |
ee3e9658 OZ |
549 | case IT8718_ID: |
550 | case IT8720_ID: | |
551 | try_gameport = 0; | |
552 | break; | |
e1fee94f OS |
553 | case IT8712_ID: |
554 | if (chip_rev > 7) | |
555 | break; | |
556 | case IT8705_ID: | |
557 | printk(KERN_ERR PFX | |
558 | "Unsupported Chip found, Chip %04x Revision %02x\n", | |
559 | chip_type, chip_rev); | |
560 | return -ENODEV; | |
561 | case NO_DEV_ID: | |
562 | printk(KERN_ERR PFX "no device\n"); | |
563 | return -ENODEV; | |
564 | default: | |
565 | printk(KERN_ERR PFX | |
566 | "Unknown Chip found, Chip %04x Revision %04x\n", | |
567 | chip_type, chip_rev); | |
568 | return -ENODEV; | |
569 | } | |
570 | ||
571 | spin_lock_irqsave(&spinlock, flags); | |
572 | superio_enter(); | |
573 | ||
574 | superio_select(GPIO); | |
575 | superio_outb(WDT_TOV1, WDTCFG); | |
576 | superio_outb(0x00, WDTCTRL); | |
577 | ||
578 | /* First try to get Gameport support */ | |
ee3e9658 | 579 | if (try_gameport) { |
e1fee94f OS |
580 | superio_select(GAMEPORT); |
581 | base = superio_inw(BASEREG); | |
582 | if (!base) { | |
583 | base = GP_BASE_DEFAULT; | |
584 | superio_outw(base, BASEREG); | |
585 | } | |
586 | gpact = superio_inb(ACTREG); | |
587 | superio_outb(0x01, ACTREG); | |
588 | superio_exit(); | |
589 | spin_unlock_irqrestore(&spinlock, flags); | |
590 | if (request_region(base, 1, WATCHDOG_NAME)) | |
591 | set_bit(WDTS_USE_GP, &wdt_status); | |
592 | else | |
593 | rc = -EIO; | |
594 | } else { | |
595 | superio_exit(); | |
596 | spin_unlock_irqrestore(&spinlock, flags); | |
597 | } | |
598 | ||
599 | /* If we haven't Gameport support, try to get CIR support */ | |
600 | if (!test_bit(WDTS_USE_GP, &wdt_status)) { | |
601 | if (!request_region(CIR_BASE, 8, WATCHDOG_NAME)) { | |
602 | if (rc == -EIO) | |
603 | printk(KERN_ERR PFX | |
604 | "I/O Address 0x%04x and 0x%04x" | |
605 | " already in use\n", base, CIR_BASE); | |
606 | else | |
607 | printk(KERN_ERR PFX | |
608 | "I/O Address 0x%04x already in use\n", | |
609 | CIR_BASE); | |
610 | rc = -EIO; | |
611 | goto err_out; | |
612 | } | |
613 | base = CIR_BASE; | |
614 | spin_lock_irqsave(&spinlock, flags); | |
615 | superio_enter(); | |
616 | ||
617 | superio_select(CIR); | |
618 | superio_outw(base, BASEREG); | |
619 | superio_outb(0x00, CIR_ILS); | |
620 | ciract = superio_inb(ACTREG); | |
621 | superio_outb(0x01, ACTREG); | |
622 | if (rc == -EIO) { | |
623 | superio_select(GAMEPORT); | |
624 | superio_outb(gpact, ACTREG); | |
625 | } | |
626 | ||
627 | superio_exit(); | |
628 | spin_unlock_irqrestore(&spinlock, flags); | |
629 | } | |
630 | ||
631 | if (timeout < 1 || timeout > 65535) { | |
632 | timeout = DEFAULT_TIMEOUT; | |
633 | printk(KERN_WARNING PFX | |
634 | "Timeout value out of range, use default %d sec\n", | |
635 | DEFAULT_TIMEOUT); | |
636 | } | |
637 | ||
638 | rc = register_reboot_notifier(&wdt_notifier); | |
639 | if (rc) { | |
640 | printk(KERN_ERR PFX | |
641 | "Cannot register reboot notifier (err=%d)\n", rc); | |
642 | goto err_out_region; | |
643 | } | |
644 | ||
645 | rc = misc_register(&wdt_miscdev); | |
646 | if (rc) { | |
647 | printk(KERN_ERR PFX | |
648 | "Cannot register miscdev on minor=%d (err=%d)\n", | |
649 | wdt_miscdev.minor, rc); | |
650 | goto err_out_reboot; | |
651 | } | |
652 | ||
653 | /* Initialize CIR to use it as keepalive source */ | |
654 | if (!test_bit(WDTS_USE_GP, &wdt_status)) { | |
655 | outb(0x00, CIR_RCR(base)); | |
656 | outb(0xc0, CIR_TCR1(base)); | |
657 | outb(0x5c, CIR_TCR2(base)); | |
658 | outb(0x10, CIR_IER(base)); | |
659 | outb(0x00, CIR_BDHR(base)); | |
660 | outb(0x01, CIR_BDLR(base)); | |
661 | outb(0x09, CIR_IER(base)); | |
662 | } | |
663 | ||
664 | printk(KERN_INFO PFX "Chip it%04x revision %d initialized. " | |
665 | "timeout=%d sec (nowayout=%d testmode=%d exclusive=%d " | |
666 | "nogameport=%d)\n", chip_type, chip_rev, timeout, | |
667 | nowayout, testmode, exclusive, nogameport); | |
668 | ||
669 | return 0; | |
670 | ||
671 | err_out_reboot: | |
672 | unregister_reboot_notifier(&wdt_notifier); | |
673 | err_out_region: | |
674 | release_region(base, test_bit(WDTS_USE_GP, &wdt_status) ? 1 : 8); | |
675 | if (!test_bit(WDTS_USE_GP, &wdt_status)) { | |
676 | spin_lock_irqsave(&spinlock, flags); | |
677 | superio_enter(); | |
678 | superio_select(CIR); | |
679 | superio_outb(ciract, ACTREG); | |
680 | superio_exit(); | |
681 | spin_unlock_irqrestore(&spinlock, flags); | |
682 | } | |
683 | err_out: | |
ee3e9658 | 684 | if (try_gameport) { |
e1fee94f OS |
685 | spin_lock_irqsave(&spinlock, flags); |
686 | superio_enter(); | |
687 | superio_select(GAMEPORT); | |
688 | superio_outb(gpact, ACTREG); | |
689 | superio_exit(); | |
690 | spin_unlock_irqrestore(&spinlock, flags); | |
691 | } | |
692 | ||
693 | return rc; | |
694 | } | |
695 | ||
696 | static void __exit it87_wdt_exit(void) | |
697 | { | |
698 | unsigned long flags; | |
699 | int nolock; | |
700 | ||
701 | nolock = !spin_trylock_irqsave(&spinlock, flags); | |
702 | superio_enter(); | |
703 | superio_select(GPIO); | |
704 | superio_outb(0x00, WDTCTRL); | |
705 | superio_outb(0x00, WDTCFG); | |
706 | superio_outb(0x00, WDTVALMSB); | |
707 | superio_outb(0x00, WDTVALLSB); | |
708 | if (test_bit(WDTS_USE_GP, &wdt_status)) { | |
709 | superio_select(GAMEPORT); | |
710 | superio_outb(gpact, ACTREG); | |
711 | } else { | |
712 | superio_select(CIR); | |
713 | superio_outb(ciract, ACTREG); | |
714 | } | |
715 | superio_exit(); | |
716 | if (!nolock) | |
717 | spin_unlock_irqrestore(&spinlock, flags); | |
718 | ||
719 | misc_deregister(&wdt_miscdev); | |
720 | unregister_reboot_notifier(&wdt_notifier); | |
721 | release_region(base, test_bit(WDTS_USE_GP, &wdt_status) ? 1 : 8); | |
722 | } | |
723 | ||
724 | module_init(it87_wdt_init); | |
725 | module_exit(it87_wdt_exit); | |
726 | ||
727 | MODULE_AUTHOR("Oliver Schuster"); | |
728 | MODULE_DESCRIPTION("Hardware Watchdog Device Driver for IT87xx EC-LPC I/O"); | |
729 | MODULE_LICENSE("GPL"); | |
730 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); |