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4c076fb4 DD |
1 | /* |
2 | * Octeon Watchdog driver | |
3 | * | |
4 | * Copyright (C) 2007, 2008, 2009, 2010 Cavium Networks | |
5 | * | |
6 | * Some parts derived from wdt.c | |
7 | * | |
8 | * (c) Copyright 1996-1997 Alan Cox <alan@lxorguk.ukuu.org.uk>, | |
9 | * All Rights Reserved. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | * Neither Alan Cox nor CymruNet Ltd. admit liability nor provide | |
17 | * warranty for any of this software. This material is provided | |
18 | * "AS-IS" and at no charge. | |
19 | * | |
20 | * (c) Copyright 1995 Alan Cox <alan@lxorguk.ukuu.org.uk> | |
21 | * | |
22 | * This file is subject to the terms and conditions of the GNU General Public | |
23 | * License. See the file "COPYING" in the main directory of this archive | |
24 | * for more details. | |
25 | * | |
26 | * | |
27 | * The OCTEON watchdog has a maximum timeout of 2^32 * io_clock. | |
28 | * For most systems this is less than 10 seconds, so to allow for | |
29 | * software to request longer watchdog heartbeats, we maintain software | |
30 | * counters to count multiples of the base rate. If the system locks | |
31 | * up in such a manner that we can not run the software counters, the | |
32 | * only result is a watchdog reset sooner than was requested. But | |
33 | * that is OK, because in this case userspace would likely not be able | |
34 | * to do anything anyhow. | |
35 | * | |
36 | * The hardware watchdog interval we call the period. The OCTEON | |
37 | * watchdog goes through several stages, after the first period an | |
38 | * irq is asserted, then if it is not reset, after the next period NMI | |
39 | * is asserted, then after an additional period a chip wide soft reset. | |
40 | * So for the software counters, we reset watchdog after each period | |
41 | * and decrement the counter. But for the last two periods we need to | |
42 | * let the watchdog progress to the NMI stage so we disable the irq | |
43 | * and let it proceed. Once in the NMI, we print the register state | |
44 | * to the serial port and then wait for the reset. | |
45 | * | |
46 | * A watchdog is maintained for each CPU in the system, that way if | |
47 | * one CPU suffers a lockup, we also get a register dump and reset. | |
48 | * The userspace ping resets the watchdog on all CPUs. | |
49 | * | |
50 | * Before userspace opens the watchdog device, we still run the | |
51 | * watchdogs to catch any lockups that may be kernel related. | |
52 | * | |
53 | */ | |
54 | ||
27c766aa JP |
55 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
56 | ||
4c076fb4 DD |
57 | #include <linux/miscdevice.h> |
58 | #include <linux/interrupt.h> | |
59 | #include <linux/watchdog.h> | |
60 | #include <linux/cpumask.h> | |
61 | #include <linux/bitops.h> | |
62 | #include <linux/kernel.h> | |
63 | #include <linux/module.h> | |
64 | #include <linux/string.h> | |
65 | #include <linux/delay.h> | |
66 | #include <linux/cpu.h> | |
67 | #include <linux/smp.h> | |
68 | #include <linux/fs.h> | |
ca4d3e67 | 69 | #include <linux/irq.h> |
4c076fb4 DD |
70 | |
71 | #include <asm/mipsregs.h> | |
72 | #include <asm/uasm.h> | |
73 | ||
74 | #include <asm/octeon/octeon.h> | |
75 | ||
76 | /* The count needed to achieve timeout_sec. */ | |
77 | static unsigned int timeout_cnt; | |
78 | ||
79 | /* The maximum period supported. */ | |
80 | static unsigned int max_timeout_sec; | |
81 | ||
82 | /* The current period. */ | |
83 | static unsigned int timeout_sec; | |
84 | ||
85 | /* Set to non-zero when userspace countdown mode active */ | |
86 | static int do_coundown; | |
87 | static unsigned int countdown_reset; | |
88 | static unsigned int per_cpu_countdown[NR_CPUS]; | |
89 | ||
90 | static cpumask_t irq_enabled_cpus; | |
91 | ||
92 | #define WD_TIMO 60 /* Default heartbeat = 60 seconds */ | |
93 | ||
94 | static int heartbeat = WD_TIMO; | |
95 | module_param(heartbeat, int, S_IRUGO); | |
96 | MODULE_PARM_DESC(heartbeat, | |
97 | "Watchdog heartbeat in seconds. (0 < heartbeat, default=" | |
98 | __MODULE_STRING(WD_TIMO) ")"); | |
99 | ||
86a1e189 WVS |
100 | static bool nowayout = WATCHDOG_NOWAYOUT; |
101 | module_param(nowayout, bool, S_IRUGO); | |
4c076fb4 DD |
102 | MODULE_PARM_DESC(nowayout, |
103 | "Watchdog cannot be stopped once started (default=" | |
104 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
105 | ||
106 | static unsigned long octeon_wdt_is_open; | |
107 | static char expect_close; | |
108 | ||
109 | static u32 __initdata nmi_stage1_insns[64]; | |
110 | /* We need one branch and therefore one relocation per target label. */ | |
111 | static struct uasm_label __initdata labels[5]; | |
112 | static struct uasm_reloc __initdata relocs[5]; | |
113 | ||
114 | enum lable_id { | |
115 | label_enter_bootloader = 1 | |
116 | }; | |
117 | ||
118 | /* Some CP0 registers */ | |
119 | #define K0 26 | |
120 | #define C0_CVMMEMCTL 11, 7 | |
121 | #define C0_STATUS 12, 0 | |
122 | #define C0_EBASE 15, 1 | |
123 | #define C0_DESAVE 31, 0 | |
124 | ||
125 | void octeon_wdt_nmi_stage2(void); | |
126 | ||
127 | static void __init octeon_wdt_build_stage1(void) | |
128 | { | |
129 | int i; | |
130 | int len; | |
131 | u32 *p = nmi_stage1_insns; | |
132 | #ifdef CONFIG_HOTPLUG_CPU | |
133 | struct uasm_label *l = labels; | |
134 | struct uasm_reloc *r = relocs; | |
135 | #endif | |
136 | ||
137 | /* | |
138 | * For the next few instructions running the debugger may | |
139 | * cause corruption of k0 in the saved registers. Since we're | |
140 | * about to crash, nobody probably cares. | |
141 | * | |
142 | * Save K0 into the debug scratch register | |
143 | */ | |
144 | uasm_i_dmtc0(&p, K0, C0_DESAVE); | |
145 | ||
146 | uasm_i_mfc0(&p, K0, C0_STATUS); | |
147 | #ifdef CONFIG_HOTPLUG_CPU | |
f64988f1 AK |
148 | if (octeon_bootloader_entry_addr) |
149 | uasm_il_bbit0(&p, &r, K0, ilog2(ST0_NMI), | |
150 | label_enter_bootloader); | |
4c076fb4 DD |
151 | #endif |
152 | /* Force 64-bit addressing enabled */ | |
153 | uasm_i_ori(&p, K0, K0, ST0_UX | ST0_SX | ST0_KX); | |
154 | uasm_i_mtc0(&p, K0, C0_STATUS); | |
155 | ||
156 | #ifdef CONFIG_HOTPLUG_CPU | |
f64988f1 AK |
157 | if (octeon_bootloader_entry_addr) { |
158 | uasm_i_mfc0(&p, K0, C0_EBASE); | |
159 | /* Coreid number in K0 */ | |
160 | uasm_i_andi(&p, K0, K0, 0xf); | |
161 | /* 8 * coreid in bits 16-31 */ | |
162 | uasm_i_dsll_safe(&p, K0, K0, 3 + 16); | |
163 | uasm_i_ori(&p, K0, K0, 0x8001); | |
164 | uasm_i_dsll_safe(&p, K0, K0, 16); | |
165 | uasm_i_ori(&p, K0, K0, 0x0700); | |
166 | uasm_i_drotr_safe(&p, K0, K0, 32); | |
167 | /* | |
168 | * Should result in: 0x8001,0700,0000,8*coreid which is | |
169 | * CVMX_CIU_WDOGX(coreid) - 0x0500 | |
170 | * | |
171 | * Now ld K0, CVMX_CIU_WDOGX(coreid) | |
172 | */ | |
173 | uasm_i_ld(&p, K0, 0x500, K0); | |
174 | /* | |
175 | * If bit one set handle the NMI as a watchdog event. | |
176 | * otherwise transfer control to bootloader. | |
177 | */ | |
178 | uasm_il_bbit0(&p, &r, K0, 1, label_enter_bootloader); | |
179 | uasm_i_nop(&p); | |
180 | } | |
4c076fb4 DD |
181 | #endif |
182 | ||
183 | /* Clear Dcache so cvmseg works right. */ | |
184 | uasm_i_cache(&p, 1, 0, 0); | |
185 | ||
186 | /* Use K0 to do a read/modify/write of CVMMEMCTL */ | |
187 | uasm_i_dmfc0(&p, K0, C0_CVMMEMCTL); | |
188 | /* Clear out the size of CVMSEG */ | |
189 | uasm_i_dins(&p, K0, 0, 0, 6); | |
190 | /* Set CVMSEG to its largest value */ | |
191 | uasm_i_ori(&p, K0, K0, 0x1c0 | 54); | |
192 | /* Store the CVMMEMCTL value */ | |
193 | uasm_i_dmtc0(&p, K0, C0_CVMMEMCTL); | |
194 | ||
195 | /* Load the address of the second stage handler */ | |
196 | UASM_i_LA(&p, K0, (long)octeon_wdt_nmi_stage2); | |
197 | uasm_i_jr(&p, K0); | |
198 | uasm_i_dmfc0(&p, K0, C0_DESAVE); | |
199 | ||
200 | #ifdef CONFIG_HOTPLUG_CPU | |
f64988f1 AK |
201 | if (octeon_bootloader_entry_addr) { |
202 | uasm_build_label(&l, p, label_enter_bootloader); | |
203 | /* Jump to the bootloader and restore K0 */ | |
204 | UASM_i_LA(&p, K0, (long)octeon_bootloader_entry_addr); | |
205 | uasm_i_jr(&p, K0); | |
206 | uasm_i_dmfc0(&p, K0, C0_DESAVE); | |
207 | } | |
4c076fb4 DD |
208 | #endif |
209 | uasm_resolve_relocs(relocs, labels); | |
210 | ||
211 | len = (int)(p - nmi_stage1_insns); | |
27c766aa | 212 | pr_debug("Synthesized NMI stage 1 handler (%d instructions)\n", len); |
4c076fb4 DD |
213 | |
214 | pr_debug("\t.set push\n"); | |
215 | pr_debug("\t.set noreorder\n"); | |
216 | for (i = 0; i < len; i++) | |
217 | pr_debug("\t.word 0x%08x\n", nmi_stage1_insns[i]); | |
218 | pr_debug("\t.set pop\n"); | |
219 | ||
220 | if (len > 32) | |
221 | panic("NMI stage 1 handler exceeds 32 instructions, was %d\n", len); | |
222 | } | |
223 | ||
224 | static int cpu2core(int cpu) | |
225 | { | |
226 | #ifdef CONFIG_SMP | |
227 | return cpu_logical_map(cpu); | |
228 | #else | |
229 | return cvmx_get_core_num(); | |
230 | #endif | |
231 | } | |
232 | ||
233 | static int core2cpu(int coreid) | |
234 | { | |
235 | #ifdef CONFIG_SMP | |
236 | return cpu_number_map(coreid); | |
237 | #else | |
238 | return 0; | |
239 | #endif | |
240 | } | |
241 | ||
242 | /** | |
243 | * Poke the watchdog when an interrupt is received | |
244 | * | |
245 | * @cpl: | |
246 | * @dev_id: | |
247 | * | |
248 | * Returns | |
249 | */ | |
250 | static irqreturn_t octeon_wdt_poke_irq(int cpl, void *dev_id) | |
251 | { | |
252 | unsigned int core = cvmx_get_core_num(); | |
253 | int cpu = core2cpu(core); | |
254 | ||
255 | if (do_coundown) { | |
256 | if (per_cpu_countdown[cpu] > 0) { | |
257 | /* We're alive, poke the watchdog */ | |
258 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
259 | per_cpu_countdown[cpu]--; | |
260 | } else { | |
261 | /* Bad news, you are about to reboot. */ | |
262 | disable_irq_nosync(cpl); | |
263 | cpumask_clear_cpu(cpu, &irq_enabled_cpus); | |
264 | } | |
265 | } else { | |
266 | /* Not open, just ping away... */ | |
267 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
268 | } | |
269 | return IRQ_HANDLED; | |
270 | } | |
271 | ||
272 | /* From setup.c */ | |
273 | extern int prom_putchar(char c); | |
274 | ||
275 | /** | |
276 | * Write a string to the uart | |
277 | * | |
278 | * @str: String to write | |
279 | */ | |
280 | static void octeon_wdt_write_string(const char *str) | |
281 | { | |
282 | /* Just loop writing one byte at a time */ | |
283 | while (*str) | |
284 | prom_putchar(*str++); | |
285 | } | |
286 | ||
287 | /** | |
288 | * Write a hex number out of the uart | |
289 | * | |
290 | * @value: Number to display | |
291 | * @digits: Number of digits to print (1 to 16) | |
292 | */ | |
293 | static void octeon_wdt_write_hex(u64 value, int digits) | |
294 | { | |
295 | int d; | |
296 | int v; | |
297 | for (d = 0; d < digits; d++) { | |
298 | v = (value >> ((digits - d - 1) * 4)) & 0xf; | |
299 | if (v >= 10) | |
300 | prom_putchar('a' + v - 10); | |
301 | else | |
302 | prom_putchar('0' + v); | |
303 | } | |
304 | } | |
305 | ||
306 | const char *reg_name[] = { | |
307 | "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
308 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
309 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
310 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
311 | }; | |
312 | ||
313 | /** | |
314 | * NMI stage 3 handler. NMIs are handled in the following manner: | |
315 | * 1) The first NMI handler enables CVMSEG and transfers from | |
316 | * the bootbus region into normal memory. It is careful to not | |
317 | * destroy any registers. | |
318 | * 2) The second stage handler uses CVMSEG to save the registers | |
319 | * and create a stack for C code. It then calls the third level | |
320 | * handler with one argument, a pointer to the register values. | |
321 | * 3) The third, and final, level handler is the following C | |
322 | * function that prints out some useful infomration. | |
323 | * | |
324 | * @reg: Pointer to register state before the NMI | |
325 | */ | |
326 | void octeon_wdt_nmi_stage3(u64 reg[32]) | |
327 | { | |
328 | u64 i; | |
329 | ||
330 | unsigned int coreid = cvmx_get_core_num(); | |
331 | /* | |
332 | * Save status and cause early to get them before any changes | |
333 | * might happen. | |
334 | */ | |
335 | u64 cp0_cause = read_c0_cause(); | |
336 | u64 cp0_status = read_c0_status(); | |
337 | u64 cp0_error_epc = read_c0_errorepc(); | |
338 | u64 cp0_epc = read_c0_epc(); | |
339 | ||
340 | /* Delay so output from all cores output is not jumbled together. */ | |
341 | __delay(100000000ull * coreid); | |
342 | ||
343 | octeon_wdt_write_string("\r\n*** NMI Watchdog interrupt on Core 0x"); | |
344 | octeon_wdt_write_hex(coreid, 1); | |
345 | octeon_wdt_write_string(" ***\r\n"); | |
346 | for (i = 0; i < 32; i++) { | |
347 | octeon_wdt_write_string("\t"); | |
348 | octeon_wdt_write_string(reg_name[i]); | |
349 | octeon_wdt_write_string("\t0x"); | |
350 | octeon_wdt_write_hex(reg[i], 16); | |
351 | if (i & 1) | |
352 | octeon_wdt_write_string("\r\n"); | |
353 | } | |
354 | octeon_wdt_write_string("\terr_epc\t0x"); | |
355 | octeon_wdt_write_hex(cp0_error_epc, 16); | |
356 | ||
357 | octeon_wdt_write_string("\tepc\t0x"); | |
358 | octeon_wdt_write_hex(cp0_epc, 16); | |
359 | octeon_wdt_write_string("\r\n"); | |
360 | ||
361 | octeon_wdt_write_string("\tstatus\t0x"); | |
362 | octeon_wdt_write_hex(cp0_status, 16); | |
363 | octeon_wdt_write_string("\tcause\t0x"); | |
364 | octeon_wdt_write_hex(cp0_cause, 16); | |
365 | octeon_wdt_write_string("\r\n"); | |
366 | ||
367 | octeon_wdt_write_string("\tsum0\t0x"); | |
368 | octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_SUM0(coreid * 2)), 16); | |
369 | octeon_wdt_write_string("\ten0\t0x"); | |
370 | octeon_wdt_write_hex(cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)), 16); | |
371 | octeon_wdt_write_string("\r\n"); | |
372 | ||
373 | octeon_wdt_write_string("*** Chip soft reset soon ***\r\n"); | |
374 | } | |
375 | ||
376 | static void octeon_wdt_disable_interrupt(int cpu) | |
377 | { | |
378 | unsigned int core; | |
379 | unsigned int irq; | |
380 | union cvmx_ciu_wdogx ciu_wdog; | |
381 | ||
382 | core = cpu2core(cpu); | |
383 | ||
384 | irq = OCTEON_IRQ_WDOG0 + core; | |
385 | ||
386 | /* Poke the watchdog to clear out its state */ | |
387 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
388 | ||
389 | /* Disable the hardware. */ | |
390 | ciu_wdog.u64 = 0; | |
391 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
392 | ||
393 | free_irq(irq, octeon_wdt_poke_irq); | |
394 | } | |
395 | ||
396 | static void octeon_wdt_setup_interrupt(int cpu) | |
397 | { | |
398 | unsigned int core; | |
399 | unsigned int irq; | |
400 | union cvmx_ciu_wdogx ciu_wdog; | |
401 | ||
402 | core = cpu2core(cpu); | |
403 | ||
404 | /* Disable it before doing anything with the interrupts. */ | |
405 | ciu_wdog.u64 = 0; | |
406 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
407 | ||
408 | per_cpu_countdown[cpu] = countdown_reset; | |
409 | ||
410 | irq = OCTEON_IRQ_WDOG0 + core; | |
411 | ||
412 | if (request_irq(irq, octeon_wdt_poke_irq, | |
47bfd058 | 413 | IRQF_NO_THREAD, "octeon_wdt", octeon_wdt_poke_irq)) |
4c076fb4 DD |
414 | panic("octeon_wdt: Couldn't obtain irq %d", irq); |
415 | ||
416 | cpumask_set_cpu(cpu, &irq_enabled_cpus); | |
417 | ||
418 | /* Poke the watchdog to clear out its state */ | |
419 | cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1); | |
420 | ||
421 | /* Finally enable the watchdog now that all handlers are installed */ | |
422 | ciu_wdog.u64 = 0; | |
423 | ciu_wdog.s.len = timeout_cnt; | |
424 | ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ | |
425 | cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64); | |
426 | } | |
427 | ||
428 | static int octeon_wdt_cpu_callback(struct notifier_block *nfb, | |
429 | unsigned long action, void *hcpu) | |
430 | { | |
431 | unsigned int cpu = (unsigned long)hcpu; | |
432 | ||
433 | switch (action) { | |
434 | case CPU_DOWN_PREPARE: | |
435 | octeon_wdt_disable_interrupt(cpu); | |
436 | break; | |
437 | case CPU_ONLINE: | |
438 | case CPU_DOWN_FAILED: | |
439 | octeon_wdt_setup_interrupt(cpu); | |
440 | break; | |
441 | default: | |
442 | break; | |
443 | } | |
444 | return NOTIFY_OK; | |
445 | } | |
446 | ||
447 | static void octeon_wdt_ping(void) | |
448 | { | |
449 | int cpu; | |
450 | int coreid; | |
451 | ||
452 | for_each_online_cpu(cpu) { | |
453 | coreid = cpu2core(cpu); | |
454 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
455 | per_cpu_countdown[cpu] = countdown_reset; | |
456 | if ((countdown_reset || !do_coundown) && | |
457 | !cpumask_test_cpu(cpu, &irq_enabled_cpus)) { | |
458 | /* We have to enable the irq */ | |
459 | int irq = OCTEON_IRQ_WDOG0 + coreid; | |
460 | enable_irq(irq); | |
461 | cpumask_set_cpu(cpu, &irq_enabled_cpus); | |
462 | } | |
463 | } | |
464 | } | |
465 | ||
466 | static void octeon_wdt_calc_parameters(int t) | |
467 | { | |
468 | unsigned int periods; | |
469 | ||
470 | timeout_sec = max_timeout_sec; | |
471 | ||
472 | ||
473 | /* | |
474 | * Find the largest interrupt period, that can evenly divide | |
475 | * the requested heartbeat time. | |
476 | */ | |
477 | while ((t % timeout_sec) != 0) | |
478 | timeout_sec--; | |
479 | ||
480 | periods = t / timeout_sec; | |
481 | ||
482 | /* | |
483 | * The last two periods are after the irq is disabled, and | |
484 | * then to the nmi, so we subtract them off. | |
485 | */ | |
486 | ||
487 | countdown_reset = periods > 2 ? periods - 2 : 0; | |
488 | heartbeat = t; | |
468ffde4 | 489 | timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * timeout_sec) >> 8; |
4c076fb4 DD |
490 | } |
491 | ||
492 | static int octeon_wdt_set_heartbeat(int t) | |
493 | { | |
494 | int cpu; | |
495 | int coreid; | |
496 | union cvmx_ciu_wdogx ciu_wdog; | |
497 | ||
498 | if (t <= 0) | |
499 | return -1; | |
500 | ||
501 | octeon_wdt_calc_parameters(t); | |
502 | ||
503 | for_each_online_cpu(cpu) { | |
504 | coreid = cpu2core(cpu); | |
505 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
506 | ciu_wdog.u64 = 0; | |
507 | ciu_wdog.s.len = timeout_cnt; | |
508 | ciu_wdog.s.mode = 3; /* 3 = Interrupt + NMI + Soft-Reset */ | |
509 | cvmx_write_csr(CVMX_CIU_WDOGX(coreid), ciu_wdog.u64); | |
510 | cvmx_write_csr(CVMX_CIU_PP_POKEX(coreid), 1); | |
511 | } | |
512 | octeon_wdt_ping(); /* Get the irqs back on. */ | |
513 | return 0; | |
514 | } | |
515 | ||
516 | /** | |
517 | * octeon_wdt_write: | |
518 | * @file: file handle to the watchdog | |
519 | * @buf: buffer to write (unused as data does not matter here | |
520 | * @count: count of bytes | |
521 | * @ppos: pointer to the position to write. No seeks allowed | |
522 | * | |
523 | * A write to a watchdog device is defined as a keepalive signal. Any | |
524 | * write of data will do, as we we don't define content meaning. | |
525 | */ | |
526 | ||
527 | static ssize_t octeon_wdt_write(struct file *file, const char __user *buf, | |
528 | size_t count, loff_t *ppos) | |
529 | { | |
530 | if (count) { | |
531 | if (!nowayout) { | |
532 | size_t i; | |
533 | ||
534 | /* In case it was set long ago */ | |
535 | expect_close = 0; | |
536 | ||
537 | for (i = 0; i != count; i++) { | |
538 | char c; | |
539 | if (get_user(c, buf + i)) | |
540 | return -EFAULT; | |
541 | if (c == 'V') | |
542 | expect_close = 1; | |
543 | } | |
544 | } | |
545 | octeon_wdt_ping(); | |
546 | } | |
547 | return count; | |
548 | } | |
549 | ||
550 | /** | |
551 | * octeon_wdt_ioctl: | |
552 | * @file: file handle to the device | |
553 | * @cmd: watchdog command | |
554 | * @arg: argument pointer | |
555 | * | |
556 | * The watchdog API defines a common set of functions for all | |
557 | * watchdogs according to their available features. We only | |
558 | * actually usefully support querying capabilities and setting | |
559 | * the timeout. | |
560 | */ | |
561 | ||
562 | static long octeon_wdt_ioctl(struct file *file, unsigned int cmd, | |
563 | unsigned long arg) | |
564 | { | |
565 | void __user *argp = (void __user *)arg; | |
566 | int __user *p = argp; | |
567 | int new_heartbeat; | |
568 | ||
569 | static struct watchdog_info ident = { | |
570 | .options = WDIOF_SETTIMEOUT| | |
571 | WDIOF_MAGICCLOSE| | |
572 | WDIOF_KEEPALIVEPING, | |
573 | .firmware_version = 1, | |
574 | .identity = "OCTEON", | |
575 | }; | |
576 | ||
577 | switch (cmd) { | |
578 | case WDIOC_GETSUPPORT: | |
579 | return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0; | |
580 | case WDIOC_GETSTATUS: | |
581 | case WDIOC_GETBOOTSTATUS: | |
582 | return put_user(0, p); | |
583 | case WDIOC_KEEPALIVE: | |
584 | octeon_wdt_ping(); | |
585 | return 0; | |
586 | case WDIOC_SETTIMEOUT: | |
587 | if (get_user(new_heartbeat, p)) | |
588 | return -EFAULT; | |
589 | if (octeon_wdt_set_heartbeat(new_heartbeat)) | |
590 | return -EINVAL; | |
591 | /* Fall through. */ | |
592 | case WDIOC_GETTIMEOUT: | |
593 | return put_user(heartbeat, p); | |
594 | default: | |
595 | return -ENOTTY; | |
596 | } | |
597 | } | |
598 | ||
599 | /** | |
600 | * octeon_wdt_open: | |
601 | * @inode: inode of device | |
602 | * @file: file handle to device | |
603 | * | |
604 | * The watchdog device has been opened. The watchdog device is single | |
605 | * open and on opening we do a ping to reset the counters. | |
606 | */ | |
607 | ||
608 | static int octeon_wdt_open(struct inode *inode, struct file *file) | |
609 | { | |
610 | if (test_and_set_bit(0, &octeon_wdt_is_open)) | |
611 | return -EBUSY; | |
612 | /* | |
613 | * Activate | |
614 | */ | |
615 | octeon_wdt_ping(); | |
616 | do_coundown = 1; | |
617 | return nonseekable_open(inode, file); | |
618 | } | |
619 | ||
620 | /** | |
621 | * octeon_wdt_release: | |
622 | * @inode: inode to board | |
623 | * @file: file handle to board | |
624 | * | |
625 | * The watchdog has a configurable API. There is a religious dispute | |
626 | * between people who want their watchdog to be able to shut down and | |
627 | * those who want to be sure if the watchdog manager dies the machine | |
628 | * reboots. In the former case we disable the counters, in the latter | |
629 | * case you have to open it again very soon. | |
630 | */ | |
631 | ||
632 | static int octeon_wdt_release(struct inode *inode, struct file *file) | |
633 | { | |
634 | if (expect_close) { | |
635 | do_coundown = 0; | |
636 | octeon_wdt_ping(); | |
637 | } else { | |
27c766aa | 638 | pr_crit("WDT device closed unexpectedly. WDT will not stop!\n"); |
4c076fb4 DD |
639 | } |
640 | clear_bit(0, &octeon_wdt_is_open); | |
641 | expect_close = 0; | |
642 | return 0; | |
643 | } | |
644 | ||
645 | static const struct file_operations octeon_wdt_fops = { | |
646 | .owner = THIS_MODULE, | |
647 | .llseek = no_llseek, | |
648 | .write = octeon_wdt_write, | |
649 | .unlocked_ioctl = octeon_wdt_ioctl, | |
650 | .open = octeon_wdt_open, | |
651 | .release = octeon_wdt_release, | |
652 | }; | |
653 | ||
654 | static struct miscdevice octeon_wdt_miscdev = { | |
655 | .minor = WATCHDOG_MINOR, | |
656 | .name = "watchdog", | |
657 | .fops = &octeon_wdt_fops, | |
658 | }; | |
659 | ||
660 | static struct notifier_block octeon_wdt_cpu_notifier = { | |
661 | .notifier_call = octeon_wdt_cpu_callback, | |
662 | }; | |
663 | ||
664 | ||
665 | /** | |
666 | * Module/ driver initialization. | |
667 | * | |
668 | * Returns Zero on success | |
669 | */ | |
670 | static int __init octeon_wdt_init(void) | |
671 | { | |
672 | int i; | |
673 | int ret; | |
674 | int cpu; | |
675 | u64 *ptr; | |
676 | ||
677 | /* | |
678 | * Watchdog time expiration length = The 16 bits of LEN | |
679 | * represent the most significant bits of a 24 bit decrementer | |
680 | * that decrements every 256 cycles. | |
681 | * | |
682 | * Try for a timeout of 5 sec, if that fails a smaller number | |
683 | * of even seconds, | |
684 | */ | |
685 | max_timeout_sec = 6; | |
686 | do { | |
687 | max_timeout_sec--; | |
468ffde4 | 688 | timeout_cnt = ((octeon_get_io_clock_rate() >> 8) * max_timeout_sec) >> 8; |
4c076fb4 DD |
689 | } while (timeout_cnt > 65535); |
690 | ||
691 | BUG_ON(timeout_cnt == 0); | |
692 | ||
693 | octeon_wdt_calc_parameters(heartbeat); | |
694 | ||
27c766aa | 695 | pr_info("Initial granularity %d Sec\n", timeout_sec); |
4c076fb4 DD |
696 | |
697 | ret = misc_register(&octeon_wdt_miscdev); | |
698 | if (ret) { | |
27c766aa JP |
699 | pr_err("cannot register miscdev on minor=%d (err=%d)\n", |
700 | WATCHDOG_MINOR, ret); | |
4c076fb4 DD |
701 | goto out; |
702 | } | |
703 | ||
704 | /* Build the NMI handler ... */ | |
705 | octeon_wdt_build_stage1(); | |
706 | ||
707 | /* ... and install it. */ | |
708 | ptr = (u64 *) nmi_stage1_insns; | |
709 | for (i = 0; i < 16; i++) { | |
710 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8); | |
711 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, ptr[i]); | |
712 | } | |
713 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000); | |
714 | ||
715 | cpumask_clear(&irq_enabled_cpus); | |
716 | ||
99c3bf36 | 717 | cpu_notifier_register_begin(); |
4c076fb4 DD |
718 | for_each_online_cpu(cpu) |
719 | octeon_wdt_setup_interrupt(cpu); | |
720 | ||
99c3bf36 SB |
721 | __register_hotcpu_notifier(&octeon_wdt_cpu_notifier); |
722 | cpu_notifier_register_done(); | |
723 | ||
4c076fb4 DD |
724 | out: |
725 | return ret; | |
726 | } | |
727 | ||
728 | /** | |
729 | * Module / driver shutdown | |
730 | */ | |
731 | static void __exit octeon_wdt_cleanup(void) | |
732 | { | |
733 | int cpu; | |
734 | ||
735 | misc_deregister(&octeon_wdt_miscdev); | |
736 | ||
99c3bf36 SB |
737 | cpu_notifier_register_begin(); |
738 | __unregister_hotcpu_notifier(&octeon_wdt_cpu_notifier); | |
4c076fb4 DD |
739 | |
740 | for_each_online_cpu(cpu) { | |
741 | int core = cpu2core(cpu); | |
742 | /* Disable the watchdog */ | |
743 | cvmx_write_csr(CVMX_CIU_WDOGX(core), 0); | |
744 | /* Free the interrupt handler */ | |
745 | free_irq(OCTEON_IRQ_WDOG0 + core, octeon_wdt_poke_irq); | |
746 | } | |
99c3bf36 SB |
747 | |
748 | cpu_notifier_register_done(); | |
749 | ||
4c076fb4 DD |
750 | /* |
751 | * Disable the boot-bus memory, the code it points to is soon | |
752 | * to go missing. | |
753 | */ | |
754 | cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0); | |
755 | } | |
756 | ||
757 | MODULE_LICENSE("GPL"); | |
758 | MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>"); | |
759 | MODULE_DESCRIPTION("Cavium Networks Octeon Watchdog driver."); | |
760 | module_init(octeon_wdt_init); | |
761 | module_exit(octeon_wdt_cleanup); |