Commit | Line | Data |
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e9659e69 | 1 | /* |
9419c07c MS |
2 | * Watchdog Device Driver for Xilinx axi/xps_timebase_wdt |
3 | * | |
d14fd964 | 4 | * (C) Copyright 2013 - 2014 Xilinx, Inc. |
9419c07c MS |
5 | * (C) Copyright 2011 (Alejandro Cabrera <aldaya@gmail.com>) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * as published by the Free Software Foundation; either version | |
10 | * 2 of the License, or (at your option) any later version. | |
11 | */ | |
e9659e69 | 12 | |
f06cdfd1 | 13 | #include <linux/err.h> |
e9659e69 AC |
14 | #include <linux/module.h> |
15 | #include <linux/types.h> | |
16 | #include <linux/kernel.h> | |
e9659e69 AC |
17 | #include <linux/ioport.h> |
18 | #include <linux/watchdog.h> | |
19 | #include <linux/io.h> | |
e9659e69 AC |
20 | #include <linux/of.h> |
21 | #include <linux/of_device.h> | |
22 | #include <linux/of_address.h> | |
23 | ||
24 | /* Register offsets for the Wdt device */ | |
25 | #define XWT_TWCSR0_OFFSET 0x0 /* Control/Status Register0 */ | |
26 | #define XWT_TWCSR1_OFFSET 0x4 /* Control/Status Register1 */ | |
27 | #define XWT_TBR_OFFSET 0x8 /* Timebase Register Offset */ | |
28 | ||
29 | /* Control/Status Register Masks */ | |
30 | #define XWT_CSR0_WRS_MASK 0x00000008 /* Reset status */ | |
31 | #define XWT_CSR0_WDS_MASK 0x00000004 /* Timer state */ | |
32 | #define XWT_CSR0_EWDT1_MASK 0x00000002 /* Enable bit 1 */ | |
33 | ||
34 | /* Control/Status Register 0/1 bits */ | |
35 | #define XWT_CSRX_EWDT2_MASK 0x00000001 /* Enable bit 2 */ | |
36 | ||
37 | /* SelfTest constants */ | |
38 | #define XWT_MAX_SELFTEST_LOOP_COUNT 0x00010000 | |
39 | #define XWT_TIMER_FAILED 0xFFFFFFFF | |
40 | ||
41 | #define WATCHDOG_NAME "Xilinx Watchdog" | |
e9659e69 AC |
42 | |
43 | struct xwdt_device { | |
e9659e69 | 44 | void __iomem *base; |
e9659e69 | 45 | u32 wdt_interval; |
90663171 MS |
46 | spinlock_t spinlock; |
47 | struct watchdog_device xilinx_wdt_wdd; | |
e9659e69 AC |
48 | }; |
49 | ||
d14fd964 | 50 | static int xilinx_wdt_start(struct watchdog_device *wdd) |
e9659e69 | 51 | { |
5cf4e69d | 52 | u32 control_status_reg; |
90663171 | 53 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 54 | |
90663171 | 55 | spin_lock(&xdev->spinlock); |
e9659e69 AC |
56 | |
57 | /* Clean previous status and enable the watchdog timer */ | |
90663171 | 58 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
59 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
60 | ||
61 | iowrite32((control_status_reg | XWT_CSR0_EWDT1_MASK), | |
90663171 | 62 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 63 | |
90663171 | 64 | iowrite32(XWT_CSRX_EWDT2_MASK, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 65 | |
90663171 | 66 | spin_unlock(&xdev->spinlock); |
d14fd964 MS |
67 | |
68 | return 0; | |
e9659e69 AC |
69 | } |
70 | ||
d14fd964 | 71 | static int xilinx_wdt_stop(struct watchdog_device *wdd) |
e9659e69 | 72 | { |
5cf4e69d | 73 | u32 control_status_reg; |
90663171 | 74 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 75 | |
90663171 | 76 | spin_lock(&xdev->spinlock); |
e9659e69 | 77 | |
90663171 | 78 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 AC |
79 | |
80 | iowrite32((control_status_reg & ~XWT_CSR0_EWDT1_MASK), | |
90663171 | 81 | xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 82 | |
90663171 | 83 | iowrite32(0, xdev->base + XWT_TWCSR1_OFFSET); |
e9659e69 | 84 | |
90663171 | 85 | spin_unlock(&xdev->spinlock); |
27c766aa | 86 | pr_info("Stopped!\n"); |
d14fd964 MS |
87 | |
88 | return 0; | |
e9659e69 AC |
89 | } |
90 | ||
d14fd964 | 91 | static int xilinx_wdt_keepalive(struct watchdog_device *wdd) |
e9659e69 | 92 | { |
5cf4e69d | 93 | u32 control_status_reg; |
90663171 | 94 | struct xwdt_device *xdev = watchdog_get_drvdata(wdd); |
5cf4e69d | 95 | |
90663171 | 96 | spin_lock(&xdev->spinlock); |
e9659e69 | 97 | |
90663171 | 98 | control_status_reg = ioread32(xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 99 | control_status_reg |= (XWT_CSR0_WRS_MASK | XWT_CSR0_WDS_MASK); |
90663171 | 100 | iowrite32(control_status_reg, xdev->base + XWT_TWCSR0_OFFSET); |
e9659e69 | 101 | |
90663171 | 102 | spin_unlock(&xdev->spinlock); |
e9659e69 | 103 | |
d14fd964 MS |
104 | return 0; |
105 | } | |
e9659e69 | 106 | |
d14fd964 MS |
107 | static const struct watchdog_info xilinx_wdt_ident = { |
108 | .options = WDIOF_MAGICCLOSE | | |
109 | WDIOF_KEEPALIVEPING, | |
110 | .firmware_version = 1, | |
111 | .identity = WATCHDOG_NAME, | |
112 | }; | |
e9659e69 | 113 | |
d14fd964 MS |
114 | static const struct watchdog_ops xilinx_wdt_ops = { |
115 | .owner = THIS_MODULE, | |
116 | .start = xilinx_wdt_start, | |
117 | .stop = xilinx_wdt_stop, | |
118 | .ping = xilinx_wdt_keepalive, | |
119 | }; | |
e9659e69 | 120 | |
90663171 | 121 | static u32 xwdt_selftest(struct xwdt_device *xdev) |
e9659e69 AC |
122 | { |
123 | int i; | |
124 | u32 timer_value1; | |
125 | u32 timer_value2; | |
126 | ||
90663171 | 127 | spin_lock(&xdev->spinlock); |
e9659e69 | 128 | |
90663171 MS |
129 | timer_value1 = ioread32(xdev->base + XWT_TBR_OFFSET); |
130 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); | |
e9659e69 AC |
131 | |
132 | for (i = 0; | |
133 | ((i <= XWT_MAX_SELFTEST_LOOP_COUNT) && | |
134 | (timer_value2 == timer_value1)); i++) { | |
90663171 | 135 | timer_value2 = ioread32(xdev->base + XWT_TBR_OFFSET); |
e9659e69 AC |
136 | } |
137 | ||
90663171 | 138 | spin_unlock(&xdev->spinlock); |
e9659e69 AC |
139 | |
140 | if (timer_value2 != timer_value1) | |
141 | return ~XWT_TIMER_FAILED; | |
142 | else | |
143 | return XWT_TIMER_FAILED; | |
144 | } | |
145 | ||
2d991a16 | 146 | static int xwdt_probe(struct platform_device *pdev) |
e9659e69 AC |
147 | { |
148 | int rc; | |
8d6a140b | 149 | u32 pfreq = 0, enable_once = 0; |
f06cdfd1 | 150 | struct resource *res; |
90663171 | 151 | struct xwdt_device *xdev; |
90663171 MS |
152 | struct watchdog_device *xilinx_wdt_wdd; |
153 | ||
154 | xdev = devm_kzalloc(&pdev->dev, sizeof(*xdev), GFP_KERNEL); | |
155 | if (!xdev) | |
156 | return -ENOMEM; | |
157 | ||
158 | xilinx_wdt_wdd = &xdev->xilinx_wdt_wdd; | |
159 | xilinx_wdt_wdd->info = &xilinx_wdt_ident; | |
160 | xilinx_wdt_wdd->ops = &xilinx_wdt_ops; | |
161 | xilinx_wdt_wdd->parent = &pdev->dev; | |
e9659e69 | 162 | |
f06cdfd1 | 163 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
90663171 MS |
164 | xdev->base = devm_ioremap_resource(&pdev->dev, res); |
165 | if (IS_ERR(xdev->base)) | |
166 | return PTR_ERR(xdev->base); | |
f06cdfd1 | 167 | |
2e79a368 | 168 | rc = of_property_read_u32(pdev->dev.of_node, "clock-frequency", &pfreq); |
8d6a140b | 169 | if (rc) |
4c7fbbc4 MS |
170 | dev_warn(&pdev->dev, |
171 | "The watchdog clock frequency cannot be obtained\n"); | |
e9659e69 | 172 | |
2e79a368 MS |
173 | rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-interval", |
174 | &xdev->wdt_interval); | |
8d6a140b | 175 | if (rc) |
4c7fbbc4 MS |
176 | dev_warn(&pdev->dev, |
177 | "Parameter \"xlnx,wdt-interval\" not found\n"); | |
e9659e69 | 178 | |
2e79a368 MS |
179 | rc = of_property_read_u32(pdev->dev.of_node, "xlnx,wdt-enable-once", |
180 | &enable_once); | |
181 | if (rc) | |
4c7fbbc4 MS |
182 | dev_warn(&pdev->dev, |
183 | "Parameter \"xlnx,wdt-enable-once\" not found\n"); | |
2e79a368 MS |
184 | |
185 | watchdog_set_nowayout(xilinx_wdt_wdd, enable_once); | |
e9659e69 | 186 | |
75b3c5a8 MS |
187 | /* |
188 | * Twice of the 2^wdt_interval / freq because the first wdt overflow is | |
189 | * ignored (interrupt), reset is only generated at second wdt overflow | |
190 | */ | |
8d6a140b | 191 | if (pfreq && xdev->wdt_interval) |
90663171 | 192 | xilinx_wdt_wdd->timeout = 2 * ((1 << xdev->wdt_interval) / |
2e79a368 | 193 | pfreq); |
90663171 MS |
194 | |
195 | spin_lock_init(&xdev->spinlock); | |
196 | watchdog_set_drvdata(xilinx_wdt_wdd, xdev); | |
e9659e69 | 197 | |
90663171 | 198 | rc = xwdt_selftest(xdev); |
e9659e69 | 199 | if (rc == XWT_TIMER_FAILED) { |
4c7fbbc4 | 200 | dev_err(&pdev->dev, "SelfTest routine error\n"); |
f06cdfd1 | 201 | return rc; |
e9659e69 AC |
202 | } |
203 | ||
90663171 | 204 | rc = watchdog_register_device(xilinx_wdt_wdd); |
e9659e69 | 205 | if (rc) { |
4c7fbbc4 | 206 | dev_err(&pdev->dev, "Cannot register watchdog (err=%d)\n", rc); |
f06cdfd1 | 207 | return rc; |
e9659e69 AC |
208 | } |
209 | ||
d14fd964 | 210 | dev_info(&pdev->dev, "Xilinx Watchdog Timer at %p with timeout %ds\n", |
90663171 MS |
211 | xdev->base, xilinx_wdt_wdd->timeout); |
212 | ||
213 | platform_set_drvdata(pdev, xdev); | |
e9659e69 AC |
214 | |
215 | return 0; | |
e9659e69 AC |
216 | } |
217 | ||
90663171 | 218 | static int xwdt_remove(struct platform_device *pdev) |
e9659e69 | 219 | { |
90663171 MS |
220 | struct xwdt_device *xdev = platform_get_drvdata(pdev); |
221 | ||
222 | watchdog_unregister_device(&xdev->xilinx_wdt_wdd); | |
e9659e69 AC |
223 | |
224 | return 0; | |
225 | } | |
226 | ||
227 | /* Match table for of_platform binding */ | |
9ebf1855 | 228 | static const struct of_device_id xwdt_of_match[] = { |
8fce9b36 | 229 | { .compatible = "xlnx,xps-timebase-wdt-1.00.a", }, |
e9659e69 AC |
230 | { .compatible = "xlnx,xps-timebase-wdt-1.01.a", }, |
231 | {}, | |
232 | }; | |
233 | MODULE_DEVICE_TABLE(of, xwdt_of_match); | |
234 | ||
235 | static struct platform_driver xwdt_driver = { | |
236 | .probe = xwdt_probe, | |
82268714 | 237 | .remove = xwdt_remove, |
e9659e69 | 238 | .driver = { |
e9659e69 AC |
239 | .name = WATCHDOG_NAME, |
240 | .of_match_table = xwdt_of_match, | |
241 | }, | |
242 | }; | |
243 | ||
b8ec6118 | 244 | module_platform_driver(xwdt_driver); |
e9659e69 AC |
245 | |
246 | MODULE_AUTHOR("Alejandro Cabrera <aldaya@gmail.com>"); | |
247 | MODULE_DESCRIPTION("Xilinx Watchdog driver"); | |
9419c07c | 248 | MODULE_LICENSE("GPL v2"); |