Commit | Line | Data |
---|---|---|
7768a13c | 1 | /* |
2817142f | 2 | * omap_wdt.c |
7768a13c | 3 | * |
2817142f | 4 | * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog |
7768a13c KS |
5 | * |
6 | * Author: MontaVista Software, Inc. | |
7 | * <gdavis@mvista.com> or <source@mvista.com> | |
8 | * | |
9 | * 2003 (c) MontaVista Software, Inc. This file is licensed under the | |
10 | * terms of the GNU General Public License version 2. This program is | |
11 | * licensed "as is" without any warranty of any kind, whether express | |
12 | * or implied. | |
13 | * | |
14 | * History: | |
15 | * | |
16 | * 20030527: George G. Davis <gdavis@mvista.com> | |
17 | * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c | |
18 | * (c) Copyright 2000 Oleg Drokin <green@crimea.edu> | |
29fa0586 | 19 | * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk> |
7768a13c KS |
20 | * |
21 | * Copyright (c) 2004 Texas Instruments. | |
22 | * 1. Modified to support OMAP1610 32-KHz watchdog timer | |
23 | * 2. Ported to 2.6 kernel | |
24 | * | |
25 | * Copyright (c) 2005 David Brownell | |
26 | * Use the driver model and standard identifiers; handle bigger timeouts. | |
27 | */ | |
28 | ||
29 | #include <linux/module.h> | |
7768a13c KS |
30 | #include <linux/types.h> |
31 | #include <linux/kernel.h> | |
32 | #include <linux/fs.h> | |
33 | #include <linux/mm.h> | |
34 | #include <linux/miscdevice.h> | |
35 | #include <linux/watchdog.h> | |
36 | #include <linux/reboot.h> | |
7768a13c KS |
37 | #include <linux/init.h> |
38 | #include <linux/err.h> | |
39 | #include <linux/platform_device.h> | |
40 | #include <linux/moduleparam.h> | |
41 | #include <linux/clk.h> | |
1977f032 | 42 | #include <linux/bitops.h> |
089ab079 | 43 | #include <linux/io.h> |
12b9df7d | 44 | #include <linux/uaccess.h> |
a09e64fb | 45 | #include <mach/hardware.h> |
a09e64fb | 46 | #include <mach/prcm.h> |
7768a13c KS |
47 | |
48 | #include "omap_wdt.h" | |
49 | ||
2817142f FB |
50 | static struct platform_device *omap_wdt_dev; |
51 | ||
7768a13c KS |
52 | static unsigned timer_margin; |
53 | module_param(timer_margin, uint, 0); | |
54 | MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)"); | |
55 | ||
7768a13c | 56 | static unsigned int wdt_trgr_pattern = 0x1234; |
12b9df7d | 57 | static spinlock_t wdt_lock; |
7768a13c | 58 | |
2817142f FB |
59 | struct omap_wdt_dev { |
60 | void __iomem *base; /* physical */ | |
61 | struct device *dev; | |
62 | int omap_wdt_users; | |
63 | struct clk *armwdt_ck; | |
64 | struct clk *mpu_wdt_ick; | |
65 | struct clk *mpu_wdt_fck; | |
66 | struct resource *mem; | |
67 | struct miscdevice omap_wdt_miscdev; | |
68 | }; | |
69 | ||
70 | static void omap_wdt_ping(struct omap_wdt_dev *wdev) | |
7768a13c | 71 | { |
2817142f | 72 | void __iomem *base = wdev->base; |
b3112180 | 73 | |
7768a13c | 74 | /* wait for posted write to complete */ |
9f69e3b0 | 75 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c | 76 | cpu_relax(); |
b3112180 | 77 | |
7768a13c | 78 | wdt_trgr_pattern = ~wdt_trgr_pattern; |
9f69e3b0 | 79 | __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); |
b3112180 | 80 | |
7768a13c | 81 | /* wait for posted write to complete */ |
9f69e3b0 | 82 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08) |
7768a13c KS |
83 | cpu_relax(); |
84 | /* reloaded WCRR from WLDR */ | |
85 | } | |
86 | ||
2817142f | 87 | static void omap_wdt_enable(struct omap_wdt_dev *wdev) |
7768a13c | 88 | { |
b3112180 FB |
89 | void __iomem *base = wdev->base; |
90 | ||
7768a13c | 91 | /* Sequence to enable the watchdog */ |
9f69e3b0 FB |
92 | __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR); |
93 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c | 94 | cpu_relax(); |
b3112180 | 95 | |
9f69e3b0 FB |
96 | __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR); |
97 | while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10) | |
7768a13c KS |
98 | cpu_relax(); |
99 | } | |
100 | ||
2817142f | 101 | static void omap_wdt_disable(struct omap_wdt_dev *wdev) |
7768a13c | 102 | { |
b3112180 FB |
103 | void __iomem *base = wdev->base; |
104 | ||
7768a13c | 105 | /* sequence required to disable watchdog */ |
9f69e3b0 FB |
106 | __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
107 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c | 108 | cpu_relax(); |
b3112180 | 109 | |
9f69e3b0 FB |
110 | __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */ |
111 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10) | |
7768a13c KS |
112 | cpu_relax(); |
113 | } | |
114 | ||
115 | static void omap_wdt_adjust_timeout(unsigned new_timeout) | |
116 | { | |
117 | if (new_timeout < TIMER_MARGIN_MIN) | |
118 | new_timeout = TIMER_MARGIN_DEFAULT; | |
119 | if (new_timeout > TIMER_MARGIN_MAX) | |
120 | new_timeout = TIMER_MARGIN_MAX; | |
121 | timer_margin = new_timeout; | |
122 | } | |
123 | ||
2817142f | 124 | static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev) |
7768a13c KS |
125 | { |
126 | u32 pre_margin = GET_WLDR_VAL(timer_margin); | |
b3112180 | 127 | void __iomem *base = wdev->base; |
7768a13c KS |
128 | |
129 | /* just count up at 32 KHz */ | |
9f69e3b0 | 130 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) |
7768a13c | 131 | cpu_relax(); |
b3112180 | 132 | |
9f69e3b0 FB |
133 | __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR); |
134 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04) | |
7768a13c KS |
135 | cpu_relax(); |
136 | } | |
137 | ||
138 | /* | |
139 | * Allow only one task to hold it open | |
140 | */ | |
7768a13c KS |
141 | static int omap_wdt_open(struct inode *inode, struct file *file) |
142 | { | |
b3112180 FB |
143 | struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev); |
144 | void __iomem *base = wdev->base; | |
145 | ||
2817142f | 146 | if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users))) |
7768a13c KS |
147 | return -EBUSY; |
148 | ||
149 | if (cpu_is_omap16xx()) | |
2817142f | 150 | clk_enable(wdev->armwdt_ck); /* Enable the clock */ |
7768a13c | 151 | |
2817142f FB |
152 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { |
153 | clk_enable(wdev->mpu_wdt_ick); /* Enable the interface clock */ | |
154 | clk_enable(wdev->mpu_wdt_fck); /* Enable the functional clock */ | |
7768a13c KS |
155 | } |
156 | ||
157 | /* initialize prescaler */ | |
9f69e3b0 | 158 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) |
7768a13c | 159 | cpu_relax(); |
b3112180 | 160 | |
9f69e3b0 FB |
161 | __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL); |
162 | while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01) | |
7768a13c KS |
163 | cpu_relax(); |
164 | ||
2817142f FB |
165 | file->private_data = (void *) wdev; |
166 | ||
167 | omap_wdt_set_timeout(wdev); | |
168 | omap_wdt_enable(wdev); | |
b3112180 | 169 | |
ec9505a7 | 170 | return nonseekable_open(inode, file); |
7768a13c KS |
171 | } |
172 | ||
173 | static int omap_wdt_release(struct inode *inode, struct file *file) | |
174 | { | |
b3112180 FB |
175 | struct omap_wdt_dev *wdev = file->private_data; |
176 | ||
7768a13c KS |
177 | /* |
178 | * Shut off the timer unless NOWAYOUT is defined. | |
179 | */ | |
180 | #ifndef CONFIG_WATCHDOG_NOWAYOUT | |
7768a13c | 181 | |
2817142f | 182 | omap_wdt_disable(wdev); |
7768a13c | 183 | |
2817142f FB |
184 | if (cpu_is_omap16xx()) |
185 | clk_disable(wdev->armwdt_ck); /* Disable the clock */ | |
186 | ||
187 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) { | |
188 | clk_disable(wdev->mpu_wdt_ick); /* Disable the clock */ | |
189 | clk_disable(wdev->mpu_wdt_fck); /* Disable the clock */ | |
7768a13c KS |
190 | } |
191 | #else | |
192 | printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n"); | |
193 | #endif | |
2817142f | 194 | wdev->omap_wdt_users = 0; |
b3112180 | 195 | |
7768a13c KS |
196 | return 0; |
197 | } | |
198 | ||
12b9df7d | 199 | static ssize_t omap_wdt_write(struct file *file, const char __user *data, |
7768a13c KS |
200 | size_t len, loff_t *ppos) |
201 | { | |
b3112180 FB |
202 | struct omap_wdt_dev *wdev = file->private_data; |
203 | ||
7768a13c | 204 | /* Refresh LOAD_TIME. */ |
12b9df7d AC |
205 | if (len) { |
206 | spin_lock(&wdt_lock); | |
2817142f | 207 | omap_wdt_ping(wdev); |
12b9df7d AC |
208 | spin_unlock(&wdt_lock); |
209 | } | |
7768a13c KS |
210 | return len; |
211 | } | |
212 | ||
12b9df7d AC |
213 | static long omap_wdt_ioctl(struct file *file, unsigned int cmd, |
214 | unsigned long arg) | |
7768a13c | 215 | { |
2817142f | 216 | struct omap_wdt_dev *wdev; |
7768a13c | 217 | int new_margin; |
12b9df7d | 218 | static const struct watchdog_info ident = { |
7768a13c KS |
219 | .identity = "OMAP Watchdog", |
220 | .options = WDIOF_SETTIMEOUT, | |
221 | .firmware_version = 0, | |
222 | }; | |
b3112180 | 223 | |
2817142f | 224 | wdev = file->private_data; |
7768a13c KS |
225 | |
226 | switch (cmd) { | |
7768a13c KS |
227 | case WDIOC_GETSUPPORT: |
228 | return copy_to_user((struct watchdog_info __user *)arg, &ident, | |
229 | sizeof(ident)); | |
230 | case WDIOC_GETSTATUS: | |
231 | return put_user(0, (int __user *)arg); | |
232 | case WDIOC_GETBOOTSTATUS: | |
233 | if (cpu_is_omap16xx()) | |
9f69e3b0 | 234 | return put_user(__raw_readw(ARM_SYSST), |
7768a13c KS |
235 | (int __user *)arg); |
236 | if (cpu_is_omap24xx()) | |
237 | return put_user(omap_prcm_get_reset_sources(), | |
238 | (int __user *)arg); | |
239 | case WDIOC_KEEPALIVE: | |
12b9df7d | 240 | spin_lock(&wdt_lock); |
2817142f | 241 | omap_wdt_ping(wdev); |
12b9df7d | 242 | spin_unlock(&wdt_lock); |
7768a13c KS |
243 | return 0; |
244 | case WDIOC_SETTIMEOUT: | |
245 | if (get_user(new_margin, (int __user *)arg)) | |
246 | return -EFAULT; | |
247 | omap_wdt_adjust_timeout(new_margin); | |
248 | ||
12b9df7d | 249 | spin_lock(&wdt_lock); |
2817142f FB |
250 | omap_wdt_disable(wdev); |
251 | omap_wdt_set_timeout(wdev); | |
252 | omap_wdt_enable(wdev); | |
7768a13c | 253 | |
2817142f | 254 | omap_wdt_ping(wdev); |
12b9df7d | 255 | spin_unlock(&wdt_lock); |
7768a13c KS |
256 | /* Fall */ |
257 | case WDIOC_GETTIMEOUT: | |
258 | return put_user(timer_margin, (int __user *)arg); | |
0c06090c WVS |
259 | default: |
260 | return -ENOTTY; | |
7768a13c KS |
261 | } |
262 | } | |
263 | ||
2b8693c0 | 264 | static const struct file_operations omap_wdt_fops = { |
7768a13c KS |
265 | .owner = THIS_MODULE, |
266 | .write = omap_wdt_write, | |
12b9df7d | 267 | .unlocked_ioctl = omap_wdt_ioctl, |
7768a13c KS |
268 | .open = omap_wdt_open, |
269 | .release = omap_wdt_release, | |
270 | }; | |
271 | ||
7768a13c KS |
272 | static int __init omap_wdt_probe(struct platform_device *pdev) |
273 | { | |
274 | struct resource *res, *mem; | |
2817142f | 275 | struct omap_wdt_dev *wdev; |
b3112180 | 276 | int ret; |
7768a13c KS |
277 | |
278 | /* reserve static register mappings */ | |
279 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
b3112180 FB |
280 | if (!res) { |
281 | ret = -ENOENT; | |
282 | goto err_get_resource; | |
283 | } | |
7768a13c | 284 | |
b3112180 FB |
285 | if (omap_wdt_dev) { |
286 | ret = -EBUSY; | |
287 | goto err_busy; | |
288 | } | |
2817142f | 289 | |
7768a13c KS |
290 | mem = request_mem_region(res->start, res->end - res->start + 1, |
291 | pdev->name); | |
b3112180 FB |
292 | if (!mem) { |
293 | ret = -EBUSY; | |
294 | goto err_busy; | |
295 | } | |
7768a13c | 296 | |
2817142f FB |
297 | wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL); |
298 | if (!wdev) { | |
299 | ret = -ENOMEM; | |
b3112180 | 300 | goto err_kzalloc; |
2817142f | 301 | } |
b3112180 | 302 | |
2817142f FB |
303 | wdev->omap_wdt_users = 0; |
304 | wdev->mem = mem; | |
7768a13c KS |
305 | |
306 | if (cpu_is_omap16xx()) { | |
2817142f FB |
307 | wdev->armwdt_ck = clk_get(&pdev->dev, "armwdt_ck"); |
308 | if (IS_ERR(wdev->armwdt_ck)) { | |
309 | ret = PTR_ERR(wdev->armwdt_ck); | |
310 | wdev->armwdt_ck = NULL; | |
b3112180 | 311 | goto err_clk; |
7768a13c KS |
312 | } |
313 | } | |
314 | ||
315 | if (cpu_is_omap24xx()) { | |
2817142f FB |
316 | wdev->mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick"); |
317 | if (IS_ERR(wdev->mpu_wdt_ick)) { | |
318 | ret = PTR_ERR(wdev->mpu_wdt_ick); | |
319 | wdev->mpu_wdt_ick = NULL; | |
b3112180 | 320 | goto err_clk; |
2817142f FB |
321 | } |
322 | wdev->mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck"); | |
323 | if (IS_ERR(wdev->mpu_wdt_fck)) { | |
324 | ret = PTR_ERR(wdev->mpu_wdt_fck); | |
325 | wdev->mpu_wdt_fck = NULL; | |
b3112180 | 326 | goto err_clk; |
2817142f FB |
327 | } |
328 | } | |
329 | ||
330 | if (cpu_is_omap34xx()) { | |
331 | wdev->mpu_wdt_ick = clk_get(&pdev->dev, "wdt2_ick"); | |
332 | if (IS_ERR(wdev->mpu_wdt_ick)) { | |
333 | ret = PTR_ERR(wdev->mpu_wdt_ick); | |
334 | wdev->mpu_wdt_ick = NULL; | |
b3112180 | 335 | goto err_clk; |
7768a13c | 336 | } |
2817142f FB |
337 | wdev->mpu_wdt_fck = clk_get(&pdev->dev, "wdt2_fck"); |
338 | if (IS_ERR(wdev->mpu_wdt_fck)) { | |
339 | ret = PTR_ERR(wdev->mpu_wdt_fck); | |
340 | wdev->mpu_wdt_fck = NULL; | |
b3112180 | 341 | goto err_clk; |
7768a13c KS |
342 | } |
343 | } | |
9f69e3b0 FB |
344 | wdev->base = ioremap(res->start, res->end - res->start + 1); |
345 | if (!wdev->base) { | |
346 | ret = -ENOMEM; | |
b3112180 | 347 | goto err_ioremap; |
9f69e3b0 FB |
348 | } |
349 | ||
2817142f | 350 | platform_set_drvdata(pdev, wdev); |
7768a13c | 351 | |
2817142f | 352 | omap_wdt_disable(wdev); |
7768a13c KS |
353 | omap_wdt_adjust_timeout(timer_margin); |
354 | ||
2817142f FB |
355 | wdev->omap_wdt_miscdev.parent = &pdev->dev; |
356 | wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR; | |
357 | wdev->omap_wdt_miscdev.name = "watchdog"; | |
358 | wdev->omap_wdt_miscdev.fops = &omap_wdt_fops; | |
359 | ||
360 | ret = misc_register(&(wdev->omap_wdt_miscdev)); | |
7768a13c | 361 | if (ret) |
b3112180 | 362 | goto err_misc; |
7768a13c | 363 | |
2817142f | 364 | pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n", |
9f69e3b0 | 365 | __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF, |
2817142f | 366 | timer_margin); |
7768a13c KS |
367 | |
368 | /* autogate OCP interface clock */ | |
9f69e3b0 | 369 | __raw_writel(0x01, wdev->base + OMAP_WATCHDOG_SYS_CONFIG); |
2817142f FB |
370 | |
371 | omap_wdt_dev = pdev; | |
372 | ||
7768a13c KS |
373 | return 0; |
374 | ||
b3112180 FB |
375 | err_misc: |
376 | platform_set_drvdata(pdev, NULL); | |
377 | iounmap(wdev->base); | |
378 | ||
379 | err_ioremap: | |
380 | wdev->base = NULL; | |
381 | ||
382 | err_clk: | |
383 | if (wdev->armwdt_ck) | |
384 | clk_put(wdev->armwdt_ck); | |
385 | if (wdev->mpu_wdt_ick) | |
386 | clk_put(wdev->mpu_wdt_ick); | |
387 | if (wdev->mpu_wdt_fck) | |
388 | clk_put(wdev->mpu_wdt_fck); | |
389 | kfree(wdev); | |
390 | ||
391 | err_kzalloc: | |
392 | release_mem_region(res->start, res->end - res->start + 1); | |
393 | ||
394 | err_busy: | |
395 | err_get_resource: | |
396 | ||
7768a13c KS |
397 | return ret; |
398 | } | |
399 | ||
400 | static void omap_wdt_shutdown(struct platform_device *pdev) | |
401 | { | |
b3112180 | 402 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
2817142f FB |
403 | |
404 | if (wdev->omap_wdt_users) | |
405 | omap_wdt_disable(wdev); | |
7768a13c KS |
406 | } |
407 | ||
408 | static int omap_wdt_remove(struct platform_device *pdev) | |
409 | { | |
b3112180 | 410 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
2817142f FB |
411 | struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
412 | ||
413 | if (!res) | |
414 | return -ENOENT; | |
415 | ||
416 | misc_deregister(&(wdev->omap_wdt_miscdev)); | |
417 | release_mem_region(res->start, res->end - res->start + 1); | |
418 | platform_set_drvdata(pdev, NULL); | |
b3112180 | 419 | |
2817142f FB |
420 | if (wdev->armwdt_ck) { |
421 | clk_put(wdev->armwdt_ck); | |
422 | wdev->armwdt_ck = NULL; | |
423 | } | |
b3112180 | 424 | |
2817142f FB |
425 | if (wdev->mpu_wdt_ick) { |
426 | clk_put(wdev->mpu_wdt_ick); | |
427 | wdev->mpu_wdt_ick = NULL; | |
428 | } | |
b3112180 | 429 | |
2817142f FB |
430 | if (wdev->mpu_wdt_fck) { |
431 | clk_put(wdev->mpu_wdt_fck); | |
432 | wdev->mpu_wdt_fck = NULL; | |
433 | } | |
9f69e3b0 FB |
434 | iounmap(wdev->base); |
435 | ||
2817142f FB |
436 | kfree(wdev); |
437 | omap_wdt_dev = NULL; | |
b3112180 | 438 | |
7768a13c KS |
439 | return 0; |
440 | } | |
441 | ||
442 | #ifdef CONFIG_PM | |
443 | ||
444 | /* REVISIT ... not clear this is the best way to handle system suspend; and | |
445 | * it's very inappropriate for selective device suspend (e.g. suspending this | |
446 | * through sysfs rather than by stopping the watchdog daemon). Also, this | |
447 | * may not play well enough with NOWAYOUT... | |
448 | */ | |
449 | ||
450 | static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state) | |
451 | { | |
b3112180 FB |
452 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
453 | ||
2817142f FB |
454 | if (wdev->omap_wdt_users) |
455 | omap_wdt_disable(wdev); | |
b3112180 | 456 | |
7768a13c KS |
457 | return 0; |
458 | } | |
459 | ||
460 | static int omap_wdt_resume(struct platform_device *pdev) | |
461 | { | |
b3112180 FB |
462 | struct omap_wdt_dev *wdev = platform_get_drvdata(pdev); |
463 | ||
2817142f FB |
464 | if (wdev->omap_wdt_users) { |
465 | omap_wdt_enable(wdev); | |
466 | omap_wdt_ping(wdev); | |
7768a13c | 467 | } |
b3112180 | 468 | |
7768a13c KS |
469 | return 0; |
470 | } | |
471 | ||
472 | #else | |
473 | #define omap_wdt_suspend NULL | |
474 | #define omap_wdt_resume NULL | |
475 | #endif | |
476 | ||
477 | static struct platform_driver omap_wdt_driver = { | |
478 | .probe = omap_wdt_probe, | |
479 | .remove = omap_wdt_remove, | |
480 | .shutdown = omap_wdt_shutdown, | |
481 | .suspend = omap_wdt_suspend, | |
482 | .resume = omap_wdt_resume, | |
483 | .driver = { | |
484 | .owner = THIS_MODULE, | |
485 | .name = "omap_wdt", | |
486 | }, | |
487 | }; | |
488 | ||
489 | static int __init omap_wdt_init(void) | |
490 | { | |
12b9df7d | 491 | spin_lock_init(&wdt_lock); |
7768a13c KS |
492 | return platform_driver_register(&omap_wdt_driver); |
493 | } | |
494 | ||
495 | static void __exit omap_wdt_exit(void) | |
496 | { | |
497 | platform_driver_unregister(&omap_wdt_driver); | |
498 | } | |
499 | ||
500 | module_init(omap_wdt_init); | |
501 | module_exit(omap_wdt_exit); | |
502 | ||
503 | MODULE_AUTHOR("George G. Davis"); | |
504 | MODULE_LICENSE("GPL"); | |
505 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
f37d193c | 506 | MODULE_ALIAS("platform:omap_wdt"); |