[deliverable/linux.git] / drivers / watchdog / omap_wdt.c

/*
 * omap_wdt.c
 *
 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
 *
 * Author: MontaVista Software, Inc.
 *	 <gdavis@mvista.com> or <source@mvista.com>
 *
 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
 * terms of the GNU General Public License version 2. This program is
 * licensed "as is" without any warranty of any kind, whether express
 * or implied.
 *
 * History:
 *
 * 20030527: George G. Davis <gdavis@mvista.com>
 *	Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
 *	(c) Copyright 2000 Oleg Drokin <green@crimea.edu>
 *	Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
 *
 * Copyright (c) 2004 Texas Instruments.
 *	1. Modified to support OMAP1610 32-KHz watchdog timer
 *	2. Ported to 2.6 kernel
 *
 * Copyright (c) 2005 David Brownell
 *	Use the driver model and standard identifiers; handle bigger timeouts.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/watchdog.h>
#include <linux/reboot.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/moduleparam.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>
#include <linux/platform_data/omap-wd-timer.h>

#include "omap_wdt.h"

static bool nowayout = WATCHDOG_NOWAYOUT;
module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");

static unsigned timer_margin;
module_param(timer_margin, uint, 0);
MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");

struct omap_wdt_dev {
	void __iomem    *base;          /* physical */
	struct device   *dev;
	bool		omap_wdt_users;
	int		wdt_trgr_pattern;
	struct mutex	lock;		/* to avoid races with PM */
};

static void omap_wdt_reload(struct omap_wdt_dev *wdev)
{
	void __iomem    *base = wdev->base;

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();

	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));

	/* wait for posted write to complete */
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
		cpu_relax();
	/* reloaded WCRR from WLDR */
}

static void omap_wdt_enable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* Sequence to enable the watchdog */
	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();

	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
		cpu_relax();
}

static void omap_wdt_disable(struct omap_wdt_dev *wdev)
{
	void __iomem *base = wdev->base;

	/* sequence required to disable watchdog */
	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();

	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR);	/* TIMER_MODE */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
		cpu_relax();
}

static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
				   unsigned int timeout)
{
	u32 pre_margin = GET_WLDR_VAL(timeout);
	void __iomem *base = wdev->base;

	/* just count up at 32 KHz */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();

	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
		cpu_relax();
}

static int omap_wdt_start(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
	void __iomem *base = wdev->base;

	mutex_lock(&wdev->lock);

	wdev->omap_wdt_users = true;

	pm_runtime_get_sync(wdev->dev);

	/* initialize prescaler */
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
		cpu_relax();

	omap_wdt_set_timer(wdev, wdog->timeout);
	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
	omap_wdt_enable(wdev);

	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_stop(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	pm_runtime_put_sync(wdev->dev);
	wdev->omap_wdt_users = false;
	mutex_unlock(&wdev->lock);
	return 0;
}

static int omap_wdt_ping(struct watchdog_device *wdog)
{
	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_reload(wdev);
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_set_timeout(struct watchdog_device *wdog,
				unsigned int timeout)
{
	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);

	mutex_lock(&wdev->lock);
	omap_wdt_disable(wdev);
	omap_wdt_set_timer(wdev, timeout);
	omap_wdt_enable(wdev);
	omap_wdt_reload(wdev);
	wdog->timeout = timeout;
	mutex_unlock(&wdev->lock);

	return 0;
}

static const struct watchdog_info omap_wdt_info = {
	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
	.identity = "OMAP Watchdog",
};

static const struct watchdog_ops omap_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= omap_wdt_start,
	.stop		= omap_wdt_stop,
	.ping		= omap_wdt_ping,
	.set_timeout	= omap_wdt_set_timeout,
};

static int omap_wdt_probe(struct platform_device *pdev)
{
	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
	struct watchdog_device *omap_wdt;
	struct resource *res;
	struct omap_wdt_dev *wdev;
	u32 rs;
	int ret;

	omap_wdt = devm_kzalloc(&pdev->dev, sizeof(*omap_wdt), GFP_KERNEL);
	if (!omap_wdt)
		return -ENOMEM;

	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	if (!wdev)
		return -ENOMEM;

	wdev->omap_wdt_users	= false;
	wdev->dev		= &pdev->dev;
	wdev->wdt_trgr_pattern	= 0x1234;
	mutex_init(&wdev->lock);

	/* reserve static register mappings */
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	wdev->base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(wdev->base))
		return PTR_ERR(wdev->base);

	omap_wdt->info	      = &omap_wdt_info;
	omap_wdt->ops	      = &omap_wdt_ops;
	omap_wdt->min_timeout = TIMER_MARGIN_MIN;
	omap_wdt->max_timeout = TIMER_MARGIN_MAX;

	if (timer_margin >= TIMER_MARGIN_MIN &&
	    timer_margin <= TIMER_MARGIN_MAX)
		omap_wdt->timeout = timer_margin;
	else
		omap_wdt->timeout = TIMER_MARGIN_DEFAULT;

	watchdog_set_drvdata(omap_wdt, wdev);
	watchdog_set_nowayout(omap_wdt, nowayout);

	platform_set_drvdata(pdev, omap_wdt);

	pm_runtime_enable(wdev->dev);
	pm_runtime_get_sync(wdev->dev);

	if (pdata && pdata->read_reset_sources)
		rs = pdata->read_reset_sources();
	else
		rs = 0;
	omap_wdt->bootstatus = (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) ?
				WDIOF_CARDRESET : 0;

	omap_wdt_disable(wdev);

	ret = watchdog_register_device(omap_wdt);
	if (ret) {
		pm_runtime_disable(wdev->dev);
		return ret;
	}

	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
		readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
		omap_wdt->timeout);

	pm_runtime_put_sync(wdev->dev);

	return 0;
}

static void omap_wdt_shutdown(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);
}

static int omap_wdt_remove(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);

	pm_runtime_disable(wdev->dev);
	watchdog_unregister_device(wdog);

	return 0;
}

#ifdef	CONFIG_PM

/* REVISIT ... not clear this is the best way to handle system suspend; and
 * it's very inappropriate for selective device suspend (e.g. suspending this
 * through sysfs rather than by stopping the watchdog daemon).  Also, this
 * may not play well enough with NOWAYOUT...
 */

static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		omap_wdt_disable(wdev);
		pm_runtime_put_sync(wdev->dev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

static int omap_wdt_resume(struct platform_device *pdev)
{
	struct watchdog_device *wdog = platform_get_drvdata(pdev);
	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);

	mutex_lock(&wdev->lock);
	if (wdev->omap_wdt_users) {
		pm_runtime_get_sync(wdev->dev);
		omap_wdt_enable(wdev);
		omap_wdt_reload(wdev);
	}
	mutex_unlock(&wdev->lock);

	return 0;
}

#else
#define	omap_wdt_suspend	NULL
#define	omap_wdt_resume		NULL
#endif

static const struct of_device_id omap_wdt_of_match[] = {
	{ .compatible = "ti,omap3-wdt", },
	{},
};
MODULE_DEVICE_TABLE(of, omap_wdt_of_match);

static struct platform_driver omap_wdt_driver = {
	.probe		= omap_wdt_probe,
	.remove		= omap_wdt_remove,
	.shutdown	= omap_wdt_shutdown,
	.suspend	= omap_wdt_suspend,
	.resume		= omap_wdt_resume,
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= "omap_wdt",
		.of_match_table = omap_wdt_of_match,
	},
};

module_platform_driver(omap_wdt_driver);

MODULE_AUTHOR("George G. Davis");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:omap_wdt");
Commit	Line	Data
7768a13c	1	/*
2817142f	2	* omap_wdt.c
7768a13c	3	*
2817142f	4	* Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c KS	5	*
	6	* Author: MontaVista Software, Inc.
	7	* <gdavis@mvista.com> or <source@mvista.com>
	8	*
	9	* 2003 (c) MontaVista Software, Inc. This file is licensed under the
	10	* terms of the GNU General Public License version 2. This program is
	11	* licensed "as is" without any warranty of any kind, whether express
	12	* or implied.
	13	*
	14	* History:
	15	*
	16	* 20030527: George G. Davis <gdavis@mvista.com>
	17	* Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
	18	* (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586	19	* Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
7768a13c KS	20	*
	21	* Copyright (c) 2004 Texas Instruments.
	22	* 1. Modified to support OMAP1610 32-KHz watchdog timer
	23	* 2. Ported to 2.6 kernel
	24	*
	25	* Copyright (c) 2005 David Brownell
	26	* Use the driver model and standard identifiers; handle bigger timeouts.
	27	*/
	28
27c766aa JP	29	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27c766aa JP	30
7768a13c	31	#include <linux/module.h>
7768a13c KS	32	#include <linux/types.h>
7768a13c KS	33	#include <linux/kernel.h>
7768a13c	34	#include <linux/mm.h>
7768a13c KS	35	#include <linux/watchdog.h>
7768a13c KS	36	#include <linux/reboot.h>
7768a13c KS	37	#include <linux/err.h>
	38	#include <linux/platform_device.h>
	39	#include <linux/moduleparam.h>
089ab079	40	#include <linux/io.h>
5a0e3ad6	41	#include <linux/slab.h>
7ec5ad0f	42	#include <linux/pm_runtime.h>
129f5577	43	#include <linux/platform_data/omap-wd-timer.h>
7768a13c KS	44
	45	#include "omap_wdt.h"
	46
2dd7b244 PR	47	static bool nowayout = WATCHDOG_NOWAYOUT;
	48	module_param(nowayout, bool, 0);
	49	MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
	50	"(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
	51
7768a13c KS	52	static unsigned timer_margin;
	53	module_param(timer_margin, uint, 0);
	54	MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
	55
2817142f FB	56	struct omap_wdt_dev {
	57	void __iomem base; / physical */
	58	struct device *dev;
67c0f554	59	bool omap_wdt_users;
67c0f554 AK	60	int wdt_trgr_pattern;
67c0f554 AK	61	struct mutex lock; /* to avoid races with PM */
2817142f FB	62	};
2817142f FB	63
67c0f554	64	static void omap_wdt_reload(struct omap_wdt_dev *wdev)
7768a13c	65	{
2817142f	66	void __iomem *base = wdev->base;
b3112180	67
7768a13c	68	/* wait for posted write to complete */
4a7e94a0	69	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c	70	cpu_relax();
b3112180	71
67c0f554	72	wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
4a7e94a0	73	writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180	74
7768a13c	75	/* wait for posted write to complete */
4a7e94a0	76	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c KS	77	cpu_relax();
	78	/* reloaded WCRR from WLDR */
	79	}
	80
2817142f	81	static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c	82	{
b3112180 FB	83	void __iomem *base = wdev->base;
b3112180 FB	84
7768a13c	85	/* Sequence to enable the watchdog */
4a7e94a0 VK	86	writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	87	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c	88	cpu_relax();
b3112180	89
4a7e94a0 VK	90	writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
4a7e94a0 VK	91	while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c KS	92	cpu_relax();
	93	}
	94
2817142f	95	static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c	96	{
b3112180 FB	97	void __iomem *base = wdev->base;
b3112180 FB	98
7768a13c	99	/* sequence required to disable watchdog */
4a7e94a0 VK	100	writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	101	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c	102	cpu_relax();
b3112180	103
4a7e94a0 VK	104	writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
4a7e94a0 VK	105	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c KS	106	cpu_relax();
	107	}
	108
67c0f554 AK	109	static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
67c0f554 AK	110	unsigned int timeout)
7768a13c	111	{
67c0f554	112	u32 pre_margin = GET_WLDR_VAL(timeout);
b3112180	113	void __iomem *base = wdev->base;
7768a13c KS	114
7768a13c KS	115	/* just count up at 32 KHz */
4a7e94a0	116	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c	117	cpu_relax();
b3112180	118
4a7e94a0 VK	119	writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
4a7e94a0 VK	120	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c KS	121	cpu_relax();
	122	}
	123
67c0f554	124	static int omap_wdt_start(struct watchdog_device *wdog)
7768a13c	125	{
67c0f554	126	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
b3112180 FB	127	void __iomem *base = wdev->base;
b3112180 FB	128
67c0f554 AK	129	mutex_lock(&wdev->lock);
	130
	131	wdev->omap_wdt_users = true;
7768a13c	132
7ec5ad0f	133	pm_runtime_get_sync(wdev->dev);
7768a13c KS	134
7768a13c KS	135	/* initialize prescaler */
4a7e94a0	136	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c	137	cpu_relax();
b3112180	138
4a7e94a0 VK	139	writel_relaxed((1 << 5) \| (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
4a7e94a0 VK	140	while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c KS	141	cpu_relax();
7768a13c KS	142
67c0f554 AK	143	omap_wdt_set_timer(wdev, wdog->timeout);
67c0f554 AK	144	omap_wdt_reload(wdev); /* trigger loading of new timeout value */
2817142f	145	omap_wdt_enable(wdev);
b3112180	146
67c0f554 AK	147	mutex_unlock(&wdev->lock);
	148
	149	return 0;
7768a13c KS	150	}
7768a13c KS	151
67c0f554	152	static int omap_wdt_stop(struct watchdog_device *wdog)
7768a13c	153	{
67c0f554	154	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
b3112180	155
67c0f554	156	mutex_lock(&wdev->lock);
2817142f	157	omap_wdt_disable(wdev);
7ec5ad0f	158	pm_runtime_put_sync(wdev->dev);
67c0f554 AK	159	wdev->omap_wdt_users = false;
67c0f554 AK	160	mutex_unlock(&wdev->lock);
7768a13c KS	161	return 0;
	162	}
	163
67c0f554	164	static int omap_wdt_ping(struct watchdog_device *wdog)
7768a13c	165	{
67c0f554	166	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
b3112180	167
67c0f554 AK	168	mutex_lock(&wdev->lock);
	169	omap_wdt_reload(wdev);
	170	mutex_unlock(&wdev->lock);
	171
	172	return 0;
7768a13c KS	173	}
7768a13c KS	174
67c0f554 AK	175	static int omap_wdt_set_timeout(struct watchdog_device *wdog,
67c0f554 AK	176	unsigned int timeout)
7768a13c	177	{
67c0f554	178	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
7768a13c	179
67c0f554 AK	180	mutex_lock(&wdev->lock);
	181	omap_wdt_disable(wdev);
	182	omap_wdt_set_timer(wdev, timeout);
	183	omap_wdt_enable(wdev);
	184	omap_wdt_reload(wdev);
	185	wdog->timeout = timeout;
	186	mutex_unlock(&wdev->lock);
	187
	188	return 0;
7768a13c KS	189	}
7768a13c KS	190
67c0f554 AK	191	static const struct watchdog_info omap_wdt_info = {
	192	.options = WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING,
	193	.identity = "OMAP Watchdog",
	194	};
	195
	196	static const struct watchdog_ops omap_wdt_ops = {
	197	.owner = THIS_MODULE,
	198	.start = omap_wdt_start,
	199	.stop = omap_wdt_stop,
	200	.ping = omap_wdt_ping,
	201	.set_timeout = omap_wdt_set_timeout,
7768a13c KS	202	};
7768a13c KS	203
2d991a16	204	static int omap_wdt_probe(struct platform_device *pdev)
7768a13c	205	{
bc8fdfbe	206	struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
67c0f554	207	struct watchdog_device *omap_wdt;
6e272061	208	struct resource *res;
2817142f	209	struct omap_wdt_dev *wdev;
67c0f554	210	u32 rs;
b3112180	211	int ret;
7768a13c	212
4f4753d9	213	omap_wdt = devm_kzalloc(&pdev->dev, sizeof(*omap_wdt), GFP_KERNEL);
67c0f554 AK	214	if (!omap_wdt)
	215	return -ENOMEM;
	216
4f4753d9 AK	217	wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
	218	if (!wdev)
	219	return -ENOMEM;
b3112180	220
67c0f554	221	wdev->omap_wdt_users = false;
67c0f554 AK	222	wdev->dev = &pdev->dev;
	223	wdev->wdt_trgr_pattern = 0x1234;
	224	mutex_init(&wdev->lock);
2817142f	225
6e272061 JH	226	/* reserve static register mappings */
	227	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	228	wdev->base = devm_ioremap_resource(&pdev->dev, res);
	229	if (IS_ERR(wdev->base))
	230	return PTR_ERR(wdev->base);
9f69e3b0	231
67c0f554 AK	232	omap_wdt->info = &omap_wdt_info;
	233	omap_wdt->ops = &omap_wdt_ops;
	234	omap_wdt->min_timeout = TIMER_MARGIN_MIN;
	235	omap_wdt->max_timeout = TIMER_MARGIN_MAX;
	236
	237	if (timer_margin >= TIMER_MARGIN_MIN &&
	238	timer_margin <= TIMER_MARGIN_MAX)
	239	omap_wdt->timeout = timer_margin;
	240	else
	241	omap_wdt->timeout = TIMER_MARGIN_DEFAULT;
	242
	243	watchdog_set_drvdata(omap_wdt, wdev);
	244	watchdog_set_nowayout(omap_wdt, nowayout);
	245
	246	platform_set_drvdata(pdev, omap_wdt);
7768a13c	247
7ec5ad0f VC	248	pm_runtime_enable(wdev->dev);
7ec5ad0f VC	249	pm_runtime_get_sync(wdev->dev);
789cd470	250
67c0f554 AK	251	if (pdata && pdata->read_reset_sources)
	252	rs = pdata->read_reset_sources();
	253	else
	254	rs = 0;
	255	omap_wdt->bootstatus = (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) ?
	256	WDIOF_CARDRESET : 0;
7768a13c	257
67c0f554	258	omap_wdt_disable(wdev);
2817142f	259
67c0f554	260	ret = watchdog_register_device(omap_wdt);
1ba85387 AK	261	if (ret) {
	262	pm_runtime_disable(wdev->dev);
	263	return ret;
	264	}
7768a13c	265
2817142f	266	pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
4a7e94a0	267	readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
67c0f554	268	omap_wdt->timeout);
7768a13c	269
7ec5ad0f	270	pm_runtime_put_sync(wdev->dev);
789cd470	271
7768a13c	272	return 0;
7768a13c KS	273	}
	274
	275	static void omap_wdt_shutdown(struct platform_device *pdev)
	276	{
67c0f554 AK	277	struct watchdog_device *wdog = platform_get_drvdata(pdev);
67c0f554 AK	278	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
2817142f	279
67c0f554	280	mutex_lock(&wdev->lock);
0503add9	281	if (wdev->omap_wdt_users) {
2817142f	282	omap_wdt_disable(wdev);
0503add9 PW	283	pm_runtime_put_sync(wdev->dev);
0503add9 PW	284	}
67c0f554	285	mutex_unlock(&wdev->lock);
7768a13c KS	286	}
7768a13c KS	287
4b12b896	288	static int omap_wdt_remove(struct platform_device *pdev)
7768a13c	289	{
67c0f554 AK	290	struct watchdog_device *wdog = platform_get_drvdata(pdev);
67c0f554 AK	291	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
2817142f	292
12c583d8	293	pm_runtime_disable(wdev->dev);
67c0f554	294	watchdog_unregister_device(wdog);
b3112180	295
7768a13c KS	296	return 0;
	297	}
	298
	299	#ifdef CONFIG_PM
	300
	301	/* REVISIT ... not clear this is the best way to handle system suspend; and
	302	* it's very inappropriate for selective device suspend (e.g. suspending this
	303	* through sysfs rather than by stopping the watchdog daemon). Also, this
	304	* may not play well enough with NOWAYOUT...
	305	*/
	306
	307	static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
	308	{
67c0f554 AK	309	struct watchdog_device *wdog = platform_get_drvdata(pdev);
67c0f554 AK	310	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
b3112180	311
67c0f554	312	mutex_lock(&wdev->lock);
0503add9	313	if (wdev->omap_wdt_users) {
2817142f	314	omap_wdt_disable(wdev);
0503add9 PW	315	pm_runtime_put_sync(wdev->dev);
0503add9 PW	316	}
67c0f554	317	mutex_unlock(&wdev->lock);
b3112180	318
7768a13c KS	319	return 0;
	320	}
	321
	322	static int omap_wdt_resume(struct platform_device *pdev)
	323	{
67c0f554 AK	324	struct watchdog_device *wdog = platform_get_drvdata(pdev);
67c0f554 AK	325	struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
b3112180	326
67c0f554	327	mutex_lock(&wdev->lock);
2817142f	328	if (wdev->omap_wdt_users) {
0503add9	329	pm_runtime_get_sync(wdev->dev);
2817142f	330	omap_wdt_enable(wdev);
67c0f554	331	omap_wdt_reload(wdev);
7768a13c	332	}
67c0f554	333	mutex_unlock(&wdev->lock);
b3112180	334
7768a13c KS	335	return 0;
	336	}
	337
	338	#else
	339	#define omap_wdt_suspend NULL
	340	#define omap_wdt_resume NULL
	341	#endif
	342
e6ca04ea XJ	343	static const struct of_device_id omap_wdt_of_match[] = {
	344	{ .compatible = "ti,omap3-wdt", },
	345	{},
	346	};
	347	MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
	348
7768a13c KS	349	static struct platform_driver omap_wdt_driver = {
7768a13c KS	350	.probe = omap_wdt_probe,
82268714	351	.remove = omap_wdt_remove,
7768a13c KS	352	.shutdown = omap_wdt_shutdown,
	353	.suspend = omap_wdt_suspend,
	354	.resume = omap_wdt_resume,
	355	.driver = {
	356	.owner = THIS_MODULE,
	357	.name = "omap_wdt",
e6ca04ea	358	.of_match_table = omap_wdt_of_match,
7768a13c KS	359	},
	360	};
	361
b8ec6118	362	module_platform_driver(omap_wdt_driver);
7768a13c KS	363
	364	MODULE_AUTHOR("George G. Davis");
	365	MODULE_LICENSE("GPL");
f37d193c	366	MODULE_ALIAS("platform:omap_wdt");