Merge tag 'mmc-merge-for-3.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...
[deliverable/linux.git] / drivers / watchdog / omap_wdt.c
CommitLineData
7768a13c 1/*
2817142f 2 * omap_wdt.c
7768a13c 3 *
2817142f 4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
7768a13c
KS
5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
29fa0586 19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
7768a13c
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20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
27c766aa
JP
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
7768a13c 31#include <linux/module.h>
7768a13c
KS
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/fs.h>
35#include <linux/mm.h>
36#include <linux/miscdevice.h>
37#include <linux/watchdog.h>
38#include <linux/reboot.h>
7768a13c
KS
39#include <linux/init.h>
40#include <linux/err.h>
41#include <linux/platform_device.h>
42#include <linux/moduleparam.h>
1977f032 43#include <linux/bitops.h>
089ab079 44#include <linux/io.h>
12b9df7d 45#include <linux/uaccess.h>
5a0e3ad6 46#include <linux/slab.h>
7ec5ad0f 47#include <linux/pm_runtime.h>
a09e64fb 48#include <mach/hardware.h>
dbc04161 49#include <plat/cpu.h>
ce491cf8 50#include <plat/prcm.h>
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51
52#include "omap_wdt.h"
53
2817142f
FB
54static struct platform_device *omap_wdt_dev;
55
7768a13c
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56static unsigned timer_margin;
57module_param(timer_margin, uint, 0);
58MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
59
7768a13c 60static unsigned int wdt_trgr_pattern = 0x1234;
1334f329 61static DEFINE_SPINLOCK(wdt_lock);
7768a13c 62
2817142f
FB
63struct omap_wdt_dev {
64 void __iomem *base; /* physical */
65 struct device *dev;
66 int omap_wdt_users;
2817142f
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67 struct resource *mem;
68 struct miscdevice omap_wdt_miscdev;
69};
70
71static void omap_wdt_ping(struct omap_wdt_dev *wdev)
7768a13c 72{
2817142f 73 void __iomem *base = wdev->base;
b3112180 74
7768a13c 75 /* wait for posted write to complete */
9f69e3b0 76 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
7768a13c 77 cpu_relax();
b3112180 78
7768a13c 79 wdt_trgr_pattern = ~wdt_trgr_pattern;
9f69e3b0 80 __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
b3112180 81
7768a13c 82 /* wait for posted write to complete */
9f69e3b0 83 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
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84 cpu_relax();
85 /* reloaded WCRR from WLDR */
86}
87
2817142f 88static void omap_wdt_enable(struct omap_wdt_dev *wdev)
7768a13c 89{
b3112180
FB
90 void __iomem *base = wdev->base;
91
7768a13c 92 /* Sequence to enable the watchdog */
9f69e3b0
FB
93 __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
94 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
7768a13c 95 cpu_relax();
b3112180 96
9f69e3b0
FB
97 __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
98 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
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99 cpu_relax();
100}
101
2817142f 102static void omap_wdt_disable(struct omap_wdt_dev *wdev)
7768a13c 103{
b3112180
FB
104 void __iomem *base = wdev->base;
105
7768a13c 106 /* sequence required to disable watchdog */
9f69e3b0
FB
107 __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
108 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
7768a13c 109 cpu_relax();
b3112180 110
9f69e3b0
FB
111 __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
112 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
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113 cpu_relax();
114}
115
116static void omap_wdt_adjust_timeout(unsigned new_timeout)
117{
118 if (new_timeout < TIMER_MARGIN_MIN)
119 new_timeout = TIMER_MARGIN_DEFAULT;
120 if (new_timeout > TIMER_MARGIN_MAX)
121 new_timeout = TIMER_MARGIN_MAX;
122 timer_margin = new_timeout;
123}
124
2817142f 125static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
7768a13c
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126{
127 u32 pre_margin = GET_WLDR_VAL(timer_margin);
b3112180 128 void __iomem *base = wdev->base;
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129
130 /* just count up at 32 KHz */
9f69e3b0 131 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
7768a13c 132 cpu_relax();
b3112180 133
9f69e3b0
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134 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
135 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
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136 cpu_relax();
137}
138
139/*
140 * Allow only one task to hold it open
141 */
7768a13c
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142static int omap_wdt_open(struct inode *inode, struct file *file)
143{
b3112180
FB
144 struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
145 void __iomem *base = wdev->base;
146
2817142f 147 if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
7768a13c
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148 return -EBUSY;
149
7ec5ad0f 150 pm_runtime_get_sync(wdev->dev);
7768a13c
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151
152 /* initialize prescaler */
9f69e3b0 153 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
7768a13c 154 cpu_relax();
b3112180 155
9f69e3b0
FB
156 __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
157 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
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158 cpu_relax();
159
2817142f
FB
160 file->private_data = (void *) wdev;
161
162 omap_wdt_set_timeout(wdev);
789cd470 163 omap_wdt_ping(wdev); /* trigger loading of new timeout value */
2817142f 164 omap_wdt_enable(wdev);
b3112180 165
ec9505a7 166 return nonseekable_open(inode, file);
7768a13c
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167}
168
169static int omap_wdt_release(struct inode *inode, struct file *file)
170{
b3112180
FB
171 struct omap_wdt_dev *wdev = file->private_data;
172
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173 /*
174 * Shut off the timer unless NOWAYOUT is defined.
175 */
176#ifndef CONFIG_WATCHDOG_NOWAYOUT
2817142f 177 omap_wdt_disable(wdev);
7768a13c 178
7ec5ad0f 179 pm_runtime_put_sync(wdev->dev);
7768a13c 180#else
27c766aa 181 pr_crit("Unexpected close, not stopping!\n");
7768a13c 182#endif
2817142f 183 wdev->omap_wdt_users = 0;
b3112180 184
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185 return 0;
186}
187
12b9df7d 188static ssize_t omap_wdt_write(struct file *file, const char __user *data,
7768a13c
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189 size_t len, loff_t *ppos)
190{
b3112180
FB
191 struct omap_wdt_dev *wdev = file->private_data;
192
7768a13c 193 /* Refresh LOAD_TIME. */
12b9df7d
AC
194 if (len) {
195 spin_lock(&wdt_lock);
2817142f 196 omap_wdt_ping(wdev);
12b9df7d
AC
197 spin_unlock(&wdt_lock);
198 }
7768a13c
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199 return len;
200}
201
12b9df7d
AC
202static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
203 unsigned long arg)
7768a13c 204{
2817142f 205 struct omap_wdt_dev *wdev;
7768a13c 206 int new_margin;
12b9df7d 207 static const struct watchdog_info ident = {
7768a13c
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208 .identity = "OMAP Watchdog",
209 .options = WDIOF_SETTIMEOUT,
210 .firmware_version = 0,
211 };
b3112180 212
2817142f 213 wdev = file->private_data;
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214
215 switch (cmd) {
7768a13c
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216 case WDIOC_GETSUPPORT:
217 return copy_to_user((struct watchdog_info __user *)arg, &ident,
218 sizeof(ident));
219 case WDIOC_GETSTATUS:
220 return put_user(0, (int __user *)arg);
221 case WDIOC_GETBOOTSTATUS:
dbc04161 222#ifdef CONFIG_ARCH_OMAP1
7768a13c 223 if (cpu_is_omap16xx())
9f69e3b0 224 return put_user(__raw_readw(ARM_SYSST),
7768a13c 225 (int __user *)arg);
dbc04161
TL
226#endif
227#ifdef CONFIG_ARCH_OMAP2PLUS
7768a13c
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228 if (cpu_is_omap24xx())
229 return put_user(omap_prcm_get_reset_sources(),
230 (int __user *)arg);
dbc04161 231#endif
e2bf7c4c 232 return put_user(0, (int __user *)arg);
7768a13c 233 case WDIOC_KEEPALIVE:
12b9df7d 234 spin_lock(&wdt_lock);
2817142f 235 omap_wdt_ping(wdev);
12b9df7d 236 spin_unlock(&wdt_lock);
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237 return 0;
238 case WDIOC_SETTIMEOUT:
239 if (get_user(new_margin, (int __user *)arg))
240 return -EFAULT;
241 omap_wdt_adjust_timeout(new_margin);
242
12b9df7d 243 spin_lock(&wdt_lock);
2817142f
FB
244 omap_wdt_disable(wdev);
245 omap_wdt_set_timeout(wdev);
246 omap_wdt_enable(wdev);
7768a13c 247
2817142f 248 omap_wdt_ping(wdev);
12b9df7d 249 spin_unlock(&wdt_lock);
7768a13c
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250 /* Fall */
251 case WDIOC_GETTIMEOUT:
252 return put_user(timer_margin, (int __user *)arg);
0c06090c
WVS
253 default:
254 return -ENOTTY;
7768a13c
KS
255 }
256}
257
2b8693c0 258static const struct file_operations omap_wdt_fops = {
7768a13c
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259 .owner = THIS_MODULE,
260 .write = omap_wdt_write,
12b9df7d 261 .unlocked_ioctl = omap_wdt_ioctl,
7768a13c
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262 .open = omap_wdt_open,
263 .release = omap_wdt_release,
6038f373 264 .llseek = no_llseek,
7768a13c
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265};
266
0e3912c7 267static int __devinit omap_wdt_probe(struct platform_device *pdev)
7768a13c
KS
268{
269 struct resource *res, *mem;
2817142f 270 struct omap_wdt_dev *wdev;
b3112180 271 int ret;
7768a13c
KS
272
273 /* reserve static register mappings */
274 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
b3112180
FB
275 if (!res) {
276 ret = -ENOENT;
277 goto err_get_resource;
278 }
7768a13c 279
b3112180
FB
280 if (omap_wdt_dev) {
281 ret = -EBUSY;
282 goto err_busy;
283 }
2817142f 284
b782a563 285 mem = request_mem_region(res->start, resource_size(res), pdev->name);
b3112180
FB
286 if (!mem) {
287 ret = -EBUSY;
288 goto err_busy;
289 }
7768a13c 290
2817142f
FB
291 wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
292 if (!wdev) {
293 ret = -ENOMEM;
b3112180 294 goto err_kzalloc;
2817142f 295 }
b3112180 296
2817142f
FB
297 wdev->omap_wdt_users = 0;
298 wdev->mem = mem;
7ec5ad0f 299 wdev->dev = &pdev->dev;
2817142f 300
b782a563 301 wdev->base = ioremap(res->start, resource_size(res));
9f69e3b0
FB
302 if (!wdev->base) {
303 ret = -ENOMEM;
b3112180 304 goto err_ioremap;
9f69e3b0
FB
305 }
306
2817142f 307 platform_set_drvdata(pdev, wdev);
7768a13c 308
7ec5ad0f
VC
309 pm_runtime_enable(wdev->dev);
310 pm_runtime_get_sync(wdev->dev);
789cd470 311
2817142f 312 omap_wdt_disable(wdev);
7768a13c
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313 omap_wdt_adjust_timeout(timer_margin);
314
2817142f
FB
315 wdev->omap_wdt_miscdev.parent = &pdev->dev;
316 wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
317 wdev->omap_wdt_miscdev.name = "watchdog";
318 wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
319
320 ret = misc_register(&(wdev->omap_wdt_miscdev));
7768a13c 321 if (ret)
b3112180 322 goto err_misc;
7768a13c 323
2817142f 324 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
9f69e3b0 325 __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
2817142f 326 timer_margin);
7768a13c 327
7ec5ad0f 328 pm_runtime_put_sync(wdev->dev);
789cd470 329
2817142f
FB
330 omap_wdt_dev = pdev;
331
7768a13c
KS
332 return 0;
333
b3112180 334err_misc:
12c583d8 335 pm_runtime_disable(wdev->dev);
b3112180
FB
336 platform_set_drvdata(pdev, NULL);
337 iounmap(wdev->base);
338
339err_ioremap:
340 wdev->base = NULL;
b3112180
FB
341 kfree(wdev);
342
343err_kzalloc:
b782a563 344 release_mem_region(res->start, resource_size(res));
b3112180
FB
345
346err_busy:
347err_get_resource:
348
7768a13c
KS
349 return ret;
350}
351
352static void omap_wdt_shutdown(struct platform_device *pdev)
353{
b3112180 354 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f 355
0503add9 356 if (wdev->omap_wdt_users) {
2817142f 357 omap_wdt_disable(wdev);
0503add9
PW
358 pm_runtime_put_sync(wdev->dev);
359 }
7768a13c
KS
360}
361
0e3912c7 362static int __devexit omap_wdt_remove(struct platform_device *pdev)
7768a13c 363{
b3112180 364 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
2817142f
FB
365 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
366
12c583d8 367 pm_runtime_disable(wdev->dev);
2817142f
FB
368 if (!res)
369 return -ENOENT;
370
371 misc_deregister(&(wdev->omap_wdt_miscdev));
b782a563 372 release_mem_region(res->start, resource_size(res));
2817142f 373 platform_set_drvdata(pdev, NULL);
b3112180 374
9f69e3b0
FB
375 iounmap(wdev->base);
376
2817142f
FB
377 kfree(wdev);
378 omap_wdt_dev = NULL;
b3112180 379
7768a13c
KS
380 return 0;
381}
382
383#ifdef CONFIG_PM
384
385/* REVISIT ... not clear this is the best way to handle system suspend; and
386 * it's very inappropriate for selective device suspend (e.g. suspending this
387 * through sysfs rather than by stopping the watchdog daemon). Also, this
388 * may not play well enough with NOWAYOUT...
389 */
390
391static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
392{
b3112180
FB
393 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
394
0503add9 395 if (wdev->omap_wdt_users) {
2817142f 396 omap_wdt_disable(wdev);
0503add9
PW
397 pm_runtime_put_sync(wdev->dev);
398 }
b3112180 399
7768a13c
KS
400 return 0;
401}
402
403static int omap_wdt_resume(struct platform_device *pdev)
404{
b3112180
FB
405 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
406
2817142f 407 if (wdev->omap_wdt_users) {
0503add9 408 pm_runtime_get_sync(wdev->dev);
2817142f
FB
409 omap_wdt_enable(wdev);
410 omap_wdt_ping(wdev);
7768a13c 411 }
b3112180 412
7768a13c
KS
413 return 0;
414}
415
416#else
417#define omap_wdt_suspend NULL
418#define omap_wdt_resume NULL
419#endif
420
e6ca04ea
XJ
421static const struct of_device_id omap_wdt_of_match[] = {
422 { .compatible = "ti,omap3-wdt", },
423 {},
424};
425MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
426
7768a13c
KS
427static struct platform_driver omap_wdt_driver = {
428 .probe = omap_wdt_probe,
0e3912c7 429 .remove = __devexit_p(omap_wdt_remove),
7768a13c
KS
430 .shutdown = omap_wdt_shutdown,
431 .suspend = omap_wdt_suspend,
432 .resume = omap_wdt_resume,
433 .driver = {
434 .owner = THIS_MODULE,
435 .name = "omap_wdt",
e6ca04ea 436 .of_match_table = omap_wdt_of_match,
7768a13c
KS
437 },
438};
439
b8ec6118 440module_platform_driver(omap_wdt_driver);
7768a13c
KS
441
442MODULE_AUTHOR("George G. Davis");
443MODULE_LICENSE("GPL");
444MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
f37d193c 445MODULE_ALIAS("platform:omap_wdt");
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