[deliverable/linux.git] / drivers / watchdog / pnx4008_wdt.c

/*
 * drivers/char/watchdog/pnx4008_wdt.c
 *
 * Watchdog driver for PNX4008 board
 *
 * Authors: Dmitry Chigirev <source@mvista.com>,
 * 	    Vitaly Wool <vitalywool@gmail.com>
 * Based on sa1100 driver,
 * Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
 *
 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
 * the terms of the GNU General Public License version 2. This program
 * is licensed "as is" without any warranty of any kind, whether express
 * or implied.
 */

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/init.h>
#include <linux/bitops.h>
#include <linux/ioport.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/spinlock.h>
#include <linux/uaccess.h>
#include <linux/io.h>
#include <mach/hardware.h>

#define MODULE_NAME "PNX4008-WDT: "

/* WatchDog Timer - Chapter 23 Page 207 */

#define DEFAULT_HEARTBEAT 19
#define MAX_HEARTBEAT     60

/* Watchdog timer register set definition */
#define WDTIM_INT(p)     ((p) + 0x0)
#define WDTIM_CTRL(p)    ((p) + 0x4)
#define WDTIM_COUNTER(p) ((p) + 0x8)
#define WDTIM_MCTRL(p)   ((p) + 0xC)
#define WDTIM_MATCH0(p)  ((p) + 0x10)
#define WDTIM_EMR(p)     ((p) + 0x14)
#define WDTIM_PULSE(p)   ((p) + 0x18)
#define WDTIM_RES(p)     ((p) + 0x1C)

/* WDTIM_INT bit definitions */
#define MATCH_INT      1

/* WDTIM_CTRL bit definitions */
#define COUNT_ENAB     1
#define RESET_COUNT    (1 << 1)
#define DEBUG_EN       (1 << 2)

/* WDTIM_MCTRL bit definitions */
#define MR0_INT        1
#undef  RESET_COUNT0
#define RESET_COUNT0   (1 << 2)
#define STOP_COUNT0    (1 << 2)
#define M_RES1         (1 << 3)
#define M_RES2         (1 << 4)
#define RESFRC1        (1 << 5)
#define RESFRC2        (1 << 6)

/* WDTIM_EMR bit definitions */
#define EXT_MATCH0      1
#define MATCH_OUTPUT_HIGH (2 << 4)	/*a MATCH_CTRL setting */

/* WDTIM_RES bit definitions */
#define WDOG_RESET      1	/* read only */

#define WDOG_COUNTER_RATE 13000000	/*the counter clock is 13 MHz fixed */

static int nowayout = WATCHDOG_NOWAYOUT;
static int heartbeat = DEFAULT_HEARTBEAT;

static DEFINE_SPINLOCK(io_lock);
static unsigned long wdt_status;
#define WDT_IN_USE        0
#define WDT_OK_TO_CLOSE   1
#define WDT_REGION_INITED 2
#define WDT_DEVICE_INITED 3

static unsigned long boot_status;

static struct resource	*wdt_mem;
static void __iomem	*wdt_base;
struct clk		*wdt_clk;

static void wdt_enable(void)
{
	spin_lock(&io_lock);

	if (wdt_clk)
		clk_set_rate(wdt_clk, 1);

	/* stop counter, initiate counter reset */
	__raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
	/*wait for reset to complete. 100% guarantee event */
	while (__raw_readl(WDTIM_COUNTER(wdt_base)))
		cpu_relax();
	/* internal and external reset, stop after that */
	__raw_writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0,
		WDTIM_MCTRL(wdt_base));
	/* configure match output */
	__raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
	/* clear interrupt, just in case */
	__raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
	/* the longest pulse period 65541/(13*10^6) seconds ~ 5 ms. */
	__raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
	__raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
	/*enable counter, stop when debugger active */
	__raw_writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base));

	spin_unlock(&io_lock);
}

static void wdt_disable(void)
{
	spin_lock(&io_lock);

	__raw_writel(0, WDTIM_CTRL(wdt_base));	/*stop counter */
	if (wdt_clk)
		clk_set_rate(wdt_clk, 0);

	spin_unlock(&io_lock);
}

static int pnx4008_wdt_open(struct inode *inode, struct file *file)
{
	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
		return -EBUSY;

	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

	wdt_enable();

	return nonseekable_open(inode, file);
}

static ssize_t pnx4008_wdt_write(struct file *file, const char *data,
					size_t len, loff_t *ppos)
{
	if (len) {
		if (!nowayout) {
			size_t i;

			clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

			for (i = 0; i != len; i++) {
				char c;

				if (get_user(c, data + i))
					return -EFAULT;
				if (c == 'V')
					set_bit(WDT_OK_TO_CLOSE, &wdt_status);
			}
		}
		wdt_enable();
	}

	return len;
}

static const struct watchdog_info ident = {
	.options = WDIOF_CARDRESET | WDIOF_MAGICCLOSE |
	    WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
	.identity = "PNX4008 Watchdog",
};

static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd,
				unsigned long arg)
{
	int ret = -ENOTTY;
	int time;

	switch (cmd) {
	case WDIOC_GETSUPPORT:
		ret = copy_to_user((struct watchdog_info *)arg, &ident,
				   sizeof(ident)) ? -EFAULT : 0;
		break;

	case WDIOC_GETSTATUS:
		ret = put_user(0, (int *)arg);
		break;

	case WDIOC_GETBOOTSTATUS:
		ret = put_user(boot_status, (int *)arg);
		break;

	case WDIOC_KEEPALIVE:
		wdt_enable();
		ret = 0;
		break;

	case WDIOC_SETTIMEOUT:
		ret = get_user(time, (int *)arg);
		if (ret)
			break;

		if (time <= 0 || time > MAX_HEARTBEAT) {
			ret = -EINVAL;
			break;
		}

		heartbeat = time;
		wdt_enable();
		/* Fall through */

	case WDIOC_GETTIMEOUT:
		ret = put_user(heartbeat, (int *)arg);
		break;
	}
	return ret;
}

static int pnx4008_wdt_release(struct inode *inode, struct file *file)
{
	if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
		printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");

	wdt_disable();
	clear_bit(WDT_IN_USE, &wdt_status);
	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);

	return 0;
}

static const struct file_operations pnx4008_wdt_fops = {
	.owner = THIS_MODULE,
	.llseek = no_llseek,
	.write = pnx4008_wdt_write,
	.unlocked_ioctl = pnx4008_wdt_ioctl,
	.open = pnx4008_wdt_open,
	.release = pnx4008_wdt_release,
};

static struct miscdevice pnx4008_wdt_miscdev = {
	.minor = WATCHDOG_MINOR,
	.name = "watchdog",
	.fops = &pnx4008_wdt_fops,
};

static int __devinit pnx4008_wdt_probe(struct platform_device *pdev)
{
	int ret = 0, size;
	struct resource *res;

	if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
		heartbeat = DEFAULT_HEARTBEAT;

	printk(KERN_INFO MODULE_NAME
		"PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (res == NULL) {
		printk(KERN_INFO MODULE_NAME
			"failed to get memory region resouce\n");
		return -ENOENT;
	}

	size = resource_size(res);
	wdt_mem = request_mem_region(res->start, size, pdev->name);

	if (wdt_mem == NULL) {
		printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
		return -ENOENT;
	}
	wdt_base = (void __iomem *)IO_ADDRESS(res->start);

	wdt_clk = clk_get(&pdev->dev, "wdt_ck");
	if (IS_ERR(wdt_clk)) {
		ret = PTR_ERR(wdt_clk);
		release_resource(wdt_mem);
		kfree(wdt_mem);
		goto out;
	} else
		clk_set_rate(wdt_clk, 1);

	ret = misc_register(&pnx4008_wdt_miscdev);
	if (ret < 0) {
		printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
		release_resource(wdt_mem);
		kfree(wdt_mem);
		clk_set_rate(wdt_clk, 0);
	} else {
		boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
		    WDIOF_CARDRESET : 0;
		wdt_disable();		/*disable for now */
		set_bit(WDT_DEVICE_INITED, &wdt_status);
	}

out:
	return ret;
}

static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
{
	misc_deregister(&pnx4008_wdt_miscdev);
	if (wdt_clk) {
		clk_set_rate(wdt_clk, 0);
		clk_put(wdt_clk);
		wdt_clk = NULL;
	}
	if (wdt_mem) {
		release_resource(wdt_mem);
		kfree(wdt_mem);
		wdt_mem = NULL;
	}
	return 0;
}

static struct platform_driver platform_wdt_driver = {
	.driver = {
		.name = "pnx4008-watchdog",
		.owner	= THIS_MODULE,
	},
	.probe = pnx4008_wdt_probe,
	.remove = __devexit_p(pnx4008_wdt_remove),
};

static int __init pnx4008_wdt_init(void)
{
	return platform_driver_register(&platform_wdt_driver);
}

static void __exit pnx4008_wdt_exit(void)
{
	platform_driver_unregister(&platform_wdt_driver);
}

module_init(pnx4008_wdt_init);
module_exit(pnx4008_wdt_exit);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("PNX4008 Watchdog Driver");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
		 "Watchdog heartbeat period in seconds from 1 to "
		 __MODULE_STRING(MAX_HEARTBEAT) ", default "
		 __MODULE_STRING(DEFAULT_HEARTBEAT));

module_param(nowayout, int, 0);
MODULE_PARM_DESC(nowayout,
		 "Set to 1 to keep watchdog running after device release");

MODULE_LICENSE("GPL");
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
MODULE_ALIAS("platform:pnx4008-watchdog");
Commit	Line	Data
9325fa36 VW	1	/*
	2	* drivers/char/watchdog/pnx4008_wdt.c
	3	*
	4	* Watchdog driver for PNX4008 board
	5	*
	6	* Authors: Dmitry Chigirev <source@mvista.com>,
	7	* Vitaly Wool <vitalywool@gmail.com>
	8	* Based on sa1100 driver,
	9	* Copyright (C) 2000 Oleg Drokin <green@crimea.edu>
	10	*
	11	* 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
	12	* the terms of the GNU General Public License version 2. This program
	13	* is licensed "as is" without any warranty of any kind, whether express
	14	* or implied.
	15	*/
	16
9325fa36 VW	17	#include <linux/module.h>
	18	#include <linux/moduleparam.h>
	19	#include <linux/types.h>
	20	#include <linux/kernel.h>
	21	#include <linux/fs.h>
	22	#include <linux/miscdevice.h>
	23	#include <linux/watchdog.h>
	24	#include <linux/init.h>
	25	#include <linux/bitops.h>
	26	#include <linux/ioport.h>
	27	#include <linux/device.h>
	28	#include <linux/platform_device.h>
	29	#include <linux/clk.h>
99d2853a	30	#include <linux/spinlock.h>
84ca995c AC	31	#include <linux/uaccess.h>
84ca995c AC	32	#include <linux/io.h>
a09e64fb	33	#include <mach/hardware.h>
9325fa36 VW	34
	35	#define MODULE_NAME "PNX4008-WDT: "
	36
	37	/* WatchDog Timer - Chapter 23 Page 207 */
	38
	39	#define DEFAULT_HEARTBEAT 19
	40	#define MAX_HEARTBEAT 60
	41
	42	/* Watchdog timer register set definition */
	43	#define WDTIM_INT(p) ((p) + 0x0)
	44	#define WDTIM_CTRL(p) ((p) + 0x4)
	45	#define WDTIM_COUNTER(p) ((p) + 0x8)
	46	#define WDTIM_MCTRL(p) ((p) + 0xC)
	47	#define WDTIM_MATCH0(p) ((p) + 0x10)
	48	#define WDTIM_EMR(p) ((p) + 0x14)
	49	#define WDTIM_PULSE(p) ((p) + 0x18)
	50	#define WDTIM_RES(p) ((p) + 0x1C)
	51
	52	/* WDTIM_INT bit definitions */
	53	#define MATCH_INT 1
	54
	55	/* WDTIM_CTRL bit definitions */
	56	#define COUNT_ENAB 1
143a2e54 WVS	57	#define RESET_COUNT (1 << 1)
143a2e54 WVS	58	#define DEBUG_EN (1 << 2)
9325fa36 VW	59
	60	/* WDTIM_MCTRL bit definitions */
	61	#define MR0_INT 1
	62	#undef RESET_COUNT0
143a2e54 WVS	63	#define RESET_COUNT0 (1 << 2)
	64	#define STOP_COUNT0 (1 << 2)
	65	#define M_RES1 (1 << 3)
	66	#define M_RES2 (1 << 4)
	67	#define RESFRC1 (1 << 5)
	68	#define RESFRC2 (1 << 6)
9325fa36 VW	69
	70	/* WDTIM_EMR bit definitions */
	71	#define EXT_MATCH0 1
143a2e54	72	#define MATCH_OUTPUT_HIGH (2 << 4) /a MATCH_CTRL setting /
9325fa36 VW	73
	74	/* WDTIM_RES bit definitions */
	75	#define WDOG_RESET 1 /* read only */
	76
	77	#define WDOG_COUNTER_RATE 13000000 /the counter clock is 13 MHz fixed /
	78
28981727	79	static int nowayout = WATCHDOG_NOWAYOUT;
9325fa36 VW	80	static int heartbeat = DEFAULT_HEARTBEAT;
9325fa36 VW	81
c7dfd0cc	82	static DEFINE_SPINLOCK(io_lock);
9325fa36 VW	83	static unsigned long wdt_status;
	84	#define WDT_IN_USE 0
	85	#define WDT_OK_TO_CLOSE 1
	86	#define WDT_REGION_INITED 2
	87	#define WDT_DEVICE_INITED 3
	88
	89	static unsigned long boot_status;
	90
	91	static struct resource *wdt_mem;
	92	static void __iomem *wdt_base;
	93	struct clk *wdt_clk;
	94
	95	static void wdt_enable(void)
	96	{
99d2853a WVS	97	spin_lock(&io_lock);
99d2853a WVS	98
9325fa36 VW	99	if (wdt_clk)
	100	clk_set_rate(wdt_clk, 1);
	101
	102	/* stop counter, initiate counter reset */
	103	__raw_writel(RESET_COUNT, WDTIM_CTRL(wdt_base));
	104	/wait for reset to complete. 100% guarantee event /
65a64ec3 VW	105	while (__raw_readl(WDTIM_COUNTER(wdt_base)))
65a64ec3 VW	106	cpu_relax();
9325fa36 VW	107	/* internal and external reset, stop after that */
	108	__raw_writel(M_RES2 \| STOP_COUNT0 \| RESET_COUNT0,
	109	WDTIM_MCTRL(wdt_base));
	110	/* configure match output */
	111	__raw_writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base));
	112	/* clear interrupt, just in case */
	113	__raw_writel(MATCH_INT, WDTIM_INT(wdt_base));
	114	/* the longest pulse period 65541/(1310^6) seconds ~ 5 ms. /
	115	__raw_writel(0xFFFF, WDTIM_PULSE(wdt_base));
	116	__raw_writel(heartbeat * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base));
	117	/enable counter, stop when debugger active /
	118	__raw_writel(COUNT_ENAB \| DEBUG_EN, WDTIM_CTRL(wdt_base));
99d2853a WVS	119
99d2853a WVS	120	spin_unlock(&io_lock);
9325fa36 VW	121	}
	122
	123	static void wdt_disable(void)
	124	{
99d2853a WVS	125	spin_lock(&io_lock);
99d2853a WVS	126
9325fa36 VW	127	__raw_writel(0, WDTIM_CTRL(wdt_base)); /stop counter /
	128	if (wdt_clk)
	129	clk_set_rate(wdt_clk, 0);
99d2853a WVS	130
99d2853a WVS	131	spin_unlock(&io_lock);
9325fa36 VW	132	}
	133
	134	static int pnx4008_wdt_open(struct inode inode, struct file file)
	135	{
	136	if (test_and_set_bit(WDT_IN_USE, &wdt_status))
	137	return -EBUSY;
	138
	139	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	140
	141	wdt_enable();
	142
	143	return nonseekable_open(inode, file);
	144	}
	145
84ca995c AC	146	static ssize_t pnx4008_wdt_write(struct file file, const char data,
84ca995c AC	147	size_t len, loff_t *ppos)
9325fa36	148	{
9325fa36 VW	149	if (len) {
	150	if (!nowayout) {
	151	size_t i;
	152
	153	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	154
	155	for (i = 0; i != len; i++) {
	156	char c;
	157
	158	if (get_user(c, data + i))
	159	return -EFAULT;
	160	if (c == 'V')
	161	set_bit(WDT_OK_TO_CLOSE, &wdt_status);
	162	}
	163	}
	164	wdt_enable();
	165	}
	166
	167	return len;
	168	}
	169
84ca995c	170	static const struct watchdog_info ident = {
9325fa36 VW	171	.options = WDIOF_CARDRESET \| WDIOF_MAGICCLOSE \|
	172	WDIOF_SETTIMEOUT \| WDIOF_KEEPALIVEPING,
	173	.identity = "PNX4008 Watchdog",
	174	};
	175
7275fc8c WVS	176	static long pnx4008_wdt_ioctl(struct file *file, unsigned int cmd,
7275fc8c WVS	177	unsigned long arg)
9325fa36	178	{
f311896a	179	int ret = -ENOTTY;
9325fa36 VW	180	int time;
	181
	182	switch (cmd) {
	183	case WDIOC_GETSUPPORT:
	184	ret = copy_to_user((struct watchdog_info *)arg, &ident,
	185	sizeof(ident)) ? -EFAULT : 0;
	186	break;
	187
	188	case WDIOC_GETSTATUS:
	189	ret = put_user(0, (int *)arg);
	190	break;
	191
	192	case WDIOC_GETBOOTSTATUS:
	193	ret = put_user(boot_status, (int *)arg);
	194	break;
	195
0c06090c WVS	196	case WDIOC_KEEPALIVE:
	197	wdt_enable();
	198	ret = 0;
	199	break;
	200
9325fa36 VW	201	case WDIOC_SETTIMEOUT:
	202	ret = get_user(time, (int *)arg);
	203	if (ret)
	204	break;
	205
	206	if (time <= 0 \|\| time > MAX_HEARTBEAT) {
	207	ret = -EINVAL;
	208	break;
	209	}
	210
	211	heartbeat = time;
	212	wdt_enable();
	213	/* Fall through */
	214
	215	case WDIOC_GETTIMEOUT:
	216	ret = put_user(heartbeat, (int *)arg);
	217	break;
9325fa36 VW	218	}
	219	return ret;
	220	}
	221
	222	static int pnx4008_wdt_release(struct inode inode, struct file file)
	223	{
	224	if (!test_bit(WDT_OK_TO_CLOSE, &wdt_status))
	225	printk(KERN_WARNING "WATCHDOG: Device closed unexpectdly\n");
	226
	227	wdt_disable();
	228	clear_bit(WDT_IN_USE, &wdt_status);
	229	clear_bit(WDT_OK_TO_CLOSE, &wdt_status);
	230
	231	return 0;
	232	}
	233
2b8693c0	234	static const struct file_operations pnx4008_wdt_fops = {
9325fa36 VW	235	.owner = THIS_MODULE,
	236	.llseek = no_llseek,
	237	.write = pnx4008_wdt_write,
84ca995c	238	.unlocked_ioctl = pnx4008_wdt_ioctl,
9325fa36 VW	239	.open = pnx4008_wdt_open,
	240	.release = pnx4008_wdt_release,
	241	};
	242
	243	static struct miscdevice pnx4008_wdt_miscdev = {
	244	.minor = WATCHDOG_MINOR,
	245	.name = "watchdog",
	246	.fops = &pnx4008_wdt_fops,
	247	};
	248
b6bf291f	249	static int __devinit pnx4008_wdt_probe(struct platform_device *pdev)
9325fa36 VW	250	{
	251	int ret = 0, size;
	252	struct resource *res;
	253
	254	if (heartbeat < 1 \|\| heartbeat > MAX_HEARTBEAT)
	255	heartbeat = DEFAULT_HEARTBEAT;
	256
	257	printk(KERN_INFO MODULE_NAME
	258	"PNX4008 Watchdog Timer: heartbeat %d sec\n", heartbeat);
	259
	260	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	261	if (res == NULL) {
	262	printk(KERN_INFO MODULE_NAME
	263	"failed to get memory region resouce\n");
	264	return -ENOENT;
	265	}
	266
b782a563	267	size = resource_size(res);
9325fa36 VW	268	wdt_mem = request_mem_region(res->start, size, pdev->name);
	269
	270	if (wdt_mem == NULL) {
	271	printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
	272	return -ENOENT;
	273	}
	274	wdt_base = (void __iomem *)IO_ADDRESS(res->start);
	275
	276	wdt_clk = clk_get(&pdev->dev, "wdt_ck");
9cd44619 AM	277	if (IS_ERR(wdt_clk)) {
9cd44619 AM	278	ret = PTR_ERR(wdt_clk);
9325fa36 VW	279	release_resource(wdt_mem);
	280	kfree(wdt_mem);
	281	goto out;
	282	} else
	283	clk_set_rate(wdt_clk, 1);
	284
	285	ret = misc_register(&pnx4008_wdt_miscdev);
	286	if (ret < 0) {
	287	printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
	288	release_resource(wdt_mem);
	289	kfree(wdt_mem);
	290	clk_set_rate(wdt_clk, 0);
	291	} else {
	292	boot_status = (__raw_readl(WDTIM_RES(wdt_base)) & WDOG_RESET) ?
	293	WDIOF_CARDRESET : 0;
	294	wdt_disable(); /disable for now /
	295	set_bit(WDT_DEVICE_INITED, &wdt_status);
	296	}
	297
	298	out:
	299	return ret;
	300	}
	301
b6bf291f	302	static int __devexit pnx4008_wdt_remove(struct platform_device *pdev)
9325fa36	303	{
f6764497	304	misc_deregister(&pnx4008_wdt_miscdev);
9325fa36 VW	305	if (wdt_clk) {
	306	clk_set_rate(wdt_clk, 0);
	307	clk_put(wdt_clk);
	308	wdt_clk = NULL;
	309	}
f6764497 WVS	310	if (wdt_mem) {
	311	release_resource(wdt_mem);
	312	kfree(wdt_mem);
	313	wdt_mem = NULL;
	314	}
9325fa36 VW	315	return 0;
	316	}
	317
	318	static struct platform_driver platform_wdt_driver = {
	319	.driver = {
1508c995	320	.name = "pnx4008-watchdog",
f37d193c	321	.owner = THIS_MODULE,
9325fa36 VW	322	},
9325fa36 VW	323	.probe = pnx4008_wdt_probe,
b6bf291f	324	.remove = __devexit_p(pnx4008_wdt_remove),
9325fa36 VW	325	};
	326
	327	static int __init pnx4008_wdt_init(void)
	328	{
	329	return platform_driver_register(&platform_wdt_driver);
	330	}
	331
	332	static void __exit pnx4008_wdt_exit(void)
	333	{
bb0a38d8	334	platform_driver_unregister(&platform_wdt_driver);
9325fa36 VW	335	}
	336
	337	module_init(pnx4008_wdt_init);
	338	module_exit(pnx4008_wdt_exit);
	339
	340	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	341	MODULE_DESCRIPTION("PNX4008 Watchdog Driver");
	342
	343	module_param(heartbeat, int, 0);
	344	MODULE_PARM_DESC(heartbeat,
	345	"Watchdog heartbeat period in seconds from 1 to "
	346	__MODULE_STRING(MAX_HEARTBEAT) ", default "
	347	__MODULE_STRING(DEFAULT_HEARTBEAT));
	348
	349	module_param(nowayout, int, 0);
	350	MODULE_PARM_DESC(nowayout,
	351	"Set to 1 to keep watchdog running after device release");
	352
	353	MODULE_LICENSE("GPL");
	354	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
1508c995	355	MODULE_ALIAS("platform:pnx4008-watchdog");