Commit | Line | Data |
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1da177e4 LT |
1 | /* linux/drivers/char/watchdog/s3c2410_wdt.c |
2 | * | |
3 | * Copyright (c) 2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * S3C2410 Watchdog Timer Support | |
7 | * | |
8 | * Based on, softdog.c by Alan Cox, | |
29fa0586 | 9 | * (c) Copyright 1996 Alan Cox <alan@lxorguk.ukuu.org.uk> |
1da177e4 LT |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
1da177e4 LT |
24 | */ |
25 | ||
26 | #include <linux/module.h> | |
27 | #include <linux/moduleparam.h> | |
1da177e4 LT |
28 | #include <linux/types.h> |
29 | #include <linux/timer.h> | |
30 | #include <linux/miscdevice.h> | |
31 | #include <linux/watchdog.h> | |
32 | #include <linux/fs.h> | |
1da177e4 | 33 | #include <linux/init.h> |
d052d1be | 34 | #include <linux/platform_device.h> |
1da177e4 | 35 | #include <linux/interrupt.h> |
f8ce2547 | 36 | #include <linux/clk.h> |
41dc8b72 AC |
37 | #include <linux/uaccess.h> |
38 | #include <linux/io.h> | |
1da177e4 | 39 | |
a09e64fb | 40 | #include <mach/map.h> |
1da177e4 | 41 | |
b430708a BD |
42 | #undef S3C_VA_WATCHDOG |
43 | #define S3C_VA_WATCHDOG (0) | |
1da177e4 | 44 | |
180ee700 | 45 | #include <plat/regs-watchdog.h> |
1da177e4 LT |
46 | |
47 | #define PFX "s3c2410-wdt: " | |
48 | ||
49 | #define CONFIG_S3C2410_WATCHDOG_ATBOOT (0) | |
50 | #define CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME (15) | |
51 | ||
25ff3780 | 52 | static int nowayout = WATCHDOG_NOWAYOUT; |
1da177e4 LT |
53 | static int tmr_margin = CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME; |
54 | static int tmr_atboot = CONFIG_S3C2410_WATCHDOG_ATBOOT; | |
41dc8b72 AC |
55 | static int soft_noboot; |
56 | static int debug; | |
1da177e4 LT |
57 | |
58 | module_param(tmr_margin, int, 0); | |
59 | module_param(tmr_atboot, int, 0); | |
60 | module_param(nowayout, int, 0); | |
61 | module_param(soft_noboot, int, 0); | |
62 | module_param(debug, int, 0); | |
63 | ||
41dc8b72 AC |
64 | MODULE_PARM_DESC(tmr_margin, "Watchdog tmr_margin in seconds. default=" |
65 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME) ")"); | |
66 | MODULE_PARM_DESC(tmr_atboot, | |
67 | "Watchdog is started at boot time if set to 1, default=" | |
68 | __MODULE_STRING(CONFIG_S3C2410_WATCHDOG_ATBOOT)); | |
69 | MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" | |
70 | __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); | |
1da177e4 | 71 | MODULE_PARM_DESC(soft_noboot, "Watchdog action, set to 1 to ignore reboots, 0 to reboot (default depends on ONLY_TESTING)"); |
1da177e4 LT |
72 | MODULE_PARM_DESC(debug, "Watchdog debug, set to >1 for debug, (default 0)"); |
73 | ||
74 | ||
75 | typedef enum close_state { | |
76 | CLOSE_STATE_NOT, | |
41dc8b72 | 77 | CLOSE_STATE_ALLOW = 0x4021 |
1da177e4 LT |
78 | } close_state_t; |
79 | ||
41dc8b72 | 80 | static unsigned long open_lock; |
e8ef92b8 | 81 | static struct device *wdt_dev; /* platform device attached to */ |
1da177e4 LT |
82 | static struct resource *wdt_mem; |
83 | static struct resource *wdt_irq; | |
84 | static struct clk *wdt_clock; | |
85 | static void __iomem *wdt_base; | |
86 | static unsigned int wdt_count; | |
87 | static close_state_t allow_close; | |
41dc8b72 | 88 | static DEFINE_SPINLOCK(wdt_lock); |
1da177e4 LT |
89 | |
90 | /* watchdog control routines */ | |
91 | ||
92 | #define DBG(msg...) do { \ | |
93 | if (debug) \ | |
94 | printk(KERN_INFO msg); \ | |
41dc8b72 | 95 | } while (0) |
1da177e4 LT |
96 | |
97 | /* functions */ | |
98 | ||
41dc8b72 | 99 | static void s3c2410wdt_keepalive(void) |
1da177e4 | 100 | { |
41dc8b72 | 101 | spin_lock(&wdt_lock); |
1da177e4 | 102 | writel(wdt_count, wdt_base + S3C2410_WTCNT); |
41dc8b72 | 103 | spin_unlock(&wdt_lock); |
1da177e4 LT |
104 | } |
105 | ||
41dc8b72 AC |
106 | static void __s3c2410wdt_stop(void) |
107 | { | |
108 | unsigned long wtcon; | |
109 | ||
110 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
111 | wtcon &= ~(S3C2410_WTCON_ENABLE | S3C2410_WTCON_RSTEN); | |
112 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
113 | } | |
114 | ||
115 | static void s3c2410wdt_stop(void) | |
116 | { | |
117 | spin_lock(&wdt_lock); | |
118 | __s3c2410wdt_stop(); | |
119 | spin_unlock(&wdt_lock); | |
1da177e4 LT |
120 | } |
121 | ||
41dc8b72 | 122 | static void s3c2410wdt_start(void) |
1da177e4 LT |
123 | { |
124 | unsigned long wtcon; | |
125 | ||
41dc8b72 AC |
126 | spin_lock(&wdt_lock); |
127 | ||
128 | __s3c2410wdt_stop(); | |
1da177e4 LT |
129 | |
130 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
131 | wtcon |= S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128; | |
132 | ||
133 | if (soft_noboot) { | |
134 | wtcon |= S3C2410_WTCON_INTEN; | |
135 | wtcon &= ~S3C2410_WTCON_RSTEN; | |
136 | } else { | |
137 | wtcon &= ~S3C2410_WTCON_INTEN; | |
138 | wtcon |= S3C2410_WTCON_RSTEN; | |
139 | } | |
140 | ||
141 | DBG("%s: wdt_count=0x%08x, wtcon=%08lx\n", | |
fa9363c5 | 142 | __func__, wdt_count, wtcon); |
1da177e4 LT |
143 | |
144 | writel(wdt_count, wdt_base + S3C2410_WTDAT); | |
145 | writel(wdt_count, wdt_base + S3C2410_WTCNT); | |
146 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
41dc8b72 | 147 | spin_unlock(&wdt_lock); |
1da177e4 LT |
148 | } |
149 | ||
150 | static int s3c2410wdt_set_heartbeat(int timeout) | |
151 | { | |
152 | unsigned int freq = clk_get_rate(wdt_clock); | |
153 | unsigned int count; | |
154 | unsigned int divisor = 1; | |
155 | unsigned long wtcon; | |
156 | ||
157 | if (timeout < 1) | |
158 | return -EINVAL; | |
159 | ||
160 | freq /= 128; | |
161 | count = timeout * freq; | |
162 | ||
163 | DBG("%s: count=%d, timeout=%d, freq=%d\n", | |
fa9363c5 | 164 | __func__, count, timeout, freq); |
1da177e4 LT |
165 | |
166 | /* if the count is bigger than the watchdog register, | |
167 | then work out what we need to do (and if) we can | |
168 | actually make this value | |
169 | */ | |
170 | ||
171 | if (count >= 0x10000) { | |
172 | for (divisor = 1; divisor <= 0x100; divisor++) { | |
173 | if ((count / divisor) < 0x10000) | |
174 | break; | |
175 | } | |
176 | ||
177 | if ((count / divisor) >= 0x10000) { | |
e8ef92b8 | 178 | dev_err(wdt_dev, "timeout %d too big\n", timeout); |
1da177e4 LT |
179 | return -EINVAL; |
180 | } | |
181 | } | |
182 | ||
183 | tmr_margin = timeout; | |
184 | ||
185 | DBG("%s: timeout=%d, divisor=%d, count=%d (%08x)\n", | |
fa9363c5 | 186 | __func__, timeout, divisor, count, count/divisor); |
1da177e4 LT |
187 | |
188 | count /= divisor; | |
189 | wdt_count = count; | |
190 | ||
191 | /* update the pre-scaler */ | |
192 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
193 | wtcon &= ~S3C2410_WTCON_PRESCALE_MASK; | |
194 | wtcon |= S3C2410_WTCON_PRESCALE(divisor-1); | |
195 | ||
196 | writel(count, wdt_base + S3C2410_WTDAT); | |
197 | writel(wtcon, wdt_base + S3C2410_WTCON); | |
198 | ||
199 | return 0; | |
200 | } | |
201 | ||
202 | /* | |
203 | * /dev/watchdog handling | |
204 | */ | |
205 | ||
206 | static int s3c2410wdt_open(struct inode *inode, struct file *file) | |
207 | { | |
41dc8b72 | 208 | if (test_and_set_bit(0, &open_lock)) |
1da177e4 LT |
209 | return -EBUSY; |
210 | ||
25ff3780 | 211 | if (nowayout) |
1da177e4 | 212 | __module_get(THIS_MODULE); |
25ff3780 BD |
213 | |
214 | allow_close = CLOSE_STATE_NOT; | |
1da177e4 LT |
215 | |
216 | /* start the timer */ | |
217 | s3c2410wdt_start(); | |
218 | return nonseekable_open(inode, file); | |
219 | } | |
220 | ||
221 | static int s3c2410wdt_release(struct inode *inode, struct file *file) | |
222 | { | |
223 | /* | |
224 | * Shut off the timer. | |
225 | * Lock it in if it's a module and we set nowayout | |
226 | */ | |
25ff3780 | 227 | |
41dc8b72 | 228 | if (allow_close == CLOSE_STATE_ALLOW) |
1da177e4 | 229 | s3c2410wdt_stop(); |
41dc8b72 | 230 | else { |
e8ef92b8 | 231 | dev_err(wdt_dev, "Unexpected close, not stopping watchdog\n"); |
1da177e4 LT |
232 | s3c2410wdt_keepalive(); |
233 | } | |
1da177e4 | 234 | allow_close = CLOSE_STATE_NOT; |
41dc8b72 | 235 | clear_bit(0, &open_lock); |
1da177e4 LT |
236 | return 0; |
237 | } | |
238 | ||
239 | static ssize_t s3c2410wdt_write(struct file *file, const char __user *data, | |
240 | size_t len, loff_t *ppos) | |
241 | { | |
242 | /* | |
243 | * Refresh the timer. | |
244 | */ | |
41dc8b72 | 245 | if (len) { |
1da177e4 LT |
246 | if (!nowayout) { |
247 | size_t i; | |
248 | ||
249 | /* In case it was set long ago */ | |
250 | allow_close = CLOSE_STATE_NOT; | |
251 | ||
252 | for (i = 0; i != len; i++) { | |
253 | char c; | |
254 | ||
255 | if (get_user(c, data + i)) | |
256 | return -EFAULT; | |
257 | if (c == 'V') | |
258 | allow_close = CLOSE_STATE_ALLOW; | |
259 | } | |
260 | } | |
1da177e4 LT |
261 | s3c2410wdt_keepalive(); |
262 | } | |
263 | return len; | |
264 | } | |
265 | ||
266 | #define OPTIONS WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | |
267 | ||
41dc8b72 | 268 | static const struct watchdog_info s3c2410_wdt_ident = { |
1da177e4 LT |
269 | .options = OPTIONS, |
270 | .firmware_version = 0, | |
271 | .identity = "S3C2410 Watchdog", | |
272 | }; | |
273 | ||
274 | ||
41dc8b72 AC |
275 | static long s3c2410wdt_ioctl(struct file *file, unsigned int cmd, |
276 | unsigned long arg) | |
1da177e4 LT |
277 | { |
278 | void __user *argp = (void __user *)arg; | |
279 | int __user *p = argp; | |
280 | int new_margin; | |
281 | ||
282 | switch (cmd) { | |
41dc8b72 AC |
283 | case WDIOC_GETSUPPORT: |
284 | return copy_to_user(argp, &s3c2410_wdt_ident, | |
285 | sizeof(s3c2410_wdt_ident)) ? -EFAULT : 0; | |
286 | case WDIOC_GETSTATUS: | |
287 | case WDIOC_GETBOOTSTATUS: | |
288 | return put_user(0, p); | |
289 | case WDIOC_KEEPALIVE: | |
290 | s3c2410wdt_keepalive(); | |
291 | return 0; | |
292 | case WDIOC_SETTIMEOUT: | |
293 | if (get_user(new_margin, p)) | |
294 | return -EFAULT; | |
295 | if (s3c2410wdt_set_heartbeat(new_margin)) | |
296 | return -EINVAL; | |
297 | s3c2410wdt_keepalive(); | |
298 | return put_user(tmr_margin, p); | |
299 | case WDIOC_GETTIMEOUT: | |
300 | return put_user(tmr_margin, p); | |
0c06090c WVS |
301 | default: |
302 | return -ENOTTY; | |
1da177e4 LT |
303 | } |
304 | } | |
305 | ||
1da177e4 LT |
306 | /* kernel interface */ |
307 | ||
62322d25 | 308 | static const struct file_operations s3c2410wdt_fops = { |
1da177e4 LT |
309 | .owner = THIS_MODULE, |
310 | .llseek = no_llseek, | |
311 | .write = s3c2410wdt_write, | |
41dc8b72 | 312 | .unlocked_ioctl = s3c2410wdt_ioctl, |
1da177e4 LT |
313 | .open = s3c2410wdt_open, |
314 | .release = s3c2410wdt_release, | |
315 | }; | |
316 | ||
317 | static struct miscdevice s3c2410wdt_miscdev = { | |
318 | .minor = WATCHDOG_MINOR, | |
319 | .name = "watchdog", | |
320 | .fops = &s3c2410wdt_fops, | |
321 | }; | |
322 | ||
1da177e4 LT |
323 | /* interrupt handler code */ |
324 | ||
7d12e780 | 325 | static irqreturn_t s3c2410wdt_irq(int irqno, void *param) |
1da177e4 | 326 | { |
e8ef92b8 | 327 | dev_info(wdt_dev, "watchdog timer expired (irq)\n"); |
1da177e4 LT |
328 | |
329 | s3c2410wdt_keepalive(); | |
330 | return IRQ_HANDLED; | |
331 | } | |
332 | /* device interface */ | |
333 | ||
3ae5eaec | 334 | static int s3c2410wdt_probe(struct platform_device *pdev) |
1da177e4 | 335 | { |
1da177e4 | 336 | struct resource *res; |
e8ef92b8 | 337 | struct device *dev; |
46b814d6 | 338 | unsigned int wtcon; |
1da177e4 LT |
339 | int started = 0; |
340 | int ret; | |
341 | int size; | |
342 | ||
fa9363c5 | 343 | DBG("%s: probe=%p\n", __func__, pdev); |
1da177e4 | 344 | |
e8ef92b8 BD |
345 | dev = &pdev->dev; |
346 | wdt_dev = &pdev->dev; | |
347 | ||
1da177e4 LT |
348 | /* get the memory region for the watchdog timer */ |
349 | ||
350 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
351 | if (res == NULL) { | |
e8ef92b8 | 352 | dev_err(dev, "no memory resource specified\n"); |
1da177e4 LT |
353 | return -ENOENT; |
354 | } | |
355 | ||
0e65fb29 | 356 | size = (res->end - res->start) + 1; |
1da177e4 LT |
357 | wdt_mem = request_mem_region(res->start, size, pdev->name); |
358 | if (wdt_mem == NULL) { | |
e8ef92b8 | 359 | dev_err(dev, "failed to get memory region\n"); |
0b6dd8a6 BD |
360 | ret = -ENOENT; |
361 | goto err_req; | |
1da177e4 LT |
362 | } |
363 | ||
364 | wdt_base = ioremap(res->start, size); | |
b4253f8f | 365 | if (wdt_base == NULL) { |
e8ef92b8 | 366 | dev_err(dev, "failed to ioremap() region\n"); |
0b6dd8a6 BD |
367 | ret = -EINVAL; |
368 | goto err_req; | |
1da177e4 LT |
369 | } |
370 | ||
371 | DBG("probe: mapped wdt_base=%p\n", wdt_base); | |
372 | ||
62be0741 AP |
373 | wdt_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
374 | if (wdt_irq == NULL) { | |
e8ef92b8 | 375 | dev_err(dev, "no irq resource specified\n"); |
0b6dd8a6 BD |
376 | ret = -ENOENT; |
377 | goto err_map; | |
1da177e4 LT |
378 | } |
379 | ||
62be0741 | 380 | ret = request_irq(wdt_irq->start, s3c2410wdt_irq, 0, pdev->name, pdev); |
1da177e4 | 381 | if (ret != 0) { |
e8ef92b8 | 382 | dev_err(dev, "failed to install irq (%d)\n", ret); |
0b6dd8a6 | 383 | goto err_map; |
1da177e4 LT |
384 | } |
385 | ||
3ae5eaec | 386 | wdt_clock = clk_get(&pdev->dev, "watchdog"); |
9cd44619 | 387 | if (IS_ERR(wdt_clock)) { |
e8ef92b8 | 388 | dev_err(dev, "failed to find watchdog clock source\n"); |
9cd44619 | 389 | ret = PTR_ERR(wdt_clock); |
0b6dd8a6 | 390 | goto err_irq; |
1da177e4 LT |
391 | } |
392 | ||
1da177e4 LT |
393 | clk_enable(wdt_clock); |
394 | ||
395 | /* see if we can actually set the requested timer margin, and if | |
396 | * not, try the default value */ | |
397 | ||
398 | if (s3c2410wdt_set_heartbeat(tmr_margin)) { | |
41dc8b72 AC |
399 | started = s3c2410wdt_set_heartbeat( |
400 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); | |
1da177e4 | 401 | |
41dc8b72 AC |
402 | if (started == 0) |
403 | dev_info(dev, | |
404 | "tmr_margin value out of range, default %d used\n", | |
1da177e4 | 405 | CONFIG_S3C2410_WATCHDOG_DEFAULT_TIME); |
41dc8b72 | 406 | else |
e8ef92b8 | 407 | dev_info(dev, "default timer value is out of range, cannot start\n"); |
1da177e4 LT |
408 | } |
409 | ||
1da177e4 LT |
410 | ret = misc_register(&s3c2410wdt_miscdev); |
411 | if (ret) { | |
e8ef92b8 | 412 | dev_err(dev, "cannot register miscdev on minor=%d (%d)\n", |
1da177e4 | 413 | WATCHDOG_MINOR, ret); |
0b6dd8a6 | 414 | goto err_clk; |
1da177e4 LT |
415 | } |
416 | ||
417 | if (tmr_atboot && started == 0) { | |
e8ef92b8 | 418 | dev_info(dev, "starting watchdog timer\n"); |
1da177e4 | 419 | s3c2410wdt_start(); |
655516c8 BD |
420 | } else if (!tmr_atboot) { |
421 | /* if we're not enabling the watchdog, then ensure it is | |
422 | * disabled if it has been left running from the bootloader | |
423 | * or other source */ | |
424 | ||
425 | s3c2410wdt_stop(); | |
1da177e4 LT |
426 | } |
427 | ||
46b814d6 BD |
428 | /* print out a statement of readiness */ |
429 | ||
430 | wtcon = readl(wdt_base + S3C2410_WTCON); | |
431 | ||
e8ef92b8 | 432 | dev_info(dev, "watchdog %sactive, reset %sabled, irq %sabled\n", |
46b814d6 BD |
433 | (wtcon & S3C2410_WTCON_ENABLE) ? "" : "in", |
434 | (wtcon & S3C2410_WTCON_RSTEN) ? "" : "dis", | |
435 | (wtcon & S3C2410_WTCON_INTEN) ? "" : "en"); | |
41dc8b72 | 436 | |
1da177e4 | 437 | return 0; |
0b6dd8a6 BD |
438 | |
439 | err_clk: | |
440 | clk_disable(wdt_clock); | |
441 | clk_put(wdt_clock); | |
442 | ||
443 | err_irq: | |
444 | free_irq(wdt_irq->start, pdev); | |
445 | ||
446 | err_map: | |
447 | iounmap(wdt_base); | |
448 | ||
449 | err_req: | |
450 | release_resource(wdt_mem); | |
451 | kfree(wdt_mem); | |
452 | ||
453 | return ret; | |
1da177e4 LT |
454 | } |
455 | ||
3ae5eaec | 456 | static int s3c2410wdt_remove(struct platform_device *dev) |
1da177e4 | 457 | { |
0b6dd8a6 BD |
458 | release_resource(wdt_mem); |
459 | kfree(wdt_mem); | |
460 | wdt_mem = NULL; | |
1da177e4 | 461 | |
0b6dd8a6 BD |
462 | free_irq(wdt_irq->start, dev); |
463 | wdt_irq = NULL; | |
1da177e4 | 464 | |
0b6dd8a6 BD |
465 | clk_disable(wdt_clock); |
466 | clk_put(wdt_clock); | |
467 | wdt_clock = NULL; | |
1da177e4 | 468 | |
e34477e9 | 469 | iounmap(wdt_base); |
1da177e4 LT |
470 | misc_deregister(&s3c2410wdt_miscdev); |
471 | return 0; | |
472 | } | |
473 | ||
3ae5eaec | 474 | static void s3c2410wdt_shutdown(struct platform_device *dev) |
94f1e9f3 | 475 | { |
41dc8b72 | 476 | s3c2410wdt_stop(); |
94f1e9f3 BD |
477 | } |
478 | ||
af4bb822 BD |
479 | #ifdef CONFIG_PM |
480 | ||
481 | static unsigned long wtcon_save; | |
482 | static unsigned long wtdat_save; | |
483 | ||
3ae5eaec | 484 | static int s3c2410wdt_suspend(struct platform_device *dev, pm_message_t state) |
af4bb822 | 485 | { |
9480e307 RK |
486 | /* Save watchdog state, and turn it off. */ |
487 | wtcon_save = readl(wdt_base + S3C2410_WTCON); | |
488 | wtdat_save = readl(wdt_base + S3C2410_WTDAT); | |
af4bb822 | 489 | |
9480e307 RK |
490 | /* Note that WTCNT doesn't need to be saved. */ |
491 | s3c2410wdt_stop(); | |
af4bb822 BD |
492 | |
493 | return 0; | |
494 | } | |
495 | ||
3ae5eaec | 496 | static int s3c2410wdt_resume(struct platform_device *dev) |
af4bb822 | 497 | { |
9480e307 | 498 | /* Restore watchdog state. */ |
af4bb822 | 499 | |
9480e307 RK |
500 | writel(wtdat_save, wdt_base + S3C2410_WTDAT); |
501 | writel(wtdat_save, wdt_base + S3C2410_WTCNT); /* Reset count */ | |
502 | writel(wtcon_save, wdt_base + S3C2410_WTCON); | |
af4bb822 | 503 | |
9480e307 RK |
504 | printk(KERN_INFO PFX "watchdog %sabled\n", |
505 | (wtcon_save & S3C2410_WTCON_ENABLE) ? "en" : "dis"); | |
af4bb822 BD |
506 | |
507 | return 0; | |
508 | } | |
509 | ||
510 | #else | |
511 | #define s3c2410wdt_suspend NULL | |
512 | #define s3c2410wdt_resume NULL | |
513 | #endif /* CONFIG_PM */ | |
514 | ||
515 | ||
3ae5eaec | 516 | static struct platform_driver s3c2410wdt_driver = { |
1da177e4 LT |
517 | .probe = s3c2410wdt_probe, |
518 | .remove = s3c2410wdt_remove, | |
94f1e9f3 | 519 | .shutdown = s3c2410wdt_shutdown, |
af4bb822 BD |
520 | .suspend = s3c2410wdt_suspend, |
521 | .resume = s3c2410wdt_resume, | |
3ae5eaec RK |
522 | .driver = { |
523 | .owner = THIS_MODULE, | |
524 | .name = "s3c2410-wdt", | |
525 | }, | |
1da177e4 LT |
526 | }; |
527 | ||
528 | ||
41dc8b72 AC |
529 | static char banner[] __initdata = |
530 | KERN_INFO "S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics\n"; | |
1da177e4 LT |
531 | |
532 | static int __init watchdog_init(void) | |
533 | { | |
534 | printk(banner); | |
3ae5eaec | 535 | return platform_driver_register(&s3c2410wdt_driver); |
1da177e4 LT |
536 | } |
537 | ||
538 | static void __exit watchdog_exit(void) | |
539 | { | |
3ae5eaec | 540 | platform_driver_unregister(&s3c2410wdt_driver); |
1da177e4 LT |
541 | } |
542 | ||
543 | module_init(watchdog_init); | |
544 | module_exit(watchdog_exit); | |
545 | ||
af4bb822 BD |
546 | MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, " |
547 | "Dimitry Andric <dimitry.andric@tomtom.com>"); | |
1da177e4 LT |
548 | MODULE_DESCRIPTION("S3C2410 Watchdog Device Driver"); |
549 | MODULE_LICENSE("GPL"); | |
550 | MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR); | |
f37d193c | 551 | MODULE_ALIAS("platform:s3c2410-wdt"); |