[deliverable/linux.git] / drivers / watchdog / shwdt.c

/*
 * drivers/watchdog/shwdt.c
 *
 * Watchdog driver for integrated watchdog in the SuperH processors.
 *
 * Copyright (C) 2001 - 2012  Paul Mundt <lethal@linux-sh.org>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
 *     Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
 *
 * 19-Apr-2002 Rob Radez <rob@osinvestor.com>
 *     Added expect close support, made emulated timeout runtime changeable
 *     general cleanups, add some ioctls
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/spinlock.h>
#include <linux/miscdevice.h>
#include <linux/watchdog.h>
#include <linux/pm_runtime.h>
#include <linux/fs.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <asm/watchdog.h>

#define DRV_NAME "sh-wdt"

/*
 * Default clock division ratio is 5.25 msecs. For an additional table of
 * values, consult the asm-sh/watchdog.h. Overload this at module load
 * time.
 *
 * In order for this to work reliably we need to have HZ set to 1000 or
 * something quite higher than 100 (or we need a proper high-res timer
 * implementation that will deal with this properly), otherwise the 10ms
 * resolution of a jiffy is enough to trigger the overflow. For things like
 * the SH-4 and SH-5, this isn't necessarily that big of a problem, though
 * for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
 * necssary.
 *
 * As a result of this timing problem, the only modes that are particularly
 * feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
 * overflow periods respectively.
 *
 * Also, since we can't really expect userspace to be responsive enough
 * before the overflow happens, we maintain two separate timers .. One in
 * the kernel for clearing out WOVF every 2ms or so (again, this depends on
 * HZ == 1000), and another for monitoring userspace writes to the WDT device.
 *
 * As such, we currently use a configurable heartbeat interval which defaults
 * to 30s. In this case, the userspace daemon is only responsible for periodic
 * writes to the device before the next heartbeat is scheduled. If the daemon
 * misses its deadline, the kernel timer will allow the WDT to overflow.
 */
static int clock_division_ratio = WTCSR_CKS_4096;
#define next_ping_period(cks)	(jiffies + msecs_to_jiffies(cks - 4))

#define WATCHDOG_HEARTBEAT 30			/* 30 sec default heartbeat */
static int heartbeat = WATCHDOG_HEARTBEAT;	/* in seconds */
static bool nowayout = WATCHDOG_NOWAYOUT;
static unsigned long next_heartbeat;

struct sh_wdt {
	void __iomem		*base;
	struct device		*dev;
	struct clk		*clk;
	spinlock_t		lock;

	struct timer_list	timer;
};

static int sh_wdt_start(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;
	u8 csr;

	pm_runtime_get_sync(wdt->dev);

	spin_lock_irqsave(&wdt->lock, flags);

	next_heartbeat = jiffies + (heartbeat * HZ);
	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));

	csr = sh_wdt_read_csr();
	csr |= WTCSR_WT | clock_division_ratio;
	sh_wdt_write_csr(csr);

	sh_wdt_write_cnt(0);

	/*
	 * These processors have a bit of an inconsistent initialization
	 * process.. starting with SH-3, RSTS was moved to WTCSR, and the
	 * RSTCSR register was removed.
	 *
	 * On the SH-2 however, in addition with bits being in different
	 * locations, we must deal with RSTCSR outright..
	 */
	csr = sh_wdt_read_csr();
	csr |= WTCSR_TME;
	csr &= ~WTCSR_RSTS;
	sh_wdt_write_csr(csr);

#ifdef CONFIG_CPU_SH2
	csr = sh_wdt_read_rstcsr();
	csr &= ~RSTCSR_RSTS;
	sh_wdt_write_rstcsr(csr);
#endif
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static int sh_wdt_stop(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;
	u8 csr;

	spin_lock_irqsave(&wdt->lock, flags);

	del_timer(&wdt->timer);

	csr = sh_wdt_read_csr();
	csr &= ~WTCSR_TME;
	sh_wdt_write_csr(csr);

	spin_unlock_irqrestore(&wdt->lock, flags);

	pm_runtime_put_sync(wdt->dev);

	return 0;
}

static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;

	spin_lock_irqsave(&wdt->lock, flags);
	next_heartbeat = jiffies + (heartbeat * HZ);
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
{
	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
	unsigned long flags;

	if (unlikely(t < 1 || t > 3600)) /* arbitrary upper limit */
		return -EINVAL;

	spin_lock_irqsave(&wdt->lock, flags);
	heartbeat = t;
	wdt_dev->timeout = t;
	spin_unlock_irqrestore(&wdt->lock, flags);

	return 0;
}

static void sh_wdt_ping(unsigned long data)
{
	struct sh_wdt *wdt = (struct sh_wdt *)data;
	unsigned long flags;

	spin_lock_irqsave(&wdt->lock, flags);
	if (time_before(jiffies, next_heartbeat)) {
		u8 csr;

		csr = sh_wdt_read_csr();
		csr &= ~WTCSR_IOVF;
		sh_wdt_write_csr(csr);

		sh_wdt_write_cnt(0);

		mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
	} else
		dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
		         "the watchdog\n");
	spin_unlock_irqrestore(&wdt->lock, flags);
}

static const struct watchdog_info sh_wdt_info = {
	.options		= WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT |
				  WDIOF_MAGICCLOSE,
	.firmware_version	= 1,
	.identity		= "SH WDT",
};

static const struct watchdog_ops sh_wdt_ops = {
	.owner		= THIS_MODULE,
	.start		= sh_wdt_start,
	.stop		= sh_wdt_stop,
	.ping		= sh_wdt_keepalive,
	.set_timeout	= sh_wdt_set_heartbeat,
};

static struct watchdog_device sh_wdt_dev = {
	.info	= &sh_wdt_info,
	.ops	= &sh_wdt_ops,
};

static int __devinit sh_wdt_probe(struct platform_device *pdev)
{
	struct sh_wdt *wdt;
	struct resource *res;
	int rc;

	/*
	 * As this driver only covers the global watchdog case, reject
	 * any attempts to register per-CPU watchdogs.
	 */
	if (pdev->id != -1)
		return -EINVAL;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(!res))
		return -EINVAL;

	wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
	if (unlikely(!wdt))
		return -ENOMEM;

	wdt->dev = &pdev->dev;

	wdt->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(wdt->clk)) {
		/*
		 * Clock framework support is optional, continue on
		 * anyways if we don't find a matching clock.
		 */
		wdt->clk = NULL;
	}

	clk_enable(wdt->clk);

	wdt->base = devm_request_and_ioremap(wdt->dev, res);
	if (unlikely(!wdt->base)) {
		rc = -EADDRNOTAVAIL;
		goto out_disable;
	}

	watchdog_set_nowayout(&sh_wdt_dev, nowayout);
	watchdog_set_drvdata(&sh_wdt_dev, wdt);

	spin_lock_init(&wdt->lock);

	rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
	if (unlikely(rc)) {
		/* Default timeout if invalid */
		sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);

		dev_warn(&pdev->dev,
			 "heartbeat value must be 1<=x<=3600, using %d\n",
			 sh_wdt_dev.timeout);
	}

	dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
		 sh_wdt_dev.timeout, nowayout);

	rc = watchdog_register_device(&sh_wdt_dev);
	if (unlikely(rc)) {
		dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
		goto out_disable;
	}

	init_timer(&wdt->timer);
	wdt->timer.function	= sh_wdt_ping;
	wdt->timer.data		= (unsigned long)wdt;
	wdt->timer.expires	= next_ping_period(clock_division_ratio);

	platform_set_drvdata(pdev, wdt);

	dev_info(&pdev->dev, "initialized.\n");

	pm_runtime_enable(&pdev->dev);

	return 0;

out_disable:
	clk_disable(wdt->clk);
	clk_put(wdt->clk);

	return rc;
}

static int __devexit sh_wdt_remove(struct platform_device *pdev)
{
	struct sh_wdt *wdt = platform_get_drvdata(pdev);

	platform_set_drvdata(pdev, NULL);

	watchdog_unregister_device(&sh_wdt_dev);

	pm_runtime_disable(&pdev->dev);
	clk_disable(wdt->clk);
	clk_put(wdt->clk);

	return 0;
}

static void sh_wdt_shutdown(struct platform_device *pdev)
{
	sh_wdt_stop(&sh_wdt_dev);
}

static struct platform_driver sh_wdt_driver = {
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},

	.probe		= sh_wdt_probe,
	.remove		= __devexit_p(sh_wdt_remove),
	.shutdown	= sh_wdt_shutdown,
};

static int __init sh_wdt_init(void)
{
	if (unlikely(clock_division_ratio < 0x5 ||
		     clock_division_ratio > 0x7)) {
		clock_division_ratio = WTCSR_CKS_4096;

		pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
			clock_division_ratio);
	}

	return platform_driver_register(&sh_wdt_driver);
}

static void __exit sh_wdt_exit(void)
{
	platform_driver_unregister(&sh_wdt_driver);
}
module_init(sh_wdt_init);
module_exit(sh_wdt_exit);

MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
MODULE_DESCRIPTION("SuperH watchdog driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);

module_param(clock_division_ratio, int, 0);
MODULE_PARM_DESC(clock_division_ratio,
	"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
	"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");

module_param(heartbeat, int, 0);
MODULE_PARM_DESC(heartbeat,
	"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
				__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");

module_param(nowayout, bool, 0);
MODULE_PARM_DESC(nowayout,
	"Watchdog cannot be stopped once started (default="
				__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
Commit	Line	Data
1da177e4	1	/*
b1fa888e	2	* drivers/watchdog/shwdt.c
1da177e4 LT	3	*
	4	* Watchdog driver for integrated watchdog in the SuperH processors.
	5	*
40968126	6	* Copyright (C) 2001 - 2012 Paul Mundt <lethal@linux-sh.org>
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*
	13	* 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
	14	* Added nowayout module option to override CONFIG_WATCHDOG_NOWAYOUT
	15	*
	16	* 19-Apr-2002 Rob Radez <rob@osinvestor.com>
	17	* Added expect close support, made emulated timeout runtime changeable
	18	* general cleanups, add some ioctls
	19	*/
27c766aa JP	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
1da177e4 LT	23	#include <linux/module.h>
1da177e4 LT	24	#include <linux/moduleparam.h>
8f5585ec	25	#include <linux/platform_device.h>
1da177e4 LT	26	#include <linux/init.h>
1da177e4 LT	27	#include <linux/types.h>
f9fb360c	28	#include <linux/spinlock.h>
1da177e4 LT	29	#include <linux/miscdevice.h>
1da177e4 LT	30	#include <linux/watchdog.h>
8c013d96	31	#include <linux/pm_runtime.h>
1da177e4	32	#include <linux/fs.h>
f118420b	33	#include <linux/mm.h>
8f5585ec	34	#include <linux/slab.h>
70b814ec	35	#include <linux/io.h>
9ea64046	36	#include <linux/clk.h>
58cf4198	37	#include <asm/watchdog.h>
1da177e4	38
8f5585ec	39	#define DRV_NAME "sh-wdt"
1da177e4 LT	40
	41	/*
	42	* Default clock division ratio is 5.25 msecs. For an additional table of
	43	* values, consult the asm-sh/watchdog.h. Overload this at module load
	44	* time.
	45	*
	46	* In order for this to work reliably we need to have HZ set to 1000 or
	47	* something quite higher than 100 (or we need a proper high-res timer
	48	* implementation that will deal with this properly), otherwise the 10ms
	49	* resolution of a jiffy is enough to trigger the overflow. For things like
	50	* the SH-4 and SH-5, this isn't necessarily that big of a problem, though
	51	* for the SH-2 and SH-3, this isn't recommended unless the WDT is absolutely
	52	* necssary.
	53	*
	54	* As a result of this timing problem, the only modes that are particularly
25985edc	55	* feasible are the 4096 and the 2048 divisors, which yield 5.25 and 2.62ms
1da177e4 LT	56	* overflow periods respectively.
	57	*
	58	* Also, since we can't really expect userspace to be responsive enough
ee0fc097	59	* before the overflow happens, we maintain two separate timers .. One in
1da177e4 LT	60	* the kernel for clearing out WOVF every 2ms or so (again, this depends on
	61	* HZ == 1000), and another for monitoring userspace writes to the WDT device.
	62	*
	63	* As such, we currently use a configurable heartbeat interval which defaults
	64	* to 30s. In this case, the userspace daemon is only responsible for periodic
	65	* writes to the device before the next heartbeat is scheduled. If the daemon
	66	* misses its deadline, the kernel timer will allow the WDT to overflow.
	67	*/
	68	static int clock_division_ratio = WTCSR_CKS_4096;
bea19066	69	#define next_ping_period(cks) (jiffies + msecs_to_jiffies(cks - 4))
1da177e4	70
1da177e4 LT	71	#define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
1da177e4 LT	72	static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
86a1e189	73	static bool nowayout = WATCHDOG_NOWAYOUT;
8f5585ec PM	74	static unsigned long next_heartbeat;
	75
	76	struct sh_wdt {
	77	void __iomem *base;
	78	struct device *dev;
9ea64046	79	struct clk *clk;
f9fb360c	80	spinlock_t lock;
1da177e4	81
8f5585ec	82	struct timer_list timer;
8f5585ec PM	83	};
8f5585ec PM	84
1950f499	85	static int sh_wdt_start(struct watchdog_device *wdt_dev)
1da177e4	86	{
1950f499	87	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec	88	unsigned long flags;
8f5585ec	89	u8 csr;
70b814ec	90
8c013d96 PM	91	pm_runtime_get_sync(wdt->dev);
8c013d96 PM	92
f9fb360c	93	spin_lock_irqsave(&wdt->lock, flags);
1da177e4 LT	94
1da177e4 LT	95	next_heartbeat = jiffies + (heartbeat * HZ);
8f5585ec	96	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
1da177e4 LT	97
	98	csr = sh_wdt_read_csr();
	99	csr \|= WTCSR_WT \| clock_division_ratio;
	100	sh_wdt_write_csr(csr);
	101
	102	sh_wdt_write_cnt(0);
	103
	104	/*
	105	* These processors have a bit of an inconsistent initialization
	106	* process.. starting with SH-3, RSTS was moved to WTCSR, and the
	107	* RSTCSR register was removed.
	108	*
	109	* On the SH-2 however, in addition with bits being in different
	110	* locations, we must deal with RSTCSR outright..
	111	*/
	112	csr = sh_wdt_read_csr();
	113	csr \|= WTCSR_TME;
	114	csr &= ~WTCSR_RSTS;
	115	sh_wdt_write_csr(csr);
	116
	117	#ifdef CONFIG_CPU_SH2
1da177e4 LT	118	csr = sh_wdt_read_rstcsr();
	119	csr &= ~RSTCSR_RSTS;
	120	sh_wdt_write_rstcsr(csr);
	121	#endif
f9fb360c	122	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499 PM	123
1950f499 PM	124	return 0;
1da177e4 LT	125	}
1da177e4 LT	126
1950f499	127	static int sh_wdt_stop(struct watchdog_device *wdt_dev)
1da177e4	128	{
1950f499	129	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec	130	unsigned long flags;
8f5585ec	131	u8 csr;
70b814ec	132
f9fb360c	133	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	134
8f5585ec	135	del_timer(&wdt->timer);
1da177e4 LT	136
	137	csr = sh_wdt_read_csr();
	138	csr &= ~WTCSR_TME;
	139	sh_wdt_write_csr(csr);
8f5585ec	140
f9fb360c	141	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499	142
8c013d96 PM	143	pm_runtime_put_sync(wdt->dev);
8c013d96 PM	144
1950f499	145	return 0;
1da177e4 LT	146	}
1da177e4 LT	147
1950f499	148	static int sh_wdt_keepalive(struct watchdog_device *wdt_dev)
1da177e4	149	{
f9fb360c	150	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec AC	151	unsigned long flags;
70b814ec AC	152
f9fb360c	153	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	154	next_heartbeat = jiffies + (heartbeat * HZ);
f9fb360c	155	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499 PM	156
1950f499 PM	157	return 0;
1da177e4 LT	158	}
1da177e4 LT	159
1950f499	160	static int sh_wdt_set_heartbeat(struct watchdog_device *wdt_dev, unsigned t)
1da177e4	161	{
f9fb360c	162	struct sh_wdt *wdt = watchdog_get_drvdata(wdt_dev);
70b814ec AC	163	unsigned long flags;
	164
	165	if (unlikely(t < 1 \|\| t > 3600)) /* arbitrary upper limit */
1da177e4 LT	166	return -EINVAL;
1da177e4 LT	167
f9fb360c	168	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	169	heartbeat = t;
1950f499	170	wdt_dev->timeout = t;
f9fb360c	171	spin_unlock_irqrestore(&wdt->lock, flags);
1950f499	172
1da177e4 LT	173	return 0;
	174	}
	175
1da177e4 LT	176	static void sh_wdt_ping(unsigned long data)
1da177e4 LT	177	{
8f5585ec	178	struct sh_wdt wdt = (struct sh_wdt )data;
70b814ec AC	179	unsigned long flags;
70b814ec AC	180
f9fb360c	181	spin_lock_irqsave(&wdt->lock, flags);
1da177e4	182	if (time_before(jiffies, next_heartbeat)) {
8f5585ec	183	u8 csr;
1da177e4 LT	184
	185	csr = sh_wdt_read_csr();
	186	csr &= ~WTCSR_IOVF;
	187	sh_wdt_write_csr(csr);
	188
	189	sh_wdt_write_cnt(0);
	190
8f5585ec	191	mod_timer(&wdt->timer, next_ping_period(clock_division_ratio));
e4c2cfee	192	} else
8f5585ec PM	193	dev_warn(wdt->dev, "Heartbeat lost! Will not ping "
8f5585ec PM	194	"the watchdog\n");
f9fb360c	195	spin_unlock_irqrestore(&wdt->lock, flags);
1da177e4 LT	196	}
1da177e4 LT	197
70b814ec	198	static const struct watchdog_info sh_wdt_info = {
e4c2cfee PM	199	.options = WDIOF_KEEPALIVEPING \| WDIOF_SETTIMEOUT \|
e4c2cfee PM	200	WDIOF_MAGICCLOSE,
1da177e4 LT	201	.firmware_version = 1,
	202	.identity = "SH WDT",
	203	};
	204
1950f499 PM	205	static const struct watchdog_ops sh_wdt_ops = {
	206	.owner = THIS_MODULE,
	207	.start = sh_wdt_start,
	208	.stop = sh_wdt_stop,
	209	.ping = sh_wdt_keepalive,
	210	.set_timeout = sh_wdt_set_heartbeat,
	211	};
	212
	213	static struct watchdog_device sh_wdt_dev = {
	214	.info = &sh_wdt_info,
	215	.ops = &sh_wdt_ops,
1da177e4 LT	216	};
1da177e4 LT	217
8f5585ec	218	static int __devinit sh_wdt_probe(struct platform_device *pdev)
1da177e4	219	{
8f5585ec PM	220	struct sh_wdt *wdt;
8f5585ec PM	221	struct resource *res;
1da177e4 LT	222	int rc;
1da177e4 LT	223
8f5585ec PM	224	/*
	225	* As this driver only covers the global watchdog case, reject
	226	* any attempts to register per-CPU watchdogs.
	227	*/
	228	if (pdev->id != -1)
	229	return -EINVAL;
	230
	231	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	232	if (unlikely(!res))
	233	return -EINVAL;
	234
8f5585ec	235	wdt = devm_kzalloc(&pdev->dev, sizeof(struct sh_wdt), GFP_KERNEL);
9ea64046 PM	236	if (unlikely(!wdt))
9ea64046 PM	237	return -ENOMEM;
1da177e4	238
8f5585ec PM	239	wdt->dev = &pdev->dev;
8f5585ec PM	240
9ea64046 PM	241	wdt->clk = clk_get(&pdev->dev, NULL);
	242	if (IS_ERR(wdt->clk)) {
	243	/*
	244	* Clock framework support is optional, continue on
	245	* anyways if we don't find a matching clock.
	246	*/
	247	wdt->clk = NULL;
	248	}
f9fb360c	249
9ea64046 PM	250	clk_enable(wdt->clk);
	251
	252	wdt->base = devm_request_and_ioremap(wdt->dev, res);
8f5585ec	253	if (unlikely(!wdt->base)) {
9ea64046 PM	254	rc = -EADDRNOTAVAIL;
9ea64046 PM	255	goto out_disable;
1da177e4 LT	256	}
1da177e4 LT	257
9ea64046 PM	258	watchdog_set_nowayout(&sh_wdt_dev, nowayout);
	259	watchdog_set_drvdata(&sh_wdt_dev, wdt);
	260
f9fb360c PM	261	spin_lock_init(&wdt->lock);
f9fb360c PM	262
1950f499 PM	263	rc = sh_wdt_set_heartbeat(&sh_wdt_dev, heartbeat);
	264	if (unlikely(rc)) {
	265	/* Default timeout if invalid */
	266	sh_wdt_set_heartbeat(&sh_wdt_dev, WATCHDOG_HEARTBEAT);
	267
	268	dev_warn(&pdev->dev,
	269	"heartbeat value must be 1<=x<=3600, using %d\n",
	270	sh_wdt_dev.timeout);
	271	}
	272
	273	dev_info(&pdev->dev, "configured with heartbeat=%d sec (nowayout=%d)\n",
	274	sh_wdt_dev.timeout, nowayout);
8f5585ec	275
1950f499	276	rc = watchdog_register_device(&sh_wdt_dev);
e4c2cfee	277	if (unlikely(rc)) {
1950f499	278	dev_err(&pdev->dev, "Can't register watchdog (err=%d)\n", rc);
9ea64046	279	goto out_disable;
1da177e4 LT	280	}
1da177e4 LT	281
8f5585ec PM	282	init_timer(&wdt->timer);
	283	wdt->timer.function = sh_wdt_ping;
	284	wdt->timer.data = (unsigned long)wdt;
	285	wdt->timer.expires = next_ping_period(clock_division_ratio);
	286
	287	platform_set_drvdata(pdev, wdt);
8f5585ec PM	288
8f5585ec PM	289	dev_info(&pdev->dev, "initialized.\n");
1da177e4	290
8c013d96 PM	291	pm_runtime_enable(&pdev->dev);
8c013d96 PM	292
1da177e4	293	return 0;
8f5585ec	294
9ea64046 PM	295	out_disable:
	296	clk_disable(wdt->clk);
	297	clk_put(wdt->clk);
8f5585ec PM	298
8f5585ec PM	299	return rc;
1da177e4 LT	300	}
1da177e4 LT	301
8f5585ec	302	static int __devexit sh_wdt_remove(struct platform_device *pdev)
1da177e4	303	{
8f5585ec	304	struct sh_wdt *wdt = platform_get_drvdata(pdev);
8f5585ec PM	305
	306	platform_set_drvdata(pdev, NULL);
	307
1950f499	308	watchdog_unregister_device(&sh_wdt_dev);
8f5585ec	309
8c013d96	310	pm_runtime_disable(&pdev->dev);
9ea64046 PM	311	clk_disable(wdt->clk);
9ea64046 PM	312	clk_put(wdt->clk);
8f5585ec PM	313
	314	return 0;
	315	}
	316
40968126 PM	317	static void sh_wdt_shutdown(struct platform_device *pdev)
40968126 PM	318	{
1950f499	319	sh_wdt_stop(&sh_wdt_dev);
40968126 PM	320	}
40968126 PM	321
8f5585ec PM	322	static struct platform_driver sh_wdt_driver = {
	323	.driver = {
	324	.name = DRV_NAME,
	325	.owner = THIS_MODULE,
	326	},
	327
40968126 PM	328	.probe = sh_wdt_probe,
	329	.remove = __devexit_p(sh_wdt_remove),
	330	.shutdown = sh_wdt_shutdown,
8f5585ec PM	331	};
	332
	333	static int __init sh_wdt_init(void)
	334	{
8f5585ec PM	335	if (unlikely(clock_division_ratio < 0x5 \|\|
	336	clock_division_ratio > 0x7)) {
	337	clock_division_ratio = WTCSR_CKS_4096;
	338
27c766aa JP	339	pr_info("divisor must be 0x5<=x<=0x7, using %d\n",
27c766aa JP	340	clock_division_ratio);
8f5585ec PM	341	}
8f5585ec PM	342
8f5585ec	343	return platform_driver_register(&sh_wdt_driver);
1da177e4 LT	344	}
1da177e4 LT	345
8f5585ec PM	346	static void __exit sh_wdt_exit(void)
	347	{
	348	platform_driver_unregister(&sh_wdt_driver);
	349	}
	350	module_init(sh_wdt_init);
	351	module_exit(sh_wdt_exit);
	352
1da177e4 LT	353	MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>");
	354	MODULE_DESCRIPTION("SuperH watchdog driver");
	355	MODULE_LICENSE("GPL");
8f5585ec	356	MODULE_ALIAS("platform:" DRV_NAME);
1da177e4 LT	357	MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
	358
	359	module_param(clock_division_ratio, int, 0);
a77dba7e WVS	360	MODULE_PARM_DESC(clock_division_ratio,
a77dba7e WVS	361	"Clock division ratio. Valid ranges are from 0x5 (1.31ms) "
76550d32	362	"to 0x7 (5.25ms). (default=" __MODULE_STRING(WTCSR_CKS_4096) ")");
1da177e4 LT	363
1da177e4 LT	364	module_param(heartbeat, int, 0);
70b814ec AC	365	MODULE_PARM_DESC(heartbeat,
	366	"Watchdog heartbeat in seconds. (1 <= heartbeat <= 3600, default="
	367	__MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
1da177e4	368
86a1e189	369	module_param(nowayout, bool, 0);
70b814ec AC	370	MODULE_PARM_DESC(nowayout,
	371	"Watchdog cannot be stopped once started (default="
	372	__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");