Linux 2.6.38-rc2
[deliverable/linux.git] / drivers / xen / events.c
CommitLineData
e46cdb66
JF
1/*
2 * Xen event channels
3 *
4 * Xen models interrupts with abstract event channels. Because each
5 * domain gets 1024 event channels, but NR_IRQ is not that large, we
6 * must dynamically map irqs<->event channels. The event channels
7 * interface with the rest of the kernel by defining a xen interrupt
8 * chip. When an event is recieved, it is mapped to an irq and sent
9 * through the normal interrupt processing path.
10 *
11 * There are four kinds of events which can be mapped to an event
12 * channel:
13 *
14 * 1. Inter-domain notifications. This includes all the virtual
15 * device events, since they're driven by front-ends in another domain
16 * (typically dom0).
17 * 2. VIRQs, typically used for timers. These are per-cpu events.
18 * 3. IPIs.
d46a78b0 19 * 4. PIRQs - Hardware interrupts.
e46cdb66
JF
20 *
21 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007
22 */
23
24#include <linux/linkage.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/module.h>
28#include <linux/string.h>
28e08861 29#include <linux/bootmem.h>
5a0e3ad6 30#include <linux/slab.h>
b21ddbf5 31#include <linux/irqnr.h>
f731e3ef 32#include <linux/pci.h>
e46cdb66 33
38e20b07 34#include <asm/desc.h>
e46cdb66
JF
35#include <asm/ptrace.h>
36#include <asm/irq.h>
792dc4f6 37#include <asm/idle.h>
0794bfc7 38#include <asm/io_apic.h>
e46cdb66 39#include <asm/sync_bitops.h>
42a1de56 40#include <asm/xen/pci.h>
e46cdb66 41#include <asm/xen/hypercall.h>
8d1b8753 42#include <asm/xen/hypervisor.h>
e46cdb66 43
38e20b07
SY
44#include <xen/xen.h>
45#include <xen/hvm.h>
e04d0d07 46#include <xen/xen-ops.h>
e46cdb66
JF
47#include <xen/events.h>
48#include <xen/interface/xen.h>
49#include <xen/interface/event_channel.h>
38e20b07
SY
50#include <xen/interface/hvm/hvm_op.h>
51#include <xen/interface/hvm/params.h>
e46cdb66 52
e46cdb66
JF
53/*
54 * This lock protects updates to the following mapping and reference-count
55 * arrays. The lock does not need to be acquired to read the mapping tables.
56 */
57static DEFINE_SPINLOCK(irq_mapping_update_lock);
58
59/* IRQ <-> VIRQ mapping. */
204fba4a 60static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1};
e46cdb66 61
f87e4cac 62/* IRQ <-> IPI mapping */
204fba4a 63static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1};
f87e4cac 64
ced40d0f
JF
65/* Interrupt types. */
66enum xen_irq_type {
d77bbd4d 67 IRQT_UNBOUND = 0,
f87e4cac
JF
68 IRQT_PIRQ,
69 IRQT_VIRQ,
70 IRQT_IPI,
71 IRQT_EVTCHN
72};
e46cdb66 73
ced40d0f
JF
74/*
75 * Packed IRQ information:
76 * type - enum xen_irq_type
77 * event channel - irq->event channel mapping
78 * cpu - cpu this event channel is bound to
79 * index - type-specific information:
42a1de56
SS
80 * PIRQ - vector, with MSB being "needs EIO", or physical IRQ of the HVM
81 * guest, or GSI (real passthrough IRQ) of the device.
ced40d0f
JF
82 * VIRQ - virq number
83 * IPI - IPI vector
84 * EVTCHN -
85 */
86struct irq_info
87{
88 enum xen_irq_type type; /* type */
89 unsigned short evtchn; /* event channel */
90 unsigned short cpu; /* cpu bound */
91
92 union {
93 unsigned short virq;
94 enum ipi_vector ipi;
95 struct {
7a043f11 96 unsigned short pirq;
ced40d0f 97 unsigned short gsi;
d46a78b0
JF
98 unsigned char vector;
99 unsigned char flags;
ced40d0f
JF
100 } pirq;
101 } u;
102};
d46a78b0 103#define PIRQ_NEEDS_EOI (1 << 0)
15ebbb82 104#define PIRQ_SHAREABLE (1 << 1)
ced40d0f 105
b21ddbf5 106static struct irq_info *irq_info;
7a043f11 107static int *pirq_to_irq;
e46cdb66 108
b21ddbf5 109static int *evtchn_to_irq;
c7a3589e
MT
110struct cpu_evtchn_s {
111 unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG];
112};
3b32f574
JF
113
114static __initdata struct cpu_evtchn_s init_evtchn_mask = {
115 .bits[0 ... (NR_EVENT_CHANNELS/BITS_PER_LONG)-1] = ~0ul,
116};
117static struct cpu_evtchn_s *cpu_evtchn_mask_p = &init_evtchn_mask;
118
c7a3589e
MT
119static inline unsigned long *cpu_evtchn_mask(int cpu)
120{
121 return cpu_evtchn_mask_p[cpu].bits;
122}
e46cdb66 123
e46cdb66
JF
124/* Xen will never allocate port zero for any purpose. */
125#define VALID_EVTCHN(chn) ((chn) != 0)
126
e46cdb66 127static struct irq_chip xen_dynamic_chip;
aaca4964 128static struct irq_chip xen_percpu_chip;
d46a78b0 129static struct irq_chip xen_pirq_chip;
e46cdb66
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130
131/* Constructor for packed IRQ information. */
ced40d0f
JF
132static struct irq_info mk_unbound_info(void)
133{
134 return (struct irq_info) { .type = IRQT_UNBOUND };
135}
136
137static struct irq_info mk_evtchn_info(unsigned short evtchn)
138{
90af9514
IC
139 return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn,
140 .cpu = 0 };
ced40d0f
JF
141}
142
143static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi)
e46cdb66 144{
ced40d0f 145 return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn,
90af9514 146 .cpu = 0, .u.ipi = ipi };
ced40d0f
JF
147}
148
149static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq)
150{
151 return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn,
90af9514 152 .cpu = 0, .u.virq = virq };
ced40d0f
JF
153}
154
7a043f11 155static struct irq_info mk_pirq_info(unsigned short evtchn, unsigned short pirq,
ced40d0f
JF
156 unsigned short gsi, unsigned short vector)
157{
158 return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn,
7a043f11
SS
159 .cpu = 0,
160 .u.pirq = { .pirq = pirq, .gsi = gsi, .vector = vector } };
e46cdb66
JF
161}
162
163/*
164 * Accessors for packed IRQ information.
165 */
ced40d0f 166static struct irq_info *info_for_irq(unsigned irq)
e46cdb66 167{
ced40d0f 168 return &irq_info[irq];
e46cdb66
JF
169}
170
ced40d0f 171static unsigned int evtchn_from_irq(unsigned irq)
e46cdb66 172{
110e7c7e
JJ
173 if (unlikely(WARN(irq < 0 || irq >= nr_irqs, "Invalid irq %d!\n", irq)))
174 return 0;
175
ced40d0f 176 return info_for_irq(irq)->evtchn;
e46cdb66
JF
177}
178
d4c04536
IC
179unsigned irq_from_evtchn(unsigned int evtchn)
180{
181 return evtchn_to_irq[evtchn];
182}
183EXPORT_SYMBOL_GPL(irq_from_evtchn);
184
ced40d0f 185static enum ipi_vector ipi_from_irq(unsigned irq)
e46cdb66 186{
ced40d0f
JF
187 struct irq_info *info = info_for_irq(irq);
188
189 BUG_ON(info == NULL);
190 BUG_ON(info->type != IRQT_IPI);
191
192 return info->u.ipi;
193}
194
195static unsigned virq_from_irq(unsigned irq)
196{
197 struct irq_info *info = info_for_irq(irq);
198
199 BUG_ON(info == NULL);
200 BUG_ON(info->type != IRQT_VIRQ);
201
202 return info->u.virq;
203}
204
7a043f11
SS
205static unsigned pirq_from_irq(unsigned irq)
206{
207 struct irq_info *info = info_for_irq(irq);
208
209 BUG_ON(info == NULL);
210 BUG_ON(info->type != IRQT_PIRQ);
211
212 return info->u.pirq.pirq;
213}
214
ced40d0f
JF
215static unsigned gsi_from_irq(unsigned irq)
216{
217 struct irq_info *info = info_for_irq(irq);
218
219 BUG_ON(info == NULL);
220 BUG_ON(info->type != IRQT_PIRQ);
221
222 return info->u.pirq.gsi;
223}
224
225static unsigned vector_from_irq(unsigned irq)
226{
227 struct irq_info *info = info_for_irq(irq);
228
229 BUG_ON(info == NULL);
230 BUG_ON(info->type != IRQT_PIRQ);
231
232 return info->u.pirq.vector;
233}
234
235static enum xen_irq_type type_from_irq(unsigned irq)
236{
237 return info_for_irq(irq)->type;
238}
239
240static unsigned cpu_from_irq(unsigned irq)
241{
242 return info_for_irq(irq)->cpu;
243}
244
245static unsigned int cpu_from_evtchn(unsigned int evtchn)
246{
247 int irq = evtchn_to_irq[evtchn];
248 unsigned ret = 0;
249
250 if (irq != -1)
251 ret = cpu_from_irq(irq);
252
253 return ret;
e46cdb66
JF
254}
255
d46a78b0
JF
256static bool pirq_needs_eoi(unsigned irq)
257{
258 struct irq_info *info = info_for_irq(irq);
259
260 BUG_ON(info->type != IRQT_PIRQ);
261
262 return info->u.pirq.flags & PIRQ_NEEDS_EOI;
263}
264
e46cdb66
JF
265static inline unsigned long active_evtchns(unsigned int cpu,
266 struct shared_info *sh,
267 unsigned int idx)
268{
269 return (sh->evtchn_pending[idx] &
c7a3589e 270 cpu_evtchn_mask(cpu)[idx] &
e46cdb66
JF
271 ~sh->evtchn_mask[idx]);
272}
273
274static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu)
275{
276 int irq = evtchn_to_irq[chn];
277
278 BUG_ON(irq == -1);
279#ifdef CONFIG_SMP
7f7ace0c 280 cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu));
e46cdb66
JF
281#endif
282
e0419564
JF
283 clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq)));
284 set_bit(chn, cpu_evtchn_mask(cpu));
e46cdb66 285
ced40d0f 286 irq_info[irq].cpu = cpu;
e46cdb66
JF
287}
288
289static void init_evtchn_cpu_bindings(void)
290{
1c6969ec 291 int i;
e46cdb66 292#ifdef CONFIG_SMP
10e58084 293 struct irq_desc *desc;
10e58084 294
e46cdb66 295 /* By default all event channels notify CPU#0. */
0b8f1efa 296 for_each_irq_desc(i, desc) {
7f7ace0c 297 cpumask_copy(desc->affinity, cpumask_of(0));
0b8f1efa 298 }
e46cdb66
JF
299#endif
300
1c6969ec
JB
301 for_each_possible_cpu(i)
302 memset(cpu_evtchn_mask(i),
303 (i == 0) ? ~0 : 0, sizeof(struct cpu_evtchn_s));
304
e46cdb66
JF
305}
306
e46cdb66
JF
307static inline void clear_evtchn(int port)
308{
309 struct shared_info *s = HYPERVISOR_shared_info;
310 sync_clear_bit(port, &s->evtchn_pending[0]);
311}
312
313static inline void set_evtchn(int port)
314{
315 struct shared_info *s = HYPERVISOR_shared_info;
316 sync_set_bit(port, &s->evtchn_pending[0]);
317}
318
168d2f46
JF
319static inline int test_evtchn(int port)
320{
321 struct shared_info *s = HYPERVISOR_shared_info;
322 return sync_test_bit(port, &s->evtchn_pending[0]);
323}
324
e46cdb66
JF
325
326/**
327 * notify_remote_via_irq - send event to remote end of event channel via irq
328 * @irq: irq of event channel to send event to
329 *
330 * Unlike notify_remote_via_evtchn(), this is safe to use across
331 * save/restore. Notifications on a broken connection are silently
332 * dropped.
333 */
334void notify_remote_via_irq(int irq)
335{
336 int evtchn = evtchn_from_irq(irq);
337
338 if (VALID_EVTCHN(evtchn))
339 notify_remote_via_evtchn(evtchn);
340}
341EXPORT_SYMBOL_GPL(notify_remote_via_irq);
342
343static void mask_evtchn(int port)
344{
345 struct shared_info *s = HYPERVISOR_shared_info;
346 sync_set_bit(port, &s->evtchn_mask[0]);
347}
348
349static void unmask_evtchn(int port)
350{
351 struct shared_info *s = HYPERVISOR_shared_info;
352 unsigned int cpu = get_cpu();
353
354 BUG_ON(!irqs_disabled());
355
356 /* Slow path (hypercall) if this is a non-local port. */
357 if (unlikely(cpu != cpu_from_evtchn(port))) {
358 struct evtchn_unmask unmask = { .port = port };
359 (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask);
360 } else {
780f36d8 361 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
e46cdb66
JF
362
363 sync_clear_bit(port, &s->evtchn_mask[0]);
364
365 /*
366 * The following is basically the equivalent of
367 * 'hw_resend_irq'. Just like a real IO-APIC we 'lose
368 * the interrupt edge' if the channel is masked.
369 */
370 if (sync_test_bit(port, &s->evtchn_pending[0]) &&
371 !sync_test_and_set_bit(port / BITS_PER_LONG,
372 &vcpu_info->evtchn_pending_sel))
373 vcpu_info->evtchn_upcall_pending = 1;
374 }
375
376 put_cpu();
377}
378
0794bfc7
KRW
379static int get_nr_hw_irqs(void)
380{
381 int ret = 1;
382
383#ifdef CONFIG_X86_IO_APIC
384 ret = get_nr_irqs_gsi();
385#endif
386
387 return ret;
388}
389
e5fc7345 390static int find_unbound_pirq(int type)
7a043f11 391{
e5fc7345
SS
392 int rc, i;
393 struct physdev_get_free_pirq op_get_free_pirq;
394 op_get_free_pirq.type = type;
395
396 rc = HYPERVISOR_physdev_op(PHYSDEVOP_get_free_pirq, &op_get_free_pirq);
397 if (!rc)
398 return op_get_free_pirq.pirq;
399
400 for (i = 0; i < nr_irqs; i++) {
7a043f11
SS
401 if (pirq_to_irq[i] < 0)
402 return i;
403 }
404 return -1;
405}
406
e46cdb66
JF
407static int find_unbound_irq(void)
408{
77dff1c7
TG
409 struct irq_data *data;
410 int irq, res;
d1b758eb
KRW
411 int bottom = get_nr_hw_irqs();
412 int top = nr_irqs-1;
e46cdb66 413
d1b758eb 414 if (bottom == nr_irqs)
3a69e916
KRW
415 goto no_irqs;
416
d1b758eb
KRW
417 /* This loop starts from the top of IRQ space and goes down.
418 * We need this b/c if we have a PCI device in a Xen PV guest
419 * we do not have an IO-APIC (though the backend might have them)
420 * mapped in. To not have a collision of physical IRQs with the Xen
421 * event channels start at the top of the IRQ space for virtual IRQs.
422 */
423 for (irq = top; irq > bottom; irq--) {
77dff1c7 424 data = irq_get_irq_data(irq);
d1b758eb 425 /* only 15->0 have init'd desc; handle irq > 16 */
77dff1c7 426 if (!data)
99ad198c 427 break;
77dff1c7 428 if (data->chip == &no_irq_chip)
99ad198c 429 break;
77dff1c7 430 if (data->chip != &xen_dynamic_chip)
99ad198c 431 continue;
d77bbd4d 432 if (irq_info[irq].type == IRQT_UNBOUND)
77dff1c7 433 return irq;
99ad198c 434 }
e46cdb66 435
d1b758eb 436 if (irq == bottom)
3a69e916 437 goto no_irqs;
e46cdb66 438
29dcbc5c 439 res = irq_alloc_desc_at(irq, -1);
6f8a0ed4 440
77dff1c7
TG
441 if (WARN_ON(res != irq))
442 return -1;
ced40d0f 443
e46cdb66 444 return irq;
3a69e916
KRW
445
446no_irqs:
447 panic("No available IRQ to bind to: increase nr_irqs!\n");
e46cdb66
JF
448}
449
d46a78b0
JF
450static bool identity_mapped_irq(unsigned irq)
451{
0794bfc7
KRW
452 /* identity map all the hardware irqs */
453 return irq < get_nr_hw_irqs();
d46a78b0
JF
454}
455
456static void pirq_unmask_notify(int irq)
457{
7a043f11 458 struct physdev_eoi eoi = { .irq = pirq_from_irq(irq) };
d46a78b0
JF
459
460 if (unlikely(pirq_needs_eoi(irq))) {
461 int rc = HYPERVISOR_physdev_op(PHYSDEVOP_eoi, &eoi);
462 WARN_ON(rc);
463 }
464}
465
466static void pirq_query_unmask(int irq)
467{
468 struct physdev_irq_status_query irq_status;
469 struct irq_info *info = info_for_irq(irq);
470
471 BUG_ON(info->type != IRQT_PIRQ);
472
7a043f11 473 irq_status.irq = pirq_from_irq(irq);
d46a78b0
JF
474 if (HYPERVISOR_physdev_op(PHYSDEVOP_irq_status_query, &irq_status))
475 irq_status.flags = 0;
476
477 info->u.pirq.flags &= ~PIRQ_NEEDS_EOI;
478 if (irq_status.flags & XENIRQSTAT_needs_eoi)
479 info->u.pirq.flags |= PIRQ_NEEDS_EOI;
480}
481
482static bool probing_irq(int irq)
483{
484 struct irq_desc *desc = irq_to_desc(irq);
485
486 return desc && desc->action == NULL;
487}
488
489static unsigned int startup_pirq(unsigned int irq)
490{
491 struct evtchn_bind_pirq bind_pirq;
492 struct irq_info *info = info_for_irq(irq);
493 int evtchn = evtchn_from_irq(irq);
15ebbb82 494 int rc;
d46a78b0
JF
495
496 BUG_ON(info->type != IRQT_PIRQ);
497
498 if (VALID_EVTCHN(evtchn))
499 goto out;
500
7a043f11 501 bind_pirq.pirq = pirq_from_irq(irq);
d46a78b0 502 /* NB. We are happy to share unless we are probing. */
15ebbb82
KRW
503 bind_pirq.flags = info->u.pirq.flags & PIRQ_SHAREABLE ?
504 BIND_PIRQ__WILL_SHARE : 0;
505 rc = HYPERVISOR_event_channel_op(EVTCHNOP_bind_pirq, &bind_pirq);
506 if (rc != 0) {
d46a78b0
JF
507 if (!probing_irq(irq))
508 printk(KERN_INFO "Failed to obtain physical IRQ %d\n",
509 irq);
510 return 0;
511 }
512 evtchn = bind_pirq.port;
513
514 pirq_query_unmask(irq);
515
516 evtchn_to_irq[evtchn] = irq;
517 bind_evtchn_to_cpu(evtchn, 0);
518 info->evtchn = evtchn;
519
520out:
521 unmask_evtchn(evtchn);
522 pirq_unmask_notify(irq);
523
524 return 0;
525}
526
527static void shutdown_pirq(unsigned int irq)
528{
529 struct evtchn_close close;
530 struct irq_info *info = info_for_irq(irq);
531 int evtchn = evtchn_from_irq(irq);
532
533 BUG_ON(info->type != IRQT_PIRQ);
534
535 if (!VALID_EVTCHN(evtchn))
536 return;
537
538 mask_evtchn(evtchn);
539
540 close.port = evtchn;
541 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
542 BUG();
543
544 bind_evtchn_to_cpu(evtchn, 0);
545 evtchn_to_irq[evtchn] = -1;
546 info->evtchn = 0;
547}
548
549static void enable_pirq(unsigned int irq)
550{
551 startup_pirq(irq);
552}
553
554static void disable_pirq(unsigned int irq)
555{
556}
557
558static void ack_pirq(unsigned int irq)
559{
560 int evtchn = evtchn_from_irq(irq);
561
562 move_native_irq(irq);
563
564 if (VALID_EVTCHN(evtchn)) {
565 mask_evtchn(evtchn);
566 clear_evtchn(evtchn);
567 }
568}
569
570static void end_pirq(unsigned int irq)
571{
572 int evtchn = evtchn_from_irq(irq);
573 struct irq_desc *desc = irq_to_desc(irq);
574
575 if (WARN_ON(!desc))
576 return;
577
578 if ((desc->status & (IRQ_DISABLED|IRQ_PENDING)) ==
579 (IRQ_DISABLED|IRQ_PENDING)) {
580 shutdown_pirq(irq);
581 } else if (VALID_EVTCHN(evtchn)) {
582 unmask_evtchn(evtchn);
583 pirq_unmask_notify(irq);
584 }
585}
586
587static int find_irq_by_gsi(unsigned gsi)
588{
589 int irq;
590
b21ddbf5 591 for (irq = 0; irq < nr_irqs; irq++) {
d46a78b0
JF
592 struct irq_info *info = info_for_irq(irq);
593
594 if (info == NULL || info->type != IRQT_PIRQ)
595 continue;
596
597 if (gsi_from_irq(irq) == gsi)
598 return irq;
599 }
600
601 return -1;
602}
603
7a043f11
SS
604int xen_allocate_pirq(unsigned gsi, int shareable, char *name)
605{
606 return xen_map_pirq_gsi(gsi, gsi, shareable, name);
607}
608
609/* xen_map_pirq_gsi might allocate irqs from the top down, as a
3a69e916
KRW
610 * consequence don't assume that the irq number returned has a low value
611 * or can be used as a pirq number unless you know otherwise.
612 *
7a043f11 613 * One notable exception is when xen_map_pirq_gsi is called passing an
3a69e916 614 * hardware gsi as argument, in that case the irq number returned
7a043f11
SS
615 * matches the gsi number passed as second argument.
616 *
617 * Note: We don't assign an event channel until the irq actually started
618 * up. Return an existing irq if we've already got one for the gsi.
d46a78b0 619 */
7a043f11 620int xen_map_pirq_gsi(unsigned pirq, unsigned gsi, int shareable, char *name)
d46a78b0 621{
7a043f11 622 int irq = 0;
d46a78b0
JF
623 struct physdev_irq irq_op;
624
625 spin_lock(&irq_mapping_update_lock);
626
e5fc7345 627 if ((pirq > nr_irqs) || (gsi > nr_irqs)) {
01557baf 628 printk(KERN_WARNING "xen_map_pirq_gsi: %s %s is incorrect!\n",
e5fc7345
SS
629 pirq > nr_irqs ? "pirq" :"",
630 gsi > nr_irqs ? "gsi" : "");
01557baf
SS
631 goto out;
632 }
633
d46a78b0
JF
634 irq = find_irq_by_gsi(gsi);
635 if (irq != -1) {
7a043f11 636 printk(KERN_INFO "xen_map_pirq_gsi: returning irq %d for gsi %u\n",
d46a78b0
JF
637 irq, gsi);
638 goto out; /* XXX need refcount? */
639 }
640
b5401a96
AN
641 /* If we are a PV guest, we don't have GSIs (no ACPI passed). Therefore
642 * we are using the !xen_initial_domain() to drop in the function.*/
3942b740
SS
643 if (identity_mapped_irq(gsi) || (!xen_initial_domain() &&
644 xen_pv_domain())) {
d46a78b0 645 irq = gsi;
29dcbc5c 646 irq_alloc_desc_at(irq, -1);
d46a78b0
JF
647 } else
648 irq = find_unbound_irq();
649
650 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
1a60d05f 651 handle_level_irq, name);
d46a78b0
JF
652
653 irq_op.irq = irq;
b5401a96
AN
654 irq_op.vector = 0;
655
656 /* Only the privileged domain can do this. For non-priv, the pcifront
657 * driver provides a PCI bus that does the call to do exactly
658 * this in the priv domain. */
659 if (xen_initial_domain() &&
660 HYPERVISOR_physdev_op(PHYSDEVOP_alloc_irq_vector, &irq_op)) {
2c52f8d3 661 irq_free_desc(irq);
d46a78b0
JF
662 irq = -ENOSPC;
663 goto out;
664 }
665
7a043f11 666 irq_info[irq] = mk_pirq_info(0, pirq, gsi, irq_op.vector);
15ebbb82 667 irq_info[irq].u.pirq.flags |= shareable ? PIRQ_SHAREABLE : 0;
7a043f11 668 pirq_to_irq[pirq] = irq;
d46a78b0
JF
669
670out:
671 spin_unlock(&irq_mapping_update_lock);
672
673 return irq;
674}
675
f731e3ef
QH
676#ifdef CONFIG_PCI_MSI
677#include <linux/msi.h>
678#include "../pci/msi.h"
679
af42b8d1 680void xen_allocate_pirq_msi(char *name, int *irq, int *pirq, int alloc)
809f9267
SS
681{
682 spin_lock(&irq_mapping_update_lock);
683
af42b8d1
SS
684 if (alloc & XEN_ALLOC_IRQ) {
685 *irq = find_unbound_irq();
686 if (*irq == -1)
687 goto out;
688 }
809f9267 689
af42b8d1
SS
690 if (alloc & XEN_ALLOC_PIRQ) {
691 *pirq = find_unbound_pirq(MAP_PIRQ_TYPE_MSI);
692 if (*pirq == -1)
693 goto out;
694 }
809f9267
SS
695
696 set_irq_chip_and_handler_name(*irq, &xen_pirq_chip,
697 handle_level_irq, name);
698
699 irq_info[*irq] = mk_pirq_info(0, *pirq, 0, 0);
700 pirq_to_irq[*pirq] = *irq;
701
702out:
703 spin_unlock(&irq_mapping_update_lock);
704}
705
f731e3ef
QH
706int xen_create_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int type)
707{
708 int irq = -1;
709 struct physdev_map_pirq map_irq;
710 int rc;
711 int pos;
712 u32 table_offset, bir;
713
714 memset(&map_irq, 0, sizeof(map_irq));
715 map_irq.domid = DOMID_SELF;
716 map_irq.type = MAP_PIRQ_TYPE_MSI;
717 map_irq.index = -1;
718 map_irq.pirq = -1;
719 map_irq.bus = dev->bus->number;
720 map_irq.devfn = dev->devfn;
721
722 if (type == PCI_CAP_ID_MSIX) {
723 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
724
725 pci_read_config_dword(dev, msix_table_offset_reg(pos),
726 &table_offset);
727 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
728
729 map_irq.table_base = pci_resource_start(dev, bir);
730 map_irq.entry_nr = msidesc->msi_attrib.entry_nr;
731 }
732
733 spin_lock(&irq_mapping_update_lock);
734
735 irq = find_unbound_irq();
736
737 if (irq == -1)
738 goto out;
739
740 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
741 if (rc) {
742 printk(KERN_WARNING "xen map irq failed %d\n", rc);
743
744 irq_free_desc(irq);
745
746 irq = -1;
747 goto out;
748 }
749 irq_info[irq] = mk_pirq_info(0, map_irq.pirq, 0, map_irq.index);
750
751 set_irq_chip_and_handler_name(irq, &xen_pirq_chip,
752 handle_level_irq,
753 (type == PCI_CAP_ID_MSIX) ? "msi-x":"msi");
754
755out:
756 spin_unlock(&irq_mapping_update_lock);
757 return irq;
758}
759#endif
760
b5401a96
AN
761int xen_destroy_irq(int irq)
762{
763 struct irq_desc *desc;
38aa66fc
JF
764 struct physdev_unmap_pirq unmap_irq;
765 struct irq_info *info = info_for_irq(irq);
b5401a96
AN
766 int rc = -ENOENT;
767
768 spin_lock(&irq_mapping_update_lock);
769
770 desc = irq_to_desc(irq);
771 if (!desc)
772 goto out;
773
38aa66fc 774 if (xen_initial_domain()) {
12334715 775 unmap_irq.pirq = info->u.pirq.pirq;
38aa66fc
JF
776 unmap_irq.domid = DOMID_SELF;
777 rc = HYPERVISOR_physdev_op(PHYSDEVOP_unmap_pirq, &unmap_irq);
778 if (rc) {
779 printk(KERN_WARNING "unmap irq failed %d\n", rc);
780 goto out;
781 }
af42b8d1 782 pirq_to_irq[info->u.pirq.pirq] = -1;
38aa66fc 783 }
b5401a96
AN
784 irq_info[irq] = mk_unbound_info();
785
2c52f8d3 786 irq_free_desc(irq);
b5401a96
AN
787
788out:
789 spin_unlock(&irq_mapping_update_lock);
790 return rc;
791}
792
d46a78b0
JF
793int xen_vector_from_irq(unsigned irq)
794{
795 return vector_from_irq(irq);
796}
797
798int xen_gsi_from_irq(unsigned irq)
799{
800 return gsi_from_irq(irq);
e46cdb66
JF
801}
802
af42b8d1
SS
803int xen_irq_from_pirq(unsigned pirq)
804{
805 return pirq_to_irq[pirq];
806}
807
b536b4b9 808int bind_evtchn_to_irq(unsigned int evtchn)
e46cdb66
JF
809{
810 int irq;
811
812 spin_lock(&irq_mapping_update_lock);
813
814 irq = evtchn_to_irq[evtchn];
815
816 if (irq == -1) {
817 irq = find_unbound_irq();
818
e46cdb66 819 set_irq_chip_and_handler_name(irq, &xen_dynamic_chip,
3588fe2e 820 handle_fasteoi_irq, "event");
e46cdb66
JF
821
822 evtchn_to_irq[evtchn] = irq;
ced40d0f 823 irq_info[irq] = mk_evtchn_info(evtchn);
e46cdb66
JF
824 }
825
e46cdb66
JF
826 spin_unlock(&irq_mapping_update_lock);
827
828 return irq;
829}
b536b4b9 830EXPORT_SYMBOL_GPL(bind_evtchn_to_irq);
e46cdb66 831
f87e4cac
JF
832static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu)
833{
834 struct evtchn_bind_ipi bind_ipi;
835 int evtchn, irq;
836
837 spin_lock(&irq_mapping_update_lock);
838
839 irq = per_cpu(ipi_to_irq, cpu)[ipi];
90af9514 840
f87e4cac
JF
841 if (irq == -1) {
842 irq = find_unbound_irq();
843 if (irq < 0)
844 goto out;
845
aaca4964
JF
846 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
847 handle_percpu_irq, "ipi");
f87e4cac
JF
848
849 bind_ipi.vcpu = cpu;
850 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
851 &bind_ipi) != 0)
852 BUG();
853 evtchn = bind_ipi.port;
854
855 evtchn_to_irq[evtchn] = irq;
ced40d0f 856 irq_info[irq] = mk_ipi_info(evtchn, ipi);
f87e4cac
JF
857 per_cpu(ipi_to_irq, cpu)[ipi] = irq;
858
859 bind_evtchn_to_cpu(evtchn, cpu);
860 }
861
f87e4cac
JF
862 out:
863 spin_unlock(&irq_mapping_update_lock);
864 return irq;
865}
866
867
4fe7d5a7 868int bind_virq_to_irq(unsigned int virq, unsigned int cpu)
e46cdb66
JF
869{
870 struct evtchn_bind_virq bind_virq;
871 int evtchn, irq;
872
873 spin_lock(&irq_mapping_update_lock);
874
875 irq = per_cpu(virq_to_irq, cpu)[virq];
876
877 if (irq == -1) {
a52521f1
JF
878 irq = find_unbound_irq();
879
880 set_irq_chip_and_handler_name(irq, &xen_percpu_chip,
881 handle_percpu_irq, "virq");
882
e46cdb66
JF
883 bind_virq.virq = virq;
884 bind_virq.vcpu = cpu;
885 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
886 &bind_virq) != 0)
887 BUG();
888 evtchn = bind_virq.port;
889
e46cdb66 890 evtchn_to_irq[evtchn] = irq;
ced40d0f 891 irq_info[irq] = mk_virq_info(evtchn, virq);
e46cdb66
JF
892
893 per_cpu(virq_to_irq, cpu)[virq] = irq;
894
895 bind_evtchn_to_cpu(evtchn, cpu);
896 }
897
e46cdb66
JF
898 spin_unlock(&irq_mapping_update_lock);
899
900 return irq;
901}
902
903static void unbind_from_irq(unsigned int irq)
904{
905 struct evtchn_close close;
906 int evtchn = evtchn_from_irq(irq);
907
908 spin_lock(&irq_mapping_update_lock);
909
d77bbd4d 910 if (VALID_EVTCHN(evtchn)) {
e46cdb66
JF
911 close.port = evtchn;
912 if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0)
913 BUG();
914
915 switch (type_from_irq(irq)) {
916 case IRQT_VIRQ:
917 per_cpu(virq_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 918 [virq_from_irq(irq)] = -1;
e46cdb66 919 break;
d68d82af
AN
920 case IRQT_IPI:
921 per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn))
ced40d0f 922 [ipi_from_irq(irq)] = -1;
d68d82af 923 break;
e46cdb66
JF
924 default:
925 break;
926 }
927
928 /* Closed ports are implicitly re-bound to VCPU0. */
929 bind_evtchn_to_cpu(evtchn, 0);
930
931 evtchn_to_irq[evtchn] = -1;
fed5ea87
IC
932 }
933
934 if (irq_info[irq].type != IRQT_UNBOUND) {
ced40d0f 935 irq_info[irq] = mk_unbound_info();
e46cdb66 936
77dff1c7 937 irq_free_desc(irq);
e46cdb66
JF
938 }
939
940 spin_unlock(&irq_mapping_update_lock);
941}
942
943int bind_evtchn_to_irqhandler(unsigned int evtchn,
7c239975 944 irq_handler_t handler,
e46cdb66
JF
945 unsigned long irqflags,
946 const char *devname, void *dev_id)
947{
948 unsigned int irq;
949 int retval;
950
951 irq = bind_evtchn_to_irq(evtchn);
952 retval = request_irq(irq, handler, irqflags, devname, dev_id);
953 if (retval != 0) {
954 unbind_from_irq(irq);
955 return retval;
956 }
957
958 return irq;
959}
960EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler);
961
962int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu,
7c239975 963 irq_handler_t handler,
e46cdb66
JF
964 unsigned long irqflags, const char *devname, void *dev_id)
965{
966 unsigned int irq;
967 int retval;
968
969 irq = bind_virq_to_irq(virq, cpu);
970 retval = request_irq(irq, handler, irqflags, devname, dev_id);
971 if (retval != 0) {
972 unbind_from_irq(irq);
973 return retval;
974 }
975
976 return irq;
977}
978EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler);
979
f87e4cac
JF
980int bind_ipi_to_irqhandler(enum ipi_vector ipi,
981 unsigned int cpu,
982 irq_handler_t handler,
983 unsigned long irqflags,
984 const char *devname,
985 void *dev_id)
986{
987 int irq, retval;
988
989 irq = bind_ipi_to_irq(ipi, cpu);
990 if (irq < 0)
991 return irq;
992
4877c737 993 irqflags |= IRQF_NO_SUSPEND;
f87e4cac
JF
994 retval = request_irq(irq, handler, irqflags, devname, dev_id);
995 if (retval != 0) {
996 unbind_from_irq(irq);
997 return retval;
998 }
999
1000 return irq;
1001}
1002
e46cdb66
JF
1003void unbind_from_irqhandler(unsigned int irq, void *dev_id)
1004{
1005 free_irq(irq, dev_id);
1006 unbind_from_irq(irq);
1007}
1008EXPORT_SYMBOL_GPL(unbind_from_irqhandler);
1009
f87e4cac
JF
1010void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector)
1011{
1012 int irq = per_cpu(ipi_to_irq, cpu)[vector];
1013 BUG_ON(irq < 0);
1014 notify_remote_via_irq(irq);
1015}
1016
ee523ca1
JF
1017irqreturn_t xen_debug_interrupt(int irq, void *dev_id)
1018{
1019 struct shared_info *sh = HYPERVISOR_shared_info;
1020 int cpu = smp_processor_id();
cb52e6d9 1021 unsigned long *cpu_evtchn = cpu_evtchn_mask(cpu);
ee523ca1
JF
1022 int i;
1023 unsigned long flags;
1024 static DEFINE_SPINLOCK(debug_lock);
cb52e6d9 1025 struct vcpu_info *v;
ee523ca1
JF
1026
1027 spin_lock_irqsave(&debug_lock, flags);
1028
cb52e6d9 1029 printk("\nvcpu %d\n ", cpu);
ee523ca1
JF
1030
1031 for_each_online_cpu(i) {
cb52e6d9
IC
1032 int pending;
1033 v = per_cpu(xen_vcpu, i);
1034 pending = (get_irq_regs() && i == cpu)
1035 ? xen_irqs_disabled(get_irq_regs())
1036 : v->evtchn_upcall_mask;
1037 printk("%d: masked=%d pending=%d event_sel %0*lx\n ", i,
1038 pending, v->evtchn_upcall_pending,
1039 (int)(sizeof(v->evtchn_pending_sel)*2),
1040 v->evtchn_pending_sel);
1041 }
1042 v = per_cpu(xen_vcpu, cpu);
1043
1044 printk("\npending:\n ");
1045 for (i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--)
1046 printk("%0*lx%s", (int)sizeof(sh->evtchn_pending[0])*2,
1047 sh->evtchn_pending[i],
1048 i % 8 == 0 ? "\n " : " ");
1049 printk("\nglobal mask:\n ");
1050 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1051 printk("%0*lx%s",
1052 (int)(sizeof(sh->evtchn_mask[0])*2),
1053 sh->evtchn_mask[i],
1054 i % 8 == 0 ? "\n " : " ");
1055
1056 printk("\nglobally unmasked:\n ");
1057 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--)
1058 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1059 sh->evtchn_pending[i] & ~sh->evtchn_mask[i],
1060 i % 8 == 0 ? "\n " : " ");
1061
1062 printk("\nlocal cpu%d mask:\n ", cpu);
1063 for (i = (NR_EVENT_CHANNELS/BITS_PER_LONG)-1; i >= 0; i--)
1064 printk("%0*lx%s", (int)(sizeof(cpu_evtchn[0])*2),
1065 cpu_evtchn[i],
1066 i % 8 == 0 ? "\n " : " ");
1067
1068 printk("\nlocally unmasked:\n ");
1069 for (i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) {
1070 unsigned long pending = sh->evtchn_pending[i]
1071 & ~sh->evtchn_mask[i]
1072 & cpu_evtchn[i];
1073 printk("%0*lx%s", (int)(sizeof(sh->evtchn_mask[0])*2),
1074 pending, i % 8 == 0 ? "\n " : " ");
ee523ca1 1075 }
ee523ca1
JF
1076
1077 printk("\npending list:\n");
cb52e6d9 1078 for (i = 0; i < NR_EVENT_CHANNELS; i++) {
ee523ca1 1079 if (sync_test_bit(i, sh->evtchn_pending)) {
cb52e6d9
IC
1080 int word_idx = i / BITS_PER_LONG;
1081 printk(" %d: event %d -> irq %d%s%s%s\n",
ced40d0f 1082 cpu_from_evtchn(i), i,
cb52e6d9
IC
1083 evtchn_to_irq[i],
1084 sync_test_bit(word_idx, &v->evtchn_pending_sel)
1085 ? "" : " l2-clear",
1086 !sync_test_bit(i, sh->evtchn_mask)
1087 ? "" : " globally-masked",
1088 sync_test_bit(i, cpu_evtchn)
1089 ? "" : " locally-masked");
ee523ca1
JF
1090 }
1091 }
1092
1093 spin_unlock_irqrestore(&debug_lock, flags);
1094
1095 return IRQ_HANDLED;
1096}
1097
245b2e70
TH
1098static DEFINE_PER_CPU(unsigned, xed_nesting_count);
1099
e46cdb66
JF
1100/*
1101 * Search the CPUs pending events bitmasks. For each one found, map
1102 * the event number to an irq, and feed it into do_IRQ() for
1103 * handling.
1104 *
1105 * Xen uses a two-level bitmap to speed searching. The first level is
1106 * a bitset of words which contain pending event bits. The second
1107 * level is a bitset of pending events themselves.
1108 */
38e20b07 1109static void __xen_evtchn_do_upcall(void)
e46cdb66
JF
1110{
1111 int cpu = get_cpu();
1112 struct shared_info *s = HYPERVISOR_shared_info;
780f36d8 1113 struct vcpu_info *vcpu_info = __this_cpu_read(xen_vcpu);
229664be 1114 unsigned count;
e46cdb66 1115
229664be
JF
1116 do {
1117 unsigned long pending_words;
e46cdb66 1118
229664be 1119 vcpu_info->evtchn_upcall_pending = 0;
e46cdb66 1120
b2e4ae69 1121 if (__this_cpu_inc_return(xed_nesting_count) - 1)
229664be 1122 goto out;
e46cdb66 1123
e849c3e9
IY
1124#ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */
1125 /* Clear master flag /before/ clearing selector flag. */
6673cf63 1126 wmb();
e849c3e9 1127#endif
229664be
JF
1128 pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0);
1129 while (pending_words != 0) {
1130 unsigned long pending_bits;
1131 int word_idx = __ffs(pending_words);
1132 pending_words &= ~(1UL << word_idx);
1133
1134 while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) {
1135 int bit_idx = __ffs(pending_bits);
1136 int port = (word_idx * BITS_PER_LONG) + bit_idx;
1137 int irq = evtchn_to_irq[port];
ca4dbc66 1138 struct irq_desc *desc;
229664be 1139
3588fe2e
JF
1140 mask_evtchn(port);
1141 clear_evtchn(port);
1142
ca4dbc66
EB
1143 if (irq != -1) {
1144 desc = irq_to_desc(irq);
1145 if (desc)
1146 generic_handle_irq_desc(irq, desc);
1147 }
e46cdb66
JF
1148 }
1149 }
e46cdb66 1150
229664be
JF
1151 BUG_ON(!irqs_disabled());
1152
780f36d8
CL
1153 count = __this_cpu_read(xed_nesting_count);
1154 __this_cpu_write(xed_nesting_count, 0);
183d03cc 1155 } while (count != 1 || vcpu_info->evtchn_upcall_pending);
229664be
JF
1156
1157out:
38e20b07
SY
1158
1159 put_cpu();
1160}
1161
1162void xen_evtchn_do_upcall(struct pt_regs *regs)
1163{
1164 struct pt_regs *old_regs = set_irq_regs(regs);
1165
1166 exit_idle();
1167 irq_enter();
1168
1169 __xen_evtchn_do_upcall();
1170
3445a8fd
JF
1171 irq_exit();
1172 set_irq_regs(old_regs);
38e20b07 1173}
3445a8fd 1174
38e20b07
SY
1175void xen_hvm_evtchn_do_upcall(void)
1176{
1177 __xen_evtchn_do_upcall();
e46cdb66 1178}
183d03cc 1179EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall);
e46cdb66 1180
eb1e305f
JF
1181/* Rebind a new event channel to an existing irq. */
1182void rebind_evtchn_irq(int evtchn, int irq)
1183{
d77bbd4d
JF
1184 struct irq_info *info = info_for_irq(irq);
1185
eb1e305f
JF
1186 /* Make sure the irq is masked, since the new event channel
1187 will also be masked. */
1188 disable_irq(irq);
1189
1190 spin_lock(&irq_mapping_update_lock);
1191
1192 /* After resume the irq<->evtchn mappings are all cleared out */
1193 BUG_ON(evtchn_to_irq[evtchn] != -1);
1194 /* Expect irq to have been bound before,
d77bbd4d
JF
1195 so there should be a proper type */
1196 BUG_ON(info->type == IRQT_UNBOUND);
eb1e305f
JF
1197
1198 evtchn_to_irq[evtchn] = irq;
ced40d0f 1199 irq_info[irq] = mk_evtchn_info(evtchn);
eb1e305f
JF
1200
1201 spin_unlock(&irq_mapping_update_lock);
1202
1203 /* new event channels are always bound to cpu 0 */
0de26520 1204 irq_set_affinity(irq, cpumask_of(0));
eb1e305f
JF
1205
1206 /* Unmask the event channel. */
1207 enable_irq(irq);
1208}
1209
e46cdb66 1210/* Rebind an evtchn so that it gets delivered to a specific cpu */
d5dedd45 1211static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu)
e46cdb66
JF
1212{
1213 struct evtchn_bind_vcpu bind_vcpu;
1214 int evtchn = evtchn_from_irq(irq);
1215
183d03cc
SS
1216 /* events delivered via platform PCI interrupts are always
1217 * routed to vcpu 0 */
1218 if (!VALID_EVTCHN(evtchn) ||
1219 (xen_hvm_domain() && !xen_have_vector_callback))
d5dedd45 1220 return -1;
e46cdb66
JF
1221
1222 /* Send future instances of this interrupt to other vcpu. */
1223 bind_vcpu.port = evtchn;
1224 bind_vcpu.vcpu = tcpu;
1225
1226 /*
1227 * If this fails, it usually just indicates that we're dealing with a
1228 * virq or IPI channel, which don't actually need to be rebound. Ignore
1229 * it, but don't do the xenlinux-level rebind in that case.
1230 */
1231 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0)
1232 bind_evtchn_to_cpu(evtchn, tcpu);
e46cdb66 1233
d5dedd45
YL
1234 return 0;
1235}
e46cdb66 1236
d5dedd45 1237static int set_affinity_irq(unsigned irq, const struct cpumask *dest)
e46cdb66 1238{
0de26520 1239 unsigned tcpu = cpumask_first(dest);
d5dedd45
YL
1240
1241 return rebind_irq_to_cpu(irq, tcpu);
e46cdb66
JF
1242}
1243
642e0c88
IY
1244int resend_irq_on_evtchn(unsigned int irq)
1245{
1246 int masked, evtchn = evtchn_from_irq(irq);
1247 struct shared_info *s = HYPERVISOR_shared_info;
1248
1249 if (!VALID_EVTCHN(evtchn))
1250 return 1;
1251
1252 masked = sync_test_and_set_bit(evtchn, s->evtchn_mask);
1253 sync_set_bit(evtchn, s->evtchn_pending);
1254 if (!masked)
1255 unmask_evtchn(evtchn);
1256
1257 return 1;
1258}
1259
e46cdb66
JF
1260static void enable_dynirq(unsigned int irq)
1261{
1262 int evtchn = evtchn_from_irq(irq);
1263
1264 if (VALID_EVTCHN(evtchn))
1265 unmask_evtchn(evtchn);
1266}
1267
1268static void disable_dynirq(unsigned int irq)
1269{
1270 int evtchn = evtchn_from_irq(irq);
1271
1272 if (VALID_EVTCHN(evtchn))
1273 mask_evtchn(evtchn);
1274}
1275
1276static void ack_dynirq(unsigned int irq)
1277{
1278 int evtchn = evtchn_from_irq(irq);
1279
3588fe2e 1280 move_masked_irq(irq);
e46cdb66
JF
1281
1282 if (VALID_EVTCHN(evtchn))
3588fe2e 1283 unmask_evtchn(evtchn);
e46cdb66
JF
1284}
1285
1286static int retrigger_dynirq(unsigned int irq)
1287{
1288 int evtchn = evtchn_from_irq(irq);
ee8fa1c6 1289 struct shared_info *sh = HYPERVISOR_shared_info;
e46cdb66
JF
1290 int ret = 0;
1291
1292 if (VALID_EVTCHN(evtchn)) {
ee8fa1c6
JF
1293 int masked;
1294
1295 masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask);
1296 sync_set_bit(evtchn, sh->evtchn_pending);
1297 if (!masked)
1298 unmask_evtchn(evtchn);
e46cdb66
JF
1299 ret = 1;
1300 }
1301
1302 return ret;
1303}
1304
9a069c33
SS
1305static void restore_cpu_pirqs(void)
1306{
1307 int pirq, rc, irq, gsi;
1308 struct physdev_map_pirq map_irq;
1309
1310 for (pirq = 0; pirq < nr_irqs; pirq++) {
1311 irq = pirq_to_irq[pirq];
1312 if (irq == -1)
1313 continue;
1314
1315 /* save/restore of PT devices doesn't work, so at this point the
1316 * only devices present are GSI based emulated devices */
1317 gsi = gsi_from_irq(irq);
1318 if (!gsi)
1319 continue;
1320
1321 map_irq.domid = DOMID_SELF;
1322 map_irq.type = MAP_PIRQ_TYPE_GSI;
1323 map_irq.index = gsi;
1324 map_irq.pirq = pirq;
1325
1326 rc = HYPERVISOR_physdev_op(PHYSDEVOP_map_pirq, &map_irq);
1327 if (rc) {
1328 printk(KERN_WARNING "xen map irq failed gsi=%d irq=%d pirq=%d rc=%d\n",
1329 gsi, irq, pirq, rc);
1330 irq_info[irq] = mk_unbound_info();
1331 pirq_to_irq[pirq] = -1;
1332 continue;
1333 }
1334
1335 printk(KERN_DEBUG "xen: --> irq=%d, pirq=%d\n", irq, map_irq.pirq);
1336
1337 startup_pirq(irq);
1338 }
1339}
1340
0e91398f
JF
1341static void restore_cpu_virqs(unsigned int cpu)
1342{
1343 struct evtchn_bind_virq bind_virq;
1344 int virq, irq, evtchn;
1345
1346 for (virq = 0; virq < NR_VIRQS; virq++) {
1347 if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1)
1348 continue;
1349
ced40d0f 1350 BUG_ON(virq_from_irq(irq) != virq);
0e91398f
JF
1351
1352 /* Get a new binding from Xen. */
1353 bind_virq.virq = virq;
1354 bind_virq.vcpu = cpu;
1355 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq,
1356 &bind_virq) != 0)
1357 BUG();
1358 evtchn = bind_virq.port;
1359
1360 /* Record the new mapping. */
1361 evtchn_to_irq[evtchn] = irq;
ced40d0f 1362 irq_info[irq] = mk_virq_info(evtchn, virq);
0e91398f 1363 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1364 }
1365}
1366
1367static void restore_cpu_ipis(unsigned int cpu)
1368{
1369 struct evtchn_bind_ipi bind_ipi;
1370 int ipi, irq, evtchn;
1371
1372 for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) {
1373 if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1)
1374 continue;
1375
ced40d0f 1376 BUG_ON(ipi_from_irq(irq) != ipi);
0e91398f
JF
1377
1378 /* Get a new binding from Xen. */
1379 bind_ipi.vcpu = cpu;
1380 if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi,
1381 &bind_ipi) != 0)
1382 BUG();
1383 evtchn = bind_ipi.port;
1384
1385 /* Record the new mapping. */
1386 evtchn_to_irq[evtchn] = irq;
ced40d0f 1387 irq_info[irq] = mk_ipi_info(evtchn, ipi);
0e91398f 1388 bind_evtchn_to_cpu(evtchn, cpu);
0e91398f
JF
1389 }
1390}
1391
2d9e1e2f
JF
1392/* Clear an irq's pending state, in preparation for polling on it */
1393void xen_clear_irq_pending(int irq)
1394{
1395 int evtchn = evtchn_from_irq(irq);
1396
1397 if (VALID_EVTCHN(evtchn))
1398 clear_evtchn(evtchn);
1399}
d9a8814f 1400EXPORT_SYMBOL(xen_clear_irq_pending);
168d2f46
JF
1401void xen_set_irq_pending(int irq)
1402{
1403 int evtchn = evtchn_from_irq(irq);
1404
1405 if (VALID_EVTCHN(evtchn))
1406 set_evtchn(evtchn);
1407}
1408
1409bool xen_test_irq_pending(int irq)
1410{
1411 int evtchn = evtchn_from_irq(irq);
1412 bool ret = false;
1413
1414 if (VALID_EVTCHN(evtchn))
1415 ret = test_evtchn(evtchn);
1416
1417 return ret;
1418}
1419
d9a8814f
KRW
1420/* Poll waiting for an irq to become pending with timeout. In the usual case,
1421 * the irq will be disabled so it won't deliver an interrupt. */
1422void xen_poll_irq_timeout(int irq, u64 timeout)
2d9e1e2f
JF
1423{
1424 evtchn_port_t evtchn = evtchn_from_irq(irq);
1425
1426 if (VALID_EVTCHN(evtchn)) {
1427 struct sched_poll poll;
1428
1429 poll.nr_ports = 1;
d9a8814f 1430 poll.timeout = timeout;
ff3c5362 1431 set_xen_guest_handle(poll.ports, &evtchn);
2d9e1e2f
JF
1432
1433 if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0)
1434 BUG();
1435 }
1436}
d9a8814f
KRW
1437EXPORT_SYMBOL(xen_poll_irq_timeout);
1438/* Poll waiting for an irq to become pending. In the usual case, the
1439 * irq will be disabled so it won't deliver an interrupt. */
1440void xen_poll_irq(int irq)
1441{
1442 xen_poll_irq_timeout(irq, 0 /* no timeout */);
1443}
2d9e1e2f 1444
0e91398f
JF
1445void xen_irq_resume(void)
1446{
1447 unsigned int cpu, irq, evtchn;
6903591f 1448 struct irq_desc *desc;
0e91398f
JF
1449
1450 init_evtchn_cpu_bindings();
1451
1452 /* New event-channel space is not 'live' yet. */
1453 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1454 mask_evtchn(evtchn);
1455
1456 /* No IRQ <-> event-channel mappings. */
0b8f1efa 1457 for (irq = 0; irq < nr_irqs; irq++)
0e91398f
JF
1458 irq_info[irq].evtchn = 0; /* zap event-channel binding */
1459
1460 for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++)
1461 evtchn_to_irq[evtchn] = -1;
1462
1463 for_each_possible_cpu(cpu) {
1464 restore_cpu_virqs(cpu);
1465 restore_cpu_ipis(cpu);
1466 }
6903591f
IC
1467
1468 /*
1469 * Unmask any IRQF_NO_SUSPEND IRQs which are enabled. These
1470 * are not handled by the IRQ core.
1471 */
1472 for_each_irq_desc(irq, desc) {
1473 if (!desc->action || !(desc->action->flags & IRQF_NO_SUSPEND))
1474 continue;
1475 if (desc->status & IRQ_DISABLED)
1476 continue;
1477
1478 evtchn = evtchn_from_irq(irq);
1479 if (evtchn == -1)
1480 continue;
1481
1482 unmask_evtchn(evtchn);
1483 }
9a069c33
SS
1484
1485 restore_cpu_pirqs();
0e91398f
JF
1486}
1487
e46cdb66
JF
1488static struct irq_chip xen_dynamic_chip __read_mostly = {
1489 .name = "xen-dyn",
54a353a0
JF
1490
1491 .disable = disable_dynirq,
e46cdb66
JF
1492 .mask = disable_dynirq,
1493 .unmask = enable_dynirq,
54a353a0 1494
3588fe2e 1495 .eoi = ack_dynirq,
e46cdb66
JF
1496 .set_affinity = set_affinity_irq,
1497 .retrigger = retrigger_dynirq,
1498};
1499
d46a78b0
JF
1500static struct irq_chip xen_pirq_chip __read_mostly = {
1501 .name = "xen-pirq",
1502
1503 .startup = startup_pirq,
1504 .shutdown = shutdown_pirq,
1505
1506 .enable = enable_pirq,
1507 .unmask = enable_pirq,
1508
1509 .disable = disable_pirq,
1510 .mask = disable_pirq,
1511
1512 .ack = ack_pirq,
1513 .end = end_pirq,
1514
1515 .set_affinity = set_affinity_irq,
1516
1517 .retrigger = retrigger_dynirq,
1518};
1519
aaca4964
JF
1520static struct irq_chip xen_percpu_chip __read_mostly = {
1521 .name = "xen-percpu",
1522
1523 .disable = disable_dynirq,
1524 .mask = disable_dynirq,
1525 .unmask = enable_dynirq,
1526
1527 .ack = ack_dynirq,
1528};
1529
38e20b07
SY
1530int xen_set_callback_via(uint64_t via)
1531{
1532 struct xen_hvm_param a;
1533 a.domid = DOMID_SELF;
1534 a.index = HVM_PARAM_CALLBACK_IRQ;
1535 a.value = via;
1536 return HYPERVISOR_hvm_op(HVMOP_set_param, &a);
1537}
1538EXPORT_SYMBOL_GPL(xen_set_callback_via);
1539
ca65f9fc 1540#ifdef CONFIG_XEN_PVHVM
38e20b07
SY
1541/* Vector callbacks are better than PCI interrupts to receive event
1542 * channel notifications because we can receive vector callbacks on any
1543 * vcpu and we don't need PCI support or APIC interactions. */
1544void xen_callback_vector(void)
1545{
1546 int rc;
1547 uint64_t callback_via;
1548 if (xen_have_vector_callback) {
1549 callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK);
1550 rc = xen_set_callback_via(callback_via);
1551 if (rc) {
1552 printk(KERN_ERR "Request for Xen HVM callback vector"
1553 " failed.\n");
1554 xen_have_vector_callback = 0;
1555 return;
1556 }
1557 printk(KERN_INFO "Xen HVM callback vector for event delivery is "
1558 "enabled\n");
1559 /* in the restore case the vector has already been allocated */
1560 if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors))
1561 alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector);
1562 }
1563}
ca65f9fc
SS
1564#else
1565void xen_callback_vector(void) {}
1566#endif
38e20b07 1567
e46cdb66
JF
1568void __init xen_init_IRQ(void)
1569{
e5fc7345 1570 int i;
c7a3589e 1571
a70c352a
PE
1572 cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s),
1573 GFP_KERNEL);
b21ddbf5
JF
1574 irq_info = kcalloc(nr_irqs, sizeof(*irq_info), GFP_KERNEL);
1575
e5fc7345
SS
1576 /* We are using nr_irqs as the maximum number of pirq available but
1577 * that number is actually chosen by Xen and we don't know exactly
1578 * what it is. Be careful choosing high pirq numbers. */
1579 pirq_to_irq = kcalloc(nr_irqs, sizeof(*pirq_to_irq), GFP_KERNEL);
1580 for (i = 0; i < nr_irqs; i++)
7a043f11
SS
1581 pirq_to_irq[i] = -1;
1582
b21ddbf5
JF
1583 evtchn_to_irq = kcalloc(NR_EVENT_CHANNELS, sizeof(*evtchn_to_irq),
1584 GFP_KERNEL);
1585 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1586 evtchn_to_irq[i] = -1;
e46cdb66
JF
1587
1588 init_evtchn_cpu_bindings();
1589
1590 /* No event channels are 'live' right now. */
1591 for (i = 0; i < NR_EVENT_CHANNELS; i++)
1592 mask_evtchn(i);
1593
38e20b07
SY
1594 if (xen_hvm_domain()) {
1595 xen_callback_vector();
1596 native_init_IRQ();
3942b740
SS
1597 /* pci_xen_hvm_init must be called after native_init_IRQ so that
1598 * __acpi_register_gsi can point at the right function */
1599 pci_xen_hvm_init();
38e20b07
SY
1600 } else {
1601 irq_ctx_init(smp_processor_id());
38aa66fc
JF
1602 if (xen_initial_domain())
1603 xen_setup_pirqs();
38e20b07 1604 }
e46cdb66 1605}
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