Commit | Line | Data |
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e46cdb66 JF |
1 | /* |
2 | * Xen event channels | |
3 | * | |
4 | * Xen models interrupts with abstract event channels. Because each | |
5 | * domain gets 1024 event channels, but NR_IRQ is not that large, we | |
6 | * must dynamically map irqs<->event channels. The event channels | |
7 | * interface with the rest of the kernel by defining a xen interrupt | |
8 | * chip. When an event is recieved, it is mapped to an irq and sent | |
9 | * through the normal interrupt processing path. | |
10 | * | |
11 | * There are four kinds of events which can be mapped to an event | |
12 | * channel: | |
13 | * | |
14 | * 1. Inter-domain notifications. This includes all the virtual | |
15 | * device events, since they're driven by front-ends in another domain | |
16 | * (typically dom0). | |
17 | * 2. VIRQs, typically used for timers. These are per-cpu events. | |
18 | * 3. IPIs. | |
19 | * 4. Hardware interrupts. Not supported at present. | |
20 | * | |
21 | * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 | |
22 | */ | |
23 | ||
24 | #include <linux/linkage.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/irq.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/string.h> | |
28e08861 | 29 | #include <linux/bootmem.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
e46cdb66 | 31 | |
38e20b07 | 32 | #include <asm/desc.h> |
e46cdb66 JF |
33 | #include <asm/ptrace.h> |
34 | #include <asm/irq.h> | |
792dc4f6 | 35 | #include <asm/idle.h> |
e46cdb66 JF |
36 | #include <asm/sync_bitops.h> |
37 | #include <asm/xen/hypercall.h> | |
8d1b8753 | 38 | #include <asm/xen/hypervisor.h> |
e46cdb66 | 39 | |
38e20b07 SY |
40 | #include <xen/xen.h> |
41 | #include <xen/hvm.h> | |
e04d0d07 | 42 | #include <xen/xen-ops.h> |
e46cdb66 JF |
43 | #include <xen/events.h> |
44 | #include <xen/interface/xen.h> | |
45 | #include <xen/interface/event_channel.h> | |
38e20b07 SY |
46 | #include <xen/interface/hvm/hvm_op.h> |
47 | #include <xen/interface/hvm/params.h> | |
e46cdb66 | 48 | |
e46cdb66 JF |
49 | /* |
50 | * This lock protects updates to the following mapping and reference-count | |
51 | * arrays. The lock does not need to be acquired to read the mapping tables. | |
52 | */ | |
53 | static DEFINE_SPINLOCK(irq_mapping_update_lock); | |
54 | ||
55 | /* IRQ <-> VIRQ mapping. */ | |
204fba4a | 56 | static DEFINE_PER_CPU(int [NR_VIRQS], virq_to_irq) = {[0 ... NR_VIRQS-1] = -1}; |
e46cdb66 | 57 | |
f87e4cac | 58 | /* IRQ <-> IPI mapping */ |
204fba4a | 59 | static DEFINE_PER_CPU(int [XEN_NR_IPIS], ipi_to_irq) = {[0 ... XEN_NR_IPIS-1] = -1}; |
f87e4cac | 60 | |
ced40d0f JF |
61 | /* Interrupt types. */ |
62 | enum xen_irq_type { | |
d77bbd4d | 63 | IRQT_UNBOUND = 0, |
f87e4cac JF |
64 | IRQT_PIRQ, |
65 | IRQT_VIRQ, | |
66 | IRQT_IPI, | |
67 | IRQT_EVTCHN | |
68 | }; | |
e46cdb66 | 69 | |
ced40d0f JF |
70 | /* |
71 | * Packed IRQ information: | |
72 | * type - enum xen_irq_type | |
73 | * event channel - irq->event channel mapping | |
74 | * cpu - cpu this event channel is bound to | |
75 | * index - type-specific information: | |
76 | * PIRQ - vector, with MSB being "needs EIO" | |
77 | * VIRQ - virq number | |
78 | * IPI - IPI vector | |
79 | * EVTCHN - | |
80 | */ | |
81 | struct irq_info | |
82 | { | |
83 | enum xen_irq_type type; /* type */ | |
84 | unsigned short evtchn; /* event channel */ | |
85 | unsigned short cpu; /* cpu bound */ | |
86 | ||
87 | union { | |
88 | unsigned short virq; | |
89 | enum ipi_vector ipi; | |
90 | struct { | |
91 | unsigned short gsi; | |
92 | unsigned short vector; | |
93 | } pirq; | |
94 | } u; | |
95 | }; | |
96 | ||
97 | static struct irq_info irq_info[NR_IRQS]; | |
e46cdb66 JF |
98 | |
99 | static int evtchn_to_irq[NR_EVENT_CHANNELS] = { | |
100 | [0 ... NR_EVENT_CHANNELS-1] = -1 | |
101 | }; | |
c7a3589e MT |
102 | struct cpu_evtchn_s { |
103 | unsigned long bits[NR_EVENT_CHANNELS/BITS_PER_LONG]; | |
104 | }; | |
105 | static struct cpu_evtchn_s *cpu_evtchn_mask_p; | |
106 | static inline unsigned long *cpu_evtchn_mask(int cpu) | |
107 | { | |
108 | return cpu_evtchn_mask_p[cpu].bits; | |
109 | } | |
e46cdb66 | 110 | |
e46cdb66 JF |
111 | /* Xen will never allocate port zero for any purpose. */ |
112 | #define VALID_EVTCHN(chn) ((chn) != 0) | |
113 | ||
e46cdb66 | 114 | static struct irq_chip xen_dynamic_chip; |
aaca4964 | 115 | static struct irq_chip xen_percpu_chip; |
e46cdb66 JF |
116 | |
117 | /* Constructor for packed IRQ information. */ | |
ced40d0f JF |
118 | static struct irq_info mk_unbound_info(void) |
119 | { | |
120 | return (struct irq_info) { .type = IRQT_UNBOUND }; | |
121 | } | |
122 | ||
123 | static struct irq_info mk_evtchn_info(unsigned short evtchn) | |
124 | { | |
90af9514 IC |
125 | return (struct irq_info) { .type = IRQT_EVTCHN, .evtchn = evtchn, |
126 | .cpu = 0 }; | |
ced40d0f JF |
127 | } |
128 | ||
129 | static struct irq_info mk_ipi_info(unsigned short evtchn, enum ipi_vector ipi) | |
e46cdb66 | 130 | { |
ced40d0f | 131 | return (struct irq_info) { .type = IRQT_IPI, .evtchn = evtchn, |
90af9514 | 132 | .cpu = 0, .u.ipi = ipi }; |
ced40d0f JF |
133 | } |
134 | ||
135 | static struct irq_info mk_virq_info(unsigned short evtchn, unsigned short virq) | |
136 | { | |
137 | return (struct irq_info) { .type = IRQT_VIRQ, .evtchn = evtchn, | |
90af9514 | 138 | .cpu = 0, .u.virq = virq }; |
ced40d0f JF |
139 | } |
140 | ||
141 | static struct irq_info mk_pirq_info(unsigned short evtchn, | |
142 | unsigned short gsi, unsigned short vector) | |
143 | { | |
144 | return (struct irq_info) { .type = IRQT_PIRQ, .evtchn = evtchn, | |
90af9514 | 145 | .cpu = 0, .u.pirq = { .gsi = gsi, .vector = vector } }; |
e46cdb66 JF |
146 | } |
147 | ||
148 | /* | |
149 | * Accessors for packed IRQ information. | |
150 | */ | |
ced40d0f | 151 | static struct irq_info *info_for_irq(unsigned irq) |
e46cdb66 | 152 | { |
ced40d0f | 153 | return &irq_info[irq]; |
e46cdb66 JF |
154 | } |
155 | ||
ced40d0f | 156 | static unsigned int evtchn_from_irq(unsigned irq) |
e46cdb66 | 157 | { |
ced40d0f | 158 | return info_for_irq(irq)->evtchn; |
e46cdb66 JF |
159 | } |
160 | ||
d4c04536 IC |
161 | unsigned irq_from_evtchn(unsigned int evtchn) |
162 | { | |
163 | return evtchn_to_irq[evtchn]; | |
164 | } | |
165 | EXPORT_SYMBOL_GPL(irq_from_evtchn); | |
166 | ||
ced40d0f | 167 | static enum ipi_vector ipi_from_irq(unsigned irq) |
e46cdb66 | 168 | { |
ced40d0f JF |
169 | struct irq_info *info = info_for_irq(irq); |
170 | ||
171 | BUG_ON(info == NULL); | |
172 | BUG_ON(info->type != IRQT_IPI); | |
173 | ||
174 | return info->u.ipi; | |
175 | } | |
176 | ||
177 | static unsigned virq_from_irq(unsigned irq) | |
178 | { | |
179 | struct irq_info *info = info_for_irq(irq); | |
180 | ||
181 | BUG_ON(info == NULL); | |
182 | BUG_ON(info->type != IRQT_VIRQ); | |
183 | ||
184 | return info->u.virq; | |
185 | } | |
186 | ||
187 | static unsigned gsi_from_irq(unsigned irq) | |
188 | { | |
189 | struct irq_info *info = info_for_irq(irq); | |
190 | ||
191 | BUG_ON(info == NULL); | |
192 | BUG_ON(info->type != IRQT_PIRQ); | |
193 | ||
194 | return info->u.pirq.gsi; | |
195 | } | |
196 | ||
197 | static unsigned vector_from_irq(unsigned irq) | |
198 | { | |
199 | struct irq_info *info = info_for_irq(irq); | |
200 | ||
201 | BUG_ON(info == NULL); | |
202 | BUG_ON(info->type != IRQT_PIRQ); | |
203 | ||
204 | return info->u.pirq.vector; | |
205 | } | |
206 | ||
207 | static enum xen_irq_type type_from_irq(unsigned irq) | |
208 | { | |
209 | return info_for_irq(irq)->type; | |
210 | } | |
211 | ||
212 | static unsigned cpu_from_irq(unsigned irq) | |
213 | { | |
214 | return info_for_irq(irq)->cpu; | |
215 | } | |
216 | ||
217 | static unsigned int cpu_from_evtchn(unsigned int evtchn) | |
218 | { | |
219 | int irq = evtchn_to_irq[evtchn]; | |
220 | unsigned ret = 0; | |
221 | ||
222 | if (irq != -1) | |
223 | ret = cpu_from_irq(irq); | |
224 | ||
225 | return ret; | |
e46cdb66 JF |
226 | } |
227 | ||
228 | static inline unsigned long active_evtchns(unsigned int cpu, | |
229 | struct shared_info *sh, | |
230 | unsigned int idx) | |
231 | { | |
232 | return (sh->evtchn_pending[idx] & | |
c7a3589e | 233 | cpu_evtchn_mask(cpu)[idx] & |
e46cdb66 JF |
234 | ~sh->evtchn_mask[idx]); |
235 | } | |
236 | ||
237 | static void bind_evtchn_to_cpu(unsigned int chn, unsigned int cpu) | |
238 | { | |
239 | int irq = evtchn_to_irq[chn]; | |
240 | ||
241 | BUG_ON(irq == -1); | |
242 | #ifdef CONFIG_SMP | |
7f7ace0c | 243 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask_of(cpu)); |
e46cdb66 JF |
244 | #endif |
245 | ||
ced40d0f | 246 | __clear_bit(chn, cpu_evtchn_mask(cpu_from_irq(irq))); |
c7a3589e | 247 | __set_bit(chn, cpu_evtchn_mask(cpu)); |
e46cdb66 | 248 | |
ced40d0f | 249 | irq_info[irq].cpu = cpu; |
e46cdb66 JF |
250 | } |
251 | ||
252 | static void init_evtchn_cpu_bindings(void) | |
253 | { | |
254 | #ifdef CONFIG_SMP | |
10e58084 | 255 | struct irq_desc *desc; |
e46cdb66 | 256 | int i; |
10e58084 | 257 | |
e46cdb66 | 258 | /* By default all event channels notify CPU#0. */ |
0b8f1efa | 259 | for_each_irq_desc(i, desc) { |
7f7ace0c | 260 | cpumask_copy(desc->affinity, cpumask_of(0)); |
0b8f1efa | 261 | } |
e46cdb66 JF |
262 | #endif |
263 | ||
c7a3589e | 264 | memset(cpu_evtchn_mask(0), ~0, sizeof(cpu_evtchn_mask(0))); |
e46cdb66 JF |
265 | } |
266 | ||
e46cdb66 JF |
267 | static inline void clear_evtchn(int port) |
268 | { | |
269 | struct shared_info *s = HYPERVISOR_shared_info; | |
270 | sync_clear_bit(port, &s->evtchn_pending[0]); | |
271 | } | |
272 | ||
273 | static inline void set_evtchn(int port) | |
274 | { | |
275 | struct shared_info *s = HYPERVISOR_shared_info; | |
276 | sync_set_bit(port, &s->evtchn_pending[0]); | |
277 | } | |
278 | ||
168d2f46 JF |
279 | static inline int test_evtchn(int port) |
280 | { | |
281 | struct shared_info *s = HYPERVISOR_shared_info; | |
282 | return sync_test_bit(port, &s->evtchn_pending[0]); | |
283 | } | |
284 | ||
e46cdb66 JF |
285 | |
286 | /** | |
287 | * notify_remote_via_irq - send event to remote end of event channel via irq | |
288 | * @irq: irq of event channel to send event to | |
289 | * | |
290 | * Unlike notify_remote_via_evtchn(), this is safe to use across | |
291 | * save/restore. Notifications on a broken connection are silently | |
292 | * dropped. | |
293 | */ | |
294 | void notify_remote_via_irq(int irq) | |
295 | { | |
296 | int evtchn = evtchn_from_irq(irq); | |
297 | ||
298 | if (VALID_EVTCHN(evtchn)) | |
299 | notify_remote_via_evtchn(evtchn); | |
300 | } | |
301 | EXPORT_SYMBOL_GPL(notify_remote_via_irq); | |
302 | ||
303 | static void mask_evtchn(int port) | |
304 | { | |
305 | struct shared_info *s = HYPERVISOR_shared_info; | |
306 | sync_set_bit(port, &s->evtchn_mask[0]); | |
307 | } | |
308 | ||
309 | static void unmask_evtchn(int port) | |
310 | { | |
311 | struct shared_info *s = HYPERVISOR_shared_info; | |
312 | unsigned int cpu = get_cpu(); | |
313 | ||
314 | BUG_ON(!irqs_disabled()); | |
315 | ||
316 | /* Slow path (hypercall) if this is a non-local port. */ | |
317 | if (unlikely(cpu != cpu_from_evtchn(port))) { | |
318 | struct evtchn_unmask unmask = { .port = port }; | |
319 | (void)HYPERVISOR_event_channel_op(EVTCHNOP_unmask, &unmask); | |
320 | } else { | |
321 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
322 | ||
323 | sync_clear_bit(port, &s->evtchn_mask[0]); | |
324 | ||
325 | /* | |
326 | * The following is basically the equivalent of | |
327 | * 'hw_resend_irq'. Just like a real IO-APIC we 'lose | |
328 | * the interrupt edge' if the channel is masked. | |
329 | */ | |
330 | if (sync_test_bit(port, &s->evtchn_pending[0]) && | |
331 | !sync_test_and_set_bit(port / BITS_PER_LONG, | |
332 | &vcpu_info->evtchn_pending_sel)) | |
333 | vcpu_info->evtchn_upcall_pending = 1; | |
334 | } | |
335 | ||
336 | put_cpu(); | |
337 | } | |
338 | ||
339 | static int find_unbound_irq(void) | |
340 | { | |
341 | int irq; | |
6f8a0ed4 | 342 | struct irq_desc *desc; |
e46cdb66 | 343 | |
99ad198c SS |
344 | for (irq = 0; irq < nr_irqs; irq++) { |
345 | desc = irq_to_desc(irq); | |
346 | /* only 0->15 have init'd desc; handle irq > 16 */ | |
347 | if (desc == NULL) | |
348 | break; | |
349 | if (desc->chip == &no_irq_chip) | |
350 | break; | |
351 | if (desc->chip != &xen_dynamic_chip) | |
352 | continue; | |
d77bbd4d | 353 | if (irq_info[irq].type == IRQT_UNBOUND) |
e46cdb66 | 354 | break; |
99ad198c | 355 | } |
e46cdb66 | 356 | |
5a15d7e8 YL |
357 | if (irq == nr_irqs) |
358 | panic("No available IRQ to bind to: increase nr_irqs!\n"); | |
e46cdb66 | 359 | |
85ac16d0 | 360 | desc = irq_to_desc_alloc_node(irq, 0); |
6f8a0ed4 JF |
361 | if (WARN_ON(desc == NULL)) |
362 | return -1; | |
363 | ||
99ad198c | 364 | dynamic_irq_init_keep_chip_data(irq); |
ced40d0f | 365 | |
e46cdb66 JF |
366 | return irq; |
367 | } | |
368 | ||
b536b4b9 | 369 | int bind_evtchn_to_irq(unsigned int evtchn) |
e46cdb66 JF |
370 | { |
371 | int irq; | |
372 | ||
373 | spin_lock(&irq_mapping_update_lock); | |
374 | ||
375 | irq = evtchn_to_irq[evtchn]; | |
376 | ||
377 | if (irq == -1) { | |
378 | irq = find_unbound_irq(); | |
379 | ||
e46cdb66 | 380 | set_irq_chip_and_handler_name(irq, &xen_dynamic_chip, |
3588fe2e | 381 | handle_fasteoi_irq, "event"); |
e46cdb66 JF |
382 | |
383 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 384 | irq_info[irq] = mk_evtchn_info(evtchn); |
e46cdb66 JF |
385 | } |
386 | ||
e46cdb66 JF |
387 | spin_unlock(&irq_mapping_update_lock); |
388 | ||
389 | return irq; | |
390 | } | |
b536b4b9 | 391 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irq); |
e46cdb66 | 392 | |
f87e4cac JF |
393 | static int bind_ipi_to_irq(unsigned int ipi, unsigned int cpu) |
394 | { | |
395 | struct evtchn_bind_ipi bind_ipi; | |
396 | int evtchn, irq; | |
397 | ||
398 | spin_lock(&irq_mapping_update_lock); | |
399 | ||
400 | irq = per_cpu(ipi_to_irq, cpu)[ipi]; | |
90af9514 | 401 | |
f87e4cac JF |
402 | if (irq == -1) { |
403 | irq = find_unbound_irq(); | |
404 | if (irq < 0) | |
405 | goto out; | |
406 | ||
aaca4964 JF |
407 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
408 | handle_percpu_irq, "ipi"); | |
f87e4cac JF |
409 | |
410 | bind_ipi.vcpu = cpu; | |
411 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
412 | &bind_ipi) != 0) | |
413 | BUG(); | |
414 | evtchn = bind_ipi.port; | |
415 | ||
416 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 417 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
f87e4cac JF |
418 | per_cpu(ipi_to_irq, cpu)[ipi] = irq; |
419 | ||
420 | bind_evtchn_to_cpu(evtchn, cpu); | |
421 | } | |
422 | ||
f87e4cac JF |
423 | out: |
424 | spin_unlock(&irq_mapping_update_lock); | |
425 | return irq; | |
426 | } | |
427 | ||
428 | ||
e46cdb66 JF |
429 | static int bind_virq_to_irq(unsigned int virq, unsigned int cpu) |
430 | { | |
431 | struct evtchn_bind_virq bind_virq; | |
432 | int evtchn, irq; | |
433 | ||
434 | spin_lock(&irq_mapping_update_lock); | |
435 | ||
436 | irq = per_cpu(virq_to_irq, cpu)[virq]; | |
437 | ||
438 | if (irq == -1) { | |
439 | bind_virq.virq = virq; | |
440 | bind_virq.vcpu = cpu; | |
441 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
442 | &bind_virq) != 0) | |
443 | BUG(); | |
444 | evtchn = bind_virq.port; | |
445 | ||
446 | irq = find_unbound_irq(); | |
447 | ||
aaca4964 JF |
448 | set_irq_chip_and_handler_name(irq, &xen_percpu_chip, |
449 | handle_percpu_irq, "virq"); | |
e46cdb66 JF |
450 | |
451 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 452 | irq_info[irq] = mk_virq_info(evtchn, virq); |
e46cdb66 JF |
453 | |
454 | per_cpu(virq_to_irq, cpu)[virq] = irq; | |
455 | ||
456 | bind_evtchn_to_cpu(evtchn, cpu); | |
457 | } | |
458 | ||
e46cdb66 JF |
459 | spin_unlock(&irq_mapping_update_lock); |
460 | ||
461 | return irq; | |
462 | } | |
463 | ||
464 | static void unbind_from_irq(unsigned int irq) | |
465 | { | |
466 | struct evtchn_close close; | |
467 | int evtchn = evtchn_from_irq(irq); | |
468 | ||
469 | spin_lock(&irq_mapping_update_lock); | |
470 | ||
d77bbd4d | 471 | if (VALID_EVTCHN(evtchn)) { |
e46cdb66 JF |
472 | close.port = evtchn; |
473 | if (HYPERVISOR_event_channel_op(EVTCHNOP_close, &close) != 0) | |
474 | BUG(); | |
475 | ||
476 | switch (type_from_irq(irq)) { | |
477 | case IRQT_VIRQ: | |
478 | per_cpu(virq_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 479 | [virq_from_irq(irq)] = -1; |
e46cdb66 | 480 | break; |
d68d82af AN |
481 | case IRQT_IPI: |
482 | per_cpu(ipi_to_irq, cpu_from_evtchn(evtchn)) | |
ced40d0f | 483 | [ipi_from_irq(irq)] = -1; |
d68d82af | 484 | break; |
e46cdb66 JF |
485 | default: |
486 | break; | |
487 | } | |
488 | ||
489 | /* Closed ports are implicitly re-bound to VCPU0. */ | |
490 | bind_evtchn_to_cpu(evtchn, 0); | |
491 | ||
492 | evtchn_to_irq[evtchn] = -1; | |
fed5ea87 IC |
493 | } |
494 | ||
495 | if (irq_info[irq].type != IRQT_UNBOUND) { | |
ced40d0f | 496 | irq_info[irq] = mk_unbound_info(); |
e46cdb66 | 497 | |
0f2287ad | 498 | dynamic_irq_cleanup(irq); |
e46cdb66 JF |
499 | } |
500 | ||
501 | spin_unlock(&irq_mapping_update_lock); | |
502 | } | |
503 | ||
504 | int bind_evtchn_to_irqhandler(unsigned int evtchn, | |
7c239975 | 505 | irq_handler_t handler, |
e46cdb66 JF |
506 | unsigned long irqflags, |
507 | const char *devname, void *dev_id) | |
508 | { | |
509 | unsigned int irq; | |
510 | int retval; | |
511 | ||
512 | irq = bind_evtchn_to_irq(evtchn); | |
513 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
514 | if (retval != 0) { | |
515 | unbind_from_irq(irq); | |
516 | return retval; | |
517 | } | |
518 | ||
519 | return irq; | |
520 | } | |
521 | EXPORT_SYMBOL_GPL(bind_evtchn_to_irqhandler); | |
522 | ||
523 | int bind_virq_to_irqhandler(unsigned int virq, unsigned int cpu, | |
7c239975 | 524 | irq_handler_t handler, |
e46cdb66 JF |
525 | unsigned long irqflags, const char *devname, void *dev_id) |
526 | { | |
527 | unsigned int irq; | |
528 | int retval; | |
529 | ||
530 | irq = bind_virq_to_irq(virq, cpu); | |
531 | retval = request_irq(irq, handler, irqflags, devname, dev_id); | |
532 | if (retval != 0) { | |
533 | unbind_from_irq(irq); | |
534 | return retval; | |
535 | } | |
536 | ||
537 | return irq; | |
538 | } | |
539 | EXPORT_SYMBOL_GPL(bind_virq_to_irqhandler); | |
540 | ||
f87e4cac JF |
541 | int bind_ipi_to_irqhandler(enum ipi_vector ipi, |
542 | unsigned int cpu, | |
543 | irq_handler_t handler, | |
544 | unsigned long irqflags, | |
545 | const char *devname, | |
546 | void *dev_id) | |
547 | { | |
548 | int irq, retval; | |
549 | ||
550 | irq = bind_ipi_to_irq(ipi, cpu); | |
551 | if (irq < 0) | |
552 | return irq; | |
553 | ||
4877c737 | 554 | irqflags |= IRQF_NO_SUSPEND; |
f87e4cac JF |
555 | retval = request_irq(irq, handler, irqflags, devname, dev_id); |
556 | if (retval != 0) { | |
557 | unbind_from_irq(irq); | |
558 | return retval; | |
559 | } | |
560 | ||
561 | return irq; | |
562 | } | |
563 | ||
e46cdb66 JF |
564 | void unbind_from_irqhandler(unsigned int irq, void *dev_id) |
565 | { | |
566 | free_irq(irq, dev_id); | |
567 | unbind_from_irq(irq); | |
568 | } | |
569 | EXPORT_SYMBOL_GPL(unbind_from_irqhandler); | |
570 | ||
f87e4cac JF |
571 | void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector) |
572 | { | |
573 | int irq = per_cpu(ipi_to_irq, cpu)[vector]; | |
574 | BUG_ON(irq < 0); | |
575 | notify_remote_via_irq(irq); | |
576 | } | |
577 | ||
ee523ca1 JF |
578 | irqreturn_t xen_debug_interrupt(int irq, void *dev_id) |
579 | { | |
580 | struct shared_info *sh = HYPERVISOR_shared_info; | |
581 | int cpu = smp_processor_id(); | |
582 | int i; | |
583 | unsigned long flags; | |
584 | static DEFINE_SPINLOCK(debug_lock); | |
585 | ||
586 | spin_lock_irqsave(&debug_lock, flags); | |
587 | ||
588 | printk("vcpu %d\n ", cpu); | |
589 | ||
590 | for_each_online_cpu(i) { | |
591 | struct vcpu_info *v = per_cpu(xen_vcpu, i); | |
592 | printk("%d: masked=%d pending=%d event_sel %08lx\n ", i, | |
e849c3e9 | 593 | (get_irq_regs() && i == cpu) ? xen_irqs_disabled(get_irq_regs()) : v->evtchn_upcall_mask, |
ee523ca1 JF |
594 | v->evtchn_upcall_pending, |
595 | v->evtchn_pending_sel); | |
596 | } | |
597 | printk("pending:\n "); | |
598 | for(i = ARRAY_SIZE(sh->evtchn_pending)-1; i >= 0; i--) | |
599 | printk("%08lx%s", sh->evtchn_pending[i], | |
600 | i % 8 == 0 ? "\n " : " "); | |
601 | printk("\nmasks:\n "); | |
602 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
603 | printk("%08lx%s", sh->evtchn_mask[i], | |
604 | i % 8 == 0 ? "\n " : " "); | |
605 | ||
606 | printk("\nunmasked:\n "); | |
607 | for(i = ARRAY_SIZE(sh->evtchn_mask)-1; i >= 0; i--) | |
608 | printk("%08lx%s", sh->evtchn_pending[i] & ~sh->evtchn_mask[i], | |
609 | i % 8 == 0 ? "\n " : " "); | |
610 | ||
611 | printk("\npending list:\n"); | |
612 | for(i = 0; i < NR_EVENT_CHANNELS; i++) { | |
613 | if (sync_test_bit(i, sh->evtchn_pending)) { | |
614 | printk(" %d: event %d -> irq %d\n", | |
ced40d0f JF |
615 | cpu_from_evtchn(i), i, |
616 | evtchn_to_irq[i]); | |
ee523ca1 JF |
617 | } |
618 | } | |
619 | ||
620 | spin_unlock_irqrestore(&debug_lock, flags); | |
621 | ||
622 | return IRQ_HANDLED; | |
623 | } | |
624 | ||
245b2e70 TH |
625 | static DEFINE_PER_CPU(unsigned, xed_nesting_count); |
626 | ||
e46cdb66 JF |
627 | /* |
628 | * Search the CPUs pending events bitmasks. For each one found, map | |
629 | * the event number to an irq, and feed it into do_IRQ() for | |
630 | * handling. | |
631 | * | |
632 | * Xen uses a two-level bitmap to speed searching. The first level is | |
633 | * a bitset of words which contain pending event bits. The second | |
634 | * level is a bitset of pending events themselves. | |
635 | */ | |
38e20b07 | 636 | static void __xen_evtchn_do_upcall(void) |
e46cdb66 JF |
637 | { |
638 | int cpu = get_cpu(); | |
639 | struct shared_info *s = HYPERVISOR_shared_info; | |
640 | struct vcpu_info *vcpu_info = __get_cpu_var(xen_vcpu); | |
229664be | 641 | unsigned count; |
e46cdb66 | 642 | |
229664be JF |
643 | do { |
644 | unsigned long pending_words; | |
e46cdb66 | 645 | |
229664be | 646 | vcpu_info->evtchn_upcall_pending = 0; |
e46cdb66 | 647 | |
245b2e70 | 648 | if (__get_cpu_var(xed_nesting_count)++) |
229664be | 649 | goto out; |
e46cdb66 | 650 | |
e849c3e9 IY |
651 | #ifndef CONFIG_X86 /* No need for a barrier -- XCHG is a barrier on x86. */ |
652 | /* Clear master flag /before/ clearing selector flag. */ | |
6673cf63 | 653 | wmb(); |
e849c3e9 | 654 | #endif |
229664be JF |
655 | pending_words = xchg(&vcpu_info->evtchn_pending_sel, 0); |
656 | while (pending_words != 0) { | |
657 | unsigned long pending_bits; | |
658 | int word_idx = __ffs(pending_words); | |
659 | pending_words &= ~(1UL << word_idx); | |
660 | ||
661 | while ((pending_bits = active_evtchns(cpu, s, word_idx)) != 0) { | |
662 | int bit_idx = __ffs(pending_bits); | |
663 | int port = (word_idx * BITS_PER_LONG) + bit_idx; | |
664 | int irq = evtchn_to_irq[port]; | |
ca4dbc66 | 665 | struct irq_desc *desc; |
229664be | 666 | |
3588fe2e JF |
667 | mask_evtchn(port); |
668 | clear_evtchn(port); | |
669 | ||
ca4dbc66 EB |
670 | if (irq != -1) { |
671 | desc = irq_to_desc(irq); | |
672 | if (desc) | |
673 | generic_handle_irq_desc(irq, desc); | |
674 | } | |
e46cdb66 JF |
675 | } |
676 | } | |
e46cdb66 | 677 | |
229664be JF |
678 | BUG_ON(!irqs_disabled()); |
679 | ||
245b2e70 TH |
680 | count = __get_cpu_var(xed_nesting_count); |
681 | __get_cpu_var(xed_nesting_count) = 0; | |
183d03cc | 682 | } while (count != 1 || vcpu_info->evtchn_upcall_pending); |
229664be JF |
683 | |
684 | out: | |
38e20b07 SY |
685 | |
686 | put_cpu(); | |
687 | } | |
688 | ||
689 | void xen_evtchn_do_upcall(struct pt_regs *regs) | |
690 | { | |
691 | struct pt_regs *old_regs = set_irq_regs(regs); | |
692 | ||
693 | exit_idle(); | |
694 | irq_enter(); | |
695 | ||
696 | __xen_evtchn_do_upcall(); | |
697 | ||
3445a8fd JF |
698 | irq_exit(); |
699 | set_irq_regs(old_regs); | |
38e20b07 | 700 | } |
3445a8fd | 701 | |
38e20b07 SY |
702 | void xen_hvm_evtchn_do_upcall(void) |
703 | { | |
704 | __xen_evtchn_do_upcall(); | |
e46cdb66 | 705 | } |
183d03cc | 706 | EXPORT_SYMBOL_GPL(xen_hvm_evtchn_do_upcall); |
e46cdb66 | 707 | |
eb1e305f JF |
708 | /* Rebind a new event channel to an existing irq. */ |
709 | void rebind_evtchn_irq(int evtchn, int irq) | |
710 | { | |
d77bbd4d JF |
711 | struct irq_info *info = info_for_irq(irq); |
712 | ||
eb1e305f JF |
713 | /* Make sure the irq is masked, since the new event channel |
714 | will also be masked. */ | |
715 | disable_irq(irq); | |
716 | ||
717 | spin_lock(&irq_mapping_update_lock); | |
718 | ||
719 | /* After resume the irq<->evtchn mappings are all cleared out */ | |
720 | BUG_ON(evtchn_to_irq[evtchn] != -1); | |
721 | /* Expect irq to have been bound before, | |
d77bbd4d JF |
722 | so there should be a proper type */ |
723 | BUG_ON(info->type == IRQT_UNBOUND); | |
eb1e305f JF |
724 | |
725 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 726 | irq_info[irq] = mk_evtchn_info(evtchn); |
eb1e305f JF |
727 | |
728 | spin_unlock(&irq_mapping_update_lock); | |
729 | ||
730 | /* new event channels are always bound to cpu 0 */ | |
0de26520 | 731 | irq_set_affinity(irq, cpumask_of(0)); |
eb1e305f JF |
732 | |
733 | /* Unmask the event channel. */ | |
734 | enable_irq(irq); | |
735 | } | |
736 | ||
e46cdb66 | 737 | /* Rebind an evtchn so that it gets delivered to a specific cpu */ |
d5dedd45 | 738 | static int rebind_irq_to_cpu(unsigned irq, unsigned tcpu) |
e46cdb66 JF |
739 | { |
740 | struct evtchn_bind_vcpu bind_vcpu; | |
741 | int evtchn = evtchn_from_irq(irq); | |
742 | ||
183d03cc SS |
743 | /* events delivered via platform PCI interrupts are always |
744 | * routed to vcpu 0 */ | |
745 | if (!VALID_EVTCHN(evtchn) || | |
746 | (xen_hvm_domain() && !xen_have_vector_callback)) | |
d5dedd45 | 747 | return -1; |
e46cdb66 JF |
748 | |
749 | /* Send future instances of this interrupt to other vcpu. */ | |
750 | bind_vcpu.port = evtchn; | |
751 | bind_vcpu.vcpu = tcpu; | |
752 | ||
753 | /* | |
754 | * If this fails, it usually just indicates that we're dealing with a | |
755 | * virq or IPI channel, which don't actually need to be rebound. Ignore | |
756 | * it, but don't do the xenlinux-level rebind in that case. | |
757 | */ | |
758 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_vcpu, &bind_vcpu) >= 0) | |
759 | bind_evtchn_to_cpu(evtchn, tcpu); | |
e46cdb66 | 760 | |
d5dedd45 YL |
761 | return 0; |
762 | } | |
e46cdb66 | 763 | |
d5dedd45 | 764 | static int set_affinity_irq(unsigned irq, const struct cpumask *dest) |
e46cdb66 | 765 | { |
0de26520 | 766 | unsigned tcpu = cpumask_first(dest); |
d5dedd45 YL |
767 | |
768 | return rebind_irq_to_cpu(irq, tcpu); | |
e46cdb66 JF |
769 | } |
770 | ||
642e0c88 IY |
771 | int resend_irq_on_evtchn(unsigned int irq) |
772 | { | |
773 | int masked, evtchn = evtchn_from_irq(irq); | |
774 | struct shared_info *s = HYPERVISOR_shared_info; | |
775 | ||
776 | if (!VALID_EVTCHN(evtchn)) | |
777 | return 1; | |
778 | ||
779 | masked = sync_test_and_set_bit(evtchn, s->evtchn_mask); | |
780 | sync_set_bit(evtchn, s->evtchn_pending); | |
781 | if (!masked) | |
782 | unmask_evtchn(evtchn); | |
783 | ||
784 | return 1; | |
785 | } | |
786 | ||
e46cdb66 JF |
787 | static void enable_dynirq(unsigned int irq) |
788 | { | |
789 | int evtchn = evtchn_from_irq(irq); | |
790 | ||
791 | if (VALID_EVTCHN(evtchn)) | |
792 | unmask_evtchn(evtchn); | |
793 | } | |
794 | ||
795 | static void disable_dynirq(unsigned int irq) | |
796 | { | |
797 | int evtchn = evtchn_from_irq(irq); | |
798 | ||
799 | if (VALID_EVTCHN(evtchn)) | |
800 | mask_evtchn(evtchn); | |
801 | } | |
802 | ||
803 | static void ack_dynirq(unsigned int irq) | |
804 | { | |
805 | int evtchn = evtchn_from_irq(irq); | |
806 | ||
3588fe2e | 807 | move_masked_irq(irq); |
e46cdb66 JF |
808 | |
809 | if (VALID_EVTCHN(evtchn)) | |
3588fe2e | 810 | unmask_evtchn(evtchn); |
e46cdb66 JF |
811 | } |
812 | ||
813 | static int retrigger_dynirq(unsigned int irq) | |
814 | { | |
815 | int evtchn = evtchn_from_irq(irq); | |
ee8fa1c6 | 816 | struct shared_info *sh = HYPERVISOR_shared_info; |
e46cdb66 JF |
817 | int ret = 0; |
818 | ||
819 | if (VALID_EVTCHN(evtchn)) { | |
ee8fa1c6 JF |
820 | int masked; |
821 | ||
822 | masked = sync_test_and_set_bit(evtchn, sh->evtchn_mask); | |
823 | sync_set_bit(evtchn, sh->evtchn_pending); | |
824 | if (!masked) | |
825 | unmask_evtchn(evtchn); | |
e46cdb66 JF |
826 | ret = 1; |
827 | } | |
828 | ||
829 | return ret; | |
830 | } | |
831 | ||
0e91398f JF |
832 | static void restore_cpu_virqs(unsigned int cpu) |
833 | { | |
834 | struct evtchn_bind_virq bind_virq; | |
835 | int virq, irq, evtchn; | |
836 | ||
837 | for (virq = 0; virq < NR_VIRQS; virq++) { | |
838 | if ((irq = per_cpu(virq_to_irq, cpu)[virq]) == -1) | |
839 | continue; | |
840 | ||
ced40d0f | 841 | BUG_ON(virq_from_irq(irq) != virq); |
0e91398f JF |
842 | |
843 | /* Get a new binding from Xen. */ | |
844 | bind_virq.virq = virq; | |
845 | bind_virq.vcpu = cpu; | |
846 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_virq, | |
847 | &bind_virq) != 0) | |
848 | BUG(); | |
849 | evtchn = bind_virq.port; | |
850 | ||
851 | /* Record the new mapping. */ | |
852 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 853 | irq_info[irq] = mk_virq_info(evtchn, virq); |
0e91398f JF |
854 | bind_evtchn_to_cpu(evtchn, cpu); |
855 | ||
856 | /* Ready for use. */ | |
857 | unmask_evtchn(evtchn); | |
858 | } | |
859 | } | |
860 | ||
861 | static void restore_cpu_ipis(unsigned int cpu) | |
862 | { | |
863 | struct evtchn_bind_ipi bind_ipi; | |
864 | int ipi, irq, evtchn; | |
865 | ||
866 | for (ipi = 0; ipi < XEN_NR_IPIS; ipi++) { | |
867 | if ((irq = per_cpu(ipi_to_irq, cpu)[ipi]) == -1) | |
868 | continue; | |
869 | ||
ced40d0f | 870 | BUG_ON(ipi_from_irq(irq) != ipi); |
0e91398f JF |
871 | |
872 | /* Get a new binding from Xen. */ | |
873 | bind_ipi.vcpu = cpu; | |
874 | if (HYPERVISOR_event_channel_op(EVTCHNOP_bind_ipi, | |
875 | &bind_ipi) != 0) | |
876 | BUG(); | |
877 | evtchn = bind_ipi.port; | |
878 | ||
879 | /* Record the new mapping. */ | |
880 | evtchn_to_irq[evtchn] = irq; | |
ced40d0f | 881 | irq_info[irq] = mk_ipi_info(evtchn, ipi); |
0e91398f JF |
882 | bind_evtchn_to_cpu(evtchn, cpu); |
883 | ||
884 | /* Ready for use. */ | |
885 | unmask_evtchn(evtchn); | |
886 | ||
887 | } | |
888 | } | |
889 | ||
2d9e1e2f JF |
890 | /* Clear an irq's pending state, in preparation for polling on it */ |
891 | void xen_clear_irq_pending(int irq) | |
892 | { | |
893 | int evtchn = evtchn_from_irq(irq); | |
894 | ||
895 | if (VALID_EVTCHN(evtchn)) | |
896 | clear_evtchn(evtchn); | |
897 | } | |
898 | ||
168d2f46 JF |
899 | void xen_set_irq_pending(int irq) |
900 | { | |
901 | int evtchn = evtchn_from_irq(irq); | |
902 | ||
903 | if (VALID_EVTCHN(evtchn)) | |
904 | set_evtchn(evtchn); | |
905 | } | |
906 | ||
907 | bool xen_test_irq_pending(int irq) | |
908 | { | |
909 | int evtchn = evtchn_from_irq(irq); | |
910 | bool ret = false; | |
911 | ||
912 | if (VALID_EVTCHN(evtchn)) | |
913 | ret = test_evtchn(evtchn); | |
914 | ||
915 | return ret; | |
916 | } | |
917 | ||
2d9e1e2f JF |
918 | /* Poll waiting for an irq to become pending. In the usual case, the |
919 | irq will be disabled so it won't deliver an interrupt. */ | |
920 | void xen_poll_irq(int irq) | |
921 | { | |
922 | evtchn_port_t evtchn = evtchn_from_irq(irq); | |
923 | ||
924 | if (VALID_EVTCHN(evtchn)) { | |
925 | struct sched_poll poll; | |
926 | ||
927 | poll.nr_ports = 1; | |
928 | poll.timeout = 0; | |
ff3c5362 | 929 | set_xen_guest_handle(poll.ports, &evtchn); |
2d9e1e2f JF |
930 | |
931 | if (HYPERVISOR_sched_op(SCHEDOP_poll, &poll) != 0) | |
932 | BUG(); | |
933 | } | |
934 | } | |
935 | ||
0e91398f JF |
936 | void xen_irq_resume(void) |
937 | { | |
938 | unsigned int cpu, irq, evtchn; | |
939 | ||
940 | init_evtchn_cpu_bindings(); | |
941 | ||
942 | /* New event-channel space is not 'live' yet. */ | |
943 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
944 | mask_evtchn(evtchn); | |
945 | ||
946 | /* No IRQ <-> event-channel mappings. */ | |
0b8f1efa | 947 | for (irq = 0; irq < nr_irqs; irq++) |
0e91398f JF |
948 | irq_info[irq].evtchn = 0; /* zap event-channel binding */ |
949 | ||
950 | for (evtchn = 0; evtchn < NR_EVENT_CHANNELS; evtchn++) | |
951 | evtchn_to_irq[evtchn] = -1; | |
952 | ||
953 | for_each_possible_cpu(cpu) { | |
954 | restore_cpu_virqs(cpu); | |
955 | restore_cpu_ipis(cpu); | |
956 | } | |
957 | } | |
958 | ||
e46cdb66 JF |
959 | static struct irq_chip xen_dynamic_chip __read_mostly = { |
960 | .name = "xen-dyn", | |
54a353a0 JF |
961 | |
962 | .disable = disable_dynirq, | |
e46cdb66 JF |
963 | .mask = disable_dynirq, |
964 | .unmask = enable_dynirq, | |
54a353a0 | 965 | |
3588fe2e | 966 | .eoi = ack_dynirq, |
e46cdb66 JF |
967 | .set_affinity = set_affinity_irq, |
968 | .retrigger = retrigger_dynirq, | |
969 | }; | |
970 | ||
aaca4964 JF |
971 | static struct irq_chip xen_percpu_chip __read_mostly = { |
972 | .name = "xen-percpu", | |
973 | ||
974 | .disable = disable_dynirq, | |
975 | .mask = disable_dynirq, | |
976 | .unmask = enable_dynirq, | |
977 | ||
978 | .ack = ack_dynirq, | |
979 | }; | |
980 | ||
38e20b07 SY |
981 | int xen_set_callback_via(uint64_t via) |
982 | { | |
983 | struct xen_hvm_param a; | |
984 | a.domid = DOMID_SELF; | |
985 | a.index = HVM_PARAM_CALLBACK_IRQ; | |
986 | a.value = via; | |
987 | return HYPERVISOR_hvm_op(HVMOP_set_param, &a); | |
988 | } | |
989 | EXPORT_SYMBOL_GPL(xen_set_callback_via); | |
990 | ||
ca65f9fc | 991 | #ifdef CONFIG_XEN_PVHVM |
38e20b07 SY |
992 | /* Vector callbacks are better than PCI interrupts to receive event |
993 | * channel notifications because we can receive vector callbacks on any | |
994 | * vcpu and we don't need PCI support or APIC interactions. */ | |
995 | void xen_callback_vector(void) | |
996 | { | |
997 | int rc; | |
998 | uint64_t callback_via; | |
999 | if (xen_have_vector_callback) { | |
1000 | callback_via = HVM_CALLBACK_VECTOR(XEN_HVM_EVTCHN_CALLBACK); | |
1001 | rc = xen_set_callback_via(callback_via); | |
1002 | if (rc) { | |
1003 | printk(KERN_ERR "Request for Xen HVM callback vector" | |
1004 | " failed.\n"); | |
1005 | xen_have_vector_callback = 0; | |
1006 | return; | |
1007 | } | |
1008 | printk(KERN_INFO "Xen HVM callback vector for event delivery is " | |
1009 | "enabled\n"); | |
1010 | /* in the restore case the vector has already been allocated */ | |
1011 | if (!test_bit(XEN_HVM_EVTCHN_CALLBACK, used_vectors)) | |
1012 | alloc_intr_gate(XEN_HVM_EVTCHN_CALLBACK, xen_hvm_callback_vector); | |
1013 | } | |
1014 | } | |
ca65f9fc SS |
1015 | #else |
1016 | void xen_callback_vector(void) {} | |
1017 | #endif | |
38e20b07 | 1018 | |
e46cdb66 JF |
1019 | void __init xen_init_IRQ(void) |
1020 | { | |
1021 | int i; | |
c7a3589e | 1022 | |
a70c352a PE |
1023 | cpu_evtchn_mask_p = kcalloc(nr_cpu_ids, sizeof(struct cpu_evtchn_s), |
1024 | GFP_KERNEL); | |
28e08861 | 1025 | BUG_ON(cpu_evtchn_mask_p == NULL); |
e46cdb66 JF |
1026 | |
1027 | init_evtchn_cpu_bindings(); | |
1028 | ||
1029 | /* No event channels are 'live' right now. */ | |
1030 | for (i = 0; i < NR_EVENT_CHANNELS; i++) | |
1031 | mask_evtchn(i); | |
1032 | ||
38e20b07 SY |
1033 | if (xen_hvm_domain()) { |
1034 | xen_callback_vector(); | |
1035 | native_init_IRQ(); | |
1036 | } else { | |
1037 | irq_ctx_init(smp_processor_id()); | |
1038 | } | |
e46cdb66 | 1039 | } |