[deliverable/linux.git] / drivers / xen / xen-pciback / conf_space_header.c

/*
 * PCI Backend - Handles the virtual fields in the configuration space headers.
 *
 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
 */

#include <linux/kernel.h>
#include <linux/pci.h>
#include "pciback.h"
#include "conf_space.h"

struct pci_bar_info {
	u32 val;
	u32 len_val;
	int which;
};

#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)

static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
{
	int i;
	int ret;

	ret = xen_pcibk_read_config_word(dev, offset, value, data);
	if (!pci_is_enabled(dev))
		return ret;

	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
		if (dev->resource[i].flags & IORESOURCE_IO)
			*value |= PCI_COMMAND_IO;
		if (dev->resource[i].flags & IORESOURCE_MEM)
			*value |= PCI_COMMAND_MEMORY;
	}

	return ret;
}

static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
{
	struct xen_pcibk_dev_data *dev_data;
	int err;

	dev_data = pci_get_drvdata(dev);
	if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
			       pci_name(dev));
		err = pci_enable_device(dev);
		if (err)
			return err;
		if (dev_data)
			dev_data->enable_intx = 1;
	} else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
			       pci_name(dev));
		pci_disable_device(dev);
		if (dev_data)
			dev_data->enable_intx = 0;
	}

	if (!dev->is_busmaster && is_master_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
			       pci_name(dev));
		pci_set_master(dev);
	}

	if (value & PCI_COMMAND_INVALIDATE) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG
			       DRV_NAME ": %s: enable memory-write-invalidate\n",
			       pci_name(dev));
		err = pci_set_mwi(dev);
		if (err) {
			printk(KERN_WARNING
			       DRV_NAME ": %s: cannot enable "
			       "memory-write-invalidate (%d)\n",
			       pci_name(dev), err);
			value &= ~PCI_COMMAND_INVALIDATE;
		}
	}

	return pci_write_config_word(dev, offset, value);
}

static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	/* A write to obtain the length must happen as a 32-bit write.
	 * This does not (yet) support writing individual bytes
	 */
	if (value == ~PCI_ROM_ADDRESS_ENABLE)
		bar->which = 1;
	else {
		u32 tmpval;
		pci_read_config_dword(dev, offset, &tmpval);
		if (tmpval != bar->val && value == bar->val) {
			/* Allow restoration of bar value. */
			pci_write_config_dword(dev, offset, bar->val);
		}
		bar->which = 0;
	}

	/* Do we need to support enabling/disabling the rom address here? */

	return 0;
}

/* For the BARs, only allow writes which write ~0 or
 * the correct resource information
 * (Needed for when the driver probes the resource usage)
 */
static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	/* A write to obtain the length must happen as a 32-bit write.
	 * This does not (yet) support writing individual bytes
	 */
	if (value == ~0)
		bar->which = 1;
	else {
		u32 tmpval;
		pci_read_config_dword(dev, offset, &tmpval);
		if (tmpval != bar->val && value == bar->val) {
			/* Allow restoration of bar value. */
			pci_write_config_dword(dev, offset, bar->val);
		}
		bar->which = 0;
	}

	return 0;
}

static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	*value = bar->which ? bar->len_val : bar->val;

	return 0;
}

static inline void read_dev_bar(struct pci_dev *dev,
				struct pci_bar_info *bar_info, int offset,
				u32 len_mask)
{
	int	pos;
	struct resource	*res = dev->resource;

	if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
		pos = PCI_ROM_RESOURCE;
	else {
		pos = (offset - PCI_BASE_ADDRESS_0) / 4;
		if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE |
				PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
			   (PCI_BASE_ADDRESS_SPACE_MEMORY |
				PCI_BASE_ADDRESS_MEM_TYPE_64))) {
			bar_info->val = res[pos - 1].start >> 32;
			bar_info->len_val = res[pos - 1].end >> 32;
			return;
		}
	}

	bar_info->val = res[pos].start |
			(res[pos].flags & PCI_REGION_FLAG_MASK);
	bar_info->len_val = resource_size(&res[pos]);
}

static void *bar_init(struct pci_dev *dev, int offset)
{
	struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);

	if (!bar)
		return ERR_PTR(-ENOMEM);

	read_dev_bar(dev, bar, offset, ~0);
	bar->which = 0;

	return bar;
}

static void *rom_init(struct pci_dev *dev, int offset)
{
	struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);

	if (!bar)
		return ERR_PTR(-ENOMEM);

	read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
	bar->which = 0;

	return bar;
}

static void bar_reset(struct pci_dev *dev, int offset, void *data)
{
	struct pci_bar_info *bar = data;

	bar->which = 0;
}

static void bar_release(struct pci_dev *dev, int offset, void *data)
{
	kfree(data);
}

static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
			       u16 *value, void *data)
{
	*value = dev->vendor;

	return 0;
}

static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
			       u16 *value, void *data)
{
	*value = dev->device;

	return 0;
}

static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
			  void *data)
{
	*value = (u8) dev->irq;

	return 0;
}

static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
{
	u8 cur_value;
	int err;

	err = pci_read_config_byte(dev, offset, &cur_value);
	if (err)
		goto out;

	if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
	    || value == PCI_BIST_START)
		err = pci_write_config_byte(dev, offset, value);

out:
	return err;
}

static const struct config_field header_common[] = {
	{
	 .offset    = PCI_VENDOR_ID,
	 .size      = 2,
	 .u.w.read  = xen_pcibk_read_vendor,
	},
	{
	 .offset    = PCI_DEVICE_ID,
	 .size      = 2,
	 .u.w.read  = xen_pcibk_read_device,
	},
	{
	 .offset    = PCI_COMMAND,
	 .size      = 2,
	 .u.w.read  = command_read,
	 .u.w.write = command_write,
	},
	{
	 .offset    = PCI_INTERRUPT_LINE,
	 .size      = 1,
	 .u.b.read  = interrupt_read,
	},
	{
	 .offset    = PCI_INTERRUPT_PIN,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	},
	{
	 /* Any side effects of letting driver domain control cache line? */
	 .offset    = PCI_CACHE_LINE_SIZE,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	 .u.b.write = xen_pcibk_write_config_byte,
	},
	{
	 .offset    = PCI_LATENCY_TIMER,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	},
	{
	 .offset    = PCI_BIST,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	 .u.b.write = bist_write,
	},
	{}
};

#define CFG_FIELD_BAR(reg_offset)			\
	{						\
	.offset     = reg_offset,			\
	.size       = 4,				\
	.init       = bar_init,				\
	.reset      = bar_reset,			\
	.release    = bar_release,			\
	.u.dw.read  = bar_read,				\
	.u.dw.write = bar_write,			\
	}

#define CFG_FIELD_ROM(reg_offset)			\
	{						\
	.offset     = reg_offset,			\
	.size       = 4,				\
	.init       = rom_init,				\
	.reset      = bar_reset,			\
	.release    = bar_release,			\
	.u.dw.read  = bar_read,				\
	.u.dw.write = rom_write,			\
	}

static const struct config_field header_0[] = {
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
	CFG_FIELD_ROM(PCI_ROM_ADDRESS),
	{}
};

static const struct config_field header_1[] = {
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
	{}
};

int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
{
	int err;

	err = xen_pcibk_config_add_fields(dev, header_common);
	if (err)
		goto out;

	switch (dev->hdr_type) {
	case PCI_HEADER_TYPE_NORMAL:
		err = xen_pcibk_config_add_fields(dev, header_0);
		break;

	case PCI_HEADER_TYPE_BRIDGE:
		err = xen_pcibk_config_add_fields(dev, header_1);
		break;

	default:
		err = -EINVAL;
		printk(KERN_ERR DRV_NAME ": %s: Unsupported header type %d!\n",
		       pci_name(dev), dev->hdr_type);
		break;
	}

out:
	return err;
}
Commit	Line	Data
30edc14b KRW	1	/*
	2	* PCI Backend - Handles the virtual fields in the configuration space headers.
	3	*
	4	* Author: Ryan Wilson <hap9@epoch.ncsc.mil>
	5	*/
	6
	7	#include <linux/kernel.h>
	8	#include <linux/pci.h>
	9	#include "pciback.h"
	10	#include "conf_space.h"
	11
	12	struct pci_bar_info {
	13	u32 val;
	14	u32 len_val;
	15	int which;
	16	};
	17
	18	#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY\|PCI_COMMAND_IO))
	19	#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
	20
fd5b221b ZY	21	static int command_read(struct pci_dev dev, int offset, u16 value, void *data)
	22	{
	23	int i;
	24	int ret;
	25
a92336a1	26	ret = xen_pcibk_read_config_word(dev, offset, value, data);
402c5e15	27	if (!pci_is_enabled(dev))
fd5b221b ZY	28	return ret;
	29
	30	for (i = 0; i < PCI_ROM_RESOURCE; i++) {
	31	if (dev->resource[i].flags & IORESOURCE_IO)
	32	*value \|= PCI_COMMAND_IO;
	33	if (dev->resource[i].flags & IORESOURCE_MEM)
	34	*value \|= PCI_COMMAND_MEMORY;
	35	}
	36
	37	return ret;
	38	}
	39
30edc14b KRW	40	static int command_write(struct pci_dev dev, int offset, u16 value, void data)
30edc14b KRW	41	{
a92336a1	42	struct xen_pcibk_dev_data *dev_data;
30edc14b KRW	43	int err;
30edc14b KRW	44
0513fe9e	45	dev_data = pci_get_drvdata(dev);
30edc14b KRW	46	if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
30edc14b KRW	47	if (unlikely(verbose_request))
a92336a1	48	printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
30edc14b KRW	49	pci_name(dev));
	50	err = pci_enable_device(dev);
	51	if (err)
	52	return err;
0513fe9e KRW	53	if (dev_data)
0513fe9e KRW	54	dev_data->enable_intx = 1;
30edc14b KRW	55	} else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
30edc14b KRW	56	if (unlikely(verbose_request))
a92336a1	57	printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
30edc14b KRW	58	pci_name(dev));
30edc14b KRW	59	pci_disable_device(dev);
0513fe9e KRW	60	if (dev_data)
0513fe9e KRW	61	dev_data->enable_intx = 0;
30edc14b KRW	62	}
	63
	64	if (!dev->is_busmaster && is_master_cmd(value)) {
	65	if (unlikely(verbose_request))
a92336a1	66	printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
30edc14b KRW	67	pci_name(dev));
	68	pci_set_master(dev);
	69	}
	70
	71	if (value & PCI_COMMAND_INVALIDATE) {
	72	if (unlikely(verbose_request))
	73	printk(KERN_DEBUG
a92336a1	74	DRV_NAME ": %s: enable memory-write-invalidate\n",
30edc14b KRW	75	pci_name(dev));
	76	err = pci_set_mwi(dev);
	77	if (err) {
	78	printk(KERN_WARNING
a92336a1	79	DRV_NAME ": %s: cannot enable "
30edc14b KRW	80	"memory-write-invalidate (%d)\n",
	81	pci_name(dev), err);
	82	value &= ~PCI_COMMAND_INVALIDATE;
	83	}
	84	}
	85
	86	return pci_write_config_word(dev, offset, value);
	87	}
	88
	89	static int rom_write(struct pci_dev dev, int offset, u32 value, void data)
	90	{
	91	struct pci_bar_info *bar = data;
	92
	93	if (unlikely(!bar)) {
a92336a1	94	printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	95	pci_name(dev));
	96	return XEN_PCI_ERR_op_failed;
	97	}
	98
	99	/* A write to obtain the length must happen as a 32-bit write.
	100	* This does not (yet) support writing individual bytes
	101	*/
	102	if (value == ~PCI_ROM_ADDRESS_ENABLE)
	103	bar->which = 1;
	104	else {
	105	u32 tmpval;
	106	pci_read_config_dword(dev, offset, &tmpval);
	107	if (tmpval != bar->val && value == bar->val) {
	108	/* Allow restoration of bar value. */
	109	pci_write_config_dword(dev, offset, bar->val);
	110	}
	111	bar->which = 0;
	112	}
	113
	114	/* Do we need to support enabling/disabling the rom address here? */
	115
	116	return 0;
	117	}
	118
	119	/* For the BARs, only allow writes which write ~0 or
	120	* the correct resource information
	121	* (Needed for when the driver probes the resource usage)
	122	*/
	123	static int bar_write(struct pci_dev dev, int offset, u32 value, void data)
	124	{
	125	struct pci_bar_info *bar = data;
	126
	127	if (unlikely(!bar)) {
a92336a1	128	printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	129	pci_name(dev));
	130	return XEN_PCI_ERR_op_failed;
	131	}
	132
	133	/* A write to obtain the length must happen as a 32-bit write.
	134	* This does not (yet) support writing individual bytes
	135	*/
	136	if (value == ~0)
	137	bar->which = 1;
	138	else {
	139	u32 tmpval;
	140	pci_read_config_dword(dev, offset, &tmpval);
	141	if (tmpval != bar->val && value == bar->val) {
	142	/* Allow restoration of bar value. */
	143	pci_write_config_dword(dev, offset, bar->val);
	144	}
	145	bar->which = 0;
	146	}
	147
	148	return 0;
	149	}
	150
	151	static int bar_read(struct pci_dev dev, int offset, u32 value, void *data)
	152	{
	153	struct pci_bar_info *bar = data;
	154
	155	if (unlikely(!bar)) {
a92336a1	156	printk(KERN_WARNING DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	157	pci_name(dev));
	158	return XEN_PCI_ERR_op_failed;
	159	}
	160
	161	*value = bar->which ? bar->len_val : bar->val;
	162
	163	return 0;
	164	}
	165
	166	static inline void read_dev_bar(struct pci_dev *dev,
	167	struct pci_bar_info *bar_info, int offset,
	168	u32 len_mask)
	169	{
fd5b221b ZY	170	int pos;
	171	struct resource *res = dev->resource;
	172
	173	if (offset == PCI_ROM_ADDRESS \|\| offset == PCI_ROM_ADDRESS1)
	174	pos = PCI_ROM_RESOURCE;
	175	else {
	176	pos = (offset - PCI_BASE_ADDRESS_0) / 4;
	177	if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE \|
	178	PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
	179	(PCI_BASE_ADDRESS_SPACE_MEMORY \|
	180	PCI_BASE_ADDRESS_MEM_TYPE_64))) {
	181	bar_info->val = res[pos - 1].start >> 32;
	182	bar_info->len_val = res[pos - 1].end >> 32;
	183	return;
	184	}
	185	}
	186
	187	bar_info->val = res[pos].start \|
	188	(res[pos].flags & PCI_REGION_FLAG_MASK);
5fa99911	189	bar_info->len_val = resource_size(&res[pos]);
30edc14b KRW	190	}
	191
	192	static void bar_init(struct pci_dev dev, int offset)
	193	{
	194	struct pci_bar_info bar = kmalloc(sizeof(bar), GFP_KERNEL);
	195
	196	if (!bar)
	197	return ERR_PTR(-ENOMEM);
	198
	199	read_dev_bar(dev, bar, offset, ~0);
	200	bar->which = 0;
	201
	202	return bar;
	203	}
	204
	205	static void rom_init(struct pci_dev dev, int offset)
	206	{
	207	struct pci_bar_info bar = kmalloc(sizeof(bar), GFP_KERNEL);
	208
	209	if (!bar)
	210	return ERR_PTR(-ENOMEM);
	211
	212	read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
	213	bar->which = 0;
	214
	215	return bar;
	216	}
	217
	218	static void bar_reset(struct pci_dev dev, int offset, void data)
	219	{
	220	struct pci_bar_info *bar = data;
	221
	222	bar->which = 0;
	223	}
	224
	225	static void bar_release(struct pci_dev dev, int offset, void data)
	226	{
	227	kfree(data);
	228	}
	229
a92336a1	230	static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
fd5b221b ZY	231	u16 value, void data)
	232	{
	233	*value = dev->vendor;
	234
	235	return 0;
	236	}
	237
a92336a1	238	static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
fd5b221b ZY	239	u16 value, void data)
	240	{
	241	*value = dev->device;
	242
	243	return 0;
	244	}
	245
30edc14b KRW	246	static int interrupt_read(struct pci_dev dev, int offset, u8 value,
	247	void *data)
	248	{
	249	*value = (u8) dev->irq;
	250
	251	return 0;
	252	}
	253
	254	static int bist_write(struct pci_dev dev, int offset, u8 value, void data)
	255	{
	256	u8 cur_value;
	257	int err;
	258
	259	err = pci_read_config_byte(dev, offset, &cur_value);
	260	if (err)
	261	goto out;
	262
	263	if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
	264	\|\| value == PCI_BIST_START)
	265	err = pci_write_config_byte(dev, offset, value);
	266
	267	out:
	268	return err;
	269	}
	270
	271	static const struct config_field header_common[] = {
fd5b221b ZY	272	{
	273	.offset = PCI_VENDOR_ID,
	274	.size = 2,
a92336a1	275	.u.w.read = xen_pcibk_read_vendor,
fd5b221b ZY	276	},
	277	{
	278	.offset = PCI_DEVICE_ID,
	279	.size = 2,
a92336a1	280	.u.w.read = xen_pcibk_read_device,
fd5b221b	281	},
30edc14b KRW	282	{
	283	.offset = PCI_COMMAND,
	284	.size = 2,
fd5b221b	285	.u.w.read = command_read,
30edc14b KRW	286	.u.w.write = command_write,
	287	},
	288	{
	289	.offset = PCI_INTERRUPT_LINE,
	290	.size = 1,
	291	.u.b.read = interrupt_read,
	292	},
	293	{
	294	.offset = PCI_INTERRUPT_PIN,
	295	.size = 1,
a92336a1	296	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	297	},
	298	{
	299	/* Any side effects of letting driver domain control cache line? */
	300	.offset = PCI_CACHE_LINE_SIZE,
	301	.size = 1,
a92336a1 KRW	302	.u.b.read = xen_pcibk_read_config_byte,
a92336a1 KRW	303	.u.b.write = xen_pcibk_write_config_byte,
30edc14b KRW	304	},
	305	{
	306	.offset = PCI_LATENCY_TIMER,
	307	.size = 1,
a92336a1	308	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	309	},
	310	{
	311	.offset = PCI_BIST,
	312	.size = 1,
a92336a1	313	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	314	.u.b.write = bist_write,
	315	},
	316	{}
	317	};
	318
8bfd4e02 KRW	319	#define CFG_FIELD_BAR(reg_offset) \
	320	{ \
	321	.offset = reg_offset, \
	322	.size = 4, \
	323	.init = bar_init, \
	324	.reset = bar_reset, \
	325	.release = bar_release, \
	326	.u.dw.read = bar_read, \
	327	.u.dw.write = bar_write, \
	328	}
	329
	330	#define CFG_FIELD_ROM(reg_offset) \
	331	{ \
	332	.offset = reg_offset, \
	333	.size = 4, \
	334	.init = rom_init, \
	335	.reset = bar_reset, \
	336	.release = bar_release, \
	337	.u.dw.read = bar_read, \
	338	.u.dw.write = rom_write, \
	339	}
30edc14b KRW	340
	341	static const struct config_field header_0[] = {
	342	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	343	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	344	CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
	345	CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
	346	CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
	347	CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
	348	CFG_FIELD_ROM(PCI_ROM_ADDRESS),
	349	{}
	350	};
	351
	352	static const struct config_field header_1[] = {
	353	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	354	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	355	CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
	356	{}
	357	};
	358
a92336a1	359	int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
30edc14b KRW	360	{
	361	int err;
	362
a92336a1	363	err = xen_pcibk_config_add_fields(dev, header_common);
30edc14b KRW	364	if (err)
	365	goto out;
	366
	367	switch (dev->hdr_type) {
	368	case PCI_HEADER_TYPE_NORMAL:
a92336a1	369	err = xen_pcibk_config_add_fields(dev, header_0);
30edc14b KRW	370	break;
	371
	372	case PCI_HEADER_TYPE_BRIDGE:
a92336a1	373	err = xen_pcibk_config_add_fields(dev, header_1);
30edc14b KRW	374	break;
	375
	376	default:
	377	err = -EINVAL;
a92336a1	378	printk(KERN_ERR DRV_NAME ": %s: Unsupported header type %d!\n",
30edc14b KRW	379	pci_name(dev), dev->hdr_type);
	380	break;
	381	}
	382
	383	out:
	384	return err;
	385	}