[deliverable/linux.git] / drivers / xen / xen-pciback / conf_space_header.c

/*
 * PCI Backend - Handles the virtual fields in the configuration space headers.
 *
 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/kernel.h>
#include <linux/pci.h>
#include "pciback.h"
#include "conf_space.h"

struct pci_cmd_info {
	u16 val;
};

struct pci_bar_info {
	u32 val;
	u32 len_val;
	int which;
};

#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)

/* Bits guests are allowed to control in permissive mode. */
#define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL| \
			   PCI_COMMAND_INVALIDATE|PCI_COMMAND_VGA_PALETTE| \
			   PCI_COMMAND_WAIT|PCI_COMMAND_FAST_BACK)

static void *command_init(struct pci_dev *dev, int offset)
{
	struct pci_cmd_info *cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
	int err;

	if (!cmd)
		return ERR_PTR(-ENOMEM);

	err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val);
	if (err) {
		kfree(cmd);
		return ERR_PTR(err);
	}

	return cmd;
}

static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
{
	int ret = pci_read_config_word(dev, offset, value);
	const struct pci_cmd_info *cmd = data;

	*value &= PCI_COMMAND_GUEST;
	*value |= cmd->val & ~PCI_COMMAND_GUEST;

	return ret;
}

static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
{
	struct xen_pcibk_dev_data *dev_data;
	int err;
	u16 val;
	struct pci_cmd_info *cmd = data;

	dev_data = pci_get_drvdata(dev);
	if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
			       pci_name(dev));
		err = pci_enable_device(dev);
		if (err)
			return err;
		if (dev_data)
			dev_data->enable_intx = 1;
	} else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
			       pci_name(dev));
		pci_disable_device(dev);
		if (dev_data)
			dev_data->enable_intx = 0;
	}

	if (!dev->is_busmaster && is_master_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
			       pci_name(dev));
		pci_set_master(dev);
	} else if (dev->is_busmaster && !is_master_cmd(value)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG DRV_NAME ": %s: clear bus master\n",
			       pci_name(dev));
		pci_clear_master(dev);
	}

	if (!(cmd->val & PCI_COMMAND_INVALIDATE) &&
	    (value & PCI_COMMAND_INVALIDATE)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG
			       DRV_NAME ": %s: enable memory-write-invalidate\n",
			       pci_name(dev));
		err = pci_set_mwi(dev);
		if (err) {
			pr_warn("%s: cannot enable memory-write-invalidate (%d)\n",
				pci_name(dev), err);
			value &= ~PCI_COMMAND_INVALIDATE;
		}
	} else if ((cmd->val & PCI_COMMAND_INVALIDATE) &&
		   !(value & PCI_COMMAND_INVALIDATE)) {
		if (unlikely(verbose_request))
			printk(KERN_DEBUG
			       DRV_NAME ": %s: disable memory-write-invalidate\n",
			       pci_name(dev));
		pci_clear_mwi(dev);
	}

	cmd->val = value;

	if (!xen_pcibk_permissive && (!dev_data || !dev_data->permissive))
		return 0;

	/* Only allow the guest to control certain bits. */
	err = pci_read_config_word(dev, offset, &val);
	if (err || val == value)
		return err;

	value &= PCI_COMMAND_GUEST;
	value |= val & ~PCI_COMMAND_GUEST;

	return pci_write_config_word(dev, offset, value);
}

static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		pr_warn(DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	/* A write to obtain the length must happen as a 32-bit write.
	 * This does not (yet) support writing individual bytes
	 */
	if ((value | ~PCI_ROM_ADDRESS_MASK) == ~0U)
		bar->which = 1;
	else {
		u32 tmpval;
		pci_read_config_dword(dev, offset, &tmpval);
		if (tmpval != bar->val && value == bar->val) {
			/* Allow restoration of bar value. */
			pci_write_config_dword(dev, offset, bar->val);
		}
		bar->which = 0;
	}

	/* Do we need to support enabling/disabling the rom address here? */

	return 0;
}

/* For the BARs, only allow writes which write ~0 or
 * the correct resource information
 * (Needed for when the driver probes the resource usage)
 */
static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		pr_warn(DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	/* A write to obtain the length must happen as a 32-bit write.
	 * This does not (yet) support writing individual bytes
	 */
	if (value == ~0)
		bar->which = 1;
	else {
		u32 tmpval;
		pci_read_config_dword(dev, offset, &tmpval);
		if (tmpval != bar->val && value == bar->val) {
			/* Allow restoration of bar value. */
			pci_write_config_dword(dev, offset, bar->val);
		}
		bar->which = 0;
	}

	return 0;
}

static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
{
	struct pci_bar_info *bar = data;

	if (unlikely(!bar)) {
		pr_warn(DRV_NAME ": driver data not found for %s\n",
		       pci_name(dev));
		return XEN_PCI_ERR_op_failed;
	}

	*value = bar->which ? bar->len_val : bar->val;

	return 0;
}

static void *bar_init(struct pci_dev *dev, int offset)
{
	unsigned int pos;
	const struct resource *res = dev->resource;
	struct pci_bar_info *bar = kzalloc(sizeof(*bar), GFP_KERNEL);

	if (!bar)
		return ERR_PTR(-ENOMEM);

	if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
		pos = PCI_ROM_RESOURCE;
	else {
		pos = (offset - PCI_BASE_ADDRESS_0) / 4;
		if (pos && (res[pos - 1].flags & IORESOURCE_MEM_64)) {
			bar->val = res[pos - 1].start >> 32;
			bar->len_val = -resource_size(&res[pos - 1]) >> 32;
			return bar;
		}
	}

	if (!res[pos].flags ||
	    (res[pos].flags & (IORESOURCE_DISABLED | IORESOURCE_UNSET |
			       IORESOURCE_BUSY)))
		return bar;

	bar->val = res[pos].start |
		   (res[pos].flags & PCI_REGION_FLAG_MASK);
	bar->len_val = -resource_size(&res[pos]) |
		       (res[pos].flags & PCI_REGION_FLAG_MASK);

	return bar;
}

static void bar_reset(struct pci_dev *dev, int offset, void *data)
{
	struct pci_bar_info *bar = data;

	bar->which = 0;
}

static void bar_release(struct pci_dev *dev, int offset, void *data)
{
	kfree(data);
}

static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
			       u16 *value, void *data)
{
	*value = dev->vendor;

	return 0;
}

static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
			       u16 *value, void *data)
{
	*value = dev->device;

	return 0;
}

static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
			  void *data)
{
	*value = (u8) dev->irq;

	return 0;
}

static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
{
	u8 cur_value;
	int err;

	err = pci_read_config_byte(dev, offset, &cur_value);
	if (err)
		goto out;

	if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
	    || value == PCI_BIST_START)
		err = pci_write_config_byte(dev, offset, value);

out:
	return err;
}

static const struct config_field header_common[] = {
	{
	 .offset    = PCI_VENDOR_ID,
	 .size      = 2,
	 .u.w.read  = xen_pcibk_read_vendor,
	},
	{
	 .offset    = PCI_DEVICE_ID,
	 .size      = 2,
	 .u.w.read  = xen_pcibk_read_device,
	},
	{
	 .offset    = PCI_COMMAND,
	 .size      = 2,
	 .init      = command_init,
	 .release   = bar_release,
	 .u.w.read  = command_read,
	 .u.w.write = command_write,
	},
	{
	 .offset    = PCI_INTERRUPT_LINE,
	 .size      = 1,
	 .u.b.read  = interrupt_read,
	},
	{
	 .offset    = PCI_INTERRUPT_PIN,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	},
	{
	 /* Any side effects of letting driver domain control cache line? */
	 .offset    = PCI_CACHE_LINE_SIZE,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	 .u.b.write = xen_pcibk_write_config_byte,
	},
	{
	 .offset    = PCI_LATENCY_TIMER,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	},
	{
	 .offset    = PCI_BIST,
	 .size      = 1,
	 .u.b.read  = xen_pcibk_read_config_byte,
	 .u.b.write = bist_write,
	},
	{}
};

#define CFG_FIELD_BAR(reg_offset)			\
	{						\
	.offset     = reg_offset,			\
	.size       = 4,				\
	.init       = bar_init,				\
	.reset      = bar_reset,			\
	.release    = bar_release,			\
	.u.dw.read  = bar_read,				\
	.u.dw.write = bar_write,			\
	}

#define CFG_FIELD_ROM(reg_offset)			\
	{						\
	.offset     = reg_offset,			\
	.size       = 4,				\
	.init       = bar_init,				\
	.reset      = bar_reset,			\
	.release    = bar_release,			\
	.u.dw.read  = bar_read,				\
	.u.dw.write = rom_write,			\
	}

static const struct config_field header_0[] = {
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
	CFG_FIELD_ROM(PCI_ROM_ADDRESS),
	{}
};

static const struct config_field header_1[] = {
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
	{}
};

int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
{
	int err;

	err = xen_pcibk_config_add_fields(dev, header_common);
	if (err)
		goto out;

	switch (dev->hdr_type) {
	case PCI_HEADER_TYPE_NORMAL:
		err = xen_pcibk_config_add_fields(dev, header_0);
		break;

	case PCI_HEADER_TYPE_BRIDGE:
		err = xen_pcibk_config_add_fields(dev, header_1);
		break;

	default:
		err = -EINVAL;
		pr_err("%s: Unsupported header type %d!\n",
		       pci_name(dev), dev->hdr_type);
		break;
	}

out:
	return err;
}
Commit	Line	Data
30edc14b KRW	1	/*
	2	* PCI Backend - Handles the virtual fields in the configuration space headers.
	3	*
	4	* Author: Ryan Wilson <hap9@epoch.ncsc.mil>
	5	*/
	6
283c0972 JP	7	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
283c0972 JP	8
30edc14b KRW	9	#include <linux/kernel.h>
	10	#include <linux/pci.h>
	11	#include "pciback.h"
	12	#include "conf_space.h"
	13
af6fc858 JB	14	struct pci_cmd_info {
	15	u16 val;
	16	};
	17
30edc14b KRW	18	struct pci_bar_info {
	19	u32 val;
	20	u32 len_val;
	21	int which;
	22	};
	23
	24	#define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY\|PCI_COMMAND_IO))
	25	#define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
	26
af6fc858 JB	27	/* Bits guests are allowed to control in permissive mode. */
	28	#define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER\|PCI_COMMAND_SPECIAL\| \
	29	PCI_COMMAND_INVALIDATE\|PCI_COMMAND_VGA_PALETTE\| \
	30	PCI_COMMAND_WAIT\|PCI_COMMAND_FAST_BACK)
	31
	32	static void command_init(struct pci_dev dev, int offset)
fd5b221b	33	{
af6fc858 JB	34	struct pci_cmd_info cmd = kmalloc(sizeof(cmd), GFP_KERNEL);
	35	int err;
	36
	37	if (!cmd)
	38	return ERR_PTR(-ENOMEM);
	39
	40	err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val);
	41	if (err) {
	42	kfree(cmd);
	43	return ERR_PTR(err);
fd5b221b ZY	44	}
fd5b221b ZY	45
af6fc858 JB	46	return cmd;
	47	}
	48
	49	static int command_read(struct pci_dev dev, int offset, u16 value, void *data)
	50	{
	51	int ret = pci_read_config_word(dev, offset, value);
	52	const struct pci_cmd_info *cmd = data;
	53
	54	*value &= PCI_COMMAND_GUEST;
	55	*value \|= cmd->val & ~PCI_COMMAND_GUEST;
	56
fd5b221b ZY	57	return ret;
	58	}
	59
30edc14b KRW	60	static int command_write(struct pci_dev dev, int offset, u16 value, void data)
30edc14b KRW	61	{
a92336a1	62	struct xen_pcibk_dev_data *dev_data;
30edc14b	63	int err;
af6fc858 JB	64	u16 val;
af6fc858 JB	65	struct pci_cmd_info *cmd = data;
30edc14b	66
0513fe9e	67	dev_data = pci_get_drvdata(dev);
30edc14b KRW	68	if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
30edc14b KRW	69	if (unlikely(verbose_request))
a92336a1	70	printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
30edc14b KRW	71	pci_name(dev));
	72	err = pci_enable_device(dev);
	73	if (err)
	74	return err;
0513fe9e KRW	75	if (dev_data)
0513fe9e KRW	76	dev_data->enable_intx = 1;
30edc14b KRW	77	} else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
30edc14b KRW	78	if (unlikely(verbose_request))
a92336a1	79	printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
30edc14b KRW	80	pci_name(dev));
30edc14b KRW	81	pci_disable_device(dev);
0513fe9e KRW	82	if (dev_data)
0513fe9e KRW	83	dev_data->enable_intx = 0;
30edc14b KRW	84	}
	85
	86	if (!dev->is_busmaster && is_master_cmd(value)) {
	87	if (unlikely(verbose_request))
a92336a1	88	printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
30edc14b KRW	89	pci_name(dev));
30edc14b KRW	90	pci_set_master(dev);
278edfc0 JB	91	} else if (dev->is_busmaster && !is_master_cmd(value)) {
	92	if (unlikely(verbose_request))
	93	printk(KERN_DEBUG DRV_NAME ": %s: clear bus master\n",
	94	pci_name(dev));
	95	pci_clear_master(dev);
30edc14b KRW	96	}
30edc14b KRW	97
278edfc0 JB	98	if (!(cmd->val & PCI_COMMAND_INVALIDATE) &&
278edfc0 JB	99	(value & PCI_COMMAND_INVALIDATE)) {
30edc14b KRW	100	if (unlikely(verbose_request))
30edc14b KRW	101	printk(KERN_DEBUG
a92336a1	102	DRV_NAME ": %s: enable memory-write-invalidate\n",
30edc14b KRW	103	pci_name(dev));
	104	err = pci_set_mwi(dev);
	105	if (err) {
283c0972 JP	106	pr_warn("%s: cannot enable memory-write-invalidate (%d)\n",
283c0972 JP	107	pci_name(dev), err);
30edc14b KRW	108	value &= ~PCI_COMMAND_INVALIDATE;
30edc14b KRW	109	}
278edfc0 JB	110	} else if ((cmd->val & PCI_COMMAND_INVALIDATE) &&
	111	!(value & PCI_COMMAND_INVALIDATE)) {
	112	if (unlikely(verbose_request))
	113	printk(KERN_DEBUG
	114	DRV_NAME ": %s: disable memory-write-invalidate\n",
	115	pci_name(dev));
	116	pci_clear_mwi(dev);
30edc14b KRW	117	}
30edc14b KRW	118
af6fc858 JB	119	cmd->val = value;
af6fc858 JB	120
8014bcc8	121	if (!xen_pcibk_permissive && (!dev_data \|\| !dev_data->permissive))
af6fc858 JB	122	return 0;
	123
	124	/* Only allow the guest to control certain bits. */
	125	err = pci_read_config_word(dev, offset, &val);
	126	if (err \|\| val == value)
	127	return err;
	128
	129	value &= PCI_COMMAND_GUEST;
	130	value \|= val & ~PCI_COMMAND_GUEST;
	131
30edc14b KRW	132	return pci_write_config_word(dev, offset, value);
	133	}
	134
	135	static int rom_write(struct pci_dev dev, int offset, u32 value, void data)
	136	{
	137	struct pci_bar_info *bar = data;
	138
	139	if (unlikely(!bar)) {
283c0972	140	pr_warn(DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	141	pci_name(dev));
	142	return XEN_PCI_ERR_op_failed;
	143	}
	144
	145	/* A write to obtain the length must happen as a 32-bit write.
	146	* This does not (yet) support writing individual bytes
	147	*/
d2bd05d8	148	if ((value \| ~PCI_ROM_ADDRESS_MASK) == ~0U)
30edc14b KRW	149	bar->which = 1;
	150	else {
	151	u32 tmpval;
	152	pci_read_config_dword(dev, offset, &tmpval);
	153	if (tmpval != bar->val && value == bar->val) {
	154	/* Allow restoration of bar value. */
	155	pci_write_config_dword(dev, offset, bar->val);
	156	}
	157	bar->which = 0;
	158	}
	159
	160	/* Do we need to support enabling/disabling the rom address here? */
	161
	162	return 0;
	163	}
	164
	165	/* For the BARs, only allow writes which write ~0 or
	166	* the correct resource information
	167	* (Needed for when the driver probes the resource usage)
	168	*/
	169	static int bar_write(struct pci_dev dev, int offset, u32 value, void data)
	170	{
	171	struct pci_bar_info *bar = data;
	172
	173	if (unlikely(!bar)) {
283c0972	174	pr_warn(DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	175	pci_name(dev));
	176	return XEN_PCI_ERR_op_failed;
	177	}
	178
	179	/* A write to obtain the length must happen as a 32-bit write.
	180	* This does not (yet) support writing individual bytes
	181	*/
	182	if (value == ~0)
	183	bar->which = 1;
	184	else {
	185	u32 tmpval;
	186	pci_read_config_dword(dev, offset, &tmpval);
	187	if (tmpval != bar->val && value == bar->val) {
	188	/* Allow restoration of bar value. */
	189	pci_write_config_dword(dev, offset, bar->val);
	190	}
	191	bar->which = 0;
	192	}
	193
	194	return 0;
	195	}
	196
	197	static int bar_read(struct pci_dev dev, int offset, u32 value, void *data)
	198	{
	199	struct pci_bar_info *bar = data;
	200
	201	if (unlikely(!bar)) {
283c0972	202	pr_warn(DRV_NAME ": driver data not found for %s\n",
30edc14b KRW	203	pci_name(dev));
	204	return XEN_PCI_ERR_op_failed;
	205	}
	206
	207	*value = bar->which ? bar->len_val : bar->val;
	208
	209	return 0;
	210	}
	211
6ad2655d	212	static void bar_init(struct pci_dev dev, int offset)
30edc14b	213	{
58520360 JB	214	unsigned int pos;
58520360 JB	215	const struct resource *res = dev->resource;
6ad2655d JB	216	struct pci_bar_info bar = kzalloc(sizeof(bar), GFP_KERNEL);
	217
	218	if (!bar)
	219	return ERR_PTR(-ENOMEM);
fd5b221b ZY	220
	221	if (offset == PCI_ROM_ADDRESS \|\| offset == PCI_ROM_ADDRESS1)
	222	pos = PCI_ROM_RESOURCE;
	223	else {
	224	pos = (offset - PCI_BASE_ADDRESS_0) / 4;
c8670c22	225	if (pos && (res[pos - 1].flags & IORESOURCE_MEM_64)) {
6ad2655d JB	226	bar->val = res[pos - 1].start >> 32;
	227	bar->len_val = -resource_size(&res[pos - 1]) >> 32;
	228	return bar;
fd5b221b ZY	229	}
	230	}
	231
d2bd05d8 JB	232	if (!res[pos].flags \|\|
	233	(res[pos].flags & (IORESOURCE_DISABLED \| IORESOURCE_UNSET \|
	234	IORESOURCE_BUSY)))
6ad2655d	235	return bar;
30edc14b	236
6ad2655d JB	237	bar->val = res[pos].start \|
	238	(res[pos].flags & PCI_REGION_FLAG_MASK);
	239	bar->len_val = -resource_size(&res[pos]) \|
	240	(res[pos].flags & PCI_REGION_FLAG_MASK);
30edc14b KRW	241
	242	return bar;
	243	}
	244
30edc14b KRW	245	static void bar_reset(struct pci_dev dev, int offset, void data)
	246	{
	247	struct pci_bar_info *bar = data;
	248
	249	bar->which = 0;
	250	}
	251
	252	static void bar_release(struct pci_dev dev, int offset, void data)
	253	{
	254	kfree(data);
	255	}
	256
a92336a1	257	static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
fd5b221b ZY	258	u16 value, void data)
	259	{
	260	*value = dev->vendor;
	261
	262	return 0;
	263	}
	264
a92336a1	265	static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
fd5b221b ZY	266	u16 value, void data)
	267	{
	268	*value = dev->device;
	269
	270	return 0;
	271	}
	272
30edc14b KRW	273	static int interrupt_read(struct pci_dev dev, int offset, u8 value,
	274	void *data)
	275	{
	276	*value = (u8) dev->irq;
	277
	278	return 0;
	279	}
	280
	281	static int bist_write(struct pci_dev dev, int offset, u8 value, void data)
	282	{
	283	u8 cur_value;
	284	int err;
	285
	286	err = pci_read_config_byte(dev, offset, &cur_value);
	287	if (err)
	288	goto out;
	289
	290	if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
	291	\|\| value == PCI_BIST_START)
	292	err = pci_write_config_byte(dev, offset, value);
	293
	294	out:
	295	return err;
	296	}
	297
	298	static const struct config_field header_common[] = {
fd5b221b ZY	299	{
	300	.offset = PCI_VENDOR_ID,
	301	.size = 2,
a92336a1	302	.u.w.read = xen_pcibk_read_vendor,
fd5b221b ZY	303	},
	304	{
	305	.offset = PCI_DEVICE_ID,
	306	.size = 2,
a92336a1	307	.u.w.read = xen_pcibk_read_device,
fd5b221b	308	},
30edc14b KRW	309	{
	310	.offset = PCI_COMMAND,
	311	.size = 2,
af6fc858 JB	312	.init = command_init,
af6fc858 JB	313	.release = bar_release,
fd5b221b	314	.u.w.read = command_read,
30edc14b KRW	315	.u.w.write = command_write,
	316	},
	317	{
	318	.offset = PCI_INTERRUPT_LINE,
	319	.size = 1,
	320	.u.b.read = interrupt_read,
	321	},
	322	{
	323	.offset = PCI_INTERRUPT_PIN,
	324	.size = 1,
a92336a1	325	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	326	},
	327	{
	328	/* Any side effects of letting driver domain control cache line? */
	329	.offset = PCI_CACHE_LINE_SIZE,
	330	.size = 1,
a92336a1 KRW	331	.u.b.read = xen_pcibk_read_config_byte,
a92336a1 KRW	332	.u.b.write = xen_pcibk_write_config_byte,
30edc14b KRW	333	},
	334	{
	335	.offset = PCI_LATENCY_TIMER,
	336	.size = 1,
a92336a1	337	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	338	},
	339	{
	340	.offset = PCI_BIST,
	341	.size = 1,
a92336a1	342	.u.b.read = xen_pcibk_read_config_byte,
30edc14b KRW	343	.u.b.write = bist_write,
	344	},
	345	{}
	346	};
	347
8bfd4e02 KRW	348	#define CFG_FIELD_BAR(reg_offset) \
	349	{ \
	350	.offset = reg_offset, \
	351	.size = 4, \
	352	.init = bar_init, \
	353	.reset = bar_reset, \
	354	.release = bar_release, \
	355	.u.dw.read = bar_read, \
	356	.u.dw.write = bar_write, \
	357	}
	358
	359	#define CFG_FIELD_ROM(reg_offset) \
	360	{ \
	361	.offset = reg_offset, \
	362	.size = 4, \
664093bb	363	.init = bar_init, \
8bfd4e02 KRW	364	.reset = bar_reset, \
	365	.release = bar_release, \
	366	.u.dw.read = bar_read, \
	367	.u.dw.write = rom_write, \
	368	}
30edc14b KRW	369
	370	static const struct config_field header_0[] = {
	371	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	372	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	373	CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
	374	CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
	375	CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
	376	CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
	377	CFG_FIELD_ROM(PCI_ROM_ADDRESS),
	378	{}
	379	};
	380
	381	static const struct config_field header_1[] = {
	382	CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
	383	CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
	384	CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
	385	{}
	386	};
	387
a92336a1	388	int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
30edc14b KRW	389	{
	390	int err;
	391
a92336a1	392	err = xen_pcibk_config_add_fields(dev, header_common);
30edc14b KRW	393	if (err)
	394	goto out;
	395
	396	switch (dev->hdr_type) {
	397	case PCI_HEADER_TYPE_NORMAL:
a92336a1	398	err = xen_pcibk_config_add_fields(dev, header_0);
30edc14b KRW	399	break;
	400
	401	case PCI_HEADER_TYPE_BRIDGE:
a92336a1	402	err = xen_pcibk_config_add_fields(dev, header_1);
30edc14b KRW	403	break;
	404
	405	default:
	406	err = -EINVAL;
283c0972	407	pr_err("%s: Unsupported header type %d!\n",
30edc14b KRW	408	pci_name(dev), dev->hdr_type);
	409	break;
	410	}
	411
	412	out:
	413	return err;
	414	}